From d64519249e1d5520e8420936d662ec2cfb155dfc Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Fri, 9 Jul 2021 18:45:24 +0900 Subject: phy: samsung-ufs: support exynosauto ufs phy driver This patch adds to support phy-exynosautov9-ufs driver for ExynosAuto v9 series SoCs. The patch adds "samsung,exynosautov9-ufs-phy" compatible. Unlike previous exynos ufs phy, the chip uses 0x50 offset as PHY_TRSV_REG_CFG_OFFSET. Signed-off-by: Chanho Park Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210709094524.110193-3-chanho61.park@samsung.com Signed-off-by: Vinod Koul --- drivers/phy/samsung/phy-samsung-ufs.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/phy/samsung/phy-samsung-ufs.h') diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h index 5ab6ca6fa187..91a0e9f94f98 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.h +++ b/drivers/phy/samsung/phy-samsung-ufs.h @@ -27,14 +27,17 @@ .id = PHY_COMN_BLK, \ } -#define PHY_TRSV_REG_CFG(o, v, d) { \ +#define PHY_TRSV_REG_CFG_OFFSET(o, v, d, c) { \ .off_0 = PHY_APB_ADDR((o)), \ - .off_1 = PHY_APB_ADDR((o) + PHY_TRSV_CH_OFFSET), \ + .off_1 = PHY_APB_ADDR((o) + (c)), \ .val = (v), \ .desc = (d), \ .id = PHY_TRSV_BLK, \ } +#define PHY_TRSV_REG_CFG(o, v, d) \ + PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_TRSV_CH_OFFSET) + /* UFS PHY registers */ #define PHY_PLL_LOCK_STATUS 0x1e #define PHY_CDR_LOCK_STATUS 0x5e @@ -138,5 +141,6 @@ static inline void samsung_ufs_phy_ctrl_isol( } extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy; +extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy; #endif /* _PHY_SAMSUNG_UFS_ */ -- cgit v1.2.3