From 1ff79a4a49c239dedd67a12a16a8c3a8b53cf838 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Wed, 16 Dec 2020 12:42:01 +0100 Subject: drm/etnaviv: provide more ID values via GET_PARAM ioctl. Make it possible for the user space to access these ID values. Signed-off-by: Christian Gmeiner Signed-off-by: Lucas Stach --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index c6404b8d067f..ec16991ba8b6 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -156,6 +156,18 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) *value = ~0ULL; break; + case ETNAVIV_PARAM_GPU_PRODUCT_ID: + *value = gpu->identity.product_id; + break; + + case ETNAVIV_PARAM_GPU_CUSTOMER_ID: + *value = gpu->identity.customer_id; + break; + + case ETNAVIV_PARAM_GPU_ECO_ID: + *value = gpu->identity.eco_id; + break; + default: DBG("%s: invalid param: %u", dev_name(gpu->dev), param); return -EINVAL; -- cgit v1.2.3 From 03a2753936e85beb8239fd20ae3fb2ce90209212 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 23 Dec 2020 20:51:10 +0100 Subject: drm/etnaviv: dump: fix sparse warnings This patch fixes the following sparse warnings, by adding the missing endianess conversion functions. | etnaviv/etnaviv_dump.c:78:26: warning: restricted __le32 degrades to integer | etnaviv/etnaviv_dump.c:88:26: warning: incorrect type in assignment (different base types) | etnaviv/etnaviv_dump.c:88:26: expected restricted __le32 [usertype] reg | etnaviv/etnaviv_dump.c:88:26: got unsigned short const | etnaviv/etnaviv_dump.c:89:28: warning: incorrect type in assignment (different base types) | etnaviv/etnaviv_dump.c:89:28: expected restricted __le32 [usertype] value | etnaviv/etnaviv_dump.c:89:28: got unsigned int | etnaviv/etnaviv_dump.c:210:43: warning: incorrect type in assignment (different base types) | etnaviv/etnaviv_dump.c:210:43: expected restricted __le32 | etnaviv/etnaviv_dump.c:210:43: got long Signed-off-by: Marc Kleine-Budde Signed-off-by: Lucas Stach --- drivers/gpu/drm/etnaviv/etnaviv_dump.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/etnaviv/etnaviv_dump.c b/drivers/gpu/drm/etnaviv/etnaviv_dump.c index 706af0304ca4..f418e0b75772 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_dump.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_dump.c @@ -75,7 +75,7 @@ static void etnaviv_core_dump_header(struct core_dump_iterator *iter, hdr->file_size = cpu_to_le32(data_end - iter->data); iter->hdr++; - iter->data += hdr->file_size; + iter->data += le32_to_cpu(hdr->file_size); } static void etnaviv_core_dump_registers(struct core_dump_iterator *iter, @@ -85,8 +85,8 @@ static void etnaviv_core_dump_registers(struct core_dump_iterator *iter, unsigned int i; for (i = 0; i < ARRAY_SIZE(etnaviv_dump_registers); i++, reg++) { - reg->reg = etnaviv_dump_registers[i]; - reg->value = gpu_read(gpu, etnaviv_dump_registers[i]); + reg->reg = cpu_to_le32(etnaviv_dump_registers[i]); + reg->value = cpu_to_le32(gpu_read(gpu, etnaviv_dump_registers[i])); } etnaviv_core_dump_header(iter, ETDUMP_BUF_REG, reg); @@ -207,7 +207,7 @@ void etnaviv_core_dump(struct etnaviv_gem_submit *submit) if (!IS_ERR(pages)) { int j; - iter.hdr->data[0] = bomap - bomap_start; + iter.hdr->data[0] = cpu_to_le32((bomap - bomap_start)); for (j = 0; j < obj->base.size >> PAGE_SHIFT; j++) *bomap++ = cpu_to_le64(page_to_phys(*pages++)); -- cgit v1.2.3 From 7d614ab2f20503ed8766363d41f8607337571adf Mon Sep 17 00:00:00 2001 From: Tian Tao Date: Mon, 25 Jan 2021 11:27:27 +0800 Subject: drm/etnaviv: fix NULL check before some freeing functions is not needed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fixed the below warning: drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c:84:2-8: WARNING: NULL check before some freeing functions is not needed. Signed-off-by: Tian Tao Acked-by: Christian König Signed-off-by: Lucas Stach --- drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c index 4aa3426a9ba4..059ec31d532d 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c @@ -77,8 +77,7 @@ static void etnaviv_gem_prime_release(struct etnaviv_gem_object *etnaviv_obj) /* Don't drop the pages for imported dmabuf, as they are not * ours, just free the array we allocated: */ - if (etnaviv_obj->pages) - kvfree(etnaviv_obj->pages); + kvfree(etnaviv_obj->pages); drm_prime_gem_destroy(&etnaviv_obj->base, etnaviv_obj->sgt); } -- cgit v1.2.3 From efc52308c6a51125138c0034b3c7c24acbdd4173 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 30 Mar 2021 19:24:15 +0300 Subject: drm/i915: Split out glk_plane_min_cdclk() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Split the glk+ stuff into it's own version of the .min_cdclk() vfunc. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20210330162416.18616-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 53 ++++++++++++++-------- 1 file changed, 35 insertions(+), 18 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 7ffd7b570b54..5127489a0446 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -287,39 +287,54 @@ bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) } static void -skl_plane_ratio(const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state, +glk_plane_ratio(const struct intel_plane_state *plane_state, unsigned int *num, unsigned int *den) { - struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); const struct drm_framebuffer *fb = plane_state->hw.fb; if (fb->format->cpp[0] == 8) { - if (DISPLAY_VER(dev_priv) >= 10) { - *num = 10; - *den = 8; - } else { - *num = 9; - *den = 8; - } + *num = 10; + *den = 8; } else { *num = 1; *den = 1; } } -static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, +static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); - unsigned int num, den; unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); + unsigned int num, den; - skl_plane_ratio(crtc_state, plane_state, &num, &den); + glk_plane_ratio(plane_state, &num, &den); - /* two pixels per clock on glk+ */ - if (DISPLAY_VER(dev_priv) >= 10) - den *= 2; + /* two pixels per clock */ + return DIV_ROUND_UP(pixel_rate * num, 2 * den); +} + +static void +skl_plane_ratio(const struct intel_plane_state *plane_state, + unsigned int *num, unsigned int *den) +{ + const struct drm_framebuffer *fb = plane_state->hw.fb; + + if (fb->format->cpp[0] == 8) { + *num = 9; + *den = 8; + } else { + *num = 1; + *den = 1; + } +} + +static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state) +{ + unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); + unsigned int num, den; + + skl_plane_ratio(plane_state, &num, &den); return DIV_ROUND_UP(pixel_rate * num, den); } @@ -1965,12 +1980,15 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->min_width = icl_plane_min_width; plane->max_width = icl_plane_max_width; plane->max_height = icl_plane_max_height; + plane->min_cdclk = glk_plane_min_cdclk; } else if (DISPLAY_VER(dev_priv) >= 10) { plane->max_width = glk_plane_max_width; plane->max_height = skl_plane_max_height; + plane->min_cdclk = glk_plane_min_cdclk; } else { plane->max_width = skl_plane_max_width; plane->max_height = skl_plane_max_height; + plane->min_cdclk = skl_plane_min_cdclk; } plane->max_stride = skl_plane_max_stride; @@ -1978,7 +1996,6 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->disable_plane = skl_disable_plane; plane->get_hw_state = skl_plane_get_hw_state; plane->check_plane = skl_plane_check; - plane->min_cdclk = skl_plane_min_cdclk; if (plane_id == PLANE_PRIMARY) { plane->need_async_flip_disable_wa = IS_DISPLAY_RANGE(dev_priv, -- cgit v1.2.3 From 6195f8502dad4d6d2e715797c994a969fe7e209a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 30 Mar 2021 19:24:16 +0300 Subject: drm/i915: Update plane ratio for icl+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to bspec icl+ no longer need any extra cdclk guardband for 64bpp formats. Make it so. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20210330162416.18616-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 5127489a0446..098636c811a8 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -286,6 +286,15 @@ bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) icl_hdr_plane_mask() & BIT(plane_id); } +static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state) +{ + unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); + + /* two pixels per clock */ + return DIV_ROUND_UP(pixel_rate, 2); +} + static void glk_plane_ratio(const struct intel_plane_state *plane_state, unsigned int *num, unsigned int *den) @@ -1980,7 +1989,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->min_width = icl_plane_min_width; plane->max_width = icl_plane_max_width; plane->max_height = icl_plane_max_height; - plane->min_cdclk = glk_plane_min_cdclk; + plane->min_cdclk = icl_plane_min_cdclk; } else if (DISPLAY_VER(dev_priv) >= 10) { plane->max_width = glk_plane_max_width; plane->max_height = skl_plane_max_height; -- cgit v1.2.3 From d339ef1c4d6bb351251211d296ecbe05c2a54819 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 11 Mar 2021 16:45:29 +0200 Subject: drm/i915: Uninit the DMC FW loader state during shutdown MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need to wait for the DMC FW loader work to complete during shutdown, even if it's unlikely to be still pending by that time, fix this. This also fixes the wakeref tracking WARN during shutdown about the leaked reference we hold due to a missing DMC firmware. While at it add a TODO comment about unifying the shutdown and PM power-off sequences and later these sequences with the driver remove and system/runtime suspend sequences. Cc: Ville Syrjälä References: https://lore.kernel.org/lkml/20210303055517.GB2708@xsang-OptiPlex-9020 Reported-and-tested-by: kernel test robot Reported-and-tested-by: Edward Baker Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20210311144529.3059024-1-imre.deak@intel.com --- drivers/gpu/drm/i915/i915_drv.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 8bd80a46ba0a..abb0152b56f4 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1029,10 +1029,18 @@ void i915_driver_shutdown(struct drm_i915_private *i915) intel_suspend_encoders(i915); intel_shutdown_encoders(i915); + intel_csr_ucode_suspend(i915); + /* * The only requirement is to reboot with display DC states disabled, * for now leaving all display power wells in the INIT power domain - * enabled matching the driver reload sequence. + * enabled. + * + * TODO: + * - unify the pci_driver::shutdown sequence here with the + * pci_driver.driver.pm.poweroff,poweroff_late sequence. + * - unify the driver remove and system/runtime suspend sequences with + * the above unified shutdown/poweroff sequence. */ intel_power_domains_driver_remove(i915); enable_rpm_wakeref_asserts(&i915->runtime_pm); -- cgit v1.2.3 From 2d667442dbe70e7e78c3450b17ba5aa5032a7b6b Mon Sep 17 00:00:00 2001 From: Gwan-gyeong Mun Date: Thu, 1 Apr 2021 20:02:37 +0300 Subject: drm/i915/display/psr: Disable DC3CO when the PSR2 is used MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Due to the changed sequence of activating/deactivating DC3CO, disable DC3CO until the changed dc3co activating/deactivating sequence is applied. References: https://gitlab.freedesktop.org/drm/intel/-/issues/3134 Signed-off-by: Gwan-gyeong Mun Reviewed-by: José Roberto de Souza Signed-off-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20210401170237.40472-1-gwan-gyeong.mun@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1d561812fcad..32d3d56259c2 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -654,6 +654,13 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u32 exit_scanlines; + /* + * FIXME: Due to the changed sequence of activating/deactivating DC3CO, + * disable DC3CO until the changed dc3co activating/deactivating sequence + * is applied. B.Specs:49196 + */ + return; + /* * DMC's DC3CO exit mechanism has an issue with Selective Fecth * TODO: when the issue is addressed, this restriction should be removed. -- cgit v1.2.3 From 11cda4967a33003dc19e90f5df3470031a864d8d Mon Sep 17 00:00:00 2001 From: Xuezhi Zhang Date: Sun, 4 Apr 2021 08:41:03 +0000 Subject: drm/i915/sysfs: convert snprintf to sysfs_emit Fix the following coccicheck warning: drivers/gpu/drm/i915//i915_sysfs.c:266:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:285:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:276:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:335:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:390:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:465:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:107:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:75:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:83:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:91:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:99:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:326:8-16: WARNING: use scnprintf or sprintf Signed-off-by: Xuezhi Zhang Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20210404084103.528211-1-llyz108@163.com --- drivers/gpu/drm/i915/i915_sysfs.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 45d32ef42787..4c6b5d52b5ca 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -72,7 +72,7 @@ show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf) if (HAS_RC6pp(dev_priv)) mask |= BIT(2); - return snprintf(buf, PAGE_SIZE, "%x\n", mask); + return sysfs_emit(buf, "%x\n", mask); } static ssize_t @@ -80,7 +80,7 @@ show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) { struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6); - return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); + return sysfs_emit(buf, "%u\n", rc6_residency); } static ssize_t @@ -88,7 +88,7 @@ show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf) { struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p); - return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency); + return sysfs_emit(buf, "%u\n", rc6p_residency); } static ssize_t @@ -96,7 +96,7 @@ show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf) { struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp); - return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency); + return sysfs_emit(buf, "%u\n", rc6pp_residency); } static ssize_t @@ -104,7 +104,7 @@ show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) { struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6); - return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); + return sysfs_emit(buf, "%u\n", rc6_residency); } static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL); @@ -263,8 +263,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev, struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); struct intel_rps *rps = &i915->gt.rps; - return snprintf(buf, PAGE_SIZE, "%d\n", - intel_rps_read_actual_frequency(rps)); + return sysfs_emit(buf, "%d\n", intel_rps_read_actual_frequency(rps)); } static ssize_t gt_cur_freq_mhz_show(struct device *kdev, @@ -273,8 +272,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev, struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); struct intel_rps *rps = &i915->gt.rps; - return snprintf(buf, PAGE_SIZE, "%d\n", - intel_gpu_freq(rps, rps->cur_freq)); + return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->cur_freq)); } static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) @@ -282,8 +280,7 @@ static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribu struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); struct intel_rps *rps = &i915->gt.rps; - return snprintf(buf, PAGE_SIZE, "%d\n", - intel_gpu_freq(rps, rps->boost_freq)); + return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->boost_freq)); } static ssize_t gt_boost_freq_mhz_store(struct device *kdev, @@ -323,8 +320,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); struct intel_rps *rps = &dev_priv->gt.rps; - return snprintf(buf, PAGE_SIZE, "%d\n", - intel_gpu_freq(rps, rps->efficient_freq)); + return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->efficient_freq)); } static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) @@ -332,8 +328,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); struct intel_rps *rps = &dev_priv->gt.rps; - return snprintf(buf, PAGE_SIZE, "%d\n", - intel_gpu_freq(rps, rps->max_freq_softlimit)); + return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->max_freq_softlimit)); } static ssize_t gt_max_freq_mhz_store(struct device *kdev, @@ -387,8 +382,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); struct intel_rps *rps = &dev_priv->gt.rps; - return snprintf(buf, PAGE_SIZE, "%d\n", - intel_gpu_freq(rps, rps->min_freq_softlimit)); + return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->min_freq_softlimit)); } static ssize_t gt_min_freq_mhz_store(struct device *kdev, @@ -462,7 +456,7 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr else BUG(); - return snprintf(buf, PAGE_SIZE, "%d\n", val); + return sysfs_emit(buf, "%d\n", val); } static const struct attribute * const gen6_attrs[] = { -- cgit v1.2.3 From 337d7a1621c7f02af867229990ac67c97da1b53a Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Fri, 2 Apr 2021 10:23:17 +0200 Subject: drm/i915: Fix invalid access to ACPI _DSM objects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit intel_dsm_platform_mux_info() tries to parse the ACPI package data from _DSM for the debug information, but it assumes the fixed format without checking what values are stored in the elements actually. When an unexpected value is returned from BIOS, it may lead to GPF or NULL dereference, as reported recently. Add the checks of the contents in the returned values and skip the values for invalid cases. v1->v2: Check the info contents before dereferencing, too BugLink: http://bugzilla.opensuse.org/show_bug.cgi?id=1184074 Cc: Signed-off-by: Takashi Iwai Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20210402082317.871-1-tiwai@suse.de --- drivers/gpu/drm/i915/display/intel_acpi.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c b/drivers/gpu/drm/i915/display/intel_acpi.c index e21fb14d5e07..833d0c1be4f1 100644 --- a/drivers/gpu/drm/i915/display/intel_acpi.c +++ b/drivers/gpu/drm/i915/display/intel_acpi.c @@ -84,13 +84,31 @@ static void intel_dsm_platform_mux_info(acpi_handle dhandle) return; } + if (!pkg->package.count) { + DRM_DEBUG_DRIVER("no connection in _DSM\n"); + return; + } + connector_count = &pkg->package.elements[0]; DRM_DEBUG_DRIVER("MUX info connectors: %lld\n", (unsigned long long)connector_count->integer.value); for (i = 1; i < pkg->package.count; i++) { union acpi_object *obj = &pkg->package.elements[i]; - union acpi_object *connector_id = &obj->package.elements[0]; - union acpi_object *info = &obj->package.elements[1]; + union acpi_object *connector_id; + union acpi_object *info; + + if (obj->type != ACPI_TYPE_PACKAGE || obj->package.count < 2) { + DRM_DEBUG_DRIVER("Invalid object for MUX #%d\n", i); + continue; + } + + connector_id = &obj->package.elements[0]; + info = &obj->package.elements[1]; + if (info->type != ACPI_TYPE_BUFFER || info->buffer.length < 4) { + DRM_DEBUG_DRIVER("Invalid info for MUX obj #%d\n", i); + continue; + } + DRM_DEBUG_DRIVER("Connector id: 0x%016llx\n", (unsigned long long)connector_id->integer.value); DRM_DEBUG_DRIVER(" port id: %s\n", -- cgit v1.2.3 From 70bfb30743d5da73058b0a2271e9c127a84fb494 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Wed, 7 Apr 2021 13:39:45 -0700 Subject: drm/i915/display: Eliminate IS_GEN9_{BC,LP} MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that we've eliminated INTEL_GEN(), IS_GEN_RANGE(), etc. from the display code, we should also kill off our use of the IS_GEN9_* macros too. We'll do the conversion manually this time instead of using Coccinelle since the most logical substitution can depend heavily on the code context, and sometimes we can keep the code simpler if we make additional adjustments such as swapping the order of if/else arms. v2: - Restore a lost negation in intel_pll_is_valid(). Cc: Ville Syrjälä Cc: Lucas De Marchi Signed-off-by: Matt Roper Reviewed-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20210407203945.1432531-1-matthew.d.roper@intel.com --- drivers/gpu/drm/i915/display/intel_bios.c | 7 ++-- drivers/gpu/drm/i915/display/intel_cdclk.c | 34 ++++++++-------- drivers/gpu/drm/i915/display/intel_csr.c | 2 +- drivers/gpu/drm/i915/display/intel_ddi.c | 37 +++++++++-------- drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 8 ++-- drivers/gpu/drm/i915/display/intel_display.c | 11 +++--- .../gpu/drm/i915/display/intel_display_debugfs.c | 2 +- drivers/gpu/drm/i915/display/intel_display_power.c | 43 ++++++++++---------- drivers/gpu/drm/i915/display/intel_dp.c | 4 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll.c | 6 +-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 +-- drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++-- drivers/gpu/drm/i915/display/intel_gmbus.c | 12 +++--- drivers/gpu/drm/i915/display/intel_hdcp.c | 9 +++-- drivers/gpu/drm/i915/display/intel_hdmi.c | 7 ++-- drivers/gpu/drm/i915/display/intel_panel.c | 2 +- drivers/gpu/drm/i915/display/intel_pps.c | 14 +++---- drivers/gpu/drm/i915/display/vlv_dsi.c | 46 +++++++++++----------- drivers/gpu/drm/i915/i915_irq.c | 13 +++--- drivers/gpu/drm/i915/intel_pm.c | 8 ++-- 21 files changed, 146 insertions(+), 134 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 3d0c035b5e38..ea4837d485a1 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -917,7 +917,7 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb) * Old decimal value is wake up time in multiples of 100 us. */ if (bdb->version >= 205 && - (IS_GEN9_BC(i915) || DISPLAY_VER(i915) >= 10)) { + (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) { switch (psr_table->tp1_wakeup_time) { case 0: i915->vbt.psr.tp1_wakeup_time_us = 500; @@ -1659,7 +1659,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) { ddc_pin_map = rkl_pch_tgp_ddc_pin_map; n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); - } else if (HAS_PCH_TGP(i915) && IS_GEN9_BC(i915)) { + } else if (HAS_PCH_TGP(i915) && IS_DISPLAY_VER(i915, 9)) { ddc_pin_map = gen9bc_tgp_ddc_pin_map; n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { @@ -2770,7 +2770,8 @@ intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915, const struct intel_bios_encoder_data *devdata = i915->vbt.ddi_port_info[port].devdata; - if (drm_WARN_ON_ONCE(&i915->drm, !IS_GEN9_LP(i915))) + if (drm_WARN_ON_ONCE(&i915->drm, + !IS_GEMINILAKE(i915) && !IS_BROXTON(i915))) return false; return devdata && devdata->child.hpd_invert; diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 3f43ad4d7362..489acf6b5cf1 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1631,7 +1631,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, * Disable SSA Precharge when CD clock frequency < 500 MHz, * enable otherwise. */ - if (IS_GEN9_LP(dev_priv) && cdclk >= 500000) + if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && + cdclk >= 500000) val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; intel_de_write(dev_priv, CDCLK_CTL, val); @@ -1732,7 +1733,8 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) * Disable SSA Precharge when CD clock frequency < 500 MHz, * enable otherwise. */ - if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000) + if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && + dev_priv->cdclk.hw.cdclk >= 500000) expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; if (cdctl == expected) @@ -1797,9 +1799,9 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) */ void intel_cdclk_init_hw(struct drm_i915_private *i915) { - if (IS_GEN9_LP(i915) || DISPLAY_VER(i915) >= 10) + if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) bxt_cdclk_init_hw(i915); - else if (IS_GEN9_BC(i915)) + else if (IS_DISPLAY_VER(i915, 9)) skl_cdclk_init_hw(i915); } @@ -1812,9 +1814,9 @@ void intel_cdclk_init_hw(struct drm_i915_private *i915) */ void intel_cdclk_uninit_hw(struct drm_i915_private *i915) { - if (DISPLAY_VER(i915) >= 10 || IS_GEN9_LP(i915)) + if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) bxt_cdclk_uninit_hw(i915); - else if (IS_GEN9_BC(i915)) + else if (IS_DISPLAY_VER(i915, 9)) skl_cdclk_uninit_hw(i915); } @@ -1852,7 +1854,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *b) { /* Older hw doesn't have the capability */ - if (DISPLAY_VER(dev_priv) < 10 && !IS_GEN9_LP(dev_priv)) + if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) return false; return a->cdclk != b->cdclk && @@ -2625,7 +2627,11 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) dev_priv->max_cdclk_freq = 652800; } else if (IS_CANNONLAKE(dev_priv)) { dev_priv->max_cdclk_freq = 528000; - } else if (IS_GEN9_BC(dev_priv)) { + } else if (IS_GEMINILAKE(dev_priv)) { + dev_priv->max_cdclk_freq = 316800; + } else if (IS_BROXTON(dev_priv)) { + dev_priv->max_cdclk_freq = 624000; + } else if (IS_DISPLAY_VER(dev_priv, 9)) { u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; int max_cdclk, vco; @@ -2647,10 +2653,6 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) max_cdclk = 308571; dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); - } else if (IS_GEMINILAKE(dev_priv)) { - dev_priv->max_cdclk_freq = 316800; - } else if (IS_BROXTON(dev_priv)) { - dev_priv->max_cdclk_freq = 624000; } else if (IS_BROADWELL(dev_priv)) { /* * FIXME with extra cooling we can allow @@ -2878,7 +2880,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; dev_priv->display.calc_voltage_level = cnl_calc_voltage_level; dev_priv->cdclk.table = cnl_cdclk_table; - } else if (IS_GEN9_LP(dev_priv)) { + } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; dev_priv->display.set_cdclk = bxt_set_cdclk; dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; @@ -2887,7 +2889,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->cdclk.table = glk_cdclk_table; else dev_priv->cdclk.table = bxt_cdclk_table; - } else if (IS_GEN9_BC(dev_priv)) { + } else if (IS_DISPLAY_VER(dev_priv, 9)) { dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; dev_priv->display.set_cdclk = skl_set_cdclk; dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk; @@ -2908,9 +2910,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk; } - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEN9_LP(dev_priv)) + if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv)) dev_priv->display.get_cdclk = bxt_get_cdclk; - else if (IS_GEN9_BC(dev_priv)) + else if (IS_DISPLAY_VER(dev_priv, 9)) dev_priv->display.get_cdclk = skl_get_cdclk; else if (IS_BROADWELL(dev_priv)) dev_priv->display.get_cdclk = bdw_get_cdclk; diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 794efcc3ca08..e54521d7b931 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -284,7 +284,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) mask = DC_STATE_DEBUG_MASK_MEMORY_UP; - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) mask |= DC_STATE_DEBUG_MASK_CORES; /* The below bit doesn't need to be cleared ever afterwards */ diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 953de42e277c..deef24da00b5 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -113,7 +113,8 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, &n_entries); /* If we're boosting the current, set bit 31 of trans1 */ - if (IS_GEN9_BC(dev_priv) && intel_bios_encoder_dp_boost_level(encoder->devdata)) + if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv) && + intel_bios_encoder_dp_boost_level(encoder->devdata)) iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; for (i = 0; i < n_entries; i++) { @@ -146,7 +147,8 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, level = n_entries - 1; /* If we're boosting the current, set bit 31 of trans1 */ - if (IS_GEN9_BC(dev_priv) && intel_bios_encoder_hdmi_boost_level(encoder->devdata)) + if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv) && + intel_bios_encoder_hdmi_boost_level(encoder->devdata)) iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; /* Entry 9 is for HDMI: */ @@ -759,7 +761,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, *is_dp_mst = mst_pipe_mask; out: - if (*pipe_mask && IS_GEN9_LP(dev_priv)) { + if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | BXT_PHY_LANE_POWERDOWN_ACK | @@ -987,7 +989,7 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); } else if (IS_CANNONLAKE(dev_priv)) { cnl_get_buf_trans(encoder, crtc_state, &n_entries); - } else if (IS_GEN9_LP(dev_priv)) { + } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { bxt_get_buf_trans(encoder, crtc_state, &n_entries); } else { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) @@ -1555,7 +1557,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp, intel_dp->DP &= ~DDI_BUF_EMP_MASK; intel_dp->DP |= signal_levels; - if (IS_GEN9_BC(dev_priv)) + if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) skl_ddi_set_iboost(encoder, crtc_state, level); intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); @@ -2648,7 +2650,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, icl_ddi_vswing_sequence(encoder, crtc_state, level); else if (IS_CANNONLAKE(dev_priv)) cnl_ddi_vswing_sequence(encoder, crtc_state, level); - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_ddi_vswing_sequence(encoder, crtc_state, level); else intel_prepare_dp_ddi_buffers(encoder, crtc_state); @@ -3096,16 +3098,16 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, icl_ddi_vswing_sequence(encoder, crtc_state, level); else if (IS_CANNONLAKE(dev_priv)) cnl_ddi_vswing_sequence(encoder, crtc_state, level); - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_ddi_vswing_sequence(encoder, crtc_state, level); else intel_prepare_hdmi_ddi_buffers(encoder, level); - if (IS_GEN9_BC(dev_priv)) + if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) skl_ddi_set_iboost(encoder, crtc_state, level); /* Display WA #1143: skl,kbl,cfl */ - if (IS_GEN9_BC(dev_priv)) { + if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) { /* * For some reason these chicken bits have been * stuffed into a transcoder register, event though @@ -3321,7 +3323,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, * Type-C ports. Skip this step for TBT. */ intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_ddi_phy_set_lane_optim_mask(encoder, crtc_state->lane_lat_optim_mask); } @@ -3679,7 +3681,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, if (!pipe_config->bigjoiner_slave) ddi_dotclock_get(pipe_config); - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) pipe_config->lane_lat_optim_mask = bxt_ddi_phy_get_lane_lat_optim_mask(encoder); @@ -3885,7 +3887,7 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder, pipe_config->pch_pfit.enabled || pipe_config->crc_enabled; - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) pipe_config->lane_lat_optim_mask = bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); @@ -4053,7 +4055,7 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) dig_port->dp.set_signal_levels = icl_set_signal_levels; else if (IS_CANNONLAKE(dev_priv)) dig_port->dp.set_signal_levels = cnl_set_signal_levels; - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) dig_port->dp.set_signal_levels = bxt_set_signal_levels; else dig_port->dp.set_signal_levels = hsw_set_signal_levels; @@ -4296,7 +4298,7 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only * supported configuration */ - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) return true; /* Cannonlake: Most of SKUs don't support DDI_E, and the only @@ -4585,10 +4587,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->disable_clock = cnl_ddi_disable_clock; encoder->is_clock_enabled = cnl_ddi_is_clock_enabled; encoder->get_config = cnl_ddi_get_config; - } else if (IS_GEN9_LP(dev_priv)) { + } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { /* BXT/GLK have fixed PLL->port mapping */ encoder->get_config = bxt_ddi_get_config; - } else if (IS_GEN9_BC(dev_priv)) { + } else if (IS_DISPLAY_VER(dev_priv, 9)) { encoder->enable_clock = skl_ddi_enable_clock; encoder->disable_clock = skl_ddi_disable_clock; encoder->is_clock_enabled = skl_ddi_is_clock_enabled; @@ -4672,7 +4674,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) else dig_port->connected = lpt_digital_port_connected; } else if (DISPLAY_VER(dev_priv) >= 8) { - if (port == PORT_A || IS_GEN9_LP(dev_priv)) + if (port == PORT_A || IS_GEMINILAKE(dev_priv) || + IS_BROXTON(dev_priv)) dig_port->connected = bdw_digital_port_connected; else dig_port->connected = lpt_digital_port_connected; diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 5d9ce6042e87..fdd25861edd5 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -881,7 +881,7 @@ intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - if (IS_GEN9_BC(dev_priv)) { + if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) { const struct ddi_buf_trans *ddi_translations = skl_get_buf_trans_edp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); @@ -919,7 +919,7 @@ intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - if (IS_GEN9_BC(dev_priv)) { + if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) { return skl_get_buf_trans_hdmi(dev_priv, n_entries); } else if (IS_BROADWELL(dev_priv)) { *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); @@ -1370,10 +1370,10 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, } else if (IS_CANNONLAKE(dev_priv)) { cnl_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = n_entries - 1; - } else if (IS_GEN9_LP(dev_priv)) { + } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { bxt_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = n_entries - 1; - } else if (IS_GEN9_BC(dev_priv)) { + } else if (IS_DISPLAY_VER(dev_priv, 9)) { intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = 8; } else if (IS_BROADWELL(dev_priv)) { diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index bdb2adb4d748..d3af51e63380 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5921,7 +5921,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set); - if (IS_GEN9_LP(dev_priv) && + if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) { drm_WARN_ON(&dev_priv->drm, active); active = true; @@ -6839,7 +6839,8 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) crtc_state->pixel_rate); /* Display WA #1135: BXT:ALL GLK:ALL */ - if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) + if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && + dev_priv->ipc_enabled) linetime_wm /= 2; return min(linetime_wm, 0x1ff); @@ -10858,7 +10859,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) intel_ddi_init(dev_priv, PORT_F); icl_dsi_init(dev_priv); - } else if (IS_GEN9_LP(dev_priv)) { + } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { /* * FIXME: Broxton doesn't support port detection via the * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to @@ -10883,7 +10884,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) */ found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; /* WaIgnoreDDIAStrap: skl */ - if (found || IS_GEN9_BC(dev_priv)) + if (found || IS_DISPLAY_VER(dev_priv, 9)) intel_ddi_init(dev_priv, PORT_A); /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP @@ -10908,7 +10909,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) /* * On SKL we don't have a way to detect DDI-E so we rely on VBT. */ - if (IS_GEN9_BC(dev_priv) && + if (IS_DISPLAY_VER(dev_priv, 9) && intel_bios_is_port_present(dev_priv, PORT_E)) intel_ddi_init(dev_priv, PORT_E); diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 1f5aa98bfcd5..490b6550a810 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -569,7 +569,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused) } else { dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT : SKL_CSR_DC3_DC5_COUNT; - if (!IS_GEN9_LP(dev_priv)) + if (!IS_GEMINILAKE(dev_priv) && !IS_BROXTON(dev_priv)) dc6_reg = SKL_CSR_DC5_DC6_COUNT; } diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 99126caf5747..9419ae8c6111 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -709,7 +709,7 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, * BIOS's own request bits, which are forced-on for these power wells * when exiting DC5/6. */ - if (IS_DISPLAY_VER(dev_priv, 9) && !IS_GEN9_LP(dev_priv) && + if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv) && (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) val |= intel_de_read(dev_priv, regs->bios); @@ -809,7 +809,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) | DC_STATE_EN_DC9; else if (IS_DISPLAY_VER(dev_priv, 11)) mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) mask |= DC_STATE_EN_DC9; else mask |= DC_STATE_EN_UPTO_DC6; @@ -1060,7 +1060,7 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv) drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n"); /* Wa Display #1183: skl,kbl,cfl */ - if (IS_GEN9_BC(dev_priv)) + if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1, intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT); @@ -1087,7 +1087,7 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv) drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n"); /* Wa Display #1183: skl,kbl,cfl */ - if (IS_GEN9_BC(dev_priv)) + if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1, intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT); @@ -1189,7 +1189,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) gen9_assert_dbuf_enabled(dev_priv); - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_verify_ddi_phy_power_wells(dev_priv); if (DISPLAY_VER(dev_priv) >= 11) @@ -4537,10 +4537,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, max_dc = 3; else if (DISPLAY_VER(dev_priv) >= 12) max_dc = 4; - else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv) || IS_GEN9_BC(dev_priv)) - max_dc = 2; - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) max_dc = 1; + else if (DISPLAY_VER(dev_priv) >= 9) + max_dc = 2; else max_dc = 0; @@ -4549,7 +4549,8 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, * not depending on the DMC firmware. It's needed by system * suspend/resume, so allow it unconditionally. */ - mask = IS_GEN9_LP(dev_priv) || DISPLAY_VER(dev_priv) >= 11 ? + mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || + DISPLAY_VER(dev_priv) >= 11 ? DC_STATE_EN_DC9 : 0; if (!dev_priv->params.disable_power_well) @@ -4692,7 +4693,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) err = set_power_wells(power_domains, glk_power_wells); } else if (IS_BROXTON(dev_priv)) { err = set_power_wells(power_domains, bxt_power_wells); - } else if (IS_GEN9_BC(dev_priv)) { + } else if (IS_DISPLAY_VER(dev_priv, 9)) { err = set_power_wells(power_domains, skl_power_wells); } else if (IS_CHERRYVIEW(dev_priv)) { err = set_power_wells(power_domains, chv_power_wells); @@ -5623,10 +5624,10 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) icl_display_core_init(i915, resume); } else if (IS_CANNONLAKE(i915)) { cnl_display_core_init(i915, resume); - } else if (IS_GEN9_BC(i915)) { - skl_display_core_init(i915, resume); - } else if (IS_GEN9_LP(i915)) { + } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { bxt_display_core_init(i915, resume); + } else if (IS_DISPLAY_VER(i915, 9)) { + skl_display_core_init(i915, resume); } else if (IS_CHERRYVIEW(i915)) { mutex_lock(&power_domains->lock); chv_phy_control_init(i915); @@ -5784,10 +5785,10 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, icl_display_core_uninit(i915); else if (IS_CANNONLAKE(i915)) cnl_display_core_uninit(i915); - else if (IS_GEN9_BC(i915)) - skl_display_core_uninit(i915); - else if (IS_GEN9_LP(i915)) + else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) bxt_display_core_uninit(i915); + else if (IS_DISPLAY_VER(i915, 9)) + skl_display_core_uninit(i915); power_domains->display_core_suspended = true; } @@ -5908,7 +5909,8 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915) void intel_display_power_suspend_late(struct drm_i915_private *i915) { - if (DISPLAY_VER(i915) >= 11 || IS_GEN9_LP(i915)) { + if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || + IS_BROXTON(i915)) { bxt_enable_dc9(i915); /* Tweaked Wa_14010685332:icp,jsp,mcc */ if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC) @@ -5921,7 +5923,8 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915) void intel_display_power_resume_early(struct drm_i915_private *i915) { - if (DISPLAY_VER(i915) >= 11 || IS_GEN9_LP(i915)) { + if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || + IS_BROXTON(i915)) { gen9_sanitize_dc_state(i915); bxt_disable_dc9(i915); /* Tweaked Wa_14010685332:icp,jsp,mcc */ @@ -5938,7 +5941,7 @@ void intel_display_power_suspend(struct drm_i915_private *i915) if (DISPLAY_VER(i915) >= 11) { icl_display_core_uninit(i915); bxt_enable_dc9(i915); - } else if (IS_GEN9_LP(i915)) { + } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { bxt_display_core_uninit(i915); bxt_enable_dc9(i915); } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { @@ -5959,7 +5962,7 @@ void intel_display_power_resume(struct drm_i915_private *i915) DC_STATE_EN_UPTO_DC5) gen9_enable_dc5(i915); } - } else if (IS_GEN9_LP(i915)) { + } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { bxt_disable_dc9(i915); bxt_display_core_init(i915, true); if (i915->csr.dmc_payload && diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a560468765c0..a5231ac3443a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -301,10 +301,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) max_rate = ehl_max_source_rate(intel_dp); else max_rate = icl_max_source_rate(intel_dp); - } else if (IS_GEN9_LP(dev_priv)) { + } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { source_rates = bxt_rates; size = ARRAY_SIZE(bxt_rates); - } else if (IS_GEN9_BC(dev_priv)) { + } else if (IS_DISPLAY_VER(dev_priv, 9)) { source_rates = skl_rates; size = ARRAY_SIZE(skl_rates); } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 2daa3f67791e..180f97cd74cb 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -154,7 +154,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, pipe_config->limited_color_range = intel_dp_limited_color_range(pipe_config, conn_state); - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) pipe_config->lane_lat_optim_mask = bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 3e3c5eed1600..158f271299a4 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -366,13 +366,11 @@ static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) return false; - if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && - !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) + if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv)) if (clock->m1 <= clock->m2) return false; - if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && - !IS_GEN9_LP(dev_priv)) { + if (!IS_LP(dev_priv)) { if (clock->p < limit->p.min || limit->p.max < clock->p) return false; if (clock->m < limit->m.min || limit->m.max < clock->m) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 1ae158d12c07..e32de7c848e9 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -4441,10 +4441,10 @@ void intel_shared_dpll_init(struct drm_device *dev) dpll_mgr = &icl_pll_mgr; else if (IS_CANNONLAKE(dev_priv)) dpll_mgr = &cnl_pll_mgr; - else if (IS_GEN9_BC(dev_priv)) - dpll_mgr = &skl_pll_mgr; - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) dpll_mgr = &bxt_pll_mgr; + else if (IS_DISPLAY_VER(dev_priv, 9)) + dpll_mgr = &skl_pll_mgr; else if (HAS_DDI(dev_priv)) dpll_mgr = &hsw_pll_mgr; else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 986bbbe3b12f..04d9c7d22b04 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -302,7 +302,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) int threshold = dev_priv->fbc.threshold; /* Display WA #0529: skl, kbl, bxt. */ - if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) { + if (IS_DISPLAY_VER(dev_priv, 9)) { u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4); val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK); @@ -445,7 +445,8 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, * reserved range size, so it always assumes the maximum (8mb) is used. * If we enable FBC using a CFB on that memory range we'll get FIFO * underruns, even if that range is not reserved by the BIOS. */ - if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv)) + if (IS_BROADWELL(dev_priv) || (IS_DISPLAY_VER(dev_priv, 9) && + !IS_BROXTON(dev_priv))) end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024; else end = U64_MAX; @@ -759,7 +760,7 @@ static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv) struct intel_fbc *fbc = &dev_priv->fbc; struct intel_fbc_state_cache *cache = &fbc->state_cache; - if ((IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) && + if ((IS_DISPLAY_VER(dev_priv, 9)) && cache->fb.modifier != I915_FORMAT_MOD_X_TILED) return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8; else diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index 8ddc20daef64..13ba280d0228 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -107,9 +107,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, return &gmbus_pins_icp[pin]; else if (HAS_PCH_CNP(dev_priv)) return &gmbus_pins_cnp[pin]; - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) return &gmbus_pins_bxt[pin]; - else if (IS_GEN9_BC(dev_priv)) + else if (IS_DISPLAY_VER(dev_priv, 9)) return &gmbus_pins_skl[pin]; else if (IS_BROADWELL(dev_priv)) return &gmbus_pins_bdw[pin]; @@ -128,9 +128,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, size = ARRAY_SIZE(gmbus_pins_icp); else if (HAS_PCH_CNP(dev_priv)) size = ARRAY_SIZE(gmbus_pins_cnp); - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) size = ARRAY_SIZE(gmbus_pins_bxt); - else if (IS_GEN9_BC(dev_priv)) + else if (IS_DISPLAY_VER(dev_priv, 9)) size = ARRAY_SIZE(gmbus_pins_skl); else if (IS_BROADWELL(dev_priv)) size = ARRAY_SIZE(gmbus_pins_bdw); @@ -600,7 +600,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, int ret = 0; /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_gmbus_clock_gating(dev_priv, false); else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) pch_gmbus_clock_gating(dev_priv, false); @@ -713,7 +713,7 @@ timeout: out: /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_gmbus_clock_gating(dev_priv, true); else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) pch_gmbus_clock_gating(dev_priv, true); diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index d8570e14fe60..75050a040577 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -286,11 +286,12 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) /* * Initiate loading the HDCP key from fuses. * - * BXT+ platforms, HDCP key needs to be loaded by SW. Only Gen 9 - * platforms except BXT and GLK, differ in the key load trigger process - * from other platforms. So GEN9_BC uses the GT Driver Mailbox i/f. + * BXT+ platforms, HDCP key needs to be loaded by SW. Only display + * version 9 platforms (minus BXT) differ in the key load trigger + * process from other platforms. These platforms use the GT Driver + * Mailbox interface. */ - if (IS_GEN9_BC(dev_priv)) { + if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) { ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1); if (ret) { diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index d69f0a6dc26d..f2d1fef8bd9d 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1841,7 +1841,8 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, return MODE_CLOCK_RANGE; /* BXT/GLK DPLL can't generate 223-240 MHz */ - if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) + if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && + clock > 223333 && clock < 240000) return MODE_CLOCK_RANGE; /* CHV DPLL can't generate 216-240 MHz */ @@ -2714,7 +2715,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); else if (IS_ROCKETLAKE(dev_priv)) ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); - else if (IS_GEN9_BC(dev_priv) && HAS_PCH_TGP(dev_priv)) + else if (IS_DISPLAY_VER(dev_priv, 9) && HAS_PCH_TGP(dev_priv)) ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port); else if (HAS_PCH_MCC(dev_priv)) ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); @@ -2722,7 +2723,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) ddc_pin = icl_port_to_ddc_pin(dev_priv, port); else if (HAS_PCH_CNP(dev_priv)) ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); else if (IS_CHERRYVIEW(dev_priv)) ddc_pin = chv_port_to_ddc_pin(dev_priv, port); diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 10022d1575e1..2fcbb2ba2d78 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -2161,7 +2161,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) intel_dsi_dcs_init_backlight_funcs(connector) == 0) return; - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { panel->backlight.pwm_funcs = &bxt_pwm_funcs; } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) { panel->backlight.pwm_funcs = &cnp_pwm_funcs; diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index c55da130773b..3a0985f1f531 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -313,10 +313,7 @@ void intel_pps_reset_all(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; - if (drm_WARN_ON(&dev_priv->drm, - !(IS_VALLEYVIEW(dev_priv) || - IS_CHERRYVIEW(dev_priv) || - IS_GEN9_LP(dev_priv)))) + if (drm_WARN_ON(&dev_priv->drm, !IS_LP(dev_priv))) return; /* @@ -338,7 +335,7 @@ void intel_pps_reset_all(struct drm_i915_private *dev_priv) if (encoder->type != INTEL_OUTPUT_EDP) continue; - if (IS_GEN9_LP(dev_priv)) + if (DISPLAY_VER(dev_priv) >= 9) intel_dp->pps.pps_reset = true; else intel_dp->pps.pps_pipe = INVALID_PIPE; @@ -361,7 +358,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, memset(regs, 0, sizeof(*regs)); - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) pps_idx = bxt_power_sequencer_idx(intel_dp); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) pps_idx = vlv_power_sequencer_pipe(intel_dp); @@ -372,7 +369,8 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, regs->pp_off = PP_OFF_DELAYS(pps_idx); /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ - if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || + INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) regs->pp_div = INVALID_MMIO_REG; else regs->pp_div = PP_DIVISOR(pps_idx); @@ -1399,7 +1397,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) void intel_pps_setup(struct drm_i915_private *i915) { - if (HAS_PCH_SPLIT(i915) || IS_GEN9_LP(i915)) + if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915)) i915->pps_mmio_base = PCH_PPS_BASE; else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) i915->pps_mmio_base = VLV_PPS_BASE; diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index 1059a26c1f58..9bee99fe5495 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -297,7 +297,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder, else pipe_config->pipe_bpp = 18; - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { /* Enable Frame time stamp based scanline reporting */ pipe_config->mode_flags |= I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; @@ -522,7 +522,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) if (IS_GEMINILAKE(dev_priv)) glk_dsi_device_ready(encoder); - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_dsi_device_ready(encoder); else vlv_dsi_device_ready(encoder); @@ -601,7 +601,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) drm_dbg_kms(&dev_priv->drm, "\n"); for_each_dsi_port(port, intel_dsi->ports) { /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ - i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? + i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); u32 val; @@ -621,7 +621,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI * Port A only. MIPI Port C has no similar bit for checking. */ - if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && + if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) && intel_de_wait_for_clear(dev_priv, port_ctrl, AFE_LATCHOUT, 30)) drm_err(&dev_priv->drm, "DSI LP not going Low\n"); @@ -646,7 +646,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { u32 temp; - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { for_each_dsi_port(port, intel_dsi->ports) { temp = intel_de_read(dev_priv, MIPI_CTRL(port)); @@ -666,7 +666,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, } for_each_dsi_port(port, intel_dsi->ports) { - i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? + i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); u32 temp; @@ -703,7 +703,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) enum port port; for_each_dsi_port(port, intel_dsi->ports) { - i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? + i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); u32 temp; @@ -781,7 +781,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, * The BIOS may leave the PLL in a wonky state where it doesn't * lock. It needs to be fully powered down to fix it. */ - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { bxt_dsi_pll_disable(encoder); bxt_dsi_pll_enable(encoder, pipe_config); } else { @@ -932,7 +932,7 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, drm_dbg_kms(&dev_priv->drm, "\n"); - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { intel_crtc_vblank_off(old_crtc_state); skl_scaler_disable(old_crtc_state); @@ -971,7 +971,7 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, val & ~MIPIO_RST_CTRL); } - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { bxt_dsi_pll_disable(encoder); } else { u32 val; @@ -1024,12 +1024,13 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, * configuration, otherwise accessing DSI registers will hang the * machine. See BSpec North Display Engine registers/MIPI[BXT]. */ - if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) + if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && + !bxt_dsi_pll_is_enabled(dev_priv)) goto out_put_power; /* XXX: this only works for one DSI output */ for_each_dsi_port(port, intel_dsi->ports) { - i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? + i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; @@ -1055,7 +1056,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) continue; - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); tmp &= BXT_PIPE_SELECT_MASK; tmp >>= BXT_PIPE_SELECT_SHIFT; @@ -1251,7 +1252,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { bxt_dsi_get_pipe_config(encoder, pipe_config); pclk = bxt_dsi_get_pclk(encoder, pipe_config); } else { @@ -1317,7 +1318,7 @@ static void set_dsi_timings(struct drm_encoder *encoder, hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); for_each_dsi_port(port, intel_dsi->ports) { - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { /* * Program hdisplay and vdisplay on MIPI transcoder. * This is different from calculated hactive and @@ -1407,7 +1408,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, tmp &= ~READ_REQUEST_PRIORITY_MASK; intel_de_write(dev_priv, MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); - } else if (IS_GEN9_LP(dev_priv)) { + } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { enum pipe pipe = intel_crtc->pipe; tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); @@ -1445,7 +1446,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, if (intel_dsi->clock_stop) tmp |= CLOCKSTOP; - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { tmp |= BXT_DPHY_DEFEATURE_EN; if (!is_cmd_mode(intel_dsi)) tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; @@ -1492,7 +1493,8 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, intel_de_write(dev_priv, MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100)); - if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { + if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && + !intel_dsi->dual_link) { /* * BXT spec says write MIPI_INIT_COUNT for * both the ports, even if only one is @@ -1570,7 +1572,7 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder) /* Panel commands can be sent when clock is in LP11 */ intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_dsi_reset_clocks(encoder, port); else vlv_dsi_reset_clocks(encoder, port); @@ -1828,7 +1830,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) if (!intel_bios_is_dsi_present(dev_priv, &port)) return; - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) dev_priv->mipi_mmio_base = BXT_MIPI_BASE; else dev_priv->mipi_mmio_base = VLV_MIPI_BASE; @@ -1854,7 +1856,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) intel_encoder->compute_config = intel_dsi_compute_config; intel_encoder->pre_enable = intel_dsi_pre_enable; - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) intel_encoder->enable = bxt_dsi_enable; intel_encoder->disable = intel_dsi_disable; intel_encoder->post_disable = intel_dsi_post_disable; @@ -1874,7 +1876,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI * port C. BXT isn't limited like this. */ - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) intel_encoder->pipe_mask = ~0; else if (port == PORT_A) intel_encoder->pipe_mask = BIT(PIPE_A); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 7eefbdec25a2..9aff790817c0 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -194,7 +194,7 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) if (DISPLAY_VER(dev_priv) >= 11) hpd->hpd = hpd_gen11; - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) hpd->hpd = hpd_bxt; else if (DISPLAY_VER(dev_priv) >= 8) hpd->hpd = hpd_bdw; @@ -2458,7 +2458,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) found = true; } - if (IS_GEN9_LP(dev_priv)) { + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK; if (hotplug_trigger) { @@ -2474,7 +2474,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) } } - if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { + if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && + (iir & BXT_DE_PORT_GMBUS)) { gmbus_irq_handler(dev_priv); found = true; } @@ -3717,7 +3718,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) if (DISPLAY_VER(dev_priv) <= 10) de_misc_masked |= GEN8_DE_MISC_GSE; - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) de_port_masked |= BXT_DE_PORT_GMBUS; if (DISPLAY_VER(dev_priv) >= 11) { @@ -3732,7 +3733,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) gen8_de_pipe_flip_done_mask(dev_priv); de_port_enables = de_port_masked; - if (IS_GEN9_LP(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; else if (IS_BROADWELL(dev_priv)) de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK; @@ -4317,7 +4318,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup; else if (DISPLAY_VER(dev_priv) >= 11) dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup; - else if (IS_GEN9_LP(dev_priv)) + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 066abaa73a06..32f301ca3ab0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3654,13 +3654,13 @@ u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv) */ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv) { - return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv); + return IS_DISPLAY_VER(dev_priv, 9); } static bool intel_has_sagv(struct drm_i915_private *dev_priv) { - return (IS_GEN9_BC(dev_priv) || DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && + return DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv) && dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; } @@ -5258,7 +5258,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, lines = div_round_up_fixed16(selected_result, wp->plane_blocks_per_line); - if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) { + if (IS_DISPLAY_VER(dev_priv, 9)) { /* Display WA #1125: skl,bxt,kbl */ if (level == 0 && wp->rc_surface) blocks += fixed16_to_u32_round_up(wp->y_tile_minimum); @@ -5375,7 +5375,7 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv, * WaDisableTWM:skl,kbl,cfl,bxt * Transition WM are not recommended by HW team for GEN9 */ - if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) + if (IS_DISPLAY_VER(dev_priv, 9)) return; if (DISPLAY_VER(dev_priv) >= 11) -- cgit v1.2.3 From 9e2eb6d5380e9dadcd2baecb51f238e5eba94bee Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Thu, 18 Mar 2021 13:02:02 -0400 Subject: drm/i915/dpcd_bl: Don't try vesa interface unless specified by VBT Looks like that there actually are another subset of laptops on the market that don't support the Intel HDR backlight interface, but do advertise support for the VESA DPCD backlight interface despite the fact it doesn't seem to work. Note though I'm not entirely clear on this - on one of the machines where this issue was observed, I also noticed that we appeared to be rejecting the VBT defined backlight frequency in intel_dp_aux_vesa_calc_max_backlight(). It's noted in this function that: /* Use highest possible value of Pn for more granularity of brightness * adjustment while satifying the conditions below. * ... * - FxP is within 25% of desired value. * Note: 25% is arbitrary value and may need some tweak. */ So it's possible that this value might just need to be tweaked, but for now let's just disable the VESA backlight interface unless it's specified in the VBT just to be safe. We might be able to try enabling this again by default in the future. Fixes: 2227816e647a ("drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlight") Cc: Jani Nikula Cc: Rodrigo Vivi Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/3169 Signed-off-by: Lyude Paul Reviewed-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20210318170204.513000-1-lyude@redhat.com --- drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 651884390137..4f8337c7fd2e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -646,7 +646,6 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector) break; case INTEL_BACKLIGHT_DISPLAY_DDI: try_intel_interface = true; - try_vesa_interface = true; break; default: return -ENODEV; -- cgit v1.2.3 From f99b805fb9413ff007ca0b6add871737664117dd Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Sat, 27 Mar 2021 02:59:45 +0200 Subject: drm/i915: Don't zero out the Y plane's watermarks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Don't zero out the watermarks for the Y plane since we've already computed them when computing the UV plane's watermarks (since the UV plane always appears before ethe Y plane when iterating through the planes). This leads to allocating no DDB for the Y plane since .min_ddb_alloc also gets zeroed. And that of course leads to underruns when scanning out planar formats. Cc: stable@vger.kernel.org Cc: Stanislav Lisovskiy Fixes: dbf71381d733 ("drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code") Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20210327005945.4929-1-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 32f301ca3ab0..3ecbd62915cf 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5511,12 +5511,12 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; int ret; - memset(wm, 0, sizeof(*wm)); - /* Watermarks calculated in master */ if (plane_state->planar_slave) return 0; + memset(wm, 0, sizeof(*wm)); + if (plane_state->planar_linked_plane) { const struct drm_framebuffer *fb = plane_state->hw.fb; enum plane_id y_plane_id = plane_state->planar_linked_plane->id; -- cgit v1.2.3 From 2b5298b0aa09be3d789052107cb864603b88bc93 Mon Sep 17 00:00:00 2001 From: Caz Yokoyama Date: Wed, 24 Mar 2021 13:04:59 -0700 Subject: drm/i915/gen12: Add recommended hardware tuning value Follow Bspec 31870 to set recommended tuning values for certain GT register. These values aren't workarounds per-se, but it's best to handle them in the same general area of the driver, especially since there may be real workarounds that update other bits of the same registers. At the moment the only value we need to worry about is the TDS_TIMER setting in FF_MODE2. This setting was previously described as "Wa_1604555607" on some platforms, but the spec tells us that we should continue to program this on all current gen12 platforms, even those that do not have that WA. Bspec: 31870 v2: Rephrase some comments to make them clearer (Matt) Cc: Clinton Taylor Signed-off-by: Caz Yokoyama Signed-off-by: Lucas De Marchi Reviewed-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20210324200502.1731265-2-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++++++++++++++++++++++------- 1 file changed, 37 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2c6f7217469f..25785b46d1e4 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -607,9 +607,38 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); } +/* + * These settings aren't actually workarounds, but general tuning settings that + * need to be programmed on several platforms. + */ +static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + /* + * Although some platforms refer to it as Wa_1604555607, we need to + * program it even on those that don't explicitly list that + * workaround. + * + * Note that the programming of this register is further modified + * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. + * Wa_1608008084 tells us the FF_MODE2 register will return the wrong + * value when read. The default value for this register is zero for all + * fields and there are no bit masks. So instead of doing a RMW we + * should just write TDS timer value. For the same reason read + * verification is ignored. + */ + wa_add(wal, + FF_MODE2, + FF_MODE2_TDS_TIMER_MASK, + FF_MODE2_TDS_TIMER_128, + 0); +} + static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { + gen12_ctx_gt_tuning_init(engine, wal); + /* * Wa_1409142259:tgl * Wa_1409347922:tgl @@ -636,19 +665,15 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, gen12_ctx_workarounds_init(engine, wal); /* - * Wa_1604555607:tgl,rkl + * Wa_16011163337 * - * Note that the implementation of this workaround is further modified - * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. - * FF_MODE2 register will return the wrong value when read. The default - * value for this register is zero for all fields and there are no bit - * masks. So instead of doing a RMW we should just write the GS Timer - * and TDS timer values for Wa_1604555607 and Wa_16011163337. + * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due + * to Wa_1608008084. */ wa_add(wal, FF_MODE2, - FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, - FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, + FF_MODE2_GS_TIMER_MASK, + FF_MODE2_GS_TIMER_224, 0); } @@ -668,12 +693,13 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, /* * Wa_16011163337 * - * Like in tgl_ctx_workarounds_init(), read verification is ignored due + * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due * to Wa_1608008084. */ wa_add(wal, FF_MODE2, - FF_MODE2_GS_TIMER_MASK, FF_MODE2_GS_TIMER_224, 0); + FF_MODE2_GS_TIMER_MASK, + FF_MODE2_GS_TIMER_224, 0); } static void -- cgit v1.2.3 From 503c7ef3b47d7c4274e01d0703ef2d987284716b Mon Sep 17 00:00:00 2001 From: Caz Yokoyama Date: Wed, 24 Mar 2021 13:05:00 -0700 Subject: drm/i915/icl: add Wa_22010271021 for all gen11 Wa_22010271021 does not apply only to EHL, but to all gen11 and other gen12 platforms. Gen12 is already covered in another code path, but we need to stop checking for EHL when handling gen11. Bspec: 33450, 52887 v2: Remove "gen11" suffix as it also applies to gen12 platforms Cc: Clinton Taylor Signed-off-by: Caz Yokoyama Signed-off-by: Lucas De Marchi Reviewed-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20210324200502.1731265-3-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 25785b46d1e4..30b902fade1d 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1781,11 +1781,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN7_FF_THREAD_MODE, GEN12_FF_TESSELATION_DOP_GATE_DISABLE); - /* Wa_22010271021:ehl */ - if (IS_JSL_EHL(i915)) - wa_masked_en(wal, - GEN9_CS_DEBUG_MODE1, - FF_DOP_CLOCK_GATE_DISABLE); + /* Wa_22010271021 */ + wa_masked_en(wal, + GEN9_CS_DEBUG_MODE1, + FF_DOP_CLOCK_GATE_DISABLE); } if (IS_GEN_RANGE(i915, 9, 12)) { -- cgit v1.2.3 From 0a6b3d35c033b340f0bb1f6d3236ebdb953020ac Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Wed, 24 Mar 2021 13:05:01 -0700 Subject: drm/i915: Move Wa_16011163337 to gen12_ctx_workarounds_init() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This WA is needed in all gen12 platforms, moving it to gen12_ctx_workarounds_init() allow us to remove the duplicated implementation. Also allow us to remove the tgl_ctx_workarounds_init() that after the WA move above was empty. Signed-off-by: José Roberto de Souza Reviewed-by: Lucas De Marchi Signed-off-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20210324200502.1731265-4-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 -------------------- 1 file changed, 20 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 30b902fade1d..38a2813220b9 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -657,12 +657,6 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, wa_masked_field_set(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK, GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); -} - -static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, - struct i915_wa_list *wal) -{ - gen12_ctx_workarounds_init(engine, wal); /* * Wa_16011163337 @@ -689,17 +683,6 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_22010493298 */ wa_masked_en(wal, HIZ_CHICKEN, DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); - - /* - * Wa_16011163337 - * - * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due - * to Wa_1608008084. - */ - wa_add(wal, - FF_MODE2, - FF_MODE2_GS_TIMER_MASK, - FF_MODE2_GS_TIMER_224, 0); } static void @@ -716,9 +699,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, if (IS_DG1(i915)) dg1_ctx_workarounds_init(engine, wal); - else if (IS_ALDERLAKE_S(i915) || IS_ROCKETLAKE(i915) || - IS_TIGERLAKE(i915)) - tgl_ctx_workarounds_init(engine, wal); else if (IS_GEN(i915, 12)) gen12_ctx_workarounds_init(engine, wal); else if (IS_GEN(i915, 11)) -- cgit v1.2.3 From cade4696ff8dadf5521eba0d92abad20c20097e1 Mon Sep 17 00:00:00 2001 From: Swathi Dhanavanthri Date: Wed, 24 Mar 2021 13:05:02 -0700 Subject: drm/i915: Add Wa_14011060649 This is a permanent workaround for TGL,RKL,DG1 and ADLS. Signed-off-by: Swathi Dhanavanthri Reviewed-by: Lucas De Marchi Signed-off-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20210324200502.1731265-5-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 29 insertions(+) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 38a2813220b9..5a03a76bb9e2 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1084,11 +1084,37 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); } +/* + * Though there are per-engine instances of these registers, + * they retain their value through engine resets and should + * only be provided on the GT workaround list rather than + * the engine-specific workaround list. + */ +static void +wa_14011060649(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + struct intel_engine_cs *engine; + struct intel_gt *gt = &i915->gt; + int id; + + for_each_engine(engine, gt, id) { + if (engine->class != VIDEO_DECODE_CLASS || + (engine->instance % 2)) + continue; + + wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), + IECPUNIT_CLKGATE_DIS); + } +} + static void gen12_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { wa_init_mcr(i915, wal); + + /* Wa_14011060649:tgl,rkl,dg1,adls */ + wa_14011060649(i915, wal); } static void diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cbf7a60afe54..e087bcd21911 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2715,6 +2715,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ +#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10) +#define IECPUNIT_CLKGATE_DIS REG_BIT(22) + #define ERROR_GEN6 _MMIO(0x40a0) #define GEN7_ERR_INT _MMIO(0x44040) #define ERR_INT_POISON (1 << 31) -- cgit v1.2.3 From 28972f821ea773edaae2d40444bd08a33c9a46a5 Mon Sep 17 00:00:00 2001 From: Anshuman Gupta Date: Thu, 8 Apr 2021 13:56:42 +0530 Subject: drm/i915/hdcp: Fix uninitialized symbol 'msg_end' Fix static analysis tool uninitialized symbol error. v2: - use ktime_set(0, 0) instead to initialize to zero. [Ankit] Reported-by: kernel test robot Reported-by: Dan Carpenter Signed-off-by: Anshuman Gupta Reviewed-by: Ankit Nautiyal Link: https://patchwork.freedesktop.org/patch/msgid/20210408082642.27066-1-anshuman.gupta@intel.com --- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index 90868e156c69..2dd9360bdf9a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -532,7 +532,7 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port, u8 *byte = buf; ssize_t ret, bytes_to_recv, len; const struct hdcp2_dp_msg_data *hdcp2_msg_data; - ktime_t msg_end; + ktime_t msg_end = ktime_set(0, 0); bool msg_expired; hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); -- cgit v1.2.3 From d4e6823609442953f272dd25507b82b9a3f76ee5 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 15 Feb 2021 16:17:26 +0100 Subject: drm/ttm: make global mutex and use count static MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only needed during device hot plug and remove and not exported. Signed-off-by: Christian König Suggested-by: Bernard Acked-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20210409110730.2958-1-christian.koenig@amd.com --- drivers/gpu/drm/ttm/ttm_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index 9b787b3caeb5..1f2024164d72 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -39,8 +39,8 @@ /** * ttm_global_mutex - protecting the global state */ -DEFINE_MUTEX(ttm_global_mutex); -unsigned ttm_glob_use_count; +static DEFINE_MUTEX(ttm_global_mutex); +static unsigned ttm_glob_use_count; struct ttm_global ttm_glob; EXPORT_SYMBOL(ttm_glob); -- cgit v1.2.3 From f7c379779161d364eb30338529490eac7dc377b7 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Fri, 26 Mar 2021 10:57:59 +0000 Subject: drm/i915: Take request reference before arming the watchdog timer Reference needs to be taken before arming the timer. Luckily, given the default timer period of 20s, the potential to hit the race is extremely unlikely. Signed-off-by: Tvrtko Ursulin Fixes: 9b4d0598ee94 ("drm/i915: Request watchdog infrastructure") Cc: Daniel Vetter Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20210326105759.2387104-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_request.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 9165971c3c47..bec9c3652188 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -350,6 +350,8 @@ static void __rq_arm_watchdog(struct i915_request *rq) if (!ce->watchdog.timeout_us) return; + i915_request_get(rq); + hrtimer_init(&wdg->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); wdg->timer.function = __rq_watchdog_expired; hrtimer_start_range_ns(&wdg->timer, @@ -357,7 +359,6 @@ static void __rq_arm_watchdog(struct i915_request *rq) NSEC_PER_USEC), NSEC_PER_MSEC, HRTIMER_MODE_REL); - i915_request_get(rq); } static void __rq_cancel_watchdog(struct i915_request *rq) -- cgit v1.2.3 From 399cd9797052f5732f7e1db89d15a05bca712be1 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Wed, 31 Mar 2021 11:18:50 +0100 Subject: drm/i915/pmu: Check actual RC6 status RC6 support cannot be simply established by looking at the static device HAS_RC6() flag. There are cases which disable RC6 at driver load time so use the status of those check when deciding whether to enumerate the rc6 counter. Signed-off-by: Tvrtko Ursulin Reported-by: Eero T Tamminen Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20210331101850.2582027-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_pmu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 41651ac255fa..a75cd1db320b 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -476,6 +476,8 @@ engine_event_status(struct intel_engine_cs *engine, static int config_status(struct drm_i915_private *i915, u64 config) { + struct intel_gt *gt = &i915->gt; + switch (config) { case I915_PMU_ACTUAL_FREQUENCY: if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) @@ -489,7 +491,7 @@ config_status(struct drm_i915_private *i915, u64 config) case I915_PMU_INTERRUPTS: break; case I915_PMU_RC6_RESIDENCY: - if (!HAS_RC6(i915)) + if (!gt->rc6.supported) return -ENODEV; break; case I915_PMU_SOFTWARE_GT_AWAKE_TIME: -- cgit v1.2.3 From a844cfbe648d15d9f1031c45508c194f2d61c917 Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Thu, 8 Apr 2021 13:31:48 -0700 Subject: drm/i915: Skip display interruption setup when display is not available MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Return ealier in the functions doing interruption setup for GEN8+ also adding a warning in gen8_de_irq_handler() to let us know that something else is still missing. Reviewed-by: Radhakrishna Sripada Cc: Ville Syrjälä Cc: Lucas De Marchi Signed-off-by: José Roberto de Souza Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20210408203150.237947-1-jose.souza@intel.com --- drivers/gpu/drm/i915/i915_irq.c | 39 ++++++++++++++++++++++++++++++++------- 1 file changed, 32 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 9aff790817c0..920327bdcb10 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2421,6 +2421,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) u32 iir; enum pipe pipe; + drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); + if (master_ctl & GEN8_DE_MISC_IRQ) { iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR); if (iir) { @@ -3059,14 +3061,13 @@ static void cnp_display_clock_wa(struct drm_i915_private *dev_priv) } } -static void gen8_irq_reset(struct drm_i915_private *dev_priv) +static void gen8_display_irq_reset(struct drm_i915_private *dev_priv) { struct intel_uncore *uncore = &dev_priv->uncore; enum pipe pipe; - gen8_master_intr_disable(dev_priv->uncore.regs); - - gen8_gt_irq_reset(&dev_priv->gt); + if (!HAS_DISPLAY(dev_priv)) + return; intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); @@ -3078,6 +3079,16 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv) GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); +} + +static void gen8_irq_reset(struct drm_i915_private *dev_priv) +{ + struct intel_uncore *uncore = &dev_priv->uncore; + + gen8_master_intr_disable(dev_priv->uncore.regs); + + gen8_gt_irq_reset(&dev_priv->gt); + gen8_display_irq_reset(dev_priv); GEN3_IRQ_RESET(uncore, GEN8_PCU_); if (HAS_PCH_SPLIT(dev_priv)) @@ -3093,6 +3104,9 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_D); + if (!HAS_DISPLAY(dev_priv)) + return; + intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0); if (DISPLAY_VER(dev_priv) >= 12) { @@ -3715,6 +3729,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) BIT(TRANSCODER_C) | BIT(TRANSCODER_D); enum pipe pipe; + if (!HAS_DISPLAY(dev_priv)) + return; + if (DISPLAY_VER(dev_priv) <= 10) de_misc_masked |= GEN8_DE_MISC_GSE; @@ -3798,6 +3815,16 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) gen8_master_intr_enable(dev_priv->uncore.regs); } +static void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv) +{ + if (!HAS_DISPLAY(dev_priv)) + return; + + gen8_de_irq_postinstall(dev_priv); + + intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, + GEN11_DISPLAY_IRQ_ENABLE); +} static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) { @@ -3808,12 +3835,10 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) icp_irq_postinstall(dev_priv); gen11_gt_irq_postinstall(&dev_priv->gt); - gen8_de_irq_postinstall(dev_priv); + gen11_de_irq_postinstall(dev_priv); GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); - intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); - if (HAS_MASTER_UNIT_IRQ(dev_priv)) { dg1_master_intr_enable(uncore->regs); intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_UNIT_INTR); -- cgit v1.2.3 From 61a60d7962a6e8ed94ece62764f94368cd6082b2 Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Thu, 8 Apr 2021 13:31:49 -0700 Subject: drm/i915: Do not set any power wells when there is no display MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Power wells are only part of display block and not necessary when running a headless driver. Reviewed-by: Radhakrishna Sripada Cc: Lucas De Marchi Signed-off-by: José Roberto de Souza Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20210408203150.237947-2-jose.souza@intel.com --- drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 9419ae8c6111..53311b9764dc 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4674,7 +4674,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) * The enabling order will be from lower to higher indexed wells, * the disabling order is reversed. */ - if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { + if (!HAS_DISPLAY(dev_priv)) { + power_domains->power_well_count = 0; + err = 0; + } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { err = set_power_wells_mask(power_domains, tgl_power_wells, BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); } else if (IS_ROCKETLAKE(dev_priv)) { -- cgit v1.2.3 From 5df7bd130818dfdc9047c2a81b19737d66e55f9a Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Thu, 8 Apr 2021 13:31:50 -0700 Subject: drm/i915: skip display initialization when there is no display MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Display features should not be initialized or de-initialized when there is no display. Skip modeset initialization, output setup, plane, crtc, encoder, connector registration, display cdclk and rawclk initialization, display core initialization, etc. Skip the functionality at as high level as possible, and remove any redundant checks. If the functionality is conditional to *other* display checks, do not add more. If the un-initialization has checks for initialization, do not add more. We explicitly do not care about any GMCH/VLV/CHV code paths, as they've always had and will have display. Reviewed-by: Radhakrishna Sripada Cc: Lucas De Marchi Signed-off-by: José Roberto de Souza Signed-off-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20210408203150.237947-3-jose.souza@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 44 +++++++++++++++++----- drivers/gpu/drm/i915/display/intel_display_power.c | 36 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.c | 6 +++ drivers/gpu/drm/i915/display/intel_gmbus.c | 3 -- drivers/gpu/drm/i915/display/intel_hotplug.c | 12 ++++++ drivers/gpu/drm/i915/display/intel_pps.c | 5 ++- drivers/gpu/drm/i915/i915_drv.c | 28 ++++++++++---- drivers/gpu/drm/i915/i915_suspend.c | 6 +++ 8 files changed, 120 insertions(+), 20 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4f8f994a639f..411b46c012f8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1335,6 +1335,9 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, struct intel_crtc *crtc; struct intel_plane *plane; + if (!HAS_DISPLAY(dev_priv)) + return 0; + /* * We assume the primary plane for pipe A has * the highest stride limits of them all, @@ -3838,6 +3841,9 @@ int intel_display_suspend(struct drm_device *dev) struct drm_atomic_state *state; int ret; + if (!HAS_DISPLAY(dev_priv)) + return 0; + state = drm_atomic_helper_suspend(dev); ret = PTR_ERR_OR_ZERO(state); if (ret) @@ -11429,6 +11435,9 @@ static const struct drm_mode_config_funcs intel_mode_funcs = { */ void intel_init_display_hooks(struct drm_i915_private *dev_priv) { + if (!HAS_DISPLAY(dev_priv)) + return; + intel_init_cdclk_hooks(dev_priv); intel_init_audio_hooks(dev_priv); @@ -11471,8 +11480,12 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) void intel_modeset_init_hw(struct drm_i915_private *i915) { - struct intel_cdclk_state *cdclk_state = - to_intel_cdclk_state(i915->cdclk.obj.state); + struct intel_cdclk_state *cdclk_state; + + if (!HAS_DISPLAY(i915)) + return; + + cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); intel_update_cdclk(i915); intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK"); @@ -11788,6 +11801,9 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915) /* FIXME: completely on the wrong abstraction layer */ intel_power_domains_init_hw(i915, false); + if (!HAS_DISPLAY(i915)) + return 0; + intel_csr_ucode_init(i915); i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); @@ -11838,6 +11854,9 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915) struct intel_crtc *crtc; int ret; + if (!HAS_DISPLAY(i915)) + return 0; + intel_init_pm(i915); intel_panel_sanitize_ssc(i915); @@ -11850,13 +11869,11 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915) INTEL_NUM_PIPES(i915), INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); - if (HAS_DISPLAY(i915)) { - for_each_pipe(i915, pipe) { - ret = intel_crtc_init(i915, pipe); - if (ret) { - intel_mode_config_cleanup(i915); - return ret; - } + for_each_pipe(i915, pipe) { + ret = intel_crtc_init(i915, pipe); + if (ret) { + intel_mode_config_cleanup(i915); + return ret; } } @@ -12791,6 +12808,9 @@ void intel_display_resume(struct drm_device *dev) struct drm_modeset_acquire_ctx ctx; int ret; + if (!HAS_DISPLAY(dev_priv)) + return; + dev_priv->modeset_restore_state = NULL; if (state) state->acquire_ctx = &ctx; @@ -12840,6 +12860,9 @@ static void intel_hpd_poll_fini(struct drm_i915_private *i915) /* part #1: call before irq uninstall */ void intel_modeset_driver_remove(struct drm_i915_private *i915) { + if (!HAS_DISPLAY(i915)) + return; + flush_workqueue(i915->flip_wq); flush_workqueue(i915->modeset_wq); @@ -12850,6 +12873,9 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915) /* part #2: call after irq uninstall */ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) { + if (!HAS_DISPLAY(i915)) + return; + /* * Due to the hpd irq storm handling the hotplug work can re-arm the * poll handlers. Hence disable polling after hpd handling is shut down. diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 53311b9764dc..ad30947c58a3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -821,6 +821,9 @@ static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) { u32 val; + if (!HAS_DISPLAY(dev_priv)) + return; + val = intel_de_read(dev_priv, DC_STATE_EN) & gen9_dc_mask(dev_priv); drm_dbg_kms(&dev_priv->drm, @@ -857,6 +860,9 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) u32 val; u32 mask; + if (!HAS_DISPLAY(dev_priv)) + return; + if (drm_WARN_ON_ONCE(&dev_priv->drm, state & ~dev_priv->csr.allowed_dc_mask)) state &= dev_priv->csr.allowed_dc_mask; @@ -1181,6 +1187,9 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + if (!HAS_DISPLAY(dev_priv)) + return; + dev_priv->display.get_cdclk(dev_priv, &cdclk_config); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ drm_WARN_ON(&dev_priv->drm, @@ -4533,6 +4542,9 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, int requested_dc; int max_dc; + if (!HAS_DISPLAY(dev_priv)) + return 0; + if (IS_DG1(dev_priv)) max_dc = 3; else if (DISPLAY_VER(dev_priv) >= 12) @@ -5126,6 +5138,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, /* enable PCH reset handshake */ intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); + if (!HAS_DISPLAY(dev_priv)) + return; + /* enable PG1 and Misc I/O */ mutex_lock(&power_domains->lock); @@ -5150,6 +5165,9 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) struct i915_power_domains *power_domains = &dev_priv->power_domains; struct i915_power_well *well; + if (!HAS_DISPLAY(dev_priv)) + return; + gen9_disable_dc_states(dev_priv); gen9_dbuf_disable(dev_priv); @@ -5190,6 +5208,9 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume */ intel_pch_reset_handshake(dev_priv, false); + if (!HAS_DISPLAY(dev_priv)) + return; + /* Enable PG1 */ mutex_lock(&power_domains->lock); @@ -5211,6 +5232,9 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) struct i915_power_domains *power_domains = &dev_priv->power_domains; struct i915_power_well *well; + if (!HAS_DISPLAY(dev_priv)) + return; + gen9_disable_dc_states(dev_priv); gen9_dbuf_disable(dev_priv); @@ -5244,6 +5268,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume /* 1. Enable PCH Reset Handshake */ intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); + if (!HAS_DISPLAY(dev_priv)) + return; + /* 2-3. */ intel_combo_phy_init(dev_priv); @@ -5271,6 +5298,9 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) struct i915_power_domains *power_domains = &dev_priv->power_domains; struct i915_power_well *well; + if (!HAS_DISPLAY(dev_priv)) + return; + gen9_disable_dc_states(dev_priv); /* 1. Disable all display engine functions -> aready done */ @@ -5385,6 +5415,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, /* 1. Enable PCH reset handshake. */ intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); + if (!HAS_DISPLAY(dev_priv)) + return; + /* 2. Initialize all combo phys */ intel_combo_phy_init(dev_priv); @@ -5429,6 +5462,9 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) struct i915_power_domains *power_domains = &dev_priv->power_domains; struct i915_power_well *well; + if (!HAS_DISPLAY(dev_priv)) + return; + gen9_disable_dc_states(dev_priv); /* 1. Disable all display engine functions -> aready done */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a5231ac3443a..6750949aa261 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5430,6 +5430,9 @@ void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; + if (!HAS_DISPLAY(dev_priv)) + return; + for_each_intel_encoder(&dev_priv->drm, encoder) { struct intel_dp *intel_dp; @@ -5450,6 +5453,9 @@ void intel_dp_mst_resume(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; + if (!HAS_DISPLAY(dev_priv)) + return; + for_each_intel_encoder(&dev_priv->drm, encoder) { struct intel_dp *intel_dp; int ret; diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index 13ba280d0228..2ea6adc3bd3e 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -845,9 +845,6 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv) unsigned int pin; int ret; - if (!HAS_DISPLAY(dev_priv)) - return 0; - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; else if (!HAS_GMCH(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index f46a1b7190b8..47c85ac97c87 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -595,6 +595,9 @@ void intel_hpd_init(struct drm_i915_private *dev_priv) { int i; + if (!HAS_DISPLAY(dev_priv)) + return; + for_each_hpd_pin(i) { dev_priv->hotplug.stats[i].count = 0; dev_priv->hotplug.stats[i].state = HPD_ENABLED; @@ -670,6 +673,9 @@ static void i915_hpd_poll_init_work(struct work_struct *work) */ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv) { + if (!HAS_DISPLAY(dev_priv)) + return; + WRITE_ONCE(dev_priv->hotplug.poll_enabled, true); /* @@ -702,6 +708,9 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv) */ void intel_hpd_poll_disable(struct drm_i915_private *dev_priv) { + if (!HAS_DISPLAY(dev_priv)) + return; + WRITE_ONCE(dev_priv->hotplug.poll_enabled, false); schedule_work(&dev_priv->hotplug.poll_init_work); } @@ -718,6 +727,9 @@ void intel_hpd_init_work(struct drm_i915_private *dev_priv) void intel_hpd_cancel_work(struct drm_i915_private *dev_priv) { + if (!HAS_DISPLAY(dev_priv)) + return; + spin_lock_irq(&dev_priv->irq_lock); dev_priv->hotplug.long_port_mask = 0; diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 3a0985f1f531..0fd28902d779 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -316,6 +316,9 @@ void intel_pps_reset_all(struct drm_i915_private *dev_priv) if (drm_WARN_ON(&dev_priv->drm, !IS_LP(dev_priv))) return; + if (!HAS_DISPLAY(dev_priv)) + return; + /* * We can't grab pps_mutex here due to deadlock with power_domain * mutex when power_domain functions are called while holding pps_mutex. @@ -1376,7 +1379,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) int pps_num; int pps_idx; - if (HAS_DDI(dev_priv)) + if (!HAS_DISPLAY(dev_priv) || HAS_DDI(dev_priv)) return; /* * This w/a is needed at least on CPT/PPT, but to be sure apply it diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 2483447ff8dc..305557e1942a 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -973,8 +973,12 @@ static int i915_driver_open(struct drm_device *dev, struct drm_file *file) */ static void i915_driver_lastclose(struct drm_device *dev) { + struct drm_i915_private *i915 = to_i915(dev); + intel_fbdev_restore_mode(dev); - vga_switcheroo_process_delayed_switch(); + + if (HAS_DISPLAY(i915)) + vga_switcheroo_process_delayed_switch(); } static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) @@ -994,6 +998,9 @@ static void intel_suspend_encoders(struct drm_i915_private *dev_priv) struct drm_device *dev = &dev_priv->drm; struct intel_encoder *encoder; + if (!HAS_DISPLAY(dev_priv)) + return; + drm_modeset_lock_all(dev); for_each_intel_encoder(dev, encoder) if (encoder->suspend) @@ -1006,6 +1013,9 @@ static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) struct drm_device *dev = &dev_priv->drm; struct intel_encoder *encoder; + if (!HAS_DISPLAY(dev_priv)) + return; + drm_modeset_lock_all(dev); for_each_intel_encoder(dev, encoder) if (encoder->shutdown) @@ -1021,9 +1031,11 @@ void i915_driver_shutdown(struct drm_i915_private *i915) i915_gem_suspend(i915); - drm_kms_helper_poll_disable(&i915->drm); + if (HAS_DISPLAY(i915)) { + drm_kms_helper_poll_disable(&i915->drm); - drm_atomic_helper_shutdown(&i915->drm); + drm_atomic_helper_shutdown(&i915->drm); + } intel_dp_mst_suspend(i915); @@ -1087,8 +1099,8 @@ static int i915_drm_suspend(struct drm_device *dev) /* We do a lot of poking in a lot of registers, make sure they work * properly. */ intel_power_domains_disable(dev_priv); - - drm_kms_helper_poll_disable(dev); + if (HAS_DISPLAY(dev_priv)) + drm_kms_helper_poll_disable(dev); pci_save_state(pdev); @@ -1235,7 +1247,8 @@ static int i915_drm_resume(struct drm_device *dev) */ intel_runtime_pm_enable_interrupts(dev_priv); - drm_mode_config_reset(dev); + if (HAS_DISPLAY(dev_priv)) + drm_mode_config_reset(dev); i915_gem_resume(dev_priv); @@ -1248,7 +1261,8 @@ static int i915_drm_resume(struct drm_device *dev) intel_display_resume(dev); intel_hpd_poll_disable(dev_priv); - drm_kms_helper_poll_enable(dev); + if (HAS_DISPLAY(dev_priv)) + drm_kms_helper_poll_enable(dev); intel_opregion_resume(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 0bc7b49f843c..5fcc32821e18 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -87,6 +87,9 @@ void i915_save_display(struct drm_i915_private *dev_priv) { struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + if (!HAS_DISPLAY(dev_priv)) + return; + /* Display arbitration control */ if (INTEL_GEN(dev_priv) <= 4) dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB); @@ -102,6 +105,9 @@ void i915_restore_display(struct drm_i915_private *dev_priv) { struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + if (!HAS_DISPLAY(dev_priv)) + return; + intel_restore_swf(dev_priv); if (IS_GEN(dev_priv, 4)) -- cgit v1.2.3 From 8f2546dd3e3e29d3a13e28746ba75cee2b3c850d Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Thu, 8 Apr 2021 14:42:05 -0700 Subject: drm/i915/display: Defeature PSR2 for RKL and ADL-S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PSR2 is defeatured for RKL and ADL-S, no important power impact as those are desktop CPUs and PSR2 was not even enabled by default yet in platforms without PSR2 HW tracking. HSDES: 14011750631 HSDES: 14011741325 BSpec: 53273 Cc: Caz Yokoyama Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20210408214205.327704-1-jose.souza@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 32d3d56259c2..2627d0b558f3 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -739,6 +739,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } + /* Wa_16011181250 */ + if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv)) { + drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); + return false; + } + if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { drm_dbg_kms(&dev_priv->drm, "PSR2 not supported in transcoder %s\n", -- cgit v1.2.3 From 5690e4863930801a17ef67d279bc5306f2cf6efb Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 8 Apr 2021 16:01:36 +0200 Subject: drm/gem-ttm-helper: Provide helper for struct drm_driver.dumb_map_offset Provides an implementation of struct drm_driver.dumb_map_offset that can be used by TTM-based GEM drivers. Signed-off-by: Thomas Zimmermann Acked-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20210408140139.27731-2-tzimmermann@suse.de --- drivers/gpu/drm/drm_gem_ttm_helper.c | 33 +++++++++++++++++++++++++++++++++ include/drm/drm_gem_ttm_helper.h | 5 ++++- 2 files changed, 37 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/drm_gem_ttm_helper.c b/drivers/gpu/drm/drm_gem_ttm_helper.c index de28720757af..b14bed8be771 100644 --- a/drivers/gpu/drm/drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/drm_gem_ttm_helper.c @@ -114,5 +114,38 @@ int drm_gem_ttm_mmap(struct drm_gem_object *gem, } EXPORT_SYMBOL(drm_gem_ttm_mmap); +/** + * drm_gem_ttm_dumb_map_offset() - Implements struct &drm_driver.dumb_map_offset + * @file: DRM file pointer. + * @dev: DRM device. + * @handle: GEM handle + * @offset: Returns the mapping's memory offset on success + * + * Provides an implementation of struct &drm_driver.dumb_map_offset for + * TTM-based GEM drivers. TTM allocates the offset internally and + * drm_gem_ttm_dumb_map_offset() returns it for dumb-buffer implementations. + * + * See struct &drm_driver.dumb_map_offset. + * + * Returns: + * 0 on success, or a negative errno code otherwise. + */ +int drm_gem_ttm_dumb_map_offset(struct drm_file *file, struct drm_device *dev, + uint32_t handle, uint64_t *offset) +{ + struct drm_gem_object *gem; + + gem = drm_gem_object_lookup(file, handle); + if (!gem) + return -ENOENT; + + *offset = drm_vma_node_offset_addr(&gem->vma_node); + + drm_gem_object_put(gem); + + return 0; +} +EXPORT_SYMBOL(drm_gem_ttm_dumb_map_offset); + MODULE_DESCRIPTION("DRM gem ttm helpers"); MODULE_LICENSE("GPL"); diff --git a/include/drm/drm_gem_ttm_helper.h b/include/drm/drm_gem_ttm_helper.h index 7c6d874910b8..c1aa02bd4c89 100644 --- a/include/drm/drm_gem_ttm_helper.h +++ b/include/drm/drm_gem_ttm_helper.h @@ -5,8 +5,8 @@ #include -#include #include +#include #include #include @@ -24,4 +24,7 @@ void drm_gem_ttm_vunmap(struct drm_gem_object *gem, int drm_gem_ttm_mmap(struct drm_gem_object *gem, struct vm_area_struct *vma); +int drm_gem_ttm_dumb_map_offset(struct drm_file *file, struct drm_device *dev, + uint32_t handle, uint64_t *offset); + #endif -- cgit v1.2.3 From ede0c69ceb3fa4e139ffd95083c2698880c25b6f Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 8 Apr 2021 16:01:37 +0200 Subject: drm/vram-helper: Use drm_gem_ttm_dumb_map_offset() VRAM helpers now use drm_gem_ttm_dumb_map_offset() to implement struct drm_driver.dumb_map_offset. v2: * update hibmc as well (kernel test robot) Signed-off-by: Thomas Zimmermann Acked-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20210408140139.27731-3-tzimmermann@suse.de --- drivers/gpu/drm/drm_gem_vram_helper.c | 48 ------------------------- drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 2 +- include/drm/drm_gem_vram_helper.h | 7 ++-- 3 files changed, 3 insertions(+), 54 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c index 2b7c3a07956d..797200315854 100644 --- a/drivers/gpu/drm/drm_gem_vram_helper.c +++ b/drivers/gpu/drm/drm_gem_vram_helper.c @@ -245,22 +245,6 @@ void drm_gem_vram_put(struct drm_gem_vram_object *gbo) } EXPORT_SYMBOL(drm_gem_vram_put); -/** - * drm_gem_vram_mmap_offset() - Returns a GEM VRAM object's mmap offset - * @gbo: the GEM VRAM object - * - * See drm_vma_node_offset_addr() for more information. - * - * Returns: - * The buffer object's offset for userspace mappings on success, or - * 0 if no offset is allocated. - */ -u64 drm_gem_vram_mmap_offset(struct drm_gem_vram_object *gbo) -{ - return drm_vma_node_offset_addr(&gbo->bo.base.vma_node); -} -EXPORT_SYMBOL(drm_gem_vram_mmap_offset); - static u64 drm_gem_vram_pg_offset(struct drm_gem_vram_object *gbo) { /* Keep TTM behavior for now, remove when drivers are audited */ @@ -638,38 +622,6 @@ int drm_gem_vram_driver_dumb_create(struct drm_file *file, } EXPORT_SYMBOL(drm_gem_vram_driver_dumb_create); -/** - * drm_gem_vram_driver_dumb_mmap_offset() - \ - Implements &struct drm_driver.dumb_mmap_offset - * @file: DRM file pointer. - * @dev: DRM device. - * @handle: GEM handle - * @offset: Returns the mapping's memory offset on success - * - * Returns: - * 0 on success, or - * a negative errno code otherwise. - */ -int drm_gem_vram_driver_dumb_mmap_offset(struct drm_file *file, - struct drm_device *dev, - uint32_t handle, uint64_t *offset) -{ - struct drm_gem_object *gem; - struct drm_gem_vram_object *gbo; - - gem = drm_gem_object_lookup(file, handle); - if (!gem) - return -ENOENT; - - gbo = drm_gem_vram_of_gem(gem); - *offset = drm_gem_vram_mmap_offset(gbo); - - drm_gem_object_put(gem); - - return 0; -} -EXPORT_SYMBOL(drm_gem_vram_driver_dumb_mmap_offset); - /* * Helpers for struct drm_plane_helper_funcs */ diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c index abd6250d5a14..89edc796deda 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -60,7 +60,7 @@ static const struct drm_driver hibmc_driver = { .minor = 0, .debugfs_init = drm_vram_mm_debugfs_init, .dumb_create = hibmc_dumb_create, - .dumb_map_offset = drm_gem_vram_driver_dumb_mmap_offset, + .dumb_map_offset = drm_gem_ttm_dumb_map_offset, .gem_prime_mmap = drm_gem_prime_mmap, .irq_handler = hibmc_drm_interrupt, }; diff --git a/include/drm/drm_gem_vram_helper.h b/include/drm/drm_gem_vram_helper.h index 288055d397d9..27ed7e9243b9 100644 --- a/include/drm/drm_gem_vram_helper.h +++ b/include/drm/drm_gem_vram_helper.h @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -93,7 +94,6 @@ struct drm_gem_vram_object *drm_gem_vram_create(struct drm_device *dev, size_t size, unsigned long pg_align); void drm_gem_vram_put(struct drm_gem_vram_object *gbo); -u64 drm_gem_vram_mmap_offset(struct drm_gem_vram_object *gbo); s64 drm_gem_vram_offset(struct drm_gem_vram_object *gbo); int drm_gem_vram_pin(struct drm_gem_vram_object *gbo, unsigned long pl_flag); int drm_gem_vram_unpin(struct drm_gem_vram_object *gbo); @@ -113,9 +113,6 @@ int drm_gem_vram_fill_create_dumb(struct drm_file *file, int drm_gem_vram_driver_dumb_create(struct drm_file *file, struct drm_device *dev, struct drm_mode_create_dumb *args); -int drm_gem_vram_driver_dumb_mmap_offset(struct drm_file *file, - struct drm_device *dev, - uint32_t handle, uint64_t *offset); /* * Helpers for struct drm_plane_helper_funcs @@ -149,7 +146,7 @@ void drm_gem_vram_simple_display_pipe_cleanup_fb( #define DRM_GEM_VRAM_DRIVER \ .debugfs_init = drm_vram_mm_debugfs_init, \ .dumb_create = drm_gem_vram_driver_dumb_create, \ - .dumb_map_offset = drm_gem_vram_driver_dumb_mmap_offset, \ + .dumb_map_offset = drm_gem_ttm_dumb_map_offset, \ .gem_prime_mmap = drm_gem_prime_mmap /* -- cgit v1.2.3 From 4c398f50a1fbc94d0c3615f284244dbb19e06add Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 8 Apr 2021 16:01:38 +0200 Subject: drm/nouveau: Use drm_gem_ttm_dumb_map_offset() Nouveau now uses drm_gem_ttm_dumb_map_offset() to implement struct drm_driver.dumb_map_offset. Signed-off-by: Thomas Zimmermann Acked-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20210408140139.27731-4-tzimmermann@suse.de --- drivers/gpu/drm/nouveau/nouveau_display.c | 18 ------------------ drivers/gpu/drm/nouveau/nouveau_display.h | 2 -- drivers/gpu/drm/nouveau/nouveau_drm.c | 3 ++- 3 files changed, 2 insertions(+), 21 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index dac02c7be54d..14101bd2a0ff 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -838,21 +838,3 @@ nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev, drm_gem_object_put(&bo->bo.base); return ret; } - -int -nouveau_display_dumb_map_offset(struct drm_file *file_priv, - struct drm_device *dev, - uint32_t handle, uint64_t *poffset) -{ - struct drm_gem_object *gem; - - gem = drm_gem_object_lookup(file_priv, handle); - if (gem) { - struct nouveau_bo *bo = nouveau_gem_object(gem); - *poffset = drm_vma_node_offset_addr(&bo->bo.base.vma_node); - drm_gem_object_put(gem); - return 0; - } - - return -ENOENT; -} diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h index 616c43427059..2ab2ddb1eadf 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.h +++ b/drivers/gpu/drm/nouveau/nouveau_display.h @@ -58,8 +58,6 @@ bool nouveau_display_scanoutpos(struct drm_crtc *crtc, int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, struct drm_mode_create_dumb *args); -int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, - u32 handle, u64 *offset); void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 885815ea917f..9766218a99ca 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -31,6 +31,7 @@ #include #include +#include #include #include @@ -1212,7 +1213,7 @@ driver_stub = { .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, .dumb_create = nouveau_display_dumb_create, - .dumb_map_offset = nouveau_display_dumb_map_offset, + .dumb_map_offset = drm_gem_ttm_dumb_map_offset, .name = DRIVER_NAME, .desc = DRIVER_DESC, -- cgit v1.2.3 From f4268a4bf1eecb4b38353f6310e561502e04f4dd Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 8 Apr 2021 16:01:39 +0200 Subject: drm/qxl: Use drm_gem_ttm_dumb_map_offset() Qxl now uses drm_gem_ttm_dumb_map_offset() to implement struct drm_driver.dumb_map_offset. Signed-off-by: Thomas Zimmermann Acked-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20210408140139.27731-5-tzimmermann@suse.de --- drivers/gpu/drm/qxl/qxl_drv.c | 3 ++- drivers/gpu/drm/qxl/qxl_drv.h | 3 --- drivers/gpu/drm/qxl/qxl_dumb.c | 17 ----------------- drivers/gpu/drm/qxl/qxl_ioctl.c | 4 ++-- drivers/gpu/drm/qxl/qxl_object.h | 5 ----- 5 files changed, 4 insertions(+), 28 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c index 1864467f1063..db92eec07d96 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.c +++ b/drivers/gpu/drm/qxl/qxl_drv.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -271,7 +272,7 @@ static struct drm_driver qxl_driver = { .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, .dumb_create = qxl_mode_dumb_create, - .dumb_map_offset = qxl_mode_dumb_mmap, + .dumb_map_offset = drm_gem_ttm_dumb_map_offset, #if defined(CONFIG_DEBUG_FS) .debugfs_init = qxl_debugfs_init, #endif diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h index 6dd57cfb2e7c..20a0f3ab84ad 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.h +++ b/drivers/gpu/drm/qxl/qxl_drv.h @@ -330,9 +330,6 @@ void qxl_bo_force_delete(struct qxl_device *qdev); int qxl_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, struct drm_mode_create_dumb *args); -int qxl_mode_dumb_mmap(struct drm_file *filp, - struct drm_device *dev, - uint32_t handle, uint64_t *offset_p); /* qxl ttm */ int qxl_ttm_init(struct qxl_device *qdev); diff --git a/drivers/gpu/drm/qxl/qxl_dumb.c b/drivers/gpu/drm/qxl/qxl_dumb.c index 48a58ba1db96..a635d9fdf8ac 100644 --- a/drivers/gpu/drm/qxl/qxl_dumb.c +++ b/drivers/gpu/drm/qxl/qxl_dumb.c @@ -69,20 +69,3 @@ int qxl_mode_dumb_create(struct drm_file *file_priv, args->handle = handle; return 0; } - -int qxl_mode_dumb_mmap(struct drm_file *file_priv, - struct drm_device *dev, - uint32_t handle, uint64_t *offset_p) -{ - struct drm_gem_object *gobj; - struct qxl_bo *qobj; - - BUG_ON(!offset_p); - gobj = drm_gem_object_lookup(file_priv, handle); - if (gobj == NULL) - return -ENOENT; - qobj = gem_to_qxl_bo(gobj); - *offset_p = qxl_bo_mmap_offset(qobj); - drm_gem_object_put(gobj); - return 0; -} diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c index b6075f452b9e..38aabcbe2238 100644 --- a/drivers/gpu/drm/qxl/qxl_ioctl.c +++ b/drivers/gpu/drm/qxl/qxl_ioctl.c @@ -67,8 +67,8 @@ static int qxl_map_ioctl(struct drm_device *dev, void *data, struct qxl_device *qdev = to_qxl(dev); struct drm_qxl_map *qxl_map = data; - return qxl_mode_dumb_mmap(file_priv, &qdev->ddev, qxl_map->handle, - &qxl_map->offset); + return drm_gem_ttm_dumb_map_offset(file_priv, &qdev->ddev, qxl_map->handle, + &qxl_map->offset); } struct qxl_reloc_info { diff --git a/drivers/gpu/drm/qxl/qxl_object.h b/drivers/gpu/drm/qxl/qxl_object.h index ee9c29de4d3d..cee4b52b75dd 100644 --- a/drivers/gpu/drm/qxl/qxl_object.h +++ b/drivers/gpu/drm/qxl/qxl_object.h @@ -53,11 +53,6 @@ static inline unsigned long qxl_bo_size(struct qxl_bo *bo) return bo->tbo.base.size; } -static inline u64 qxl_bo_mmap_offset(struct qxl_bo *bo) -{ - return drm_vma_node_offset_addr(&bo->tbo.base.vma_node); -} - extern int qxl_bo_create(struct qxl_device *qdev, unsigned long size, bool kernel, bool pinned, u32 domain, -- cgit v1.2.3 From 2878b29fc25a0dac0e1c6c94177f07c7f94240f0 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 25 Mar 2021 12:48:22 +0100 Subject: drm/i915/display/vlv_dsi: Do not skip panel_pwr_cycle_delay when disabling the panel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After the recently added commit fe0f1e3bfdfe ("drm/i915: Shut down displays gracefully on reboot"), the DSI panel on a Cherry Trail based Predia Basic tablet would no longer properly light up after reboot. I've managed to reproduce this without rebooting by doing: chvt 3; echo 1 > /sys/class/graphics/fb0/blank;\ echo 0 > /sys/class/graphics/fb0/blank Which rapidly turns the panel off and back on again. The vlv_dsi.c code uses an intel_dsi_msleep() helper for the various delays used for panel on/off, since starting with MIPI-sequences version >= 3 the delays are already included inside the MIPI-sequences. The problems exposed by the "Shut down displays gracefully on reboot" change, show that using this helper for the panel_pwr_cycle_delay is not the right thing to do. This has not been noticed until now because normally the panel never is cycled off and directly on again in quick succession. Change the msleep for the panel_pwr_cycle_delay to a normal msleep() call to avoid the panel staying black after a quick off + on cycle. Cc: Ville Syrjälä Fixes: fe0f1e3bfdfe ("drm/i915: Shut down displays gracefully on reboot") Signed-off-by: Hans de Goede Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20210325114823.44922-1-hdegoede@redhat.com --- drivers/gpu/drm/i915/display/vlv_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index 9bee99fe5495..f461a8f03e19 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -993,14 +993,14 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, * FIXME As we do with eDP, just make a note of the time here * and perform the wait before the next panel power on. */ - intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); + msleep(intel_dsi->panel_pwr_cycle_delay); } static void intel_dsi_shutdown(struct intel_encoder *encoder) { struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); - intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); + msleep(intel_dsi->panel_pwr_cycle_delay); } static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, -- cgit v1.2.3 From c87eba80470e4103f4c2cbb915e297e5242f85fa Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 25 Mar 2021 12:48:23 +0100 Subject: drm/i915/display/vlv_dsi: Move panel_pwr_cycle_delay to next panel-on MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of sleeping panel_pwr_cycle_delay ms when turning the panel off, record the time it is turned off and if necessary wait any (remaining) time when the panel is turned on again. Also sleep the remaining time on shutdown, because on reboot the GOP will immediately turn on the panel again. Cc: Ville Syrjälä Signed-off-by: Hans de Goede Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20210325114823.44922-2-hdegoede@redhat.com --- drivers/gpu/drm/i915/display/intel_dsi.h | 1 + drivers/gpu/drm/i915/display/vlv_dsi.c | 25 +++++++++++++++++++------ 2 files changed, 20 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h index 625f2f1ae061..50d6da0b2419 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi.h +++ b/drivers/gpu/drm/i915/display/intel_dsi.h @@ -124,6 +124,7 @@ struct intel_dsi { u16 panel_on_delay; u16 panel_off_delay; u16 panel_pwr_cycle_delay; + ktime_t panel_power_off_time; }; struct intel_dsi_host { diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index f461a8f03e19..cf51860a1429 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -714,6 +714,19 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) } } +static void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi) +{ + ktime_t panel_power_on_time; + s64 panel_power_off_duration; + + panel_power_on_time = ktime_get_boottime(); + panel_power_off_duration = ktime_ms_delta(panel_power_on_time, + intel_dsi->panel_power_off_time); + + if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay) + msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration); +} + static void intel_dsi_prepare(struct intel_encoder *intel_encoder, const struct intel_crtc_state *pipe_config); static void intel_dsi_unprepare(struct intel_encoder *encoder); @@ -775,6 +788,8 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, drm_dbg_kms(&dev_priv->drm, "\n"); + intel_dsi_wait_panel_power_cycle(intel_dsi); + intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); /* @@ -989,18 +1004,14 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); - /* - * FIXME As we do with eDP, just make a note of the time here - * and perform the wait before the next panel power on. - */ - msleep(intel_dsi->panel_pwr_cycle_delay); + intel_dsi->panel_power_off_time = ktime_get_boottime(); } static void intel_dsi_shutdown(struct intel_encoder *encoder) { struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); - msleep(intel_dsi->panel_pwr_cycle_delay); + intel_dsi_wait_panel_power_cycle(intel_dsi); } static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, @@ -1883,6 +1894,8 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) else intel_encoder->pipe_mask = BIT(PIPE_B); + intel_dsi->panel_power_off_time = ktime_get_boottime(); + if (dev_priv->vbt.dsi.config->dual_link) intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); else -- cgit v1.2.3 From a28e10ed99bcf57cbd55a6146367f7ea752af6be Mon Sep 17 00:00:00 2001 From: Christian König Date: Fri, 9 Apr 2021 14:58:43 +0200 Subject: drm/ttm: fix return value check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The function returns the number of swapped pages here. Only abort when we get a negative error code. Signed-off-by: Christian König Reviewed-by: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20210409130113.1459-1-christian.koenig@amd.com --- drivers/gpu/drm/ttm/ttm_tt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 7dcd3fb69495..7d479095dcf8 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -326,7 +326,7 @@ int ttm_tt_populate(struct ttm_device *bdev, ttm_dma32_pages_limit) { ret = ttm_global_swapout(ctx, GFP_KERNEL); - if (ret) + if (ret < 0) goto error; } -- cgit v1.2.3 From b057f37bb24f9c4f833549ce48a0d2d6fccba2c4 Mon Sep 17 00:00:00 2001 From: Christian König Date: Fri, 9 Apr 2021 15:00:10 +0200 Subject: drm/ttm: re-add debugfs tt_shrink file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit That got lost when we moved back to a static limit. Signed-off-by: Christian König Reviewed-by: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20210409130113.1459-2-christian.koenig@amd.com --- drivers/gpu/drm/ttm/ttm_tt.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 7d479095dcf8..4d8498a3d642 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -389,6 +389,21 @@ void ttm_tt_unpopulate(struct ttm_device *bdev, struct ttm_tt *ttm) ttm->page_flags &= ~TTM_PAGE_FLAG_PRIV_POPULATED; } +#ifdef CONFIG_DEBUG_FS + +/* Test the shrinker functions and dump the result */ +static int ttm_tt_debugfs_shrink_show(struct seq_file *m, void *data) +{ + struct ttm_operation_ctx ctx = { false, false }; + + seq_printf(m, "%d\n", ttm_global_swapout(&ctx, GFP_KERNEL)); + return 0; +} +DEFINE_SHOW_ATTRIBUTE(ttm_tt_debugfs_shrink); + +#endif + + /** * ttm_tt_mgr_init - register with the MM shrinker * @@ -396,6 +411,11 @@ void ttm_tt_unpopulate(struct ttm_device *bdev, struct ttm_tt *ttm) */ void ttm_tt_mgr_init(unsigned long num_pages, unsigned long num_dma32_pages) { +#ifdef CONFIG_DEBUG_FS + debugfs_create_file("tt_shrink", 0400, ttm_debugfs_root, NULL, + &ttm_tt_debugfs_shrink_fops); +#endif + if (!ttm_pages_limit) ttm_pages_limit = num_pages; -- cgit v1.2.3 From 1cdb005d6ef14a45db62528806f9b47012266bcd Mon Sep 17 00:00:00 2001 From: "Fabio M. De Francesco" Date: Mon, 12 Apr 2021 12:53:09 +0200 Subject: gpu: drm: Replace bare "unsigned" with "unsigned int" Replaced the type "unsigned" with "unsigned int" because it is preferred. Issue detected by checkpatch.pl. Signed-off-by: Fabio M. De Francesco Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20210412105309.27156-1-fmdefrancesco@gmail.com --- drivers/gpu/drm/drm_atomic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 5b4547e0f775..46dceb51c90f 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -1302,8 +1302,8 @@ int drm_atomic_check_only(struct drm_atomic_state *state) struct drm_crtc_state *new_crtc_state; struct drm_connector *conn; struct drm_connector_state *conn_state; - unsigned requested_crtc = 0; - unsigned affected_crtc = 0; + unsigned int requested_crtc = 0; + unsigned int affected_crtc = 0; int i, ret = 0; DRM_DEBUG_ATOMIC("checking %p\n", state); -- cgit v1.2.3 From 9237ec1f3b87d776638e72b26e2fe515ccafabaa Mon Sep 17 00:00:00 2001 From: "Fabio M. De Francesco" Date: Mon, 12 Apr 2021 14:42:14 +0200 Subject: drm: drm_atomic_helper.c: Replace "unsigned" with "unsigned int" Replaced "unsigned with "unsigned int" since the latter is preferred. Signed-off-by: Fabio M. De Francesco Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20210412124213.4628-2-fmdefrancesco@gmail.com --- drivers/gpu/drm/drm_atomic_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index f2b3e28d938b..cd748ff61162 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -106,7 +106,7 @@ static int handle_conflicting_encoders(struct drm_atomic_state *state, struct drm_connector *connector; struct drm_connector_list_iter conn_iter; struct drm_encoder *encoder; - unsigned encoder_mask = 0; + unsigned int encoder_mask = 0; int i, ret = 0; /* @@ -609,7 +609,7 @@ drm_atomic_helper_check_modeset(struct drm_device *dev, struct drm_connector *connector; struct drm_connector_state *old_connector_state, *new_connector_state; int i, ret; - unsigned connectors_mask = 0; + unsigned int connectors_mask = 0; for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { bool has_connectors = @@ -1478,7 +1478,7 @@ drm_atomic_helper_wait_for_vblanks(struct drm_device *dev, struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; int i, ret; - unsigned crtc_mask = 0; + unsigned int crtc_mask = 0; /* * Legacy cursor ioctls are completely unsynced, and userspace @@ -2575,7 +2575,7 @@ drm_atomic_helper_commit_planes_on_crtc(struct drm_crtc_state *old_crtc_state) struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc); struct drm_plane *plane; - unsigned plane_mask; + unsigned int plane_mask; plane_mask = old_crtc_state->plane_mask; plane_mask |= new_crtc_state->plane_mask; -- cgit v1.2.3 From 1758f403d8faff5d3ddb98f43c4adc4f715f9236 Mon Sep 17 00:00:00 2001 From: "Fabio M. De Francesco" Date: Mon, 12 Apr 2021 14:42:16 +0200 Subject: drm: drm_atomic_helper.c: Correct comments format Corrected comments format in accordance to the Linux style guides. Signed-off-by: Fabio M. De Francesco Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20210412124213.4628-3-fmdefrancesco@gmail.com --- drivers/gpu/drm/drm_atomic_helper.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index cd748ff61162..bc3487964fb5 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -1018,8 +1018,10 @@ disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state) struct drm_encoder *encoder; struct drm_bridge *bridge; - /* Shut down everything that's in the changeset and currently - * still on. So need to check the old, saved state. */ + /* + * Shut down everything that's in the changeset and currently + * still on. So need to check the old, saved state. + */ if (!old_conn_state->crtc) continue; @@ -1409,7 +1411,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_modeset_enables); * @dev: DRM device * @state: atomic state object with old state structures * @pre_swap: If true, do an interruptible wait, and @state is the new state. - * Otherwise @state is the old state. + * Otherwise @state is the old state. * * For implicit sync, driver should fish the exclusive fence out from the * incoming fb's and stash it in the drm_plane_state. This is called after @@ -1953,8 +1955,10 @@ static int stall_checks(struct drm_crtc *crtc, bool nonblock) list_for_each_entry(commit, &crtc->commit_list, commit_entry) { if (i == 0) { completed = try_wait_for_completion(&commit->flip_done); - /* Userspace is not allowed to get ahead of the previous - * commit with nonblocking ones. */ + /* + * Userspace is not allowed to get ahead of the previous + * commit with nonblocking ones. + */ if (!completed && nonblock) { spin_unlock(&crtc->commit_lock); DRM_DEBUG_ATOMIC("[CRTC:%d:%s] busy with a previous commit\n", @@ -2103,9 +2107,11 @@ int drm_atomic_helper_setup_commit(struct drm_atomic_state *state, if (ret) return ret; - /* Drivers only send out events when at least either current or + /* + * Drivers only send out events when at least either current or * new CRTC state is active. Complete right away if everything - * stays off. */ + * stays off. + */ if (!old_crtc_state->active && !new_crtc_state->active) { complete_all(&commit->flip_done); continue; @@ -2137,8 +2143,10 @@ int drm_atomic_helper_setup_commit(struct drm_atomic_state *state, } for_each_oldnew_connector_in_state(state, conn, old_conn_state, new_conn_state, i) { - /* Userspace is not allowed to get ahead of the previous - * commit with nonblocking ones. */ + /* + * Userspace is not allowed to get ahead of the previous + * commit with nonblocking ones. + */ if (nonblock && old_conn_state->commit && !try_wait_for_completion(&old_conn_state->commit->flip_done)) { DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] busy with a previous commit\n", @@ -2156,8 +2164,10 @@ int drm_atomic_helper_setup_commit(struct drm_atomic_state *state, } for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { - /* Userspace is not allowed to get ahead of the previous - * commit with nonblocking ones. */ + /* + * Userspace is not allowed to get ahead of the previous + * commit with nonblocking ones. + */ if (nonblock && old_plane_state->commit && !try_wait_for_completion(&old_plane_state->commit->flip_done)) { DRM_DEBUG_ATOMIC("[PLANE:%d:%s] busy with a previous commit\n", -- cgit v1.2.3 From 41c70d2b7170274b8aa93b7f1d33eabd55871a0e Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Thu, 8 Apr 2021 13:49:16 -0700 Subject: drm/i915/display: Implement Wa_14013723622 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This WA fix some display glitches when the system is under high memory pressure. BSpec: 52890 Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun Tested-by: Gwan-gyeong Mun Link: https://patchwork.freedesktop.org/patch/msgid/20210408204917.254272-1-jose.souza@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 5 +++++ 2 files changed, 8 insertions(+) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cbf7a60afe54..f4a779643f4d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -12549,4 +12549,7 @@ enum skl_power_gate { #define TGL_ROOT_DEVICE_SKU_ULX 0x2 #define TGL_ROOT_DEVICE_SKU_ULT 0x4 +#define CLKREQ_POLICY _MMIO(0x101038) +#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3ecbd62915cf..3f6d8b502a61 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7141,6 +7141,11 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) /* Wa_14011059788:tgl,rkl,adl_s,dg1 */ intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN, 0, DFR_DISABLE); + + /* Wa_14013723622:tgl,rkl,dg1,adl-s */ + if (DISPLAY_VER(dev_priv) == 12) + intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY, + CLKREQ_POLICY_MEM_UP_OVRD, 0); } static void dg1_init_clock_gating(struct drm_i915_private *dev_priv) -- cgit v1.2.3 From f10fe8f89d85ab170ec4491cd15ba7410a03a4c8 Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Thu, 8 Apr 2021 13:49:17 -0700 Subject: Revert "drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 71c1a4998320962f7b8362b2c5ee36610d49e8fb. The proper fix is Wa_14013723622, so now we can revert this WA and get back some power savings. Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun Tested-by: Gwan-gyeong Mun Link: https://patchwork.freedesktop.org/patch/msgid/20210408204917.254272-2-jose.souza@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 2627d0b558f3..bf8e4ede2a6c 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1167,21 +1167,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (IS_TIGERLAKE(dev_priv)) - /* - * Writes to CURSURFLIVE in TGL are causing IOMMU errors and - * visual glitches that are often reproduced when executing - * CPU intensive workloads while a eDP 4K panel is attached. - * - * Manually exiting PSR causes the frontbuffer to be updated - * without glitches and the IOMMU errors are also gone but - * this comes at the cost of less time with PSR active. - * - * So using this workaround until this issue is root caused - * and a better fix is found. - */ - intel_psr_exit(intel_dp); - else if (DISPLAY_VER(dev_priv) >= 9) + if (DISPLAY_VER(dev_priv) >= 9) /* * Display WA #0884: skl+ * This documented WA for bxt can be safely applied -- cgit v1.2.3 From 6a3608eae6d33a478a29348eb5e9ca330a528ae6 Mon Sep 17 00:00:00 2001 From: Parshuram Thombare Date: Sat, 10 Apr 2021 20:15:42 +0200 Subject: drm: bridge: cdns-mhdp8546: Enable HDCP This patch enable HDCP in MHDP driver. Signed-off-by: Parshuram Thombare Reviewed-by: Robert Foss Signed-off-by: Robert Foss Link: https://patchwork.freedesktop.org/patch/msgid/1618078542-30679-1-git-send-email-pthombar@cadence.com --- drivers/gpu/drm/bridge/cadence/Makefile | 2 +- .../gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 128 ++++- .../gpu/drm/bridge/cadence/cdns-mhdp8546-core.h | 22 + .../gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c | 570 +++++++++++++++++++++ .../gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.h | 92 ++++ 5 files changed, 801 insertions(+), 13 deletions(-) create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.h (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile index 8f647991b374..4d2db8df1bc6 100644 --- a/drivers/gpu/drm/bridge/cadence/Makefile +++ b/drivers/gpu/drm/bridge/cadence/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o -cdns-mhdp8546-y := cdns-mhdp8546-core.o +cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c index 989a05bc8197..01e95466502a 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include #include @@ -49,7 +50,7 @@ #include #include "cdns-mhdp8546-core.h" - +#include "cdns-mhdp8546-hdcp.h" #include "cdns-mhdp8546-j721e.h" static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp) @@ -1614,10 +1615,51 @@ enum drm_mode_status cdns_mhdp_mode_valid(struct drm_connector *conn, return MODE_OK; } +static int cdns_mhdp_connector_atomic_check(struct drm_connector *conn, + struct drm_atomic_state *state) +{ + struct cdns_mhdp_device *mhdp = connector_to_mhdp(conn); + struct drm_connector_state *old_state, *new_state; + struct drm_crtc_state *crtc_state; + u64 old_cp, new_cp; + + if (!mhdp->hdcp_supported) + return 0; + + old_state = drm_atomic_get_old_connector_state(state, conn); + new_state = drm_atomic_get_new_connector_state(state, conn); + old_cp = old_state->content_protection; + new_cp = new_state->content_protection; + + if (old_state->hdcp_content_type != new_state->hdcp_content_type && + new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { + new_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; + goto mode_changed; + } + + if (!new_state->crtc) { + if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) + new_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; + return 0; + } + + if (old_cp == new_cp || + (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && + new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) + return 0; + +mode_changed: + crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); + crtc_state->mode_changed = true; + + return 0; +} + static const struct drm_connector_helper_funcs cdns_mhdp_conn_helper_funcs = { .detect_ctx = cdns_mhdp_connector_detect, .get_modes = cdns_mhdp_get_modes, .mode_valid = cdns_mhdp_mode_valid, + .atomic_check = cdns_mhdp_connector_atomic_check, }; static const struct drm_connector_funcs cdns_mhdp_conn_funcs = { @@ -1662,7 +1704,10 @@ static int cdns_mhdp_connector_init(struct cdns_mhdp_device *mhdp) return ret; } - return 0; + if (mhdp->hdcp_supported) + ret = drm_connector_attach_content_protection_property(conn, true); + + return ret; } static int cdns_mhdp_attach(struct drm_bridge *bridge, @@ -1957,6 +2002,15 @@ static void cdns_mhdp_atomic_enable(struct drm_bridge *bridge, if (WARN_ON(!conn_state)) goto out; + if (mhdp->hdcp_supported && + mhdp->hw_state == MHDP_HW_READY && + conn_state->content_protection == + DRM_MODE_CONTENT_PROTECTION_DESIRED) { + mutex_unlock(&mhdp->link_mutex); + cdns_mhdp_hdcp_enable(mhdp, conn_state->hdcp_content_type); + mutex_lock(&mhdp->link_mutex); + } + crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); if (WARN_ON(!crtc_state)) goto out; @@ -2000,6 +2054,9 @@ static void cdns_mhdp_atomic_disable(struct drm_bridge *bridge, mutex_lock(&mhdp->link_mutex); + if (mhdp->hdcp_supported) + cdns_mhdp_hdcp_disable(mhdp); + mhdp->bridge_enabled = false; cdns_mhdp_reg_read(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG, &resp); resp &= ~CDNS_DP_FRAMER_EN; @@ -2288,7 +2345,6 @@ static irqreturn_t cdns_mhdp_irq_handler(int irq, void *data) struct cdns_mhdp_device *mhdp = data; u32 apb_stat, sw_ev0; bool bridge_attached; - int ret; apb_stat = readl(mhdp->regs + CDNS_APB_INT_STATUS); if (!(apb_stat & CDNS_APB_INT_MASK_SW_EVENT_INT)) @@ -2307,20 +2363,54 @@ static irqreturn_t cdns_mhdp_irq_handler(int irq, void *data) spin_unlock(&mhdp->start_lock); if (bridge_attached && (sw_ev0 & CDNS_DPTX_HPD)) { - ret = cdns_mhdp_update_link_status(mhdp); - if (mhdp->connector.dev) { - if (ret < 0) - schedule_work(&mhdp->modeset_retry_work); - else - drm_kms_helper_hotplug_event(mhdp->bridge.dev); - } else { - drm_bridge_hpd_notify(&mhdp->bridge, cdns_mhdp_detect(mhdp)); - } + schedule_work(&mhdp->hpd_work); + } + + if (sw_ev0 & ~CDNS_DPTX_HPD) { + mhdp->sw_events |= (sw_ev0 & ~CDNS_DPTX_HPD); + wake_up(&mhdp->sw_events_wq); } return IRQ_HANDLED; } +u32 cdns_mhdp_wait_for_sw_event(struct cdns_mhdp_device *mhdp, u32 event) +{ + u32 ret; + + ret = wait_event_timeout(mhdp->sw_events_wq, + mhdp->sw_events & event, + msecs_to_jiffies(500)); + if (!ret) { + dev_dbg(mhdp->dev, "SW event 0x%x timeout\n", event); + goto sw_event_out; + } + + ret = mhdp->sw_events; + mhdp->sw_events &= ~event; + +sw_event_out: + return ret; +} + +static void cdns_mhdp_hpd_work(struct work_struct *work) +{ + struct cdns_mhdp_device *mhdp = container_of(work, + struct cdns_mhdp_device, + hpd_work); + int ret; + + ret = cdns_mhdp_update_link_status(mhdp); + if (mhdp->connector.dev) { + if (ret < 0) + schedule_work(&mhdp->modeset_retry_work); + else + drm_kms_helper_hotplug_event(mhdp->bridge.dev); + } else { + drm_bridge_hpd_notify(&mhdp->bridge, cdns_mhdp_detect(mhdp)); + } +} + static int cdns_mhdp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -2356,6 +2446,15 @@ static int cdns_mhdp_probe(struct platform_device *pdev) return PTR_ERR(mhdp->regs); } + mhdp->sapb_regs = devm_platform_ioremap_resource_byname(pdev, "mhdptx-sapb"); + if (IS_ERR(mhdp->sapb_regs)) { + mhdp->hdcp_supported = false; + dev_warn(dev, + "Failed to get SAPB memory resource, HDCP not supported\n"); + } else { + mhdp->hdcp_supported = true; + } + mhdp->phy = devm_of_phy_get_by_index(dev, pdev->dev.of_node, 0); if (IS_ERR(mhdp->phy)) { dev_err(dev, "no PHY configured\n"); @@ -2430,13 +2529,18 @@ static int cdns_mhdp_probe(struct platform_device *pdev) /* Initialize the work for modeset in case of link train failure */ INIT_WORK(&mhdp->modeset_retry_work, cdns_mhdp_modeset_retry_fn); + INIT_WORK(&mhdp->hpd_work, cdns_mhdp_hpd_work); init_waitqueue_head(&mhdp->fw_load_wq); + init_waitqueue_head(&mhdp->sw_events_wq); ret = cdns_mhdp_load_firmware(mhdp); if (ret) goto phy_exit; + if (mhdp->hdcp_supported) + cdns_mhdp_hdcp_init(mhdp); + drm_bridge_add(&mhdp->bridge); return 0; diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h index 5897a85e3159..c74439d0b1a7 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h @@ -47,6 +47,10 @@ struct phy; #define CDNS_SW_EVENT0 0x00044 #define CDNS_DPTX_HPD BIT(0) +#define CDNS_HDCP_TX_STATUS BIT(4) +#define CDNS_HDCP2_TX_IS_KM_STORED BIT(5) +#define CDNS_HDCP2_TX_STORE_KM BIT(6) +#define CDNS_HDCP_TX_IS_RCVR_ID_VALID BIT(7) #define CDNS_SW_EVENT1 0x00048 #define CDNS_SW_EVENT2 0x0004c @@ -339,8 +343,17 @@ struct cdns_mhdp_platform_info { #define to_cdns_mhdp_bridge_state(s) \ container_of(s, struct cdns_mhdp_bridge_state, base) +struct cdns_mhdp_hdcp { + struct delayed_work check_work; + struct work_struct prop_work; + struct mutex mutex; /* mutex to protect hdcp.value */ + u32 value; + u8 hdcp_content_type; +}; + struct cdns_mhdp_device { void __iomem *regs; + void __iomem *sapb_regs; void __iomem *j721e_regs; struct device *dev; @@ -392,9 +405,18 @@ struct cdns_mhdp_device { /* Work struct to schedule a uevent on link train failure */ struct work_struct modeset_retry_work; + struct work_struct hpd_work; + + wait_queue_head_t sw_events_wq; + u32 sw_events; + + struct cdns_mhdp_hdcp hdcp; + bool hdcp_supported; }; #define connector_to_mhdp(x) container_of(x, struct cdns_mhdp_device, connector) #define bridge_to_mhdp(x) container_of(x, struct cdns_mhdp_device, bridge) +u32 cdns_mhdp_wait_for_sw_event(struct cdns_mhdp_device *mhdp, uint32_t event); + #endif diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c new file mode 100644 index 000000000000..fccd6fbcc257 --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c @@ -0,0 +1,570 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cadence MHDP8546 DP bridge driver. + * + * Copyright (C) 2020 Cadence Design Systems, Inc. + * + */ + +#include +#include + +#include + +#include + +#include "cdns-mhdp8546-hdcp.h" + +static int cdns_mhdp_secure_mailbox_read(struct cdns_mhdp_device *mhdp) +{ + int ret, empty; + + WARN_ON(!mutex_is_locked(&mhdp->mbox_mutex)); + + ret = readx_poll_timeout(readl, mhdp->sapb_regs + CDNS_MAILBOX_EMPTY, + empty, !empty, MAILBOX_RETRY_US, + MAILBOX_TIMEOUT_US); + if (ret < 0) + return ret; + + return readl(mhdp->sapb_regs + CDNS_MAILBOX_RX_DATA) & 0xff; +} + +static int cdns_mhdp_secure_mailbox_write(struct cdns_mhdp_device *mhdp, + u8 val) +{ + int ret, full; + + WARN_ON(!mutex_is_locked(&mhdp->mbox_mutex)); + + ret = readx_poll_timeout(readl, mhdp->sapb_regs + CDNS_MAILBOX_FULL, + full, !full, MAILBOX_RETRY_US, + MAILBOX_TIMEOUT_US); + if (ret < 0) + return ret; + + writel(val, mhdp->sapb_regs + CDNS_MAILBOX_TX_DATA); + + return 0; +} + +static int cdns_mhdp_secure_mailbox_recv_header(struct cdns_mhdp_device *mhdp, + u8 module_id, + u8 opcode, + u16 req_size) +{ + u32 mbox_size, i; + u8 header[4]; + int ret; + + /* read the header of the message */ + for (i = 0; i < sizeof(header); i++) { + ret = cdns_mhdp_secure_mailbox_read(mhdp); + if (ret < 0) + return ret; + + header[i] = ret; + } + + mbox_size = get_unaligned_be16(header + 2); + + if (opcode != header[0] || module_id != header[1] || + (opcode != HDCP_TRAN_IS_REC_ID_VALID && req_size != mbox_size)) { + for (i = 0; i < mbox_size; i++) + if (cdns_mhdp_secure_mailbox_read(mhdp) < 0) + break; + return -EINVAL; + } + + return 0; +} + +static int cdns_mhdp_secure_mailbox_recv_data(struct cdns_mhdp_device *mhdp, + u8 *buff, u16 buff_size) +{ + int ret; + u32 i; + + for (i = 0; i < buff_size; i++) { + ret = cdns_mhdp_secure_mailbox_read(mhdp); + if (ret < 0) + return ret; + + buff[i] = ret; + } + + return 0; +} + +static int cdns_mhdp_secure_mailbox_send(struct cdns_mhdp_device *mhdp, + u8 module_id, + u8 opcode, + u16 size, + u8 *message) +{ + u8 header[4]; + int ret; + u32 i; + + header[0] = opcode; + header[1] = module_id; + put_unaligned_be16(size, header + 2); + + for (i = 0; i < sizeof(header); i++) { + ret = cdns_mhdp_secure_mailbox_write(mhdp, header[i]); + if (ret) + return ret; + } + + for (i = 0; i < size; i++) { + ret = cdns_mhdp_secure_mailbox_write(mhdp, message[i]); + if (ret) + return ret; + } + + return 0; +} + +static int cdns_mhdp_hdcp_get_status(struct cdns_mhdp_device *mhdp, + u16 *hdcp_port_status) +{ + u8 hdcp_status[HDCP_STATUS_SIZE]; + int ret; + + mutex_lock(&mhdp->mbox_mutex); + ret = cdns_mhdp_secure_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP_TRAN_STATUS_CHANGE, 0, NULL); + if (ret) + goto err_get_hdcp_status; + + ret = cdns_mhdp_secure_mailbox_recv_header(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP_TRAN_STATUS_CHANGE, + sizeof(hdcp_status)); + if (ret) + goto err_get_hdcp_status; + + ret = cdns_mhdp_secure_mailbox_recv_data(mhdp, hdcp_status, + sizeof(hdcp_status)); + if (ret) + goto err_get_hdcp_status; + + *hdcp_port_status = ((u16)(hdcp_status[0] << 8) | hdcp_status[1]); + +err_get_hdcp_status: + mutex_unlock(&mhdp->mbox_mutex); + + return ret; +} + +static u8 cdns_mhdp_hdcp_handle_status(struct cdns_mhdp_device *mhdp, + u16 status) +{ + u8 err = GET_HDCP_PORT_STS_LAST_ERR(status); + + if (err) + dev_dbg(mhdp->dev, "HDCP Error = %d", err); + + return err; +} + +static int cdns_mhdp_hdcp_rx_id_valid_response(struct cdns_mhdp_device *mhdp, + u8 valid) +{ + int ret; + + mutex_lock(&mhdp->mbox_mutex); + ret = cdns_mhdp_secure_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP_TRAN_RESPOND_RECEIVER_ID_VALID, + 1, &valid); + mutex_unlock(&mhdp->mbox_mutex); + + return ret; +} + +static int cdns_mhdp_hdcp_rx_id_valid(struct cdns_mhdp_device *mhdp, + u8 *recv_num, u8 *hdcp_rx_id) +{ + u8 rec_id_hdr[2]; + u8 status; + int ret; + + mutex_lock(&mhdp->mbox_mutex); + ret = cdns_mhdp_secure_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP_TRAN_IS_REC_ID_VALID, 0, NULL); + if (ret) + goto err_rx_id_valid; + + ret = cdns_mhdp_secure_mailbox_recv_header(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP_TRAN_IS_REC_ID_VALID, + sizeof(status)); + if (ret) + goto err_rx_id_valid; + + ret = cdns_mhdp_secure_mailbox_recv_data(mhdp, rec_id_hdr, 2); + if (ret) + goto err_rx_id_valid; + + *recv_num = rec_id_hdr[0]; + + ret = cdns_mhdp_secure_mailbox_recv_data(mhdp, hdcp_rx_id, 5 * *recv_num); + +err_rx_id_valid: + mutex_unlock(&mhdp->mbox_mutex); + + return ret; +} + +static int cdns_mhdp_hdcp_km_stored_resp(struct cdns_mhdp_device *mhdp, + u32 size, u8 *km) +{ + int ret; + + mutex_lock(&mhdp->mbox_mutex); + ret = cdns_mhdp_secure_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP2X_TX_RESPOND_KM, size, km); + mutex_unlock(&mhdp->mbox_mutex); + + return ret; +} + +static int cdns_mhdp_hdcp_tx_is_km_stored(struct cdns_mhdp_device *mhdp, + u8 *resp, u32 size) +{ + int ret; + + mutex_lock(&mhdp->mbox_mutex); + ret = cdns_mhdp_secure_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP2X_TX_IS_KM_STORED, 0, NULL); + if (ret) + goto err_is_km_stored; + + ret = cdns_mhdp_secure_mailbox_recv_header(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP2X_TX_IS_KM_STORED, + size); + if (ret) + goto err_is_km_stored; + + ret = cdns_mhdp_secure_mailbox_recv_data(mhdp, resp, size); +err_is_km_stored: + mutex_unlock(&mhdp->mbox_mutex); + + return ret; +} + +static int cdns_mhdp_hdcp_tx_config(struct cdns_mhdp_device *mhdp, + u8 hdcp_cfg) +{ + int ret; + + mutex_lock(&mhdp->mbox_mutex); + ret = cdns_mhdp_secure_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP_TRAN_CONFIGURATION, 1, &hdcp_cfg); + mutex_unlock(&mhdp->mbox_mutex); + + return ret; +} + +static int cdns_mhdp_hdcp_set_config(struct cdns_mhdp_device *mhdp, + u8 hdcp_config, bool enable) +{ + u16 hdcp_port_status; + u32 ret_event; + u8 hdcp_cfg; + int ret; + + hdcp_cfg = hdcp_config | (enable ? 0x04 : 0) | + (HDCP_CONTENT_TYPE_0 << 3); + cdns_mhdp_hdcp_tx_config(mhdp, hdcp_cfg); + ret_event = cdns_mhdp_wait_for_sw_event(mhdp, CDNS_HDCP_TX_STATUS); + if (!ret_event) + return -1; + + ret = cdns_mhdp_hdcp_get_status(mhdp, &hdcp_port_status); + if (ret || cdns_mhdp_hdcp_handle_status(mhdp, hdcp_port_status)) + return -1; + + return 0; +} + +static int cdns_mhdp_hdcp_auth_check(struct cdns_mhdp_device *mhdp) +{ + u16 hdcp_port_status; + u32 ret_event; + int ret; + + ret_event = cdns_mhdp_wait_for_sw_event(mhdp, CDNS_HDCP_TX_STATUS); + if (!ret_event) + return -1; + + ret = cdns_mhdp_hdcp_get_status(mhdp, &hdcp_port_status); + if (ret || cdns_mhdp_hdcp_handle_status(mhdp, hdcp_port_status)) + return -1; + + if (hdcp_port_status & 1) { + dev_dbg(mhdp->dev, "Authentication completed successfully!\n"); + return 0; + } + + dev_dbg(mhdp->dev, "Authentication failed\n"); + + return -1; +} + +static int cdns_mhdp_hdcp_check_receviers(struct cdns_mhdp_device *mhdp) +{ + u8 hdcp_rec_id[HDCP_MAX_RECEIVERS][HDCP_RECEIVER_ID_SIZE_BYTES]; + u8 hdcp_num_rec; + u32 ret_event; + + ret_event = cdns_mhdp_wait_for_sw_event(mhdp, + CDNS_HDCP_TX_IS_RCVR_ID_VALID); + if (!ret_event) + return -1; + + hdcp_num_rec = 0; + memset(&hdcp_rec_id, 0, sizeof(hdcp_rec_id)); + cdns_mhdp_hdcp_rx_id_valid(mhdp, &hdcp_num_rec, (u8 *)hdcp_rec_id); + cdns_mhdp_hdcp_rx_id_valid_response(mhdp, 1); + + return 0; +} + +static int cdns_mhdp_hdcp_auth_22(struct cdns_mhdp_device *mhdp) +{ + u8 resp[HDCP_STATUS_SIZE]; + u16 hdcp_port_status; + u32 ret_event; + int ret; + + dev_dbg(mhdp->dev, "HDCP: Start 2.2 Authentication\n"); + ret_event = cdns_mhdp_wait_for_sw_event(mhdp, + CDNS_HDCP2_TX_IS_KM_STORED); + if (!ret_event) + return -1; + + if (ret_event & CDNS_HDCP_TX_STATUS) { + mhdp->sw_events &= ~CDNS_HDCP_TX_STATUS; + ret = cdns_mhdp_hdcp_get_status(mhdp, &hdcp_port_status); + if (ret || cdns_mhdp_hdcp_handle_status(mhdp, hdcp_port_status)) + return -1; + } + + cdns_mhdp_hdcp_tx_is_km_stored(mhdp, resp, sizeof(resp)); + cdns_mhdp_hdcp_km_stored_resp(mhdp, 0, NULL); + + if (cdns_mhdp_hdcp_check_receviers(mhdp)) + return -1; + + return 0; +} + +static inline int cdns_mhdp_hdcp_auth_14(struct cdns_mhdp_device *mhdp) +{ + dev_dbg(mhdp->dev, "HDCP: Starting 1.4 Authentication\n"); + return cdns_mhdp_hdcp_check_receviers(mhdp); +} + +static int cdns_mhdp_hdcp_auth(struct cdns_mhdp_device *mhdp, + u8 hdcp_config) +{ + int ret; + + ret = cdns_mhdp_hdcp_set_config(mhdp, hdcp_config, true); + if (ret) + goto auth_failed; + + if (hdcp_config == HDCP_TX_1) + ret = cdns_mhdp_hdcp_auth_14(mhdp); + else + ret = cdns_mhdp_hdcp_auth_22(mhdp); + + if (ret) + goto auth_failed; + + ret = cdns_mhdp_hdcp_auth_check(mhdp); + if (ret) + ret = cdns_mhdp_hdcp_auth_check(mhdp); + +auth_failed: + return ret; +} + +static int _cdns_mhdp_hdcp_disable(struct cdns_mhdp_device *mhdp) +{ + int ret; + + dev_dbg(mhdp->dev, "[%s:%d] HDCP is being disabled...\n", + mhdp->connector.name, mhdp->connector.base.id); + + ret = cdns_mhdp_hdcp_set_config(mhdp, 0, false); + + return ret; +} + +static int _cdns_mhdp_hdcp_enable(struct cdns_mhdp_device *mhdp, u8 content_type) +{ + int ret, tries = 3; + u32 i; + + for (i = 0; i < tries; i++) { + if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0 || + content_type == DRM_MODE_HDCP_CONTENT_TYPE1) { + ret = cdns_mhdp_hdcp_auth(mhdp, HDCP_TX_2); + if (!ret) + return 0; + _cdns_mhdp_hdcp_disable(mhdp); + } + + if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) { + ret = cdns_mhdp_hdcp_auth(mhdp, HDCP_TX_1); + if (!ret) + return 0; + _cdns_mhdp_hdcp_disable(mhdp); + } + } + + dev_err(mhdp->dev, "HDCP authentication failed (%d tries/%d)\n", + tries, ret); + + return ret; +} + +static int cdns_mhdp_hdcp_check_link(struct cdns_mhdp_device *mhdp) +{ + u16 hdcp_port_status; + int ret = 0; + + mutex_lock(&mhdp->hdcp.mutex); + if (mhdp->hdcp.value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) + goto out; + + ret = cdns_mhdp_hdcp_get_status(mhdp, &hdcp_port_status); + if (!ret && hdcp_port_status & HDCP_PORT_STS_AUTH) + goto out; + + dev_err(mhdp->dev, + "[%s:%d] HDCP link failed, retrying authentication\n", + mhdp->connector.name, mhdp->connector.base.id); + + ret = _cdns_mhdp_hdcp_disable(mhdp); + if (ret) { + mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_DESIRED; + schedule_work(&mhdp->hdcp.prop_work); + goto out; + } + + ret = _cdns_mhdp_hdcp_enable(mhdp, mhdp->hdcp.hdcp_content_type); + if (ret) { + mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_DESIRED; + schedule_work(&mhdp->hdcp.prop_work); + } +out: + mutex_unlock(&mhdp->hdcp.mutex); + return ret; +} + +static void cdns_mhdp_hdcp_check_work(struct work_struct *work) +{ + struct delayed_work *d_work = to_delayed_work(work); + struct cdns_mhdp_hdcp *hdcp = container_of(d_work, + struct cdns_mhdp_hdcp, + check_work); + struct cdns_mhdp_device *mhdp = container_of(hdcp, + struct cdns_mhdp_device, + hdcp); + + if (!cdns_mhdp_hdcp_check_link(mhdp)) + schedule_delayed_work(&hdcp->check_work, + DRM_HDCP_CHECK_PERIOD_MS); +} + +static void cdns_mhdp_hdcp_prop_work(struct work_struct *work) +{ + struct cdns_mhdp_hdcp *hdcp = container_of(work, + struct cdns_mhdp_hdcp, + prop_work); + struct cdns_mhdp_device *mhdp = container_of(hdcp, + struct cdns_mhdp_device, + hdcp); + struct drm_device *dev = mhdp->connector.dev; + struct drm_connector_state *state; + + drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); + mutex_lock(&mhdp->hdcp.mutex); + if (mhdp->hdcp.value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { + state = mhdp->connector.state; + state->content_protection = mhdp->hdcp.value; + } + mutex_unlock(&mhdp->hdcp.mutex); + drm_modeset_unlock(&dev->mode_config.connection_mutex); +} + +int cdns_mhdp_hdcp_set_lc(struct cdns_mhdp_device *mhdp, u8 *val) +{ + int ret; + + mutex_lock(&mhdp->mbox_mutex); + ret = cdns_mhdp_secure_mailbox_send(mhdp, MB_MODULE_ID_HDCP_GENERAL, + HDCP_GENERAL_SET_LC_128, + 16, val); + mutex_unlock(&mhdp->mbox_mutex); + + return ret; +} + +int +cdns_mhdp_hdcp_set_public_key_param(struct cdns_mhdp_device *mhdp, + struct cdns_hdcp_tx_public_key_param *val) +{ + int ret; + + mutex_lock(&mhdp->mbox_mutex); + ret = cdns_mhdp_secure_mailbox_send(mhdp, MB_MODULE_ID_HDCP_TX, + HDCP2X_TX_SET_PUBLIC_KEY_PARAMS, + sizeof(*val), (u8 *)val); + mutex_unlock(&mhdp->mbox_mutex); + + return ret; +} + +int cdns_mhdp_hdcp_enable(struct cdns_mhdp_device *mhdp, u8 content_type) +{ + int ret; + + mutex_lock(&mhdp->hdcp.mutex); + ret = _cdns_mhdp_hdcp_enable(mhdp, content_type); + if (ret) + goto out; + + mhdp->hdcp.hdcp_content_type = content_type; + mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_ENABLED; + schedule_work(&mhdp->hdcp.prop_work); + schedule_delayed_work(&mhdp->hdcp.check_work, + DRM_HDCP_CHECK_PERIOD_MS); +out: + mutex_unlock(&mhdp->hdcp.mutex); + return ret; +} + +int cdns_mhdp_hdcp_disable(struct cdns_mhdp_device *mhdp) +{ + int ret = 0; + + mutex_lock(&mhdp->hdcp.mutex); + if (mhdp->hdcp.value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { + mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; + schedule_work(&mhdp->hdcp.prop_work); + ret = _cdns_mhdp_hdcp_disable(mhdp); + } + mutex_unlock(&mhdp->hdcp.mutex); + cancel_delayed_work_sync(&mhdp->hdcp.check_work); + + return ret; +} + +void cdns_mhdp_hdcp_init(struct cdns_mhdp_device *mhdp) +{ + INIT_DELAYED_WORK(&mhdp->hdcp.check_work, cdns_mhdp_hdcp_check_work); + INIT_WORK(&mhdp->hdcp.prop_work, cdns_mhdp_hdcp_prop_work); + mutex_init(&mhdp->hdcp.mutex); +} diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.h b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.h new file mode 100644 index 000000000000..334c0b8b0d4f --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Cadence MHDP8546 DP bridge driver. + * + * Copyright (C) 2020 Cadence Design Systems, Inc. + * + */ + +#ifndef CDNS_MHDP8546_HDCP_H +#define CDNS_MHDP8546_HDCP_H + +#include "cdns-mhdp8546-core.h" + +#define HDCP_MAX_RECEIVERS 32 +#define HDCP_RECEIVER_ID_SIZE_BYTES 5 +#define HDCP_STATUS_SIZE 0x5 +#define HDCP_PORT_STS_AUTH 0x1 +#define HDCP_PORT_STS_LAST_ERR_SHIFT 0x5 +#define HDCP_PORT_STS_LAST_ERR_MASK (0x0F << 5) +#define GET_HDCP_PORT_STS_LAST_ERR(__sts__) \ + (((__sts__) & HDCP_PORT_STS_LAST_ERR_MASK) >> \ + HDCP_PORT_STS_LAST_ERR_SHIFT) + +#define HDCP_CONFIG_1_4 BIT(0) /* use HDCP 1.4 only */ +#define HDCP_CONFIG_2_2 BIT(1) /* use HDCP 2.2 only */ +/* use All HDCP versions */ +#define HDCP_CONFIG_ALL (BIT(0) | BIT(1)) +#define HDCP_CONFIG_NONE 0 + +enum { + HDCP_GENERAL_SET_LC_128, + HDCP_SET_SEED, +}; + +enum { + HDCP_TRAN_CONFIGURATION, + HDCP2X_TX_SET_PUBLIC_KEY_PARAMS, + HDCP2X_TX_SET_DEBUG_RANDOM_NUMBERS, + HDCP2X_TX_RESPOND_KM, + HDCP1_TX_SEND_KEYS, + HDCP1_TX_SEND_RANDOM_AN, + HDCP_TRAN_STATUS_CHANGE, + HDCP2X_TX_IS_KM_STORED, + HDCP2X_TX_STORE_KM, + HDCP_TRAN_IS_REC_ID_VALID, + HDCP_TRAN_RESPOND_RECEIVER_ID_VALID, + HDCP_TRAN_TEST_KEYS, + HDCP2X_TX_SET_KM_KEY_PARAMS, + HDCP_NUM_OF_SUPPORTED_MESSAGES +}; + +enum { + HDCP_CONTENT_TYPE_0, + HDCP_CONTENT_TYPE_1, +}; + +#define DRM_HDCP_CHECK_PERIOD_MS (128 * 16) + +#define HDCP_PAIRING_R_ID 5 +#define HDCP_PAIRING_M_LEN 16 +#define HDCP_KM_LEN 16 +#define HDCP_PAIRING_M_EKH 16 + +struct cdns_hdcp_pairing_data { + u8 receiver_id[HDCP_PAIRING_R_ID]; + u8 m[HDCP_PAIRING_M_LEN]; + u8 km[HDCP_KM_LEN]; + u8 ekh[HDCP_PAIRING_M_EKH]; +}; + +enum { + HDCP_TX_2, + HDCP_TX_1, + HDCP_TX_BOTH, +}; + +#define DLP_MODULUS_N 384 +#define DLP_E 3 + +struct cdns_hdcp_tx_public_key_param { + u8 N[DLP_MODULUS_N]; + u8 E[DLP_E]; +}; + +int cdns_mhdp_hdcp_set_public_key_param(struct cdns_mhdp_device *mhdp, + struct cdns_hdcp_tx_public_key_param *val); +int cdns_mhdp_hdcp_set_lc(struct cdns_mhdp_device *mhdp, u8 *val); +int cdns_mhdp_hdcp_enable(struct cdns_mhdp_device *mhdp, u8 content_type); +int cdns_mhdp_hdcp_disable(struct cdns_mhdp_device *mhdp); +void cdns_mhdp_hdcp_init(struct cdns_mhdp_device *mhdp); + +#endif -- cgit v1.2.3 From 2916059147ea38f76787d7b38dee883da2e9def2 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Mon, 12 Apr 2021 15:10:41 +0200 Subject: drm/aperture: Add infrastructure for aperture ownership Platform devices might operate on firmware framebuffers, such as VESA or EFI. Before a native driver for the graphics hardware can take over the device, it has to remove any platform driver that operates on the firmware framebuffer. Aperture helpers provide the infrastructure for native drivers to remove the generic ones. For now, this only concerns generic fbdev drivers. Code for removing these is provided by drm_fb_helper_remove_conflicting_framebuffers() et al. Simply wrap these functions for now. At a later point, code can be added for generic DRM drivers to acquire firmware framebuffers. v2: * fix docs for drm_aperture_remove_framebuffers() Signed-off-by: Thomas Zimmermann Acked-by: Daniel Vetter Acked-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20210412131043.5787-2-tzimmermann@suse.de --- Documentation/gpu/drm-internals.rst | 12 ++++ drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/drm_aperture.c | 114 ++++++++++++++++++++++++++++++++++++ include/drm/drm_aperture.h | 31 ++++++++++ 4 files changed, 158 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/drm_aperture.c create mode 100644 include/drm/drm_aperture.h (limited to 'drivers/gpu/drm') diff --git a/Documentation/gpu/drm-internals.rst b/Documentation/gpu/drm-internals.rst index 12272b168580..06af044c882f 100644 --- a/Documentation/gpu/drm-internals.rst +++ b/Documentation/gpu/drm-internals.rst @@ -75,6 +75,18 @@ update it, its value is mostly useless. The DRM core prints it to the kernel log at initialization time and passes it to userspace through the DRM_IOCTL_VERSION ioctl. +Managing Ownership of the Framebuffer Aperture +---------------------------------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_aperture.c + :doc: overview + +.. kernel-doc:: include/drm/drm_aperture.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_aperture.c + :export: + Device Instance and Driver Handling ----------------------------------- diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 5279db4392df..89e747fedc00 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -3,7 +3,7 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -drm-y := drm_auth.o drm_cache.o \ +drm-y := drm_aperture.o drm_auth.o drm_cache.o \ drm_file.o drm_gem.o drm_ioctl.o drm_irq.o \ drm_drv.o \ drm_sysfs.o drm_hashtab.o drm_mm.o \ diff --git a/drivers/gpu/drm/drm_aperture.c b/drivers/gpu/drm/drm_aperture.c new file mode 100644 index 000000000000..929dcbc0758a --- /dev/null +++ b/drivers/gpu/drm/drm_aperture.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: MIT + +#include +#include + +/** + * DOC: overview + * + * A graphics device might be supported by different drivers, but only one + * driver can be active at any given time. Many systems load a generic + * graphics drivers, such as EFI-GOP or VESA, early during the boot process. + * During later boot stages, they replace the generic driver with a dedicated, + * hardware-specific driver. To take over the device the dedicated driver + * first has to remove the generic driver. DRM aperture functions manage + * ownership of DRM framebuffer memory and hand-over between drivers. + * + * DRM drivers should call drm_aperture_remove_conflicting_framebuffers() + * at the top of their probe function. The function removes any generic + * driver that is currently associated with the given framebuffer memory. + * If the framebuffer is located at PCI BAR 0, the rsp code looks as in the + * example given below. + * + * .. code-block:: c + * + * static int remove_conflicting_framebuffers(struct pci_dev *pdev) + * { + * bool primary = false; + * resource_size_t base, size; + * int ret; + * + * base = pci_resource_start(pdev, 0); + * size = pci_resource_len(pdev, 0); + * #ifdef CONFIG_X86 + * primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; + * #endif + * + * return drm_aperture_remove_conflicting_framebuffers(base, size, primary, + * "example driver"); + * } + * + * static int probe(struct pci_dev *pdev) + * { + * int ret; + * + * // Remove any generic drivers... + * ret = remove_conflicting_framebuffers(pdev); + * if (ret) + * return ret; + * + * // ... and initialize the hardware. + * ... + * + * drm_dev_register(); + * + * return 0; + * } + * + * PCI device drivers should call + * drm_aperture_remove_conflicting_pci_framebuffers() and let it detect the + * framebuffer apertures automatically. Device drivers without knowledge of + * the framebuffer's location shall call drm_aperture_remove_framebuffers(), + * which removes all drivers for known framebuffer. + */ + +/** + * drm_aperture_remove_conflicting_framebuffers - remove existing framebuffers in the given range + * @base: the aperture's base address in physical memory + * @size: aperture size in bytes + * @primary: also kick vga16fb if present + * @name: requesting driver name + * + * This function removes graphics device drivers which use memory range described by + * @base and @size. + * + * Returns: + * 0 on success, or a negative errno code otherwise + */ +int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, + bool primary, const char *name) +{ + struct apertures_struct *a; + int ret; + + a = alloc_apertures(1); + if (!a) + return -ENOMEM; + + a->ranges[0].base = base; + a->ranges[0].size = size; + + ret = drm_fb_helper_remove_conflicting_framebuffers(a, name, primary); + kfree(a); + + return ret; +} +EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers); + +/** + * drm_aperture_remove_conflicting_pci_framebuffers - remove existing framebuffers for PCI devices + * @pdev: PCI device + * @name: requesting driver name + * + * This function removes graphics device drivers using memory range configured + * for any of @pdev's memory bars. The function assumes that PCI device with + * shadowed ROM drives a primary display and so kicks out vga16fb. + * + * Returns: + * 0 on success, or a negative errno code otherwise + */ +int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) +{ + return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, name); +} +EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers); diff --git a/include/drm/drm_aperture.h b/include/drm/drm_aperture.h new file mode 100644 index 000000000000..23cc01647ed3 --- /dev/null +++ b/include/drm/drm_aperture.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ + +#ifndef _DRM_APERTURE_H_ +#define _DRM_APERTURE_H_ + +#include + +struct pci_dev; + +int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, + bool primary, const char *name); + +int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); + +/** + * drm_aperture_remove_framebuffers - remove all existing framebuffers + * @primary: also kick vga16fb if present + * @name: requesting driver name + * + * This function removes all graphics device drivers. Use this function on systems + * that can have their framebuffer located anywhere in memory. + * + * Returns: + * 0 on success, or a negative errno code otherwise + */ +static inline int drm_aperture_remove_framebuffers(bool primary, const char *name) +{ + return drm_aperture_remove_conflicting_framebuffers(0, (resource_size_t)-1, primary, name); +} + +#endif -- cgit v1.2.3 From 6848c291a54f8cd1e8b32f4d6e0f681acc8d5095 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Mon, 12 Apr 2021 15:10:42 +0200 Subject: drm/aperture: Convert drivers to aperture interfaces Mass-convert all drivers from FB helpers to aperture interfaces. No functional changes besides checking for returned errno codes. Signed-off-by: Thomas Zimmermann Acked-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20210412131043.5787-3-tzimmermann@suse.de --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- drivers/gpu/drm/armada/armada_drv.c | 5 ++--- drivers/gpu/drm/ast/ast_drv.c | 23 +++++++++------------ drivers/gpu/drm/bochs/bochs_drv.c | 3 ++- drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 4 ++-- drivers/gpu/drm/i915/i915_drv.c | 3 ++- drivers/gpu/drm/meson/meson_drv.c | 27 ++++++++----------------- drivers/gpu/drm/mgag200/mgag200_drv.c | 5 ++++- drivers/gpu/drm/msm/msm_fbdev.c | 5 ++++- drivers/gpu/drm/nouveau/nouveau_drm.c | 3 ++- drivers/gpu/drm/qxl/qxl_drv.c | 5 ++++- drivers/gpu/drm/radeon/radeon_drv.c | 3 ++- drivers/gpu/drm/sun4i/sun4i_drv.c | 5 ++++- drivers/gpu/drm/tegra/drm.c | 4 ++-- drivers/gpu/drm/tiny/cirrus.c | 3 ++- drivers/gpu/drm/vboxvideo/vbox_drv.c | 3 ++- drivers/gpu/drm/vc4/vc4_drv.c | 5 ++++- drivers/gpu/drm/virtio/virtgpu_drv.c | 10 ++++++--- drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 4 ++-- 19 files changed, 67 insertions(+), 56 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index b26e2fd1c538..671ec1002230 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include @@ -1196,7 +1197,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, #endif /* Get rid of things like offb */ - ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); if (ret) return ret; diff --git a/drivers/gpu/drm/armada/armada_drv.c b/drivers/gpu/drm/armada/armada_drv.c index 44fe9f994fc5..dab0a1f0983b 100644 --- a/drivers/gpu/drm/armada/armada_drv.c +++ b/drivers/gpu/drm/armada/armada_drv.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -94,9 +95,7 @@ static int armada_drm_bind(struct device *dev) } /* Remove early framebuffers */ - ret = drm_fb_helper_remove_conflicting_framebuffers(NULL, - "armada-drm-fb", - false); + ret = drm_aperture_remove_framebuffers(false, "armada-drm-fb"); if (ret) { dev_err(dev, "[" DRM_NAME ":%s] can't kick out simple-fb: %d\n", __func__, ret); diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c index 01837bea18c2..5aa452b4efe6 100644 --- a/drivers/gpu/drm/ast/ast_drv.c +++ b/drivers/gpu/drm/ast/ast_drv.c @@ -30,10 +30,10 @@ #include #include +#include #include #include #include -#include #include #include @@ -89,23 +89,18 @@ static const struct pci_device_id ast_pciidlist[] = { MODULE_DEVICE_TABLE(pci, ast_pciidlist); -static void ast_kick_out_firmware_fb(struct pci_dev *pdev) +static int ast_remove_conflicting_framebuffers(struct pci_dev *pdev) { - struct apertures_struct *ap; bool primary = false; + resource_size_t base, size; - ap = alloc_apertures(1); - if (!ap) - return; - - ap->ranges[0].base = pci_resource_start(pdev, 0); - ap->ranges[0].size = pci_resource_len(pdev, 0); - + base = pci_resource_start(pdev, 0); + size = pci_resource_len(pdev, 0); #ifdef CONFIG_X86 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; #endif - drm_fb_helper_remove_conflicting_framebuffers(ap, "astdrmfb", primary); - kfree(ap); + + return drm_aperture_remove_conflicting_framebuffers(base, size, primary, "astdrmfb"); } static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -114,7 +109,9 @@ static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) struct drm_device *dev; int ret; - ast_kick_out_firmware_fb(pdev); + ret = ast_remove_conflicting_framebuffers(pdev); + if (ret) + return ret; ret = pcim_enable_device(pdev); if (ret) diff --git a/drivers/gpu/drm/bochs/bochs_drv.c b/drivers/gpu/drm/bochs/bochs_drv.c index b469624fe40d..c828cadbabff 100644 --- a/drivers/gpu/drm/bochs/bochs_drv.c +++ b/drivers/gpu/drm/bochs/bochs_drv.c @@ -6,6 +6,7 @@ #include #include +#include #include #include @@ -109,7 +110,7 @@ static int bochs_pci_probe(struct pci_dev *pdev, return -ENOMEM; } - ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "bochsdrmfb"); + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "bochsdrmfb"); if (ret) return ret; diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c index 89edc796deda..f4bc5386574a 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -313,8 +314,7 @@ static int hibmc_pci_probe(struct pci_dev *pdev, struct drm_device *dev; int ret; - ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, - "hibmcdrmfb"); + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "hibmcdrmfb"); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 8e9cb44e66e5..e1ae7b804c01 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -40,6 +40,7 @@ #include #include +#include #include #include #include @@ -557,7 +558,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) if (ret) goto err_perf; - ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb"); + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb"); if (ret) goto err_ggtt; diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c index 453d8b4c5763..66de3f4f7222 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -156,23 +157,6 @@ static void meson_vpu_init(struct meson_drm *priv) writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); } -static void meson_remove_framebuffers(void) -{ - struct apertures_struct *ap; - - ap = alloc_apertures(1); - if (!ap) - return; - - /* The framebuffer can be located anywhere in RAM */ - ap->ranges[0].base = 0; - ap->ranges[0].size = ~0; - - drm_fb_helper_remove_conflicting_framebuffers(ap, "meson-drm-fb", - false); - kfree(ap); -} - struct meson_drm_soc_attr { struct meson_drm_soc_limits limits; const struct soc_device_attribute *attrs; @@ -297,8 +281,13 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) } } - /* Remove early framebuffers (ie. simplefb) */ - meson_remove_framebuffers(); + /* + * Remove early framebuffers (ie. simplefb). The framebuffer can be + * located anywhere in RAM + */ + ret = drm_aperture_remove_framebuffers(false, "meson-drm-fb"); + if (ret) + goto free_drm; ret = drmm_mode_config_init(drm); if (ret) diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c b/drivers/gpu/drm/mgag200/mgag200_drv.c index 4e4c105f9a50..a701d9563257 100644 --- a/drivers/gpu/drm/mgag200/mgag200_drv.c +++ b/drivers/gpu/drm/mgag200/mgag200_drv.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -341,7 +342,9 @@ mgag200_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) struct drm_device *dev; int ret; - drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "mgag200drmfb"); + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "mgag200drmfb"); + if (ret) + return ret; ret = pcim_enable_device(pdev); if (ret) diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c index 678dba1725a6..227404077e39 100644 --- a/drivers/gpu/drm/msm/msm_fbdev.c +++ b/drivers/gpu/drm/msm/msm_fbdev.c @@ -4,6 +4,7 @@ * Author: Rob Clark */ +#include #include #include #include @@ -168,7 +169,9 @@ struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev) } /* the fw fb could be anywhere in memory */ - drm_fb_helper_remove_conflicting_framebuffers(NULL, "msm", false); + ret = drm_aperture_remove_framebuffers(false, "msm"); + if (ret) + goto fini; ret = drm_fb_helper_initial_config(helper, 32); if (ret) diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 9766218a99ca..3204fc0a90d2 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -30,6 +30,7 @@ #include #include +#include #include #include #include @@ -737,7 +738,7 @@ static int nouveau_drm_probe(struct pci_dev *pdev, nvkm_device_del(&device); /* Remove conflicting drivers (vesafb, efifb etc). */ - ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "nouveaufb"); + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "nouveaufb"); if (ret) return ret; diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c index db92eec07d96..bba0fc39028c 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.c +++ b/drivers/gpu/drm/qxl/qxl_drv.c @@ -29,11 +29,14 @@ */ #include "qxl_drv.h" + #include #include #include +#include #include +#include #include #include #include @@ -93,7 +96,7 @@ qxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (ret) return ret; - ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "qxl"); + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "qxl"); if (ret) goto disable_pci; diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index efeb115ae70e..8885e849717d 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -38,6 +38,7 @@ #include #include +#include #include #include #include @@ -330,7 +331,7 @@ static int radeon_pci_probe(struct pci_dev *pdev, return -EPROBE_DEFER; /* Get rid of things like offb */ - ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb"); + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb"); if (ret) return ret; diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c index 91502937f26d..af335f58bdfc 100644 --- a/drivers/gpu/drm/sun4i/sun4i_drv.c +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -99,7 +100,9 @@ static int sun4i_drv_bind(struct device *dev) drm->irq_enabled = true; /* Remove early framebuffers (ie. simplefb) */ - drm_fb_helper_remove_conflicting_framebuffers(NULL, "sun4i-drm-fb", false); + ret = drm_aperture_remove_framebuffers(false, "sun4i-drm-fb"); + if (ret) + goto cleanup_mode_config; sun4i_framebuffer_init(drm); diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 90709c38c993..e32c0dcf2762 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -1198,8 +1199,7 @@ static int host1x_drm_probe(struct host1x_device *dev) drm_mode_config_reset(drm); - err = drm_fb_helper_remove_conflicting_framebuffers(NULL, "tegradrmfb", - false); + err = drm_aperture_remove_framebuffers(false, "tegradrmfb"); if (err < 0) goto hub; diff --git a/drivers/gpu/drm/tiny/cirrus.c b/drivers/gpu/drm/tiny/cirrus.c index ad922c3ec681..e3afb45d9a5c 100644 --- a/drivers/gpu/drm/tiny/cirrus.c +++ b/drivers/gpu/drm/tiny/cirrus.c @@ -24,6 +24,7 @@ #include