From 4b09c07383132d67e4e297d4eb35dbae596ea74e Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 4 Nov 2018 19:26:46 +0100 Subject: drm/sun4i: Rework DE2 register defines Most, if not all, registers found in DE2 still exists in DE3. However, units are on different base addresses. To prepare for addition of DE3 support, registers macros are reworked so they take base address as parameter. Signed-off-by: Jernej Skrabec [rebased] Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-10-jernej.skrabec@siol.net --- drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 41 ++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/drm/sun4i/sun8i_ui_scaler.c') diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c index 6bb2aa164c8e..698401ecb53d 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c @@ -10,6 +10,7 @@ */ #include "sun8i_ui_scaler.h" +#include "sun8i_vi_scaler.h" static const u32 lan2coefftab16[240] = { 0x00004000, 0x00033ffe, 0x00063efc, 0x000a3bfb, @@ -88,6 +89,14 @@ static const u32 lan2coefftab16[240] = { 0x0b1c1603, 0x0d1c1502, 0x0e1d1401, 0x0f1d1301, }; +static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel) +{ + int vi_num = mixer->cfg->vi_num; + + return DE2_VI_SCALER_UNIT_BASE + DE2_VI_SCALER_UNIT_SIZE * vi_num + + DE2_UI_SCALER_UNIT_SIZE * (channel - vi_num); +} + static int sun8i_ui_scaler_coef_index(unsigned int step) { unsigned int scale, int_part, float_part; @@ -114,33 +123,35 @@ static int sun8i_ui_scaler_coef_index(unsigned int step) void sun8i_ui_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable) { - int vi_cnt = mixer->cfg->vi_num; - u32 val; + u32 val, base; - if (WARN_ON(layer < vi_cnt)) + if (WARN_ON(layer < mixer->cfg->vi_num)) return; + base = sun8i_ui_scaler_base(mixer, layer); + if (enable) val = SUN8I_SCALER_GSU_CTRL_EN | SUN8I_SCALER_GSU_CTRL_COEFF_RDY; else val = 0; - regmap_write(mixer->engine.regs, - SUN8I_SCALER_GSU_CTRL(vi_cnt, layer - vi_cnt), val); + regmap_write(mixer->engine.regs, SUN8I_SCALER_GSU_CTRL(base), val); } void sun8i_ui_scaler_setup(struct sun8i_mixer *mixer, int layer, u32 src_w, u32 src_h, u32 dst_w, u32 dst_h, u32 hscale, u32 vscale, u32 hphase, u32 vphase) { - int vi_cnt = mixer->cfg->vi_num; u32 insize, outsize; int i, offset; + u32 base; - if (WARN_ON(layer < vi_cnt)) + if (WARN_ON(layer < mixer->cfg->vi_num)) return; + base = sun8i_ui_scaler_base(mixer, layer); + hphase <<= SUN8I_UI_SCALER_PHASE_FRAC - 16; vphase <<= SUN8I_UI_SCALER_PHASE_FRAC - 16; hscale <<= SUN8I_UI_SCALER_SCALE_FRAC - 16; @@ -149,24 +160,22 @@ void sun8i_ui_scaler_setup(struct sun8i_mixer *mixer, int layer, insize = SUN8I_UI_SCALER_SIZE(src_w, src_h); outsize = SUN8I_UI_SCALER_SIZE(dst_w, dst_h); - layer -= vi_cnt; - regmap_write(mixer->engine.regs, - SUN8I_SCALER_GSU_OUTSIZE(vi_cnt, layer), outsize); + SUN8I_SCALER_GSU_OUTSIZE(base), outsize); regmap_write(mixer->engine.regs, - SUN8I_SCALER_GSU_INSIZE(vi_cnt, layer), insize); + SUN8I_SCALER_GSU_INSIZE(base), insize); regmap_write(mixer->engine.regs, - SUN8I_SCALER_GSU_HSTEP(vi_cnt, layer), hscale); + SUN8I_SCALER_GSU_HSTEP(base), hscale); regmap_write(mixer->engine.regs, - SUN8I_SCALER_GSU_VSTEP(vi_cnt, layer), vscale); + SUN8I_SCALER_GSU_VSTEP(base), vscale); regmap_write(mixer->engine.regs, - SUN8I_SCALER_GSU_HPHASE(vi_cnt, layer), hphase); + SUN8I_SCALER_GSU_HPHASE(base), hphase); regmap_write(mixer->engine.regs, - SUN8I_SCALER_GSU_VPHASE(vi_cnt, layer), vphase); + SUN8I_SCALER_GSU_VPHASE(base), vphase); offset = sun8i_ui_scaler_coef_index(hscale) * SUN8I_UI_SCALER_COEFF_COUNT; for (i = 0; i < SUN8I_UI_SCALER_COEFF_COUNT; i++) regmap_write(mixer->engine.regs, - SUN8I_SCALER_GSU_HCOEFF(vi_cnt, layer, i), + SUN8I_SCALER_GSU_HCOEFF(base, i), lan2coefftab16[offset + i]); } -- cgit v1.2.3