From 808032ee296ee7b37a6df090be40a330e09ae30e Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Sat, 6 Mar 2010 13:03:33 +0000 Subject: drm/radeon/kms: clean HDMI definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We already know same offsets are used for different encoders/transmitters, so just numeric them instead naming incorrectly. Additionaly we found additional registers needed for RV770+ Signed-off-by: Rafał Miłecki Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600_hdmi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/radeon/r600_hdmi.c') diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index fcc949df0e5d..4d09973ad6a6 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c @@ -470,27 +470,27 @@ void r600_hdmi_init(struct drm_encoder *encoder) case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - radeon_encoder->hdmi_offset = R600_HDMI_TMDS1; + radeon_encoder->hdmi_offset = R600_HDMI_BLOCK1; break; case ENCODER_OBJECT_ID_INTERNAL_LVTM1: switch (r600_audio_tmds_index(encoder)) { case 0: - radeon_encoder->hdmi_offset = R600_HDMI_TMDS1; + radeon_encoder->hdmi_offset = R600_HDMI_BLOCK1; break; case 1: - radeon_encoder->hdmi_offset = R600_HDMI_TMDS2; + radeon_encoder->hdmi_offset = R600_HDMI_BLOCK2; break; default: radeon_encoder->hdmi_offset = 0; break; } case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - radeon_encoder->hdmi_offset = R600_HDMI_TMDS2; + radeon_encoder->hdmi_offset = R600_HDMI_BLOCK2; break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - radeon_encoder->hdmi_offset = R600_HDMI_DIG; + radeon_encoder->hdmi_offset = R600_HDMI_BLOCK3; break; default: -- cgit v1.2.3