From 412e85b605315fd129a849599cf4a5a7959573a8 Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Thu, 1 Aug 2019 18:02:15 -0400 Subject: drm/nouveau: Only release VCPI slots on mode changes Looks like a regression got introduced into nv50_mstc_atomic_check() that somehow didn't get found until now. If userspace changes crtc_state->active to false but leaves the CRTC enabled, we end up calling drm_dp_atomic_find_vcpi_slots() using the PBN calculated in asyh->dp.pbn. However, if the display is inactive we end up calculating a PBN of 0, which inadvertently causes us to have an allocation of 0. >From there, if userspace then disables the CRTC afterwards we end up accidentally attempting to free the VCPI twice: WARNING: CPU: 0 PID: 1484 at drivers/gpu/drm/drm_dp_mst_topology.c:3336 drm_dp_atomic_release_vcpi_slots+0x87/0xb0 [drm_kms_helper] RIP: 0010:drm_dp_atomic_release_vcpi_slots+0x87/0xb0 [drm_kms_helper] Call Trace: drm_atomic_helper_check_modeset+0x3f3/0xa60 [drm_kms_helper] ? drm_atomic_check_only+0x43/0x780 [drm] drm_atomic_helper_check+0x15/0x90 [drm_kms_helper] nv50_disp_atomic_check+0x83/0x1d0 [nouveau] drm_atomic_check_only+0x54d/0x780 [drm] ? drm_atomic_set_crtc_for_connector+0xec/0x100 [drm] drm_atomic_commit+0x13/0x50 [drm] drm_atomic_helper_set_config+0x81/0x90 [drm_kms_helper] drm_mode_setcrtc+0x194/0x6a0 [drm] ? vprintk_emit+0x16a/0x230 ? drm_ioctl+0x163/0x390 [drm] ? drm_mode_getcrtc+0x180/0x180 [drm] drm_ioctl_kernel+0xaa/0xf0 [drm] drm_ioctl+0x208/0x390 [drm] ? drm_mode_getcrtc+0x180/0x180 [drm] nouveau_drm_ioctl+0x63/0xb0 [nouveau] do_vfs_ioctl+0x405/0x660 ? recalc_sigpending+0x17/0x50 ? _copy_from_user+0x37/0x60 ksys_ioctl+0x5e/0x90 ? exit_to_usermode_loop+0x92/0xe0 __x64_sys_ioctl+0x16/0x20 do_syscall_64+0x59/0x190 entry_SYSCALL_64_after_hwframe+0x44/0xa9 WARNING: CPU: 0 PID: 1484 at drivers/gpu/drm/drm_dp_mst_topology.c:3336 drm_dp_atomic_release_vcpi_slots+0x87/0xb0 [drm_kms_helper] ---[ end trace 4c395c0c51b1f88d ]--- [drm:drm_dp_atomic_release_vcpi_slots [drm_kms_helper]] *ERROR* no VCPI for [MST PORT:00000000e288eb7d] found in mst state 000000008e642070 So, fix this by doing what we probably should have done from the start: only call drm_dp_atomic_find_vcpi_slots() when crtc_state->mode_changed is set, so that VCPI allocations remain for as long as the CRTC is enabled. Signed-off-by: Lyude Paul Fixes: 232c9eec417a ("drm/nouveau: Use atomic VCPI helpers for MST") Cc: Lyude Paul Cc: Ben Skeggs Cc: Daniel Vetter Cc: David Airlie Cc: Jerry Zuo Cc: Harry Wentland Cc: Juston Li Cc: Karol Herbst Cc: Laurent Pinchart Cc: Ilia Mirkin Cc: # v5.1+ Acked-by: Ben Skeggs Signed-off-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/20190801220216.15323-1-lyude@redhat.com --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 8497768f1b41..126703816794 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -780,7 +780,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder, drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, connector->display_info.bpc * 3); - if (drm_atomic_crtc_needs_modeset(crtc_state)) { + if (crtc_state->mode_changed) { slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn); -- cgit v1.2.3 From db1231ddc04682f60d56ff42447f13099c6c4a4c Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Thu, 8 Aug 2019 20:53:05 -0400 Subject: drm/nouveau: Only recalculate PBN/VCPI on mode/connector changes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I -thought- I had fixed this entirely, but it looks like that I didn't test this thoroughly enough as we apparently still make one big mistake with nv50_msto_atomic_check() - we don't handle the following scenario: * CRTC #1 has n VCPI allocated to it, is attached to connector DP-4 which is attached to encoder #1. enabled=y active=n * CRTC #1 is changed from DP-4 to DP-5, causing: * DP-4 crtc=#1→NULL (VCPI n→0) * DP-5 crtc=NULL→#1 * CRTC #1 steals encoder #1 back from DP-4 and gives it to DP-5 * CRTC #1 maintains the same mode as before, just with a different connector * mode_changed=n connectors_changed=y (we _SHOULD_ do VCPI 0→n here, but don't) Once the above scenario is repeated once, we'll attempt freeing VCPI from the connector that we didn't allocate due to the connectors changing, but the mode staying the same. Sigh. Since nv50_msto_atomic_check() has broken a few times now, let's rethink things a bit to be more careful: limit both VCPI/PBN allocations to mode_changed || connectors_changed, since neither VCPI or PBN should ever need to change outside of routing and mode changes. Changes since v1: * Fix accidental reversal of clock and bpp arguments in drm_dp_calc_pbn_mode() - William Lewis Signed-off-by: Lyude Paul Reported-by: Bohdan Milar Tested-by: Bohdan Milar Fixes: 232c9eec417a ("drm/nouveau: Use atomic VCPI helpers for MST") References: 412e85b60531 ("drm/nouveau: Only release VCPI slots on mode changes") Cc: Lyude Paul Cc: Ben Skeggs Cc: Daniel Vetter Cc: David Airlie Cc: Jerry Zuo Cc: Harry Wentland Cc: Juston Li Cc: Laurent Pinchart Cc: Karol Herbst Cc: Ilia Mirkin Cc: # v5.1+ Acked-by: Ben Skeggs Signed-off-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/20190809005307.18391-1-lyude@redhat.com --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 126703816794..5c36c75232e6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -771,16 +771,20 @@ nv50_msto_atomic_check(struct drm_encoder *encoder, struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); int slots; - /* When restoring duplicated states, we need to make sure that the - * bw remains the same and avoid recalculating it, as the connector's - * bpc may have changed after the state was duplicated - */ - if (!state->duplicated) - asyh->dp.pbn = - drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, - connector->display_info.bpc * 3); + if (crtc_state->mode_changed || crtc_state->connectors_changed) { + /* + * When restoring duplicated states, we need to make sure that + * the bw remains the same and avoid recalculating it, as the + * connector's bpc may have changed after the state was + * duplicated + */ + if (!state->duplicated) { + const int bpp = connector->display_info.bpc * 3; + const int clock = crtc_state->adjusted_mode.clock; + + asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, bpp); + } - if (crtc_state->mode_changed) { slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn); -- cgit v1.2.3 From c587cd6fc8b3ed497d1b478ba789311b3156d560 Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sun, 19 May 2019 16:00:42 +0200 Subject: drm/nouveau: drop drmP.h from nouveau_drv.h Drop the deprecated drmP.h header from nouveau_drv.h. Fix fallout in other parts of the driver. Build tested using allmodconfig and allyesconfig. Signed-off-by: Sam Ravnborg Cc: Ben Skeggs Cc: nouveau@lists.freedesktop.org Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 2 ++ drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 1 + drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 ++ drivers/gpu/drm/nouveau/nouveau_display.h | 4 ++++ drivers/gpu/drm/nouveau/nouveau_drv.h | 5 ++++- 5 files changed, 13 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index d5e295ca2caa..80e020611bcb 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -25,7 +25,9 @@ #include #include +#include #include + #include "nouveau_bo.h" void diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index cc417664f823..7354aaf79158 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -23,6 +23,7 @@ #include "atom.h" #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 027a01b97d1c..2dfb652d1e93 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -26,6 +26,8 @@ #include #include +#include + #include "nouveau_bo.h" static void diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h index 9185f01e2d9b..6e8e66882e45 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.h +++ b/drivers/gpu/drm/nouveau/nouveau_display.h @@ -1,9 +1,13 @@ /* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_DISPLAY_H__ #define __NOUVEAU_DISPLAY_H__ + #include "nouveau_drv.h" + #include +#include + struct nouveau_framebuffer { struct drm_framebuffer base; struct nouveau_bo *nvbo; diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index aae035816383..62e01919bb5f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -46,7 +46,10 @@ #include #include -#include +#include +#include +#include +#include #include #include -- cgit v1.2.3 From 690ae20c0426f8a6f48d2c285a53c465ebcb0c1f Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sun, 19 May 2019 16:00:44 +0200 Subject: drm/nouveau: drop use of drmp.h Drop use of the deprecated drmP.h file from drm/nouveau. Build tested using allyesconfig and allmodconfig. Signed-off-by: Sam Ravnborg Cc: Ben Skeggs Cc: nouveau@lists.freedesktop.org Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv04/arb.c | 2 -- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 3 ++- drivers/gpu/drm/nouveau/dispnv04/cursor.c | 1 - drivers/gpu/drm/nouveau/dispnv04/dac.c | 1 - drivers/gpu/drm/nouveau/dispnv04/dfp.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/disp.c | 1 - drivers/gpu/drm/nouveau/dispnv04/hw.c | 1 - drivers/gpu/drm/nouveau/dispnv04/overlay.c | 1 - drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c | 1 - drivers/gpu/drm/nouveau/dispnv04/tvnv04.c | 1 - drivers/gpu/drm/nouveau/dispnv04/tvnv17.c | 1 - drivers/gpu/drm/nouveau/dispnv50/disp.c | 4 ++-- drivers/gpu/drm/nouveau/nouveau_bios.c | 2 -- drivers/gpu/drm/nouveau/nouveau_connector.c | 1 - drivers/gpu/drm/nouveau/nouveau_display.c | 4 +++- drivers/gpu/drm/nouveau/nouveau_dp.c | 1 - drivers/gpu/drm/nouveau/nouveau_drm.c | 3 ++- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 2 +- drivers/gpu/drm/nouveau/nouveau_fence.c | 3 +-- drivers/gpu/drm/nouveau/nouveau_hwmon.c | 2 -- drivers/gpu/drm/nouveau/nouveau_ioc32.c | 3 ++- drivers/gpu/drm/nouveau/nouveau_prime.c | 1 - drivers/gpu/drm/nouveau/nouveau_vga.c | 1 - 23 files changed, 14 insertions(+), 28 deletions(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv04/arb.c b/drivers/gpu/drm/nouveau/dispnv04/arb.c index c79160c37f84..362495535e69 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/arb.c +++ b/drivers/gpu/drm/nouveau/dispnv04/arb.c @@ -21,8 +21,6 @@ * SOFTWARE. */ -#include - #include "nouveau_drv.h" #include "nouveau_reg.h" #include "hw.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index f22f01020625..210f13b145c1 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -24,9 +24,10 @@ */ #include -#include #include +#include #include +#include #include "nouveau_drv.h" #include "nouveau_reg.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/cursor.c b/drivers/gpu/drm/nouveau/dispnv04/cursor.c index 16e09f6b9113..4c6440d29c3f 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/cursor.c +++ b/drivers/gpu/drm/nouveau/dispnv04/cursor.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: MIT -#include #include #include "nouveau_drv.h" #include "nouveau_reg.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/dac.c b/drivers/gpu/drm/nouveau/dispnv04/dac.c index e7af95d37ddb..e8eef88a8382 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dac.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dac.c @@ -24,7 +24,6 @@ * DEALINGS IN THE SOFTWARE. */ -#include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/dfp.c b/drivers/gpu/drm/nouveau/dispnv04/dfp.c index 73d41abbb510..f9f4482c79b5 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dfp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dfp.c @@ -24,8 +24,8 @@ * DEALINGS IN THE SOFTWARE. */ -#include #include +#include #include "nouveau_drv.h" #include "nouveau_reg.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c index 5713bacaee80..0f8e186f3d07 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c @@ -22,7 +22,6 @@ * Author: Ben Skeggs */ -#include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c index 0c9bdf023f5b..3fdfafa8b0ad 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/hw.c +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c @@ -22,7 +22,6 @@ * SOFTWARE. */ -#include #include "nouveau_drv.h" #include "hw.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c index df4358e31075..a3a0a73ae8ab 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c @@ -23,7 +23,6 @@ * written by Arthur Huillet. */ -#include #include #include diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c b/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c index 2b83b2c39d1d..2f6d2b6711ab 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c +++ b/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c @@ -24,7 +24,6 @@ * */ -#include #include #include "nouveau_drv.h" #include "nouveau_encoder.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c index de4490b4ed30..b701a4d8fe76 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c +++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c @@ -24,7 +24,6 @@ * */ -#include #include "nouveau_drv.h" #include "nouveau_reg.h" #include "nouveau_encoder.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c index 26fd71c06626..03466f04c741 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c +++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c @@ -24,7 +24,6 @@ * */ -#include #include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 126703816794..7ce7145f82b8 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -30,14 +30,14 @@ #include #include -#include #include #include +#include #include #include #include #include -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index 66bf2aff4a3e..1e93f82c96fa 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -22,8 +22,6 @@ * SOFTWARE. */ -#include - #include "nouveau_drv.h" #include "nouveau_reg.h" #include "dispnv04/hw.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 330d7d29a6e3..94dfa2e5a9ab 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -29,7 +29,6 @@ #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 98afc50162e9..6f038511a03a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -25,12 +25,14 @@ */ #include -#include + #include #include #include #include +#include #include +#include #include "nouveau_fbcon.h" #include "nouveau_crtc.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c index 0d052e1660f8..2674f1587457 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dp.c +++ b/drivers/gpu/drm/nouveau/nouveau_dp.c @@ -22,7 +22,6 @@ * Authors: Ben Skeggs */ -#include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 7e045580a3a4..bdc948352467 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -29,8 +29,9 @@ #include #include -#include #include +#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 73cc3217068a..f439f0a5b43a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -37,10 +37,10 @@ #include #include -#include #include #include #include +#include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c index 8df390078c85..9118df035b28 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/drivers/gpu/drm/nouveau/nouveau_fence.c @@ -24,10 +24,9 @@ * */ -#include - #include #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c index 6af2d299c3f9..d445c6f3fece 100644 --- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c +++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c @@ -29,8 +29,6 @@ #include #include -#include - #include "nouveau_drv.h" #include "nouveau_hwmon.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_ioc32.c b/drivers/gpu/drm/nouveau/nouveau_ioc32.c index 462679a8fec5..adf01ca9e035 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ioc32.c +++ b/drivers/gpu/drm/nouveau/nouveau_ioc32.c @@ -33,7 +33,8 @@ #include -#include +#include +#include #include "nouveau_ioctl.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c index 7262ced9688a..6a222cdf2935 100644 --- a/drivers/gpu/drm/nouveau/nouveau_prime.c +++ b/drivers/gpu/drm/nouveau/nouveau_prime.c @@ -22,7 +22,6 @@ * Authors: Dave Airlie */ -#include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.c b/drivers/gpu/drm/nouveau/nouveau_vga.c index 8f4b12a8092c..d865d8aeac3c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_vga.c +++ b/drivers/gpu/drm/nouveau/nouveau_vga.c @@ -2,7 +2,6 @@ #include #include -#include #include #include -- cgit v1.2.3 From 0446f48cb53d0fa2e122504ce235fcb25b1e2a19 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 28 May 2019 16:33:59 +1000 Subject: drm/nouveau/kms/gv100: allow windows to use PACKED8BPP formats Required for upcoming FP16 scanout support. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c index 7860774b65bc..40d9b654ab8c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c @@ -82,7 +82,7 @@ corec37d_init(struct nv50_core *core) for (i = 0; i < windows; i++) { evo_mthd(push, 0x1000 + (i * 0x080), 3); evo_data(push, i >> 1); - evo_data(push, 0x00000017); + evo_data(push, 0x0000001f); evo_data(push, 0x00000000); evo_mthd(push, 0x1010 + (i * 0x080), 1); evo_data(push, 0x00127fff); -- cgit v1.2.3 From 1e339ab2ac3c769c1b06b9fb7d532f8495ebc56d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 29 May 2019 15:44:57 +1000 Subject: drm/nouveau/kms/tu102-: disable input lut when input is already FP16 On Turing, an input LUT is required to transform inputs in fixed-point formats to FP16 for the internal display pipe. We provide an identity mapping whenever a window is enabled for this reason. HW has error checks to ensure when the input is already FP16, that the input LUT is also disabled. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 2dfb652d1e93..5a8af9a0479a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -322,7 +322,9 @@ nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, asyh->wndw.olut &= ~BIT(wndw->id); } - if (!ilut && wndw->func->ilut_identity) { + if (!ilut && wndw->func->ilut_identity && + asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F && + asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) { static struct drm_property_blob dummy = {}; ilut = &dummy; } -- cgit v1.2.3 From ebf8ca6b3d6d7310646b092f3d5219abe2858e81 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 29 May 2019 16:39:53 +1000 Subject: drm/nouveau/kms/nv50-: disable input lut harder Under some circumstances, it could be left enabled when it shouldn't be. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 5a8af9a0479a..0aaa7e0013f6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -336,6 +336,8 @@ nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, asyw->xlut.handle = wndw->wndw.vram.handle; asyw->xlut.i.buffer = !asyw->xlut.i.buffer; asyw->set.xlut = true; + } else { + asyw->clr.xlut = armw->xlut.handle != 0; } /* Handle setting base SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT. */ -- cgit v1.2.3 From 38a72243235ecf2c1359ce66ebed29a7dfb680f7 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Mon, 27 May 2019 22:58:37 -0400 Subject: drm/nouveau/kms/nv50-: add fp16 scanout support Older hardware seems to want 0..1024 values, while new hardware takes 0..1 values. We set the gain to 1024 for the earlier display classes. Signed-off-by: Ilia Mirkin Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 24 ++++++++++++++++++++---- drivers/gpu/drm/nouveau/dispnv50/base827c.c | 11 ++++++++++- drivers/gpu/drm/nouveau/dispnv50/base917c.c | 2 ++ drivers/gpu/drm/nouveau/dispnv50/ovly907e.c | 17 ++++++++++++++++- drivers/gpu/drm/nouveau/dispnv50/ovly917e.c | 2 ++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 26 ++++++++++++++------------ drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 ++ 7 files changed, 66 insertions(+), 18 deletions(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index 80e020611bcb..00a85f1e1a4a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -58,12 +58,21 @@ static void base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { u32 *push; - if ((push = evo_wait(&wndw->wndw, 10))) { + if ((push = evo_wait(&wndw->wndw, 13))) { evo_mthd(push, 0x0084, 1); evo_data(push, asyw->image.mode << 8 | asyw->image.interval << 4); evo_mthd(push, 0x00c0, 1); evo_data(push, asyw->image.handle[0]); + if (asyw->image.format == 0xca) { + evo_mthd(push, 0x0110, 2); + evo_data(push, 1); + evo_data(push, 0x6400); + } else { + evo_mthd(push, 0x0110, 2); + evo_data(push, 0); + evo_data(push, 0); + } evo_mthd(push, 0x0800, 5); evo_data(push, asyw->image.offset[0] >> 8); evo_data(push, 0x00000000); @@ -181,9 +190,6 @@ base507c_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, const struct drm_framebuffer *fb = asyw->state.fb; int ret; - if (!fb->format->depth) - return -EINVAL; - ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state, DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING, @@ -202,6 +208,14 @@ base507c_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, asyh->base.y = asyw->state.src.y1 >> 16; asyh->base.w = asyw->state.fb->width; asyh->base.h = asyw->state.fb->height; + + /* Some newer formats, esp FP16 ones, don't have a + * "depth". There's nothing that really makes sense there + * either, so just set it to the implicit bit count. + */ + if (!asyh->base.depth) + asyh->base.depth = asyh->base.cpp * 8; + return 0; } @@ -217,6 +231,8 @@ base507c_format[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_XBGR8888, DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR16161616F, + DRM_FORMAT_ABGR16161616F, 0 }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/base827c.c b/drivers/gpu/drm/nouveau/dispnv50/base827c.c index 73646819a0d6..f4c05949dd62 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base827c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base827c.c @@ -25,12 +25,21 @@ static void base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { u32 *push; - if ((push = evo_wait(&wndw->wndw, 10))) { + if ((push = evo_wait(&wndw->wndw, 13))) { evo_mthd(push, 0x0084, 1); evo_data(push, asyw->image.mode << 8 | asyw->image.interval << 4); evo_mthd(push, 0x00c0, 1); evo_data(push, asyw->image.handle[0]); + if (asyw->image.format == 0xca) { + evo_mthd(push, 0x0110, 2); + evo_data(push, 1); + evo_data(push, 0x6400); + } else { + evo_mthd(push, 0x0110, 2); + evo_data(push, 0); + evo_data(push, 0); + } evo_mthd(push, 0x0800, 5); evo_data(push, asyw->image.offset[0] >> 8); evo_data(push, 0x00000000); diff --git a/drivers/gpu/drm/nouveau/dispnv50/base917c.c b/drivers/gpu/drm/nouveau/dispnv50/base917c.c index 54d705bb81a5..a1baed4fe0e9 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base917c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base917c.c @@ -36,6 +36,8 @@ base917c_format[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_XRGB2101010, DRM_FORMAT_ARGB2101010, + DRM_FORMAT_XBGR16161616F, + DRM_FORMAT_ABGR16161616F, 0 }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c index a3ce53046015..f947117d62b1 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c @@ -61,10 +61,25 @@ ovly907e = { .update = ovly507e_update, }; +static const u32 +ovly907e_format[] = { + DRM_FORMAT_YUYV, + DRM_FORMAT_UYVY, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_XRGB1555, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_XBGR16161616F, + DRM_FORMAT_ABGR16161616F, + 0 +}; + int ovly907e_new(struct nouveau_drm *drm, int head, s32 oclass, struct nv50_wndw **pwndw) { - return ovly507e_new_(&ovly907e, ovly827e_format, drm, head, oclass, + return ovly507e_new_(&ovly907e, ovly907e_format, drm, head, oclass, 0x00000004 << (head * 4), pwndw); } diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c index 505fa7e78523..fab567e258f9 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c @@ -33,6 +33,8 @@ ovly917e_format[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_XRGB2101010, DRM_FORMAT_ARGB2101010, + DRM_FORMAT_XBGR16161616F, + DRM_FORMAT_ABGR16161616F, 0 }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 0aaa7e0013f6..dd01ea21da97 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -204,18 +204,20 @@ static int nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw) { switch (asyw->state.fb->format->format) { - case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; - case DRM_FORMAT_XRGB8888 : - case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break; - case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; - case DRM_FORMAT_XRGB1555 : - case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break; - case DRM_FORMAT_XBGR2101010: - case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break; - case DRM_FORMAT_XBGR8888 : - case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break; - case DRM_FORMAT_XRGB2101010: - case DRM_FORMAT_ARGB2101010: asyw->image.format = 0xdf; break; + case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; + case DRM_FORMAT_XRGB8888 : + case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break; + case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; + case DRM_FORMAT_XRGB1555 : + case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break; + case DRM_FORMAT_XBGR2101010 : + case DRM_FORMAT_ABGR2101010 : asyw->image.format = 0xd1; break; + case DRM_FORMAT_XBGR8888 : + case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break; + case DRM_FORMAT_XRGB2101010 : + case DRM_FORMAT_ARGB2101010 : asyw->image.format = 0xdf; break; + case DRM_FORMAT_XBGR16161616F: + case DRM_FORMAT_ABGR16161616F: asyw->image.format = 0xca; break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index e52a85c83f7a..826d1d760d3a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -216,6 +216,8 @@ wndwc37e_format[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_XRGB2101010, DRM_FORMAT_ARGB2101010, + DRM_FORMAT_XBGR16161616F, + DRM_FORMAT_ABGR16161616F, 0 }; -- cgit v1.2.3 From 7c844e9d95fb210b40398516d3d7525e8fa38a5f Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Mon, 3 Jun 2019 01:59:42 -0400 Subject: drm/nouveau/kms/nv50-: remove overlay alpha formats The overlay logic can only do colorkey-based selection, not alpha-blending. Signed-off-by: Ilia Mirkin Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 2 -- drivers/gpu/drm/nouveau/dispnv50/ovly827e.c | 3 --- drivers/gpu/drm/nouveau/dispnv50/ovly907e.c | 4 ---- drivers/gpu/drm/nouveau/dispnv50/ovly917e.c | 5 ----- 4 files changed, 14 deletions(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index 7354aaf79158..8ccd96113bad 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -161,9 +161,7 @@ ovly507e_format[] = { DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB1555, 0 }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c index aaa9fe5a4fc8..2e68fc736fe1 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c @@ -90,11 +90,8 @@ ovly827e_format[] = { DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_XBGR2101010, - DRM_FORMAT_ABGR2101010, 0 }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c index f947117d62b1..9efe5e9d5ce4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c @@ -66,13 +66,9 @@ ovly907e_format[] = { DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_XBGR2101010, - DRM_FORMAT_ABGR2101010, DRM_FORMAT_XBGR16161616F, - DRM_FORMAT_ABGR16161616F, 0 }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c index fab567e258f9..e24d6fd23450 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c @@ -26,15 +26,10 @@ ovly917e_format[] = { DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_XBGR2101010, - DRM_FORMAT_ABGR2101010, DRM_FORMAT_XRGB2101010, - DRM_FORMAT_ARGB2101010, DRM_FORMAT_XBGR16161616F, - DRM_FORMAT_ABGR16161616F, 0 }; -- cgit v1.2.3 From 88b703527ba70659365d989f29579f1292ebf9c3 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Tue, 11 Jun 2019 22:40:36 -0400 Subject: drm/nouveau/kms/gf119-: add ctm property support This adds support on GF119:GV100 (exclusive) for CTM (aka CSC). Signed-off-by: Ilia Mirkin --- drivers/gpu/drm/nouveau/dispnv50/atom.h | 6 +++ drivers/gpu/drm/nouveau/dispnv50/base907c.c | 65 +++++++++++++++++++++++++++++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 14 +++++++ drivers/gpu/drm/nouveau/dispnv50/wndw.h | 4 ++ 4 files changed, 89 insertions(+) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/atom.h b/drivers/gpu/drm/nouveau/dispnv50/atom.h index b5fae5ab3fa8..75bda111da10 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/atom.h +++ b/drivers/gpu/drm/nouveau/dispnv50/atom.h @@ -184,6 +184,11 @@ struct nv50_wndw_atom { } i; } xlut; + struct { + u32 matrix[12]; + bool valid; + } csc; + struct { u8 mode:2; u8 interval:4; @@ -221,6 +226,7 @@ struct nv50_wndw_atom { bool ntfy:1; bool sema:1; bool xlut:1; + bool csc:1; bool image:1; bool scale:1; bool point:1; diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index 049ce6da321c..fd0c1d84730b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -83,6 +83,68 @@ base907c_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) asyw->xlut.i.load = head907d_olut_load; } +static inline u32 +csc_drm_to_base(u64 in) +{ + /* base takes a 19-bit 2's complement value in S3.16 format */ + bool sign = in & BIT_ULL(63); + u32 integer = (in >> 32) & 0x7fffffff; + u32 fraction = in & 0xffffffff; + + if (integer >= 4) { + return (1 << 18) - (sign ? 0 : 1); + } else { + u32 ret = (integer << 16) | (fraction >> 16); + if (sign) + ret = -ret; + return ret & GENMASK(18, 0); + } +} + +static void +base907c_csc(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, + const struct drm_color_ctm *ctm) +{ + int i, j; + + for (j = 0; j < 3; j++) { + for (i = 0; i < 4; i++) { + u32 *val = &asyw->csc.matrix[j * 4 + i]; + /* DRM does not support constant offset, while + * HW CSC does. Skip it. */ + if (i == 3) { + *val = 0; + } else { + *val = csc_drm_to_base(ctm->matrix[j * 3 + i]); + } + } + } +} + +static void +base907c_csc_clr(struct nv50_wndw *wndw) +{ + u32 *push; + if ((push = evo_wait(&wndw->wndw, 2))) { + evo_mthd(push, 0x0140, 1); + evo_data(push, 0x00000000); + evo_kick(push, &wndw->wndw); + } +} + +static void +base907c_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) +{ + u32 *push, i; + if ((push = evo_wait(&wndw->wndw, 13))) { + evo_mthd(push, 0x0140, 12); + evo_data(push, asyw->csc.matrix[0] | 0x80000000); + for (i = 1; i < 12; i++) + evo_data(push, asyw->csc.matrix[i]); + evo_kick(push, &wndw->wndw); + } +} + const struct nv50_wndw_func base907c = { .acquire = base507c_acquire, @@ -94,6 +156,9 @@ base907c = { .ntfy_clr = base507c_ntfy_clr, .ntfy_wait_begun = base507c_ntfy_wait_begun, .ilut = base907c_ilut, + .csc = base907c_csc, + .csc_set = base907c_csc_set, + .csc_clr = base907c_csc_clr, .olut_core = true, .xlut_set = base907c_xlut_set, .xlut_clr = base907c_xlut_clr, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index dd01ea21da97..c8d078629722 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -120,6 +120,7 @@ nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush, if (clr.sema ) wndw->func-> sema_clr(wndw); if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); if (clr.xlut ) wndw->func-> xlut_clr(wndw); + if (clr.csc ) wndw->func-> csc_clr(wndw); if (clr.image) wndw->func->image_clr(wndw); interlock[wndw->interlock.type] |= wndw->interlock.data; @@ -147,6 +148,7 @@ nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, wndw->func->xlut_set(wndw, asyw); } + if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); if (asyw->set.scale) wndw->func->scale_set(wndw, asyw); if (asyw->set.point) { if (asyw->set.point = false, asyw->set.mask) @@ -347,6 +349,16 @@ nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle))) asyw->set.xlut = true; + if (wndw->func->csc && asyh->state.ctm) { + const struct drm_color_ctm *ctm = asyh->state.ctm->data; + wndw->func->csc(wndw, asyw, ctm); + asyw->csc.valid = true; + asyw->set.csc = true; + } else { + asyw->csc.valid = false; + asyw->clr.csc = armw->csc.valid; + } + /* Can't do an immediate flip while changing the LUT. */ asyh->state.pageflip_flags &= ~DRM_MODE_PAGE_FLIP_ASYNC; } @@ -416,6 +428,7 @@ nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) asyw->clr.ntfy = armw->ntfy.handle != 0; asyw->clr.sema = armw->sema.handle != 0; asyw->clr.xlut = armw->xlut.handle != 0; + asyw->clr.csc = armw->csc.valid; if (wndw->func->image_clr) asyw->clr.image = armw->image.handle[0] != 0; } @@ -507,6 +520,7 @@ nv50_wndw_atomic_duplicate_state(struct drm_plane *plane) asyw->ntfy = armw->ntfy; asyw->ilut = NULL; asyw->xlut = armw->xlut; + asyw->csc = armw->csc; asyw->image = armw->image; asyw->point = armw->point; asyw->clr.mask = 0; diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 03f3d8dc235a..1e781d80c990 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -65,6 +65,10 @@ struct nv50_wndw_func { int (*ntfy_wait_begun)(struct nouveau_bo *, u32 offset, struct nvif_device *); void (*ilut)(struct nv50_wndw *, struct nv50_wndw_atom *); + void (*csc)(struct nv50_wndw *, struct nv50_wndw_atom *, + const struct drm_color_ctm *); + void (*csc_set)(struct nv50_wndw *, struct nv50_wndw_atom *); + void (*csc_clr)(struct nv50_wndw *); bool ilut_identity; bool olut_core; void (*xlut_set)(struct nv50_wndw *, struct nv50_wndw_atom *); -- cgit v1.2.3 From af364a447b4ac34c719751fdec5dbdd74d888c3b Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Mon, 10 Jun 2019 22:32:45 -0400 Subject: drm/nouveau/kms/nv50-: enable modern color management properties For GF119:GV100, we can enable DEGAMMA/CTM/GAMMA. For earlier GPUs, as there is no CTM, having both degamma and gamma is a bit pointless. Later GPUs currently lack an implementation. Signed-off-by: Ilia Mirkin Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/head.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index 929d93b1677e..46e7f4c51f10 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c @@ -512,6 +512,11 @@ nv50_head_create(struct drm_device *dev, int index) &nv50_head_func, "head-%d", head->base.index); drm_crtc_helper_add(crtc, &nv50_head_help); drm_mode_crtc_set_gamma_size(crtc, 256); + if (disp->disp->object.oclass >= GF110_DISP && + disp->disp->object.oclass < GV100_DISP) + drm_crtc_enable_color_mgmt(crtc, 256, true, 256); + else + drm_crtc_enable_color_mgmt(crtc, 0, false, 256); if (head->func->olut_set) { ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut); -- cgit v1.2.3 From 2c7442ea17f32a9d6eb8c6672478e7a6fafd4631 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 14:54:32 +1000 Subject: drm/nouveau/kms/gv100-: use premultiplied alpha blending between planes This is apparently the assumed default behaviour when blend properties are absent. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 826d1d760d3a..8a4f0e436be6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -107,10 +107,10 @@ wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) asyw->state.crtc_w); /*XXX: Composition-related stuff. Need to implement properly. */ - evo_mthd(push, 0x02ec, 1); + evo_mthd(push, 0x02ec, 7); evo_data(push, (2 - (wndw->id & 1)) << 4); - evo_mthd(push, 0x02f4, 5); - evo_data(push, 0x00000011); + evo_data(push, 0x000000ff); + evo_data(push, 0x00007722); evo_data(push, 0xffff0000); evo_data(push, 0xffff0000); evo_data(push, 0xffff0000); -- cgit v1.2.3 From dffa487822d1ff8f44817124d8f2927057a57775 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 17:46:39 +1000 Subject: drm/nouveau/kms/gv100-: implement csc + enable modern colour managment properties Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/base907c.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/head.c | 3 +- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 4 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 26 ++++++++++- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 71 ++++++++++++++++++++++++++++- 5 files changed, 99 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index fd0c1d84730b..5f2de77e0f32 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -101,7 +101,7 @@ csc_drm_to_base(u64 in) } } -static void +void base907c_csc(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, const struct drm_color_ctm *ctm) { diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index 46e7f4c51f10..0d1108eadcff 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c @@ -512,8 +512,7 @@ nv50_head_create(struct drm_device *dev, int index) &nv50_head_func, "head-%d", head->base.index); drm_crtc_helper_add(crtc, &nv50_head_help); drm_mode_crtc_set_gamma_size(crtc, 256); - if (disp->disp->object.oclass >= GF110_DISP && - disp->disp->object.oclass < GV100_DISP) + if (disp->disp->object.oclass >= GF110_DISP) drm_crtc_enable_color_mgmt(crtc, 256, true, 256); else drm_crtc_enable_color_mgmt(crtc, 0, false, 256); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 1e781d80c990..59ff8f082542 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -85,6 +85,9 @@ extern const struct drm_plane_funcs nv50_wndw; void base507c_ntfy_reset(struct nouveau_bo *, u32); int base507c_ntfy_wait_begun(struct nouveau_bo *, u32, struct nvif_device *); +void base907c_csc(struct nv50_wndw *, struct nv50_wndw_atom *, + const struct drm_color_ctm *); + struct nv50_wimm_func { void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *); @@ -106,7 +109,6 @@ void wndwc37e_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_sema_clr(struct nv50_wndw *); void wndwc37e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_ntfy_clr(struct nv50_wndw *); -void wndwc37e_image_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_image_clr(struct nv50_wndw *); void wndwc37e_update(struct nv50_wndw *, u32 *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 8a4f0e436be6..0d270cd5ac4c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -28,6 +28,23 @@ #include +static void +wndwc37e_csc_clr(struct nv50_wndw *wndw) +{ +} + +static void +wndwc37e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) +{ + u32 *push, i; + if ((push = evo_wait(&wndw->wndw, 13))) { + evo_mthd(push, 0x02bc, 12); + for (i = 0; i < 12; i++) + evo_data(push, asyw->csc.matrix[i]); + evo_kick(push, &wndw->wndw); + } +} + static void wndwc37e_ilut_clr(struct nv50_wndw *wndw) { @@ -77,7 +94,7 @@ wndwc37e_image_clr(struct nv50_wndw *wndw) } } -void +static void wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { u32 *push; @@ -90,7 +107,9 @@ wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) evo_mthd(push, 0x0224, 4); evo_data(push, asyw->image.h << 16 | asyw->image.w); evo_data(push, asyw->image.layout << 4 | asyw->image.blockh); - evo_data(push, asyw->image.colorspace << 8 | asyw->image.format); + evo_data(push, asyw->csc.valid << 17 | + asyw->image.colorspace << 8 | + asyw->image.format); evo_data(push, asyw->image.blocks[0] | (asyw->image.pitch[0] >> 6)); evo_mthd(push, 0x0240, 1); evo_data(push, asyw->image.handle[0]); @@ -234,6 +253,9 @@ wndwc37e = { .ilut = wndwc37e_ilut, .xlut_set = wndwc37e_ilut_set, .xlut_clr = wndwc37e_ilut_clr, + .csc = base907c_csc, + .csc_set = wndwc37e_csc_set, + .csc_clr = wndwc37e_csc_clr, .image_set = wndwc37e_image_set, .image_clr = wndwc37e_image_clr, .update = wndwc37e_update, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index ba89f1a5fcfa..d5e4b006ae1e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -28,6 +28,72 @@ #include +static void +wndwc57e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) +{ + u32 *push; + + if (!(push = evo_wait(&wndw->wndw, 17))) + return; + + evo_mthd(push, 0x0308, 1); + evo_data(push, asyw->image.mode << 4 | asyw->image.interval); + evo_mthd(push, 0x0224, 4); + evo_data(push, asyw->image.h << 16 | asyw->image.w); + evo_data(push, asyw->image.layout << 4 | asyw->image.blockh); + evo_data(push, asyw->image.colorspace << 8 | + asyw->image.format); + evo_data(push, asyw->image.blocks[0] | (asyw->image.pitch[0] >> 6)); + evo_mthd(push, 0x0240, 1); + evo_data(push, asyw->image.handle[0]); + evo_mthd(push, 0x0260, 1); + evo_data(push, asyw->image.offset[0] >> 8); + evo_mthd(push, 0x0290, 1); + evo_data(push, (asyw->state.src_y >> 16) << 16 | + (asyw->state.src_x >> 16)); + evo_mthd(push, 0x0298, 1); + evo_data(push, (asyw->state.src_h >> 16) << 16 | + (asyw->state.src_w >> 16)); + evo_mthd(push, 0x02a4, 1); + evo_data(push, asyw->state.crtc_h << 16 | + asyw->state.crtc_w); + evo_kick(push, &wndw->wndw); +} + +static void +wndwc57e_csc_clr(struct nv50_wndw *wndw) +{ + u32 *push; + if ((push = evo_wait(&wndw->wndw, 13))) { + evo_mthd(push, 0x0400, 12); + evo_data(push, 0x00010000); + evo_data(push, 0x00000000); + evo_data(push, 0x00000000); + evo_data(push, 0x00000000); + evo_data(push, 0x00000000); + evo_data(push, 0x00010000); + evo_data(push, 0x00000000); + evo_data(push, 0x00000000); + evo_data(push, 0x00000000); + evo_data(push, 0x00000000); + evo_data(push, 0x00010000); + evo_data(push, 0x00000000); + evo_kick(push, &wndw->wndw); + } +} + +static void +wndwc57e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) +{ + u32 *push, i; + if ((push = evo_wait(&wndw->wndw, 13))) { + evo_mthd(push, 0x0400, 12); + for (i = 0; i < 12; i++) + evo_data(push, asyw->csc.matrix[i]); + evo_kick(push, &wndw->wndw); + } +} + static void wndwc57e_ilut_clr(struct nv50_wndw *wndw) { @@ -119,7 +185,10 @@ wndwc57e = { .ilut_identity = true, .xlut_set = wndwc57e_ilut_set, .xlut_clr = wndwc57e_ilut_clr, - .image_set = wndwc37e_image_set, + .csc = base907c_csc, + .csc_set = wndwc57e_csc_set, + .csc_clr = wndwc57e_csc_clr, + .image_set = wndwc57e_image_set, .image_clr = wndwc37e_image_clr, .update = wndwc37e_update, }; -- cgit v1.2.3 From a4ec848910a32c0a1e35504088d579c6e2a017f4 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 18:04:42 +1000 Subject: drm/nouveau/kms/nv50-: use __drm_atomic_helper_plane_reset() We have some of this open-coded already, use the helper to prevent problems when adding (for example) support for the alpha property. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index c8d078629722..f671fea8b26d 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -538,9 +538,8 @@ nv50_wndw_reset(struct drm_plane *plane) if (plane->state) plane->funcs->atomic_destroy_state(plane, plane->state); - plane->state = &asyw->state; - plane->state->plane = plane; - plane->state->rotation = DRM_MODE_ROTATE_0; + + __drm_atomic_helper_plane_reset(plane, &asyw->state); } static void -- cgit v1.2.3 From 6f78991fbcfe44c762fe783812f08500a8411ea9 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 17:03:21 +1000 Subject: drm/nouveau/kms/nv50-: create primary plane before overlay planes zpos normalisation uses plane id to determine ordering for duplicate zpos values, and we likely want to keep primary plane on the bottom here. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/head.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index 0d1108eadcff..71c23bf1fe25 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c @@ -480,7 +480,7 @@ nv50_head_create(struct drm_device *dev, int index) struct nouveau_drm *drm = nouveau_drm(dev); struct nv50_disp *disp = nv50_disp(dev); struct nv50_head *head; - struct nv50_wndw *curs, *wndw; + struct nv50_wndw *base, *ovly, *curs; struct drm_crtc *crtc; int ret; @@ -492,13 +492,13 @@ nv50_head_create(struct drm_device *dev, int index) head->base.index = index; if (disp->disp->object.oclass < GV100_DISP) { - ret = nv50_ovly_new(drm, head->base.index, &wndw); - ret = nv50_base_new(drm, head->base.index, &wndw); + ret = nv50_base_new(drm, head->base.index, &base); + ret = nv50_ovly_new(drm, head->base.index, &ovly); } else { - ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY, - head->base.index * 2 + 1, &wndw); ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY, - head->base.index * 2 + 0, &wndw); + head->base.index * 2 + 0, &base); + ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY, + head->base.index * 2 + 1, &ovly); } if (ret == 0) ret = nv50_curs_new(drm, head->base.index, &curs); @@ -508,7 +508,7 @@ nv50_head_create(struct drm_device *dev, int index) } crtc = &head->base.base; - drm_crtc_init_with_planes(dev, crtc, &wndw->plane, &curs->plane, + drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane, &nv50_head_func, "head-%d", head->base.index); drm_crtc_helper_add(crtc, &nv50_head_help); drm_mode_crtc_set_gamma_size(crtc, 256); -- cgit v1.2.3 From 7a962f2b7276ccfb844583f0db5680e763d6f6da Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 16:40:31 +1000 Subject: drm/nouveau/kms/nv50-: attach immutable zpos property to planes Defaulting to the fixed layout enforced in HW by EVO, and that we currently use by default on NVD. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 1 + drivers/gpu/drm/nouveau/dispnv50/wndw.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 7ce7145f82b8..146e54ef672e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -2316,6 +2316,7 @@ nv50_display_create(struct drm_device *dev) disp->disp = &nouveau_display(dev)->disp; dev->mode_config.funcs = &nv50_disp_func; dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; + dev->mode_config.normalize_zpos = true; /* small shared memory area we use for notifiers and semaphores */ ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index f671fea8b26d..b347a68eebd0 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -528,6 +528,13 @@ nv50_wndw_atomic_duplicate_state(struct drm_plane *plane) return &asyw->state; } +static int +nv50_wndw_zpos_default(struct drm_plane *plane) +{ + return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : + (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255; +} + static void nv50_wndw_reset(struct drm_plane *plane) { @@ -540,6 +547,8 @@ nv50_wndw_reset(struct drm_plane *plane) plane->funcs->atomic_destroy_state(plane, plane->state); __drm_atomic_helper_plane_reset(plane, &asyw->state); + plane->state->zpos = nv50_wndw_zpos_default(plane); + plane->state->normalized_zpos = nv50_wndw_zpos_default(plane); } static void @@ -634,6 +643,14 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, } wndw->notify.func = nv50_wndw_notify; + + if (1) { + ret = drm_plane_create_zpos_immutable_property(&wndw->plane, + nv50_wndw_zpos_default(&wndw->plane)); + if (ret) + return ret; + } + return 0; } -- cgit v1.2.3 From 9a99e904cc5b08f8eda2366135404fe72dae16af Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 16:46:13 +1000 Subject: drm/nouveau/kms/gv100-: add support for plane zpos property Has a nice side-effect that we only update HW for this when it changes now, rather than every time we do a page flip. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/atom.h | 5 +++++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 14 +++++++++++++- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 2 ++ drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 30 ++++++++++++++++++----------- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 1 + 5 files changed, 40 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/atom.h b/drivers/gpu/drm/nouveau/dispnv50/atom.h index 75bda111da10..3192f067d291 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/atom.h +++ b/drivers/gpu/drm/nouveau/dispnv50/atom.h @@ -221,6 +221,10 @@ struct nv50_wndw_atom { u16 y; } point; + struct { + u8 depth; + } blend; + union nv50_wndw_atom_mask { struct { bool ntfy:1; @@ -230,6 +234,7 @@ struct nv50_wndw_atom { bool image:1; bool scale:1; bool point:1; + bool blend:1; }; u8 mask; } set, clr; diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index b347a68eebd0..10fcd4e1e44c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -150,6 +150,7 @@ nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); if (asyw->set.scale) wndw->func->scale_set(wndw, asyw); + if (asyw->set.blend) wndw->func->blend_set(wndw, asyw); if (asyw->set.point) { if (asyw->set.point = false, asyw->set.mask) interlock[wndw->interlock.type] |= wndw->interlock.data; @@ -285,6 +286,12 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, asyw->set.scale = true; } + if (wndw->func->blend_set) { + asyw->blend.depth = 255 - asyw->state.normalized_zpos; + if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) + asyw->set.blend = true; + } + if (wndw->immd) { asyw->point.x = asyw->state.crtc_x; asyw->point.y = asyw->state.crtc_y; @@ -644,7 +651,12 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, wndw->notify.func = nv50_wndw_notify; - if (1) { + if (wndw->func->blend_set) { + ret = drm_plane_create_zpos_property(&wndw->plane, + nv50_wndw_zpos_default(&wndw->plane), 0, 254); + if (ret) + return ret; + } else { ret = drm_plane_create_zpos_immutable_property(&wndw->plane, nv50_wndw_zpos_default(&wndw->plane)); if (ret) diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 59ff8f082542..c63bd3bdaf06 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -76,6 +76,7 @@ struct nv50_wndw_func { void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*image_clr)(struct nv50_wndw *); void (*scale_set)(struct nv50_wndw *, struct nv50_wndw_atom *); + void (*blend_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*update)(struct nv50_wndw *, u32 *interlock); }; @@ -110,6 +111,7 @@ void wndwc37e_sema_clr(struct nv50_wndw *); void wndwc37e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_ntfy_clr(struct nv50_wndw *); void wndwc37e_image_clr(struct nv50_wndw *); +void wndwc37e_blend_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_update(struct nv50_wndw *, u32 *); int wndwc57e_new(struct nouveau_drm *, enum drm_plane_type, int, s32, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 0d270cd5ac4c..4d2d54a8c659 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -81,6 +81,23 @@ wndwc37e_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) asyw->xlut.i.load = head907d_olut_load; } +void +wndwc37e_blend_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) +{ + u32 *push; + if ((push = evo_wait(&wndw->wndw, 8))) { + evo_mthd(push, 0x02ec, 7); + evo_data(push, asyw->blend.depth << 4); + evo_data(push, 0x000000ff); + evo_data(push, 0x00007722); + evo_data(push, 0xffff0000); + evo_data(push, 0xffff0000); + evo_data(push, 0xffff0000); + evo_data(push, 0xffff0000); + evo_kick(push, &wndw->wndw); + } +} + void wndwc37e_image_clr(struct nv50_wndw *wndw) { @@ -99,7 +116,7 @@ wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { u32 *push; - if (!(push = evo_wait(&wndw->wndw, 25))) + if (!(push = evo_wait(&wndw->wndw, 17))) return; evo_mthd(push, 0x0308, 1); @@ -124,16 +141,6 @@ wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) evo_mthd(push, 0x02a4, 1); evo_data(push, asyw->state.crtc_h << 16 | asyw->state.crtc_w); - - /*XXX: Composition-related stuff. Need to implement properly. */ - evo_mthd(push, 0x02ec, 7); - evo_data(push, (2 - (wndw->id & 1)) << 4); - evo_data(push, 0x000000ff); - evo_data(push, 0x00007722); - evo_data(push, 0xffff0000); - evo_data(push, 0xffff0000); - evo_data(push, 0xffff0000); - evo_data(push, 0xffff0000); evo_kick(push, &wndw->wndw); } @@ -258,6 +265,7 @@ wndwc37e = { .csc_clr = wndwc37e_csc_clr, .image_set = wndwc37e_image_set, .image_clr = wndwc37e_image_clr, + .blend_set = wndwc37e_blend_set, .update = wndwc37e_update, }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index d5e4b006ae1e..a311c79e5295 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -190,6 +190,7 @@ wndwc57e = { .csc_clr = wndwc57e_csc_clr, .image_set = wndwc57e_image_set, .image_clr = wndwc37e_image_clr, + .blend_set = wndwc37e_blend_set, .update = wndwc37e_update, }; -- cgit v1.2.3 From a0a76244760d8b72ba1bb9c6998e41f5d286d6aa Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 17:13:04 +1000 Subject: drm/nouveau/kms/gv100-: attach alpha property to planes Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/atom.h | 1 + drivers/gpu/drm/nouveau/dispnv50/wndw.c | 5 +++++ drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 +- 3 files changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/atom.h b/drivers/gpu/drm/nouveau/dispnv50/atom.h index 3192f067d291..973074403f3c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/atom.h +++ b/drivers/gpu/drm/nouveau/dispnv50/atom.h @@ -223,6 +223,7 @@ struct nv50_wndw_atom { struct { u8 depth; + u8 k1; } blend; union nv50_wndw_atom_mask { diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 10fcd4e1e44c..76c69c6eca77 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -288,6 +288,7 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, if (wndw->func->blend_set) { asyw->blend.depth = 255 - asyw->state.normalized_zpos; + asyw->blend.k1 = asyw->state.alpha >> 8; if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) asyw->set.blend = true; } @@ -656,6 +657,10 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, nv50_wndw_zpos_default(&wndw->plane), 0, 254); if (ret) return ret; + + ret = drm_plane_create_alpha_property(&wndw->plane); + if (ret) + return ret; } else { ret = drm_plane_create_zpos_immutable_property(&wndw->plane, nv50_wndw_zpos_default(&wndw->plane)); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 4d2d54a8c659..3c6d64d1b708 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -88,7 +88,7 @@ wndwc37e_blend_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((push = evo_wait(&wndw->wndw, 8))) { evo_mthd(push, 0x02ec, 7); evo_data(push, asyw->blend.depth << 4); - evo_data(push, 0x000000ff); + evo_data(push, asyw->blend.k1); evo_data(push, 0x00007722); evo_data(push, 0xffff0000); evo_data(push, 0xffff0000); -- cgit v1.2.3 From edc641b2b2f494ce74a2f657544133faf451a80c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 12 Jun 2019 17:37:23 +1000 Subject: drm/nouveau/kms/gv100-: attach pixel blend mode property to planes Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/atom.h | 2 ++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 5 ++++- 3 files changed, 28 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/atom.h b/drivers/gpu/drm/nouveau/dispnv50/atom.h index 973074403f3c..43df86c38f58 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/atom.h +++ b/drivers/gpu/drm/nouveau/dispnv50/atom.h @@ -224,6 +224,8 @@ struct nv50_wndw_atom { struct { u8 depth; u8 k1; + u8 src_color:4; + u8 dst_color:4; } blend; union nv50_wndw_atom_mask { diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 76c69c6eca77..2db029371c91 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -289,6 +289,21 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, if (wndw->func->blend_set) { asyw->blend.depth = 255 - asyw->state.normalized_zpos; asyw->blend.k1 = asyw->state.alpha >> 8; + switch (asyw->state.pixel_blend_mode) { + case DRM_MODE_BLEND_PREMULTI: + asyw->blend.src_color = 2; /* K1 */ + asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */ + break; + case DRM_MODE_BLEND_COVERAGE: + asyw->blend.src_color = 5; /* K1_TIMES_SRC */ + asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */ + break; + case DRM_MODE_BLEND_PIXEL_NONE: + default: + asyw->blend.src_color = 2; /* K1 */ + asyw->blend.dst_color = 4; /* NEG_K1 */ + break; + } if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) asyw->set.blend = true; } @@ -661,6 +676,13 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, ret = drm_plane_create_alpha_property(&wndw->plane); if (ret) return ret; + + ret = drm_plane_create_blend_mode_property(&wndw->plane, + BIT(DRM_MODE_BLEND_PIXEL_NONE) | + BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE)); + if (ret) + return ret; } else { ret = drm_plane_create_zpos_immutable_property(&wndw->plane, nv50_wndw_zpos_default(&wndw->plane)); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 3c6d64d1b708..0f9402162bde 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -89,7 +89,10 @@ wndwc37e_blend_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) evo_mthd(push, 0x02ec, 7); evo_data(push, asyw->blend.depth << 4); evo_data(push, asyw->blend.k1); - evo_data(push, 0x00007722); + evo_data(push, asyw->blend.dst_color << 12 | + asyw->blend.dst_color << 8 | + asyw->blend.src_color << 4 | + asyw->blend.src_color); evo_data(push, 0xffff0000); evo_data(push, 0xffff0000); evo_data(push, 0xffff0000); -- cgit v1.2.3 From ed22eb56f2bf2908fef7a108809ffa208ff62c0c Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Wed, 7 Aug 2019 19:47:06 -0400 Subject: drm/nouveau/dispnv50: Fix runtime PM ref tracking for non-blocking modesets This is something that got noticed a while ago back when I was fixing a large number of runtime PM related issues in nouveau, but never got fixed: https://patchwork.freedesktop.org/series/46815/#rev7 It's not safe to iterate the entire list of CRTCs in nv50_disp_atomic_commit(), as we could be doing a non-blocking modeset on one CRTC in parallel with one or more other CRTCs. Likewise, this means it's also not safe to do so in order to track runtime PM state. While this code is certainly wrong, so far the only issues I've seen this cause in the wild is the occasional PM ref unbalance after an atomic check failure + module reloading (since the PCI device will outlive nouveau in such scenarios). So, do this far more elegantly: grab a runtime PM ref across the modeset and commit tail, then grab/put references for each CRTC enable/disable. This also ends up being much simpler then the previous broken solution we had. Finally, since we've removed all it's users: get rid of nouveau_drm->have_disp_power_ref. Signed-off-by: Lyude Paul Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 38 +++++++++++++++------------------ drivers/gpu/drm/nouveau/nouveau_drv.h | 3 --- 2 files changed, 17 insertions(+), 24 deletions(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 146e54ef672e..f1dbc7852414 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -1826,8 +1826,11 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, asyh->clr.mask, asyh->set.mask); - if (old_crtc_state->active && !new_crtc_state->active) + + if (old_crtc_state->active && !new_crtc_state->active) { + pm_runtime_put_noidle(dev->dev); drm_crtc_vblank_off(crtc); + } if (asyh->clr.mask) { nv50_head_flush_clr(head, asyh, atom->flush_disable); @@ -1913,8 +1916,10 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) } if (new_crtc_state->active) { - if (!old_crtc_state->active) + if (!old_crtc_state->active) { drm_crtc_vblank_on(crtc); + pm_runtime_get_noresume(dev->dev); + } if (new_crtc_state->event) drm_crtc_vblank_get(crtc); } @@ -1979,6 +1984,10 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) drm_atomic_helper_cleanup_planes(dev, state); drm_atomic_helper_commit_cleanup_done(state); drm_atomic_state_put(state); + + /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ + pm_runtime_mark_last_busy(dev->dev); + pm_runtime_put_autosuspend(dev->dev); } static void @@ -1993,11 +2002,8 @@ static int nv50_disp_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, bool nonblock) { - struct nouveau_drm *drm = nouveau_drm(dev); struct drm_plane_state *new_plane_state; struct drm_plane *plane; - struct drm_crtc *crtc; - bool active = false; int ret, i; ret = pm_runtime_get_sync(dev->dev); @@ -2034,27 +2040,17 @@ nv50_disp_atomic_commit(struct drm_device *dev, drm_atomic_state_get(state); + /* + * Grab another RPM ref for the commit tail, which will release the + * ref when it's finished + */ + pm_runtime_get_noresume(dev->dev); + if (nonblock) queue_work(system_unbound_wq, &state->commit_work); else nv50_disp_atomic_commit_tail(state); - drm_for_each_crtc(crtc, dev) { - if (crtc->state->active) { - if (!drm->have_disp_power_ref) { - drm->have_disp_power_ref = true; - return 0; - } - active = true; - break; - } - } - - if (!active && drm->have_disp_power_ref) { - pm_runtime_put_autosuspend(dev->dev); - drm->have_disp_power_ref = false; - } - err_cleanup: if (ret) drm_atomic_helper_cleanup_planes(dev, state); diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index cf0d0a416af6..70f34cacc552 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -206,9 +206,6 @@ struct nouveau_drm { /* led management */ struct nouveau_led *led; - /* display power reference */ - bool have_disp_power_ref; - struct dev_pm_domain vga_pm_domain; struct nouveau_svm *svm; -- cgit v1.2.3 From 698c1aa9f83b618de79e9e5e19a58f70a4a6ae0f Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Fri, 13 Sep 2019 18:03:50 -0400 Subject: drm/nouveau/kms/nv50-: Don't create MSTMs for eDP connectors On the ThinkPad P71, we have one eDP connector exposed along with 5 DP connectors, resulting in a total of 11 TMDS encoders. Since the GPU on this system is also capable of MST, we create an additional 4 fake MST encoders for each DP port. Unfortunately, we also do this for the eDP port as well, resulting in: 1 eDP port: +1 TMDS encoder +4 DPMST encoders 5 DP ports: +2 TMDS encoders +4 DPMST encoders *5 ports == 35 encoders Which breaks things, since DRM has a hard coded limit of 32 encoders. So, fix this by not creating MSTMs for any eDP connectors. This brings us down to 31 encoders, although we can do better. This fixes driver probing for nouveau on the ThinkPad P71. Signed-off-by: Lyude Paul Cc: stable@vger.kernel.org Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index f1dbc7852414..064a69d161e3 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -1599,7 +1599,8 @@ nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) nv_encoder->aux = aux; } - if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) && + if (nv_connector->type != DCB_CONNECTOR_eDP && + (data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) { ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16, nv_connector->base.base.id, -- cgit v1.2.3 From 4d85f45c73a22bc0ee900c7505b7210a87a7966d Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 3 Sep 2019 21:06:42 +0200 Subject: drm/atomic: Rename crtc_state->pageflip_flags to async_flip MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's the only flag anyone actually cares about. Plus if we're unlucky, the atomic ioctl might need a different flag for async flips. So better to abstract this away from the uapi a bit. Reviewed-by: Maarten Lankhorst Reviewed-by: Nicholas Kazlauskas Cc: Maarten Lankhorst Cc: Michel Dänzer Cc: Alex Deucher Cc: Adam Jackson Cc: Sean Paul Cc: David Airlie Signed-off-by: Daniel Vetter Cc: Maxime Ripard Cc: Daniel Vetter Cc: Nicholas Kazlauskas Cc: Leo Li Cc: Harry Wentland Cc: David Francis Cc: Mario Kleiner Cc: Bhawanpreet Lakha Cc: Ben Skeggs Cc: "Christian König" Cc: Ilia Mirkin Cc: Sam Ravnborg Cc: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20190903190642.32588-3-daniel.vetter@ffwll.ch --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++--- drivers/gpu/drm/drm_atomic_helper.c | 2 +- drivers/gpu/drm/drm_atomic_state_helper.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 4 ++-- include/drm/drm_crtc.h | 8 ++++---- 5 files changed, 10 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/drm/nouveau/dispnv50') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0a71ed1e7762..2f0ef0820f00 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5756,8 +5756,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, * change FB pitch, DCC state, rotation or mirroing. */ bundle->flip_addrs[planes_count].flip_immediate = - (crtc->state->pageflip_flags & - DRM_MODE_PAGE_FLIP_ASYNC) != 0 && + crtc->state->async_flip && acrtc_state->update_type == UPDATE_TYPE_FAST; timestamp_ns = ktime_get_ns(); @@ -6334,7 +6333,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) amdgpu_dm_enable_crtc_interrupts(dev, state, true); for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) - if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) + if (new_crtc_state->async_flip) wait_for_vblank = false; /* update planes when needed per crtc*/ diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index aa16ea17ff9b..3a67f63c3146 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -3275,7 +3275,7 @@ static int page_flip_common(struct drm_atomic_state *state, return PTR_ERR(crtc_state); crtc_state->event = event; - crtc_state->pageflip_flags = flags; + crtc_state->async_flip = flags & DRM_MODE_PAGE_FLIP_ASYNC; plane_state = drm_atomic_get_plane_state(state, plane); if (IS_ERR(plane_state)) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index 46dc264a248b..d0a937fb0c56 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -128,7 +128,7 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc, state->zpos_changed = false; state->commit = NULL; state->event = NULL; - state->pageflip_flags = 0; + state->async_flip = false; /* Self refresh should be canceled when a new update is available */ state->active = drm_atomic_crtc_effectively_active(state); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 2db029371c91..5193b6257061 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -267,7 +267,7 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, asyw->image.pitch[0] = fb->base.pitches[0]; } - if (!(asyh->state.pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)) + if (!asyh->state.async_flip) asyw->image.interval = 1; else asyw->image.interval = 0; @@ -383,7 +383,7 @@ nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, } /* Can't do an immediate flip while changing the LUT. */ - asyh->state.pageflip_flags &= ~DRM_MODE_PAGE_FLIP_ASYNC; + asyh->state.async_flip = false; } static int diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 7d14c11bdc0a..c4528eb5d168 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -285,12 +285,12 @@ struct drm_crtc_state { u32 target_vblank; /** - * @pageflip_flags: + * @async_flip: * - * DRM_MODE_PAGE_FLIP_* flags, as passed to the page flip ioctl. - * Zero in any other case. + * This is set when DRM_MODE_PAGE_FLIP_ASYNC is set in the legacy + * PAGE_FLIP IOCTL. It's not wired up for the atomic IOCTL itself yet. */ - u32 pageflip_flags; + bool async_flip; /** * @vrr_enabled: -- cgit v1.2.3