From 42882336e62aab00278114392a16374f272a0c99 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Thu, 25 Oct 2018 17:56:36 -0700 Subject: drm/i915/glk: Remove 99% limitation. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While checking the opportunity to add a display_gen check to allow glk and cnl to be on same bucket I noticed these FIXME cases here. So I got the confirmation from HW architect that we actually never needed this workaround. "GLK supports 2 pixel per clock, so pixel clock can be up to 2 * cdclk." So, this reverts commit 97f55ca5b662 ("drm/i915/glk: limit pixel clock to 99% of cdclk workaround") Fixes: 97f55ca5b662 ("drm/i915/glk: limit pixel clock to 99% of cdclk workaround") Cc: Ville Syrjälä Cc: Madhav Chauhan Cc: Jani Nikula Cc: Clinton Taylor Cc: Arthur J Runyan Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20181026005636.22274-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_cdclk.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/drm/i915/intel_cdclk.c') diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 29075c763428..8d74276029e6 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -2138,16 +2138,8 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv, static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, int pixel_rate) { - if (INTEL_GEN(dev_priv) >= 10) + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) return DIV_ROUND_UP(pixel_rate, 2); - else if (IS_GEMINILAKE(dev_priv)) - /* - * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk - * as a temporary workaround. Use a higher cdclk instead. (Note that - * intel_compute_max_dotclk() limits the max pixel clock to 99% of max - * cdclk.) - */ - return DIV_ROUND_UP(pixel_rate * 100, 2 * 99); else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return pixel_rate; @@ -2543,14 +2535,8 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) { int max_cdclk_freq = dev_priv->max_cdclk_freq; - if (INTEL_GEN(dev_priv) >= 10) + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) return 2 * max_cdclk_freq; - else if (IS_GEMINILAKE(dev_priv)) - /* - * FIXME: Limiting to 99% as a temporary workaround. See - * intel_min_cdclk() for details. - */ - return 2 * max_cdclk_freq * 99 / 100; else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return max_cdclk_freq; -- cgit v1.2.3 From af4de6adb4999513fd41753ad6b35b67a90c3905 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Mon, 12 Nov 2018 15:23:11 -0800 Subject: drm/i915/cnp+: update to the new RAWCLK_FREQ recommendations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BSpec was updated and now there's no more "subtract 1" to the Microsecond Counter Divider field. It seems this should help fixing some GMBUS issues. I'm not aware of any specific open bug that could be solved by this patch. Cc: Ville Syrjälä Cc: Rodrigo Vivi Reviewed-by: Ville Syrjälä Signed-off-by: Paulo Zanoni Link: https://patchwork.freedesktop.org/patch/msgid/20181112232313.26373-1-paulo.r.zanoni@intel.com --- drivers/gpu/drm/i915/intel_cdclk.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/i915/intel_cdclk.c') diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 8d74276029e6..810670976e86 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -2660,7 +2660,7 @@ static int cnp_rawclk(struct drm_i915_private *dev_priv) fraction = 200; } - rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1); + rawclk = CNP_RAWCLK_DIV(divider / 1000); if (fraction) rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000, fraction) - 1); @@ -2676,12 +2676,12 @@ static int icp_rawclk(struct drm_i915_private *dev_priv) if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { frequency = 24000; - divider = 23; + divider = 24; numerator = 0; denominator = 0; } else { frequency = 19200; - divider = 18; + divider = 19; numerator = 1; denominator = 4; } -- cgit v1.2.3 From 228a5cf381f761ca16ef6b31b24c4533594468bd Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Mon, 12 Nov 2018 15:23:12 -0800 Subject: drm/i915: rename CNP_RAWCLK_FRAC to CNP_RAWCLK_DEN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Although CNP names this field "Counter Fraction", what we write to the register is really the denominator for the fractional part of the divider, not the fractional part (and the field description even says that). The ICP spec renamed the field to "Counter Fraction Denominator", which makes a lot more sense. Use the more complete ICL naming because we will merge the CNP and ICP functions into a single one, which will introduce the concept of the numerator. That will make a lot more sense when you read the "num/frac = den" calculation. Reviewed-by: Ville Syrjälä Signed-off-by: Paulo Zanoni Link: https://patchwork.freedesktop.org/patch/msgid/20181112232313.26373-2-paulo.r.zanoni@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 +-- drivers/gpu/drm/i915/intel_cdclk.c | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/i915/intel_cdclk.c') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fe4b913e46ac..16f0d73bb4fe 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7907,8 +7907,7 @@ enum { #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) #define CNP_RAWCLK_DIV(div) ((div) << 16) #define CNP_RAWCLK_FRAC_MASK (0xf << 26) -#define CNP_RAWCLK_FRAC(frac) ((frac) << 26) -#define ICP_RAWCLK_DEN(den) ((den) << 26) +#define CNP_RAWCLK_DEN(den) ((den) << 26) #define ICP_RAWCLK_NUM(num) ((num) << 11) #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 810670976e86..928671936286 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -2662,8 +2662,8 @@ static int cnp_rawclk(struct drm_i915_private *dev_priv) rawclk = CNP_RAWCLK_DIV(divider / 1000); if (fraction) - rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000, - fraction) - 1); + rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(1000, + fraction) - 1); I915_WRITE(PCH_RAWCLK_FREQ, rawclk); return divider + fraction; @@ -2687,7 +2687,7 @@ static int icp_rawclk(struct drm_i915_private *dev_priv) } rawclk = CNP_RAWCLK_DIV(divider) | ICP_RAWCLK_NUM(numerator) | - ICP_RAWCLK_DEN(denominator); + CNP_RAWCLK_DEN(denominator); I915_WRITE(PCH_RAWCLK_FREQ, rawclk); return frequency; -- cgit v1.2.3 From 704e504bd6167084dd0841c02d1d2bb58889e967 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Mon, 12 Nov 2018 15:23:13 -0800 Subject: drm/i915: add ICP support to cnp_rawclk() and kill icp_rawclk() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I think I'm probably the one who argued in favor of having separate implementations for both PCHs, but the calculations are actually the same, the clocks are the same and the only difference is that on ICP we write the numerator to the register. I have previously suggested to kill cnp_rawclk() and keep the icp_rawclk() style, but Ville gave some good arguments that what's in this patch may be the better choice. v2: Switch numerator to 1 from 1000 and adjust calculations accordingly (Ville). Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Paulo Zanoni Link: https://patchwork.freedesktop.org/patch/msgid/20181112232313.26373-3-paulo.r.zanoni@intel.com --- drivers/gpu/drm/i915/intel_cdclk.c | 37 ++++++++----------------------------- 1 file changed, 8 insertions(+), 29 deletions(-) (limited to 'drivers/gpu/drm/i915/intel_cdclk.c') diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 928671936286..25e3aba9cded 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -2661,36 +2661,17 @@ static int cnp_rawclk(struct drm_i915_private *dev_priv) } rawclk = CNP_RAWCLK_DIV(divider / 1000); - if (fraction) - rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(1000, - fraction) - 1); + if (fraction) { + int numerator = 1; - I915_WRITE(PCH_RAWCLK_FREQ, rawclk); - return divider + fraction; -} - -static int icp_rawclk(struct drm_i915_private *dev_priv) -{ - u32 rawclk; - int divider, numerator, denominator, frequency; - - if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { - frequency = 24000; - divider = 24; - numerator = 0; - denominator = 0; - } else { - frequency = 19200; - divider = 19; - numerator = 1; - denominator = 4; + rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, + fraction) - 1); + if (HAS_PCH_ICP(dev_priv)) + rawclk |= ICP_RAWCLK_NUM(numerator); } - rawclk = CNP_RAWCLK_DIV(divider) | ICP_RAWCLK_NUM(numerator) | - CNP_RAWCLK_DEN(denominator); - I915_WRITE(PCH_RAWCLK_FREQ, rawclk); - return frequency; + return divider + fraction; } static int pch_rawclk(struct drm_i915_private *dev_priv) @@ -2740,9 +2721,7 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv) */ void intel_update_rawclk(struct drm_i915_private *dev_priv) { - if (HAS_PCH_ICP(dev_priv)) - dev_priv->rawclk_freq = icp_rawclk(dev_priv); - else if (HAS_PCH_CNP(dev_priv)) + if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv)) dev_priv->rawclk_freq = cnp_rawclk(dev_priv); else if (HAS_PCH_SPLIT(dev_priv)) dev_priv->rawclk_freq = pch_rawclk(dev_priv); -- cgit v1.2.3