From c8a220c686a596a4f669b441b2ea40486dea0513 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 17 May 2016 13:51:08 +0100 Subject: drm/armada: add tracing support Add tracing support to the Armada video overlay and interrupt code. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_overlay.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/gpu/drm/armada/armada_overlay.c') diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 1ee707ef6b8d..94af7c93276e 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -15,6 +15,7 @@ #include "armada_hw.h" #include #include "armada_ioctlP.h" +#include "armada_trace.h" struct armada_ovl_plane_properties { uint32_t colorkey_yr; @@ -87,6 +88,8 @@ static void armada_ovl_plane_work(struct armada_crtc *dcrtc, { struct armada_ovl_plane *dplane = container_of(plane, struct armada_ovl_plane, base); + trace_armada_ovl_plane_work(&dcrtc->crtc, &plane->base); + armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs); armada_ovl_retire_fb(dplane, NULL); } @@ -120,6 +123,10 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, bool visible; int ret; + trace_armada_ovl_plane_update(plane, crtc, fb, + crtc_x, crtc_y, crtc_w, crtc_h, + src_x, src_y, src_w, src_h); + ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip, BIT(DRM_ROTATE_0), 0, INT_MAX, true, false, &visible); -- cgit v1.2.3 From 8be523db65ad41b6119f59e5a7136c85aad6da29 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 16 Aug 2016 22:09:08 +0100 Subject: drm/armada: move plane state to struct armada_plane Move more of the Armada plane state (source size, and displayed size and position) into a state structure inside struct armada_plane. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 29 ++++++++++++++++++++--------- drivers/gpu/drm/armada/armada_crtc.h | 8 ++++++++ drivers/gpu/drm/armada/armada_overlay.c | 32 ++++++++++++++------------------ 3 files changed, 42 insertions(+), 27 deletions(-) (limited to 'drivers/gpu/drm/armada/armada_overlay.c') diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 9ec7e6136bcc..719873be3beb 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -543,6 +543,19 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE); + val = CFG_GRA_ENA | CFG_GRA_HSMOOTH; + val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt); + val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod); + + if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420) + val |= CFG_PALETTE_ENA; + + drm_to_armada_plane(crtc->primary)->state.ctrl0 = val; + drm_to_armada_plane(crtc->primary)->state.src_hw = + drm_to_armada_plane(crtc->primary)->state.dst_hw = + adj->crtc_hdisplay << 16 | adj->crtc_vdisplay; + drm_to_armada_plane(crtc->primary)->state.dst_yx = 0; + i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb, x, y, regs, interlaced); @@ -621,8 +634,12 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay; armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE); - armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN); - armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN); + armada_reg_queue_set(regs, i, + drm_to_armada_plane(crtc->primary)->state.src_hw, + LCD_SPU_GRA_HPXL_VLN); + armada_reg_queue_set(regs, i, + drm_to_armada_plane(crtc->primary)->state.dst_hw, + LCD_SPU_GZM_HPXL_VLN); armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH); armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, @@ -634,13 +651,7 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, ADV_VSYNCOFFEN, LCD_SPU_ADV_REG); } - val = CFG_GRA_ENA | CFG_GRA_HSMOOTH; - val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt); - val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod); - - if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420) - val |= CFG_PALETTE_ENA; - + val = drm_to_armada_plane(crtc->primary)->state.ctrl0; if (interlaced) val |= CFG_GRA_FTOGGLE; diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index 04fdd22d483b..5b2b2c55589c 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -41,10 +41,18 @@ struct armada_plane_work { struct armada_plane_work *); }; +struct armada_plane_state { + u32 src_hw; + u32 dst_hw; + u32 dst_yx; + u32 ctrl0; +}; + struct armada_plane { struct drm_plane base; wait_queue_head_t frame_wait; struct armada_plane_work *work; + struct armada_plane_state state; }; #define drm_to_armada_plane(p) container_of(p, struct armada_plane, base) diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 94af7c93276e..5e979bbd5d6d 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -33,10 +33,6 @@ struct armada_ovl_plane_properties { struct armada_ovl_plane { struct armada_plane base; struct drm_framebuffer *old_fb; - uint32_t src_hw; - uint32_t dst_hw; - uint32_t dst_yx; - uint32_t ctrl0; struct { struct armada_plane_work work; struct armada_regs regs[13]; @@ -148,22 +144,22 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, /* FIXME: overlay on an interlaced display */ /* Just updating the position/size? */ - if (plane->fb == fb && dplane->ctrl0 == ctrl0) { + if (plane->fb == fb && dplane->base.state.ctrl0 == ctrl0) { val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16; - dplane->src_hw = val; + dplane->base.state.src_hw = val; writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN); val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest); - dplane->dst_hw = val; + dplane->base.state.dst_hw = val; writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN); val = dest.y1 << 16 | dest.x1; - dplane->dst_yx = val; + dplane->base.state.dst_yx = val; writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN); return 0; - } else if (~dplane->ctrl0 & ctrl0 & CFG_DMA_ENA) { + } else if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) { /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */ armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66, dcrtc->base + LCD_SPU_SRAM_PARA1); @@ -230,28 +226,28 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, } val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16; - if (dplane->src_hw != val) { - dplane->src_hw = val; + if (dplane->base.state.src_hw != val) { + dplane->base.state.src_hw = val; armada_reg_queue_set(dplane->vbl.regs, idx, val, LCD_SPU_DMA_HPXL_VLN); } val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest); - if (dplane->dst_hw != val) { - dplane->dst_hw = val; + if (dplane->base.state.dst_hw != val) { + dplane->base.state.dst_hw = val; armada_reg_queue_set(dplane->vbl.regs, idx, val, LCD_SPU_DZM_HPXL_VLN); } val = dest.y1 << 16 | dest.x1; - if (dplane->dst_yx != val) { - dplane->dst_yx = val; + if (dplane->base.state.dst_yx != val) { + dplane->base.state.dst_yx = val; armada_reg_queue_set(dplane->vbl.regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN); } - if (dplane->ctrl0 != ctrl0) { - dplane->ctrl0 = ctrl0; + if (dplane->base.state.ctrl0 != ctrl0) { + dplane->base.state.ctrl0 = ctrl0; armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0, CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE | CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE | @@ -282,7 +278,7 @@ static int armada_ovl_plane_disable(struct drm_plane *plane) armada_drm_crtc_plane_disable(dcrtc, plane); dcrtc->plane = NULL; - dplane->ctrl0 = 0; + dplane->base.state.ctrl0 = 0; fb = xchg(&dplane->old_fb, NULL); if (fb) -- cgit v1.2.3 From f0b24871cc3aa71d52553d5a0fa11584b8e4943c Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 16 Aug 2016 22:09:11 +0100 Subject: drm/armada: use common helper for plane base address Use a common helper to calculate the plane base address(es) for the framebuffer. Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_crtc.c | 26 ++++++++++++++++++++++---- drivers/gpu/drm/armada/armada_crtc.h | 2 ++ drivers/gpu/drm/armada/armada_overlay.c | 26 ++++++++++---------------- 3 files changed, 34 insertions(+), 20 deletions(-) (limited to 'drivers/gpu/drm/armada/armada_overlay.c') diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 6d3b0edde8d7..ceec930696dc 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -165,19 +165,37 @@ static void armada_drm_crtc_update(struct armada_crtc *dcrtc) } } +void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb, + int x, int y) +{ + u32 addr = drm_fb_obj(fb)->dev_addr; + u32 pixel_format = fb->pixel_format; + int num_planes = drm_format_num_planes(pixel_format); + int i; + + if (num_planes > 3) + num_planes = 3; + + for (i = 0; i < num_planes; i++) + addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] + + x * drm_format_plane_cpp(pixel_format, i); + for (; i < 3; i++) + addrs[i] = 0; +} + static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb, int x, int y, struct armada_regs *regs, bool interlaced) { - struct armada_gem_object *obj = drm_fb_obj(fb); unsigned pitch = fb->pitches[0]; - unsigned offset = y * pitch + x * fb->bits_per_pixel / 8; - uint32_t addr_odd, addr_even; + u32 addrs[3], addr_odd, addr_even; unsigned i = 0; DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n", pitch, x, y, fb->bits_per_pixel); - addr_odd = addr_even = obj->dev_addr + offset; + armada_drm_plane_calc_addrs(addrs, fb, x, y); + + addr_odd = addr_even = addrs[0]; if (interlaced) { addr_even += pitch; diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index 5b2b2c55589c..b08043e8cc3b 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -62,6 +62,8 @@ int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout); struct armada_plane_work *armada_drm_plane_work_cancel( struct armada_crtc *dcrtc, struct armada_plane *plane); +void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb, + int x, int y); struct armada_crtc { struct drm_crtc crtc; diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 5e979bbd5d6d..41fc28b1e7d1 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -169,9 +169,8 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, armada_drm_plane_work_cancel(dcrtc, &dplane->base); if (plane->fb != fb) { - struct armada_gem_object *obj = drm_fb_obj(fb); - uint32_t addr[3], pixel_format; - int i, num_planes, hsub; + u32 addrs[3], pixel_format; + int num_planes, hsub; /* * Take a reference on the new framebuffer - we want to @@ -185,6 +184,8 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, src_y = src.y1 >> 16; src_x = src.x1 >> 16; + armada_drm_plane_calc_addrs(addrs, fb, src_x, src_y); + pixel_format = fb->pixel_format; hsub = drm_format_horz_chroma_subsampling(pixel_format); num_planes = drm_format_num_planes(pixel_format); @@ -197,24 +198,17 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, if (src_x & (hsub - 1) && num_planes == 1) ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV); - for (i = 0; i < num_planes; i++) - addr[i] = obj->dev_addr + fb->offsets[i] + - src_y * fb->pitches[i] + - src_x * drm_format_plane_cpp(pixel_format, i); - for (; i < ARRAY_SIZE(addr); i++) - addr[i] = 0; - - armada_reg_queue_set(dplane->vbl.regs, idx, addr[0], + armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0], LCD_SPU_DMA_START_ADDR_Y0); - armada_reg_queue_set(dplane->vbl.regs, idx, addr[1], + armada_reg_queue_set(dplane->vbl.regs, idx, addrs[1], LCD_SPU_DMA_START_ADDR_U0); - armada_reg_queue_set(dplane->vbl.regs, idx, addr[2], + armada_reg_queue_set(dplane->vbl.regs, idx, addrs[2], LCD_SPU_DMA_START_ADDR_V0); - armada_reg_queue_set(dplane->vbl.regs, idx, addr[0], + armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0], LCD_SPU_DMA_START_ADDR_Y1); - armada_reg_queue_set(dplane->vbl.regs, idx, addr[1], + armada_reg_queue_set(dplane->vbl.regs, idx, addrs[1], LCD_SPU_DMA_START_ADDR_U1); - armada_reg_queue_set(dplane->vbl.regs, idx, addr[2], + armada_reg_queue_set(dplane->vbl.regs, idx, addrs[2], LCD_SPU_DMA_START_ADDR_V1); val = fb->pitches[0] << 16 | fb->pitches[0]; -- cgit v1.2.3