From 8a5d82451e297fc3864bb9ab0247b53c7ab8a022 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Thu, 3 Aug 2017 21:23:04 -0400 Subject: drm/amd/display: use some sensible time out 40s time out is not sensible. also make all udelay poll happen more frequently since CPU is busy anyways Signed-off-by: Tony Cheng Reviewed-by: Yongqiang Sun Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index aaff946a6d0a..92902f011418 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -262,7 +262,7 @@ static void dce_psr_wait_loop( union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; /* waitDMCUReadyForCmd */ - REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100); + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); masterCmdData1.u32 = 0; masterCmdData1.bits.wait_loop = wait_loop_number; @@ -502,7 +502,7 @@ static void dcn10_psr_wait_loop( union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; /* waitDMCUReadyForCmd */ - REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100); + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); masterCmdData1.u32 = 0; masterCmdData1.bits.wait_loop = wait_loop_number; -- cgit v1.2.3