From b314f9a997dd1d1e1fb607b68387c1e92e914e66 Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Mon, 6 Jun 2016 13:50:18 +0800 Subject: drm/amdgpu: enable BUS master after pci reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-enable bus mastering after GPU reset. We disable it at the top of these functions, so balance them by re-enabling it. Signed-off-by: Chunming Zhou eviewed-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/amdgpu/vi.c') diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 064122bfa6f9..e05e722ef6c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -612,8 +612,11 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) /* wait for asic to come out of reset */ for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) + if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { + /* enable BM */ + pci_set_master(adev->pdev); return 0; + } udelay(1); } return -EINVAL; -- cgit v1.2.3