From 67b6e5cfdb1fb2607a20e1e002719f01b025b197 Mon Sep 17 00:00:00 2001 From: Lei YU Date: Fri, 18 May 2018 16:57:02 +0800 Subject: clk: aspeed: Add 24MHz fixed clock Add a 24MHz fixed clock. This clock will be used for certain devices, e.g. pwm. Signed-off-by: Lei YU Reviewed-by: Joel Stanley Acked-by: Rob Herring Signed-off-by: Stephen Boyd --- drivers/clk/clk-aspeed.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 5eb50c31e455..466408825406 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -14,7 +14,7 @@ #include -#define ASPEED_NUM_CLKS 35 +#define ASPEED_NUM_CLKS 36 #define ASPEED_RESET_CTRL 0x04 #define ASPEED_CLK_SELECTION 0x08 @@ -474,6 +474,13 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + /* Fixed 24MHz clock */ + hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin", + 0, 24000000); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_24M] = hw; + /* * TODO: There are a number of clocks that not included in this driver * as more information is required: -- cgit v1.2.3