From 4afe2d1a6ed5cba794aeeaa816e7c97a45167b01 Mon Sep 17 00:00:00 2001 From: Harvey Hunt Date: Mon, 9 May 2016 17:29:52 +0100 Subject: clk: ingenic: Allow divider value to be divided The JZ4780's MSC clock divider registers multiply the clock divider by 2. This means that MMC devices run at half their expected speed. Add the ability to divide the clock divider in order to solve this. Signed-off-by: Harvey Hunt Cc: Paul Burton Cc: Ralf Baechle Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Stephen Boyd --- drivers/clk/ingenic/cgu.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/clk/ingenic/cgu.h') diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 99347e2b97e8..09700b2c555d 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -76,8 +76,11 @@ struct ingenic_cgu_mux_info { /** * struct ingenic_cgu_div_info - information about a divider * @reg: offset of the divider control register within the CGU - * @shift: number of bits to shift the divide value by (ie. the index of + * @shift: number of bits to left shift the divide value by (ie. the index of * the lowest bit of the divide value within its control register) + * @div: number of bits to divide the divider value by (i.e. if the + * effective divider value is the value written to the register + * multiplied by some constant) * @bits: the size of the divide value in bits * @ce_bit: the index of the change enable bit within reg, or -1 if there * isn't one @@ -87,6 +90,7 @@ struct ingenic_cgu_mux_info { struct ingenic_cgu_div_info { unsigned reg; u8 shift; + u8 div; u8 bits; s8 ce_bit; s8 busy_bit; -- cgit v1.2.3