From c77cbdd11b688fa0d1fbb140473dad4bc47cf5e6 Mon Sep 17 00:00:00 2001 From: Nikita Yushchenko Date: Mon, 19 Dec 2016 11:12:09 +0300 Subject: clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2 On vf610, PLL1 and PLL2 have registers to configure fractional part of frequency multiplier. This patch adds support for these registers. This fixes "fast system clock" issue on boards where bootloader sets fractional multiplier for PLL1. Suggested-by: Andrey Smirnov CC: Chris Healy Signed-off-by: Nikita Yushchenko Tested-by: Andrey Smirnov Signed-off-by: Stephen Boyd --- drivers/clk/imx/clk.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/imx/clk.h') diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 4afad3b96a61..e1f5e425db73 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -34,6 +34,7 @@ enum imx_pllv3_type { IMX_PLLV3_AV, IMX_PLLV3_ENET, IMX_PLLV3_ENET_IMX7, + IMX_PLLV3_SYS_VF610, }; struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, -- cgit v1.2.3