From f88c480dac88a754f84e943cb5539d59cda3c089 Mon Sep 17 00:00:00 2001
From: sonic zhang <sonic.adi@gmail.com>
Date: Tue, 27 Nov 2007 12:47:39 +0800
Subject: Set proper ATA UDMA mode for bf548 according to system clock.

UDMA Mode - Frequency compatibility

UDMA5 - 100 MB/s   - SCLK  = 133 MHz
UDMA4 - 66 MB/s    - SCLK >=  80 MHz
UDMA3 - 44.4 MB/s  - SCLK >=  50 MHz
UDMA2 - 33 MB/s    - SCLK >=  40 MHz

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
---
 drivers/ata/pata_bf54x.c | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'drivers/ata/pata_bf54x.c')

diff --git a/drivers/ata/pata_bf54x.c b/drivers/ata/pata_bf54x.c
index 81db405a5445..088a41f4e656 100644
--- a/drivers/ata/pata_bf54x.c
+++ b/drivers/ata/pata_bf54x.c
@@ -1489,6 +1489,8 @@ static int __devinit bfin_atapi_probe(struct platform_device *pdev)
 	int board_idx = 0;
 	struct resource *res;
 	struct ata_host *host;
+	unsigned int fsclk = get_sclk();
+	int udma_mode = 5;
 	const struct ata_port_info *ppi[] =
 		{ &bfin_port_info[board_idx], NULL };
 
@@ -1507,6 +1509,11 @@ static int __devinit bfin_atapi_probe(struct platform_device *pdev)
 	if (res == NULL)
 		return -EINVAL;
 
+	while (bfin_port_info[board_idx].udma_mask>0 && udma_fsclk[udma_mode] > fsclk) {
+		udma_mode--;
+		bfin_port_info[board_idx].udma_mask >>= 1;
+	}
+
 	/*
 	 * Now that that's out of the way, wire up the port..
 	 */
-- 
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