From 020f97063dd68a8e3b9aac928ac49a438b7416ce Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 1 Dec 2008 17:40:54 +0000 Subject: [ARM] omap: fix a pile of issues This patch fixes a number of sillies, from missing 'const' to using 'return' in void functions, to functions with no arguments not even 'void' and a cast which isn't required. Acked-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mach-omap1/io.c | 2 +- arch/arm/plat-omap/include/mach/omapfb.h | 4 ++-- arch/arm/plat-omap/sram.c | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index b3bd8ca85118..4c3e582f3d3c 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -128,7 +128,7 @@ void __init omap1_map_common_io(void) * Common low-level hardware init for omap1. This should only get called from * board specific init. */ -void __init omap1_init_common_hw() +void __init omap1_init_common_hw(void) { /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort * on a Posted Write in the TIPB Bridge". diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h index ec67fb428607..7b74d1255e0b 100644 --- a/arch/arm/plat-omap/include/mach/omapfb.h +++ b/arch/arm/plat-omap/include/mach/omapfb.h @@ -353,8 +353,8 @@ struct omapfb_device { u32 pseudo_palette[17]; struct lcd_panel *panel; /* LCD panel */ - struct lcd_ctrl *ctrl; /* LCD controller */ - struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */ + const struct lcd_ctrl *ctrl; /* LCD controller */ + const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */ struct lcd_ctrl_extif *ext_if; /* LCD ctrl external interface */ struct device *dev; diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 9f9a921829c0..dcd9d16da2e9 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -255,7 +255,7 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) if (!_omap_sram_reprogram_clock) omap_sram_error(); - return _omap_sram_reprogram_clock(dpllctl, ckctl); + _omap_sram_reprogram_clock(dpllctl, ckctl); } int __init omap1_sram_init(void) @@ -282,8 +282,8 @@ void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, if (!_omap2_sram_ddr_init) omap_sram_error(); - return _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl, - base_cs, force_unlock); + _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl, + base_cs, force_unlock); } static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val, @@ -294,7 +294,7 @@ void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type) if (!_omap2_sram_reprogram_sdrc) omap_sram_error(); - return _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type); + _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type); } static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); -- cgit v1.2.3 From 82676d76252680fc035247fd4cfdb07ffce5db52 Mon Sep 17 00:00:00 2001 From: Saeed Bishara Date: Thu, 27 Nov 2008 06:21:03 -1100 Subject: [ARM] Orion: fix bug in pcie configuration cycle function field mask The function field is 3 bits. Signed-off-by: Saeed Bishara Signed-off-by: Nicolas Pitre --- arch/arm/plat-orion/pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index 883902fead89..d41d41d78ad9 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c @@ -35,7 +35,7 @@ #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) -#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) +#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) #define PCIE_CONF_DATA_OFF 0x18fc #define PCIE_MASK_OFF 0x1910 #define PCIE_CTRL_OFF 0x1a00 -- cgit v1.2.3 From 94fc7336646b392234c0fafea5d696d020c3677c Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Thu, 4 Dec 2008 03:59:41 +0100 Subject: [ARM] 5339/1: fix __fls() on ARM Commit 0c65f459ce6c intended to fix truncation issues with fls() on ARMv5+ by renaming it to __fls() and wrapping it into a C function. However that didn't take into account the fact that __fls() already already had different semantics in the kernel. Let's move the __fls() code into fls() function directly, and redefine __fls() with the appropriate semantics. While at it, bring a generic __fls() definition for pre ARMv5 too. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/include/asm/bitops.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 9a1db20e032a..63a481fbbed4 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -237,6 +237,7 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset); #if __LINUX_ARM_ARCH__ < 5 #include +#include #include #include #include @@ -277,16 +278,19 @@ static inline int constant_fls(int x) * the clz instruction for much better code efficiency. */ -#define __fls(x) \ - ( __builtin_constant_p(x) ? constant_fls(x) : \ - ({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) ) - -/* Implement fls() in C so that 64-bit args are suitably truncated */ static inline int fls(int x) { - return __fls(x); + int ret; + + if (__builtin_constant_p(x)) + return constant_fls(x); + + asm("clz\t%0, %1" : "=r" (ret) : "r" (x) : "cc"); + ret = 32 - ret; + return ret; } +#define __fls(x) (fls(x) - 1) #define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); }) #define __ffs(x) (ffs(x) - 1) #define ffz(x) __ffs( ~(x) ) -- cgit v1.2.3 From 794baba637999b81aa40e60fae1fa91978e08808 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Fri, 5 Dec 2008 03:25:47 +0100 Subject: [ARM] 5340/1: fix stack placement after noexecstack changes Commit 8ec53663d2698076468b3e1edc4e1b418bd54de3 ("[ARM] Improve non-executable support") added support for detecting non-executable stack binaries. One of the things it does is to make READ_IMPLIES_EXEC be set in ->personality if we are running on a CPU that doesn't support the XN ("Execute Never") page table bit or if we are running a binary that needs an executable stack. This exposed a latent bug in ARM's asm/processor.h due to which we'll end up placing the stack at a very low address, where it will bump into the heap on any application that uses significant amount of stack or heap or both, causing many interesting crashes. Fix this by testing the ADDR_LIMIT_32BIT bit in ->personality instead of testing for equality against PER_LINUX_32BIT. Reviewed-by: Nicolas Pitre Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/include/asm/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 517a4d6ffc74..6ff33790f47b 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -23,7 +23,7 @@ #include #ifdef __KERNEL__ -#define STACK_TOP ((current->personality == PER_LINUX_32BIT) ? \ +#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \ TASK_SIZE : TASK_SIZE_26) #define STACK_TOP_MAX TASK_SIZE #endif -- cgit v1.2.3 From baa745a3378046ca1c5477495df6ccbec7690428 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 7 Dec 2008 09:44:55 +0000 Subject: [ARM] Fix alignment fault handling for ARMv6 and later CPUs On ARMv6 and later CPUs, it is possible for userspace processes to get stuck on a misaligned load or store due to the "ignore fault" setting; unlike previous CPUs, retrying the instruction without the 'A' bit set does not always cause the load to succeed. We have no real option but to default to fixing up alignment faults on these CPUs, and having the CPU fix up those misaligned accesses which it can. Reported-by: Wolfgang Grandegger Signed-off-by: Russell King --- arch/arm/mm/alignment.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 133e65d166b3..2d5884ce0435 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -70,6 +70,10 @@ static unsigned long ai_dword; static unsigned long ai_multi; static int ai_usermode; +#define UM_WARN (1 << 0) +#define UM_FIXUP (1 << 1) +#define UM_SIGNAL (1 << 2) + #ifdef CONFIG_PROC_FS static const char *usermode_action[] = { "ignored", @@ -754,7 +758,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) user: ai_user += 1; - if (ai_usermode & 1) + if (ai_usermode & UM_WARN) printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx " "Address=0x%08lx FSR 0x%03x\n", current->comm, task_pid_nr(current), instrptr, @@ -762,10 +766,10 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) thumb_mode(regs) ? tinstr : instr, addr, fsr); - if (ai_usermode & 2) + if (ai_usermode & UM_FIXUP) goto fixup; - if (ai_usermode & 4) + if (ai_usermode & UM_SIGNAL) force_sig(SIGBUS, current); else set_cr(cr_no_alignment); @@ -796,6 +800,22 @@ static int __init alignment_init(void) res->write_proc = proc_alignment_write; #endif + /* + * ARMv6 and later CPUs can perform unaligned accesses for + * most single load and store instructions up to word size. + * LDM, STM, LDRD and STRD still need to be handled. + * + * Ignoring the alignment fault is not an option on these + * CPUs since we spin re-faulting the instruction without + * making any progress. + */ + if (cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U)) { + cr_alignment &= ~CR_A; + cr_no_alignment &= ~CR_A; + set_cr(cr_alignment); + ai_usermode = UM_FIXUP; + } + hook_fault_code(1, do_alignment, SIGILL, "alignment exception"); hook_fault_code(3, do_alignment, SIGILL, "alignment exception"); -- cgit v1.2.3