From 9d2f510a66ec60411536b83dab831ee091c84307 Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Fri, 3 Nov 2017 15:13:20 +1100 Subject: powerpc/64s/idle: avoid POWER9 DD1 and DD2.0 ERAT workaround on DD2.1 DD2.1 does not have to flush the ERAT after a state-loss idle. Performance testing was done on a DD2.1 using only the stop0 idle state (the shallowest state which supports state loss), using context_switch selftest configured to ping-poing between two threads on the same core and two different cores. Performance improvement for same core is 7.0%, different cores is 14.8%. Reviewed-by: Vaidyanathan Srinivasan Signed-off-by: Nicholas Piggin Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/idle_book3s.S | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc/kernel/idle_book3s.S') diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S index 175d49f468af..d77766814090 100644 --- a/arch/powerpc/kernel/idle_book3s.S +++ b/arch/powerpc/kernel/idle_book3s.S @@ -542,7 +542,9 @@ pnv_restore_hyp_resource_arch300: * then clear bit 60 in MMCRA to ensure the PMU starts running. */ blt cr3,1f +BEGIN_FTR_SECTION PPC_INVALIDATE_ERAT +END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1 | CPU_FTR_POWER9_DD20) ld r1,PACAR1(r13) mfspr r4,SPRN_MMCRA ori r4,r4,(1 << (63-60)) -- cgit v1.2.3