From f81cc5ac8c2b5c0e2e190ea181ab2b9e5cf8497d Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Thu, 19 Sep 2019 13:42:45 +0200 Subject: openrisc: add support for LiteX This adds support for a basic LiteX-based SoC with a mor1kx soft CPU. Signed-off-by: Filip Kokosinski Signed-off-by: Mateusz Holenko [shorne: Merged in soc-cntl patch, removed CROSS_COMPILE, sort MAINT.] Signed-off-by: Stafford Horne --- arch/openrisc/boot/dts/or1klitex.dts | 55 +++++++++++++++++++++++++++++++ arch/openrisc/configs/or1klitex_defconfig | 18 ++++++++++ 2 files changed, 73 insertions(+) create mode 100644 arch/openrisc/boot/dts/or1klitex.dts create mode 100644 arch/openrisc/configs/or1klitex_defconfig (limited to 'arch/openrisc') diff --git a/arch/openrisc/boot/dts/or1klitex.dts b/arch/openrisc/boot/dts/or1klitex.dts new file mode 100644 index 000000000000..3f9867aa3844 --- /dev/null +++ b/arch/openrisc/boot/dts/or1klitex.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LiteX-based System on Chip + * + * Copyright (C) 2019 Antmicro + */ + +/dts-v1/; +/ { + compatible = "opencores,or1ksim"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + aliases { + serial0 = &serial0; + }; + + chosen { + bootargs = "console=liteuart"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <100000000>; + }; + }; + + pic: pic { + compatible = "opencores,or1k-pic"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@e0002000 { + device_type = "serial"; + compatible = "litex,liteuart"; + reg = <0xe0002000 0x100>; + }; + + soc_ctrl0: soc_controller@e0000000 { + compatible = "litex,soc-controller"; + reg = <0xe0000000 0xc>; + status = "okay"; + }; +}; diff --git a/arch/openrisc/configs/or1klitex_defconfig b/arch/openrisc/configs/or1klitex_defconfig new file mode 100644 index 000000000000..3c2c70d3d740 --- /dev/null +++ b/arch/openrisc/configs/or1klitex_defconfig @@ -0,0 +1,18 @@ +CONFIG_BLK_DEV_INITRD=y +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y +CONFIG_BUG_ON_DATA_CORRUPTION=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_EMBEDDED=y +CONFIG_HZ_100=y +CONFIG_INITRAMFS_SOURCE="openrisc-rootfs.cpio.gz" +CONFIG_OF_OVERLAY=y +CONFIG_OPENRISC_BUILTIN_DTB="or1klitex" +CONFIG_PANIC_ON_OOPS=y +CONFIG_PRINTK_TIME=y +CONFIG_LITEX_SOC_CONTROLLER=y +CONFIG_SERIAL_LITEUART=y +CONFIG_SERIAL_LITEUART_CONSOLE=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_TTY_PRINTK=y -- cgit v1.2.3 From 28b852b1dc351efc6525234c5adfd5bc2ad6d6e1 Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Sun, 18 Oct 2020 06:37:01 +0900 Subject: openrisc: fix trap for debugger breakpoint signalling I have been working on getting native Linux GDB support working for the OpenRISC port. The trap signal handler here was wrong in a few ways. During trap handling address (from the EEAR register) is not set by the CPU, so it is not correct to use here. We want to use trap as a break-point so use TRAP_BRKPT. Adding 4 to the pc was incorrect and causing GDB to think the breakpoint was not hit. Fixing these allows GDB to work now. Signed-off-by: Stafford Horne --- arch/openrisc/kernel/traps.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/openrisc') diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c index 206e5325e61b..4d61333c2623 100644 --- a/arch/openrisc/kernel/traps.c +++ b/arch/openrisc/kernel/traps.c @@ -238,9 +238,7 @@ void __init trap_init(void) asmlinkage void do_trap(struct pt_regs *regs, unsigned long address) { - force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)address); - - regs->pc += 4; + force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->pc); } asmlinkage void do_unaligned_access(struct pt_regs *regs, unsigned long address) -- cgit v1.2.3 From d8398bf840f8964220508aff7901c924e322f5e8 Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Sat, 21 Nov 2020 06:54:56 +0900 Subject: openrisc: add local64.h to fix blk-iocost build As of 5.10 OpenRISC allyesconfig builds fail with the following error. $ make ARCH=openrisc CROSS_COMPILE=or1k-elf- block/blk-iocost.o CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CC block/blk-iocost.o block/blk-iocost.c:183:10: fatal error: asm/local64.h: No such file or directory 183 | #include | ^~~~~~~~~~~~~~~ compilation terminated. The new include of local64.h was added in commit 5e124f74325d ("blk-iocost: use local[64]_t for percpu stat") by Tejun. Adding the generic version of local64.h to OpenRISC fixes the build issue. Cc: Tejun Heo Signed-off-by: Stafford Horne --- arch/openrisc/include/asm/Kbuild | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/openrisc') diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild index ca5987e11053..442f3d3bcd90 100644 --- a/arch/openrisc/include/asm/Kbuild +++ b/arch/openrisc/include/asm/Kbuild @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 generic-y += extable.h generic-y += kvm_para.h +generic-y += local64.h generic-y += mcs_spinlock.h generic-y += qspinlock_types.h generic-y += qspinlock.h -- cgit v1.2.3