From f106eac91edbd28de23b0bc58be82f68d976e24f Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Sat, 28 Apr 2012 11:13:04 -0300 Subject: m68k: fix compiler warning by properly inlining flat_set_persistent() This patch removes the following warning: fs/binfmt_flat.c:752: warning: unused variable 'persistent'. There is neither functionality change, nor extra code generated. Signed-off-by: Ezequiel Garcia Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/flat.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/flat.h b/arch/m68k/include/asm/flat.h index a0e290793978..f9454b89a51b 100644 --- a/arch/m68k/include/asm/flat.h +++ b/arch/m68k/include/asm/flat.h @@ -11,6 +11,11 @@ #define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp) #define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) #define flat_get_relocate_addr(rel) (rel) -#define flat_set_persistent(relval, p) 0 + +static inline int flat_set_persistent(unsigned long relval, + unsigned long *persistent) +{ + return 0; +} #endif /* __M68KNOMMU_FLAT_H__ */ -- cgit v1.2.3 From c269d4efaab0847947e87df7a5a8b6c5817d9f1d Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 16 Apr 2012 15:59:29 +1000 Subject: m68knommu: introduce macros to simplify ColdFire GPIO table initialization We have very large tables in the ColdFire CPU GPIO setup code that essentially boil down to 2 distinct types of GPIO pin initiaization. Using 2 macros we can reduce these large tables to at most a dozen lines of setup code, and in quite a few cases a single table entry. Introduce these 2 macros into the existing mcfgpio.h header. Signed-off-by: Greg Ungerer Acked-by: Steven King --- arch/m68k/include/asm/mcfgpio.h | 54 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h index ee5e4ccce89e..1bc877b45554 100644 --- a/arch/m68k/include/asm/mcfgpio.h +++ b/arch/m68k/include/asm/mcfgpio.h @@ -37,4 +37,58 @@ void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int); int mcf_gpio_request(struct gpio_chip *, unsigned); void mcf_gpio_free(struct gpio_chip *, unsigned); +/* + * Define macros to ease the pain of setting up the GPIO tables. There + * are two cases we need to deal with here, they cover all currently + * available ColdFire GPIO hardware. There are of course minor differences + * in the layout and number of bits in each ColdFire part, but the macros + * take all that in. + * + * Firstly is the conventional GPIO registers where we toggle individual + * bits in a register, preserving the other bits in the register. For + * lack of a better term I have called this the slow method. + */ +#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \ + { \ + .gpio_chip = { \ + .label = #mlabel, \ + .request = mcf_gpio_request, \ + .free = mcf_gpio_free, \ + .direction_input = mcf_gpio_direction_input, \ + .direction_output = mcf_gpio_direction_output,\ + .get = mcf_gpio_get_value, \ + .set = mcf_gpio_set_value, \ + .base = mbase, \ + .ngpio = mngpio, \ + }, \ + .pddr = (void __iomem *) mpddr, \ + .podr = (void __iomem *) mpodr, \ + .ppdr = (void __iomem *) mppdr, \ + } + +/* + * Secondly is the faster case, where we have set and clear registers + * that allow us to set or clear a bit with a single write, not having + * to worry about preserving other bits. + */ +#define MCFGPF(mlabel, mbase, mngpio) \ + { \ + .gpio_chip = { \ + .label = #mlabel, \ + .request = mcf_gpio_request, \ + .free = mcf_gpio_free, \ + .direction_input = mcf_gpio_direction_input, \ + .direction_output = mcf_gpio_direction_output,\ + .get = mcf_gpio_get_value, \ + .set = mcf_gpio_set_value_fast, \ + .base = mbase, \ + .ngpio = mngpio, \ + }, \ + .pddr = (void __iomem *) MCFGPIO_PDDR_##mlabel, \ + .podr = (void __iomem *) MCFGPIO_PODR_##mlabel, \ + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ + .setr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ + .clrr = (void __iomem *) MCFGPIO_PCLRR_##mlabel, \ + } + #endif -- cgit v1.2.3 From c222f5f41fca51a4639d88a940f9283d04ba2c0c Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 16 Apr 2012 16:59:37 +1000 Subject: m68knommu: switch to GPIO init macros in ColdFire 528x init code Modify the GPIO setup table to use the mcfgpio.h macros for table init. Simplifies code and reduces line count significantly. We also need to rename some of the GPIO registers to be consistent with all other ColdFire parts (we can't use the new GPIO macros otherwise). Signed-off-by: Greg Ungerer Acked-by: Steven King --- arch/m68k/include/asm/m528xsim.h | 179 ++++++++-------- arch/m68k/platform/528x/gpio.c | 427 +++------------------------------------ 2 files changed, 103 insertions(+), 503 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index 569476fba18c..d63b99ff7ff7 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -97,100 +97,81 @@ /* * GPIO registers */ -#define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000) -#define MCFGPIO_PORTB (MCF_IPSBAR + 0x00100001) -#define MCFGPIO_PORTC (MCF_IPSBAR + 0x00100002) -#define MCFGPIO_PORTD (MCF_IPSBAR + 0x00100003) -#define MCFGPIO_PORTE (MCF_IPSBAR + 0x00100004) -#define MCFGPIO_PORTF (MCF_IPSBAR + 0x00100005) -#define MCFGPIO_PORTG (MCF_IPSBAR + 0x00100006) -#define MCFGPIO_PORTH (MCF_IPSBAR + 0x00100007) -#define MCFGPIO_PORTJ (MCF_IPSBAR + 0x00100008) -#define MCFGPIO_PORTDD (MCF_IPSBAR + 0x00100009) -#define MCFGPIO_PORTEH (MCF_IPSBAR + 0x0010000A) -#define MCFGPIO_PORTEL (MCF_IPSBAR + 0x0010000B) -#define MCFGPIO_PORTAS (MCF_IPSBAR + 0x0010000C) -#define MCFGPIO_PORTQS (MCF_IPSBAR + 0x0010000D) -#define MCFGPIO_PORTSD (MCF_IPSBAR + 0x0010000E) -#define MCFGPIO_PORTTC (MCF_IPSBAR + 0x0010000F) -#define MCFGPIO_PORTTD (MCF_IPSBAR + 0x00100010) -#define MCFGPIO_PORTUA (MCF_IPSBAR + 0x00100011) - -#define MCFGPIO_DDRA (MCF_IPSBAR + 0x00100014) -#define MCFGPIO_DDRB (MCF_IPSBAR + 0x00100015) -#define MCFGPIO_DDRC (MCF_IPSBAR + 0x00100016) -#define MCFGPIO_DDRD (MCF_IPSBAR + 0x00100017) -#define MCFGPIO_DDRE (MCF_IPSBAR + 0x00100018) -#define MCFGPIO_DDRF (MCF_IPSBAR + 0x00100019) -#define MCFGPIO_DDRG (MCF_IPSBAR + 0x0010001A) -#define MCFGPIO_DDRH (MCF_IPSBAR + 0x0010001B) -#define MCFGPIO_DDRJ (MCF_IPSBAR + 0x0010001C) -#define MCFGPIO_DDRDD (MCF_IPSBAR + 0x0010001D) -#define MCFGPIO_DDREH (MCF_IPSBAR + 0x0010001E) -#define MCFGPIO_DDREL (MCF_IPSBAR + 0x0010001F) -#define MCFGPIO_DDRAS (MCF_IPSBAR + 0x00100020) -#define MCFGPIO_DDRQS (MCF_IPSBAR + 0x00100021) -#define MCFGPIO_DDRSD (MCF_IPSBAR + 0x00100022) -#define MCFGPIO_DDRTC (MCF_IPSBAR + 0x00100023) -#define MCFGPIO_DDRTD (MCF_IPSBAR + 0x00100024) -#define MCFGPIO_DDRUA (MCF_IPSBAR + 0x00100025) - -#define MCFGPIO_PORTAP (MCF_IPSBAR + 0x00100028) -#define MCFGPIO_PORTBP (MCF_IPSBAR + 0x00100029) -#define MCFGPIO_PORTCP (MCF_IPSBAR + 0x0010002A) -#define MCFGPIO_PORTDP (MCF_IPSBAR + 0x0010002B) -#define MCFGPIO_PORTEP (MCF_IPSBAR + 0x0010002C) -#define MCFGPIO_PORTFP (MCF_IPSBAR + 0x0010002D) -#define MCFGPIO_PORTGP (MCF_IPSBAR + 0x0010002E) -#define MCFGPIO_PORTHP (MCF_IPSBAR + 0x0010002F) -#define MCFGPIO_PORTJP (MCF_IPSBAR + 0x00100030) -#define MCFGPIO_PORTDDP (MCF_IPSBAR + 0x00100031) -#define MCFGPIO_PORTEHP (MCF_IPSBAR + 0x00100032) -#define MCFGPIO_PORTELP (MCF_IPSBAR + 0x00100033) -#define MCFGPIO_PORTASP (MCF_IPSBAR + 0x00100034) -#define MCFGPIO_PORTQSP (MCF_IPSBAR + 0x00100035) -#define MCFGPIO_PORTSDP (MCF_IPSBAR + 0x00100036) -#define MCFGPIO_PORTTCP (MCF_IPSBAR + 0x00100037) -#define MCFGPIO_PORTTDP (MCF_IPSBAR + 0x00100038) -#define MCFGPIO_PORTUAP (MCF_IPSBAR + 0x00100039) - -#define MCFGPIO_SETA (MCF_IPSBAR + 0x00100028) -#define MCFGPIO_SETB (MCF_IPSBAR + 0x00100029) -#define MCFGPIO_SETC (MCF_IPSBAR + 0x0010002A) -#define MCFGPIO_SETD (MCF_IPSBAR + 0x0010002B) -#define MCFGPIO_SETE (MCF_IPSBAR + 0x0010002C) -#define MCFGPIO_SETF (MCF_IPSBAR + 0x0010002D) -#define MCFGPIO_SETG (MCF_IPSBAR + 0x0010002E) -#define MCFGPIO_SETH (MCF_IPSBAR + 0x0010002F) -#define MCFGPIO_SETJ (MCF_IPSBAR + 0x00100030) -#define MCFGPIO_SETDD (MCF_IPSBAR + 0x00100031) -#define MCFGPIO_SETEH (MCF_IPSBAR + 0x00100032) -#define MCFGPIO_SETEL (MCF_IPSBAR + 0x00100033) -#define MCFGPIO_SETAS (MCF_IPSBAR + 0x00100034) -#define MCFGPIO_SETQS (MCF_IPSBAR + 0x00100035) -#define MCFGPIO_SETSD (MCF_IPSBAR + 0x00100036) -#define MCFGPIO_SETTC (MCF_IPSBAR + 0x00100037) -#define MCFGPIO_SETTD (MCF_IPSBAR + 0x00100038) -#define MCFGPIO_SETUA (MCF_IPSBAR + 0x00100039) - -#define MCFGPIO_CLRA (MCF_IPSBAR + 0x0010003C) -#define MCFGPIO_CLRB (MCF_IPSBAR + 0x0010003D) -#define MCFGPIO_CLRC (MCF_IPSBAR + 0x0010003E) -#define MCFGPIO_CLRD (MCF_IPSBAR + 0x0010003F) -#define MCFGPIO_CLRE (MCF_IPSBAR + 0x00100040) -#define MCFGPIO_CLRF (MCF_IPSBAR + 0x00100041) -#define MCFGPIO_CLRG (MCF_IPSBAR + 0x00100042) -#define MCFGPIO_CLRH (MCF_IPSBAR + 0x00100043) -#define MCFGPIO_CLRJ (MCF_IPSBAR + 0x00100044) -#define MCFGPIO_CLRDD (MCF_IPSBAR + 0x00100045) -#define MCFGPIO_CLREH (MCF_IPSBAR + 0x00100046) -#define MCFGPIO_CLREL (MCF_IPSBAR + 0x00100047) -#define MCFGPIO_CLRAS (MCF_IPSBAR + 0x00100048) -#define MCFGPIO_CLRQS (MCF_IPSBAR + 0x00100049) -#define MCFGPIO_CLRSD (MCF_IPSBAR + 0x0010004A) -#define MCFGPIO_CLRTC (MCF_IPSBAR + 0x0010004B) -#define MCFGPIO_CLRTD (MCF_IPSBAR + 0x0010004C) -#define MCFGPIO_CLRUA (MCF_IPSBAR + 0x0010004D) +#define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000) +#define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001) +#define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002) +#define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003) +#define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004) +#define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005) +#define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006) +#define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007) +#define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008) +#define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009) +#define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A) +#define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B) +#define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C) +#define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D) +#define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E) +#define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F) +#define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010) +#define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011) + +#define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014) +#define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015) +#define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016) +#define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017) +#define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018) +#define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019) +#define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A) +#define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B) +#define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C) +#define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D) +#define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E) +#define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F) +#define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020) +#define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021) +#define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022) +#define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023) +#define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024) +#define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025) + +#define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028) +#define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029) +#define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A) +#define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B) +#define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C) +#define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D) +#define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E) +#define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F) +#define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030) +#define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031) +#define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032) +#define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033) +#define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034) +#define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035) +#define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036) +#define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037) +#define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038) +#define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039) + +#define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C) +#define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D) +#define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E) +#define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F) +#define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040) +#define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041) +#define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042) +#define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043) +#define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044) +#define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045) +#define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046) +#define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047) +#define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048) +#define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049) +#define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A) +#define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B) +#define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C) +#define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D) #define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050) #define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051) @@ -242,11 +223,11 @@ * definitions for generic gpio support * */ -#define MCFGPIO_PODR MCFGPIO_PORTA /* port output data */ -#define MCFGPIO_PDDR MCFGPIO_DDRA /* port data direction */ -#define MCFGPIO_PPDR MCFGPIO_PORTAP /* port pin data */ -#define MCFGPIO_SETR MCFGPIO_SETA /* set output */ -#define MCFGPIO_CLRR MCFGPIO_CLRA /* clr output */ +#define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */ +#define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */ +#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */ +#define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */ +#define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */ #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE diff --git a/arch/m68k/platform/528x/gpio.c b/arch/m68k/platform/528x/gpio.c index 526db665d87e..81b161c8667f 100644 --- a/arch/m68k/platform/528x/gpio.c +++ b/arch/m68k/platform/528x/gpio.c @@ -21,410 +21,29 @@ #include static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "NQ", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .base = 1, - .ngpio = 7, - }, - .pddr = (void __iomem *)MCFEPORT_EPDDR, - .podr = (void __iomem *)MCFEPORT_EPDR, - .ppdr = (void __iomem *)MCFEPORT_EPPDR, - }, - { - .gpio_chip = { - .label = "TA", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 8, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPTA_GPTDDR, - .podr = (void __iomem *)MCFGPTA_GPTPORT, - .ppdr = (void __iomem *)MCFGPTB_GPTPORT, - }, - { - .gpio_chip = { - .label = "TB", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 16, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPTB_GPTDDR, - .podr = (void __iomem *)MCFGPTB_GPTPORT, - .ppdr = (void __iomem *)MCFGPTB_GPTPORT, - }, - { - .gpio_chip = { - .label = "QA", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 24, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFQADC_DDRQA, - .podr = (void __iomem *)MCFQADC_PORTQA, - .ppdr = (void __iomem *)MCFQADC_PORTQA, - }, - { - .gpio_chip = { - .label = "QB", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 32, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFQADC_DDRQB, - .podr = (void __iomem *)MCFQADC_PORTQB, - .ppdr = (void __iomem *)MCFQADC_PORTQB, - }, - { - .gpio_chip = { - .label = "A", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 40, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRA, - .podr = (void __iomem *)MCFGPIO_PORTA, - .ppdr = (void __iomem *)MCFGPIO_PORTAP, - .setr = (void __iomem *)MCFGPIO_SETA, - .clrr = (void __iomem *)MCFGPIO_CLRA, - }, - { - .gpio_chip = { - .label = "B", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 48, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRB, - .podr = (void __iomem *)MCFGPIO_PORTB, - .ppdr = (void __iomem *)MCFGPIO_PORTBP, - .setr = (void __iomem *)MCFGPIO_SETB, - .clrr = (void __iomem *)MCFGPIO_CLRB, - }, - { - .gpio_chip = { - .label = "C", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 56, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRC, - .podr = (void __iomem *)MCFGPIO_PORTC, - .ppdr = (void __iomem *)MCFGPIO_PORTCP, - .setr = (void __iomem *)MCFGPIO_SETC, - .clrr = (void __iomem *)MCFGPIO_CLRC, - }, - { - .gpio_chip = { - .label = "D", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 64, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRD, - .podr = (void __iomem *)MCFGPIO_PORTD, - .ppdr = (void __iomem *)MCFGPIO_PORTDP, - .setr = (void __iomem *)MCFGPIO_SETD, - .clrr = (void __iomem *)MCFGPIO_CLRD, - }, - { - .gpio_chip = { - .label = "E", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 72, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRE, - .podr = (void __iomem *)MCFGPIO_PORTE, - .ppdr = (void __iomem *)MCFGPIO_PORTEP, - .setr = (void __iomem *)MCFGPIO_SETE, - .clrr = (void __iomem *)MCFGPIO_CLRE, - }, - { - .gpio_chip = { - .label = "F", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 80, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRF, - .podr = (void __iomem *)MCFGPIO_PORTF, - .ppdr = (void __iomem *)MCFGPIO_PORTFP, - .setr = (void __iomem *)MCFGPIO_SETF, - .clrr = (void __iomem *)MCFGPIO_CLRF, - }, - { - .gpio_chip = { - .label = "G", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 88, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRG, - .podr = (void __iomem *)MCFGPIO_PORTG, - .ppdr = (void __iomem *)MCFGPIO_PORTGP, - .setr = (void __iomem *)MCFGPIO_SETG, - .clrr = (void __iomem *)MCFGPIO_CLRG, - }, - { - .gpio_chip = { - .label = "H", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 96, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRH, - .podr = (void __iomem *)MCFGPIO_PORTH, - .ppdr = (void __iomem *)MCFGPIO_PORTHP, - .setr = (void __iomem *)MCFGPIO_SETH, - .clrr = (void __iomem *)MCFGPIO_CLRH, - }, - { - .gpio_chip = { - .label = "J", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 104, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRJ, - .podr = (void __iomem *)MCFGPIO_PORTJ, - .ppdr = (void __iomem *)MCFGPIO_PORTJP, - .setr = (void __iomem *)MCFGPIO_SETJ, - .clrr = (void __iomem *)MCFGPIO_CLRJ, - }, - { - .gpio_chip = { - .label = "DD", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 112, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDRDD, - .podr = (void __iomem *)MCFGPIO_PORTDD, - .ppdr = (void __iomem *)MCFGPIO_PORTDDP, - .setr = (void __iomem *)MCFGPIO_SETDD, - .clrr = (void __iomem *)MCFGPIO_CLRDD, - }, - { - .gpio_chip = { - .label = "EH", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 120, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDREH, - .podr = (void __iomem *)MCFGPIO_PORTEH, - .ppdr = (void __iomem *)MCFGPIO_PORTEHP, - .setr = (void __iomem *)MCFGPIO_SETEH, - .clrr = (void __iomem *)MCFGPIO_CLREH, - }, - { - .gpio_chip = { - .label = "EL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 128, - .ngpio = 8, - }, - .pddr = (void __iomem *)MCFGPIO_DDREL, - .podr = (void __iomem *)MCFGPIO_PORTEL, - .ppdr = (void __iomem *)MCFGPIO_PORTELP, - .setr = (void __iomem *)MCFGPIO_SETEL, - .clrr = (void __iomem *)MCFGPIO_CLREL, - }, - { - .gpio_chip = { - .label = "AS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 136, - .ngpio = 6, - }, - .pddr = (void __iomem *)MCFGPIO_DDRAS, - .podr = (void __iomem *)MCFGPIO_PORTAS, - .ppdr = (void __iomem *)MCFGPIO_PORTASP, - .setr = (void __iomem *)MCFGPIO_SETAS, - .clrr = (void __iomem *)MCFGPIO_CLRAS, - }, - { - .gpio_chip = { - .label = "QS", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 144, - .ngpio = 7, - }, - .pddr = (void __iomem *)MCFGPIO_DDRQS, - .podr = (void __iomem *)MCFGPIO_PORTQS, - .ppdr = (void __iomem *)MCFGPIO_PORTQSP, - .setr = (void __iomem *)MCFGPIO_SETQS, - .clrr = (void __iomem *)MCFGPIO_CLRQS, - }, - { - .gpio_chip = { - .label = "SD", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 152, - .ngpio = 6, - }, - .pddr = (void __iomem *)MCFGPIO_DDRSD, - .podr = (void __iomem *)MCFGPIO_PORTSD, - .ppdr = (void __iomem *)MCFGPIO_PORTSDP, - .setr = (void __iomem *)MCFGPIO_SETSD, - .clrr = (void __iomem *)MCFGPIO_CLRSD, - }, - { - .gpio_chip = { - .label = "TC", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 160, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPIO_DDRTC, - .podr = (void __iomem *)MCFGPIO_PORTTC, - .ppdr = (void __iomem *)MCFGPIO_PORTTCP, - .setr = (void __iomem *)MCFGPIO_SETTC, - .clrr = (void __iomem *)MCFGPIO_CLRTC, - }, - { - .gpio_chip = { - .label = "TD", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 168, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPIO_DDRTD, - .podr = (void __iomem *)MCFGPIO_PORTTD, - .ppdr = (void __iomem *)MCFGPIO_PORTTDP, - .setr = (void __iomem *)MCFGPIO_SETTD, - .clrr = (void __iomem *)MCFGPIO_CLRTD, - }, - { - .gpio_chip = { - .label = "UA", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 176, - .ngpio = 4, - }, - .pddr = (void __iomem *)MCFGPIO_DDRUA, - .podr = (void __iomem *)MCFGPIO_PORTUA, - .ppdr = (void __iomem *)MCFGPIO_PORTUAP, - .setr = (void __iomem *)MCFGPIO_SETUA, - .clrr = (void __iomem *)MCFGPIO_CLRUA, - }, + MCFGPS(NQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), + MCFGPS(TA, 8, 4, MCFGPTA_GPTDDR, MCFGPTA_GPTPORT, MCFGPTB_GPTPORT), + MCFGPS(TB, 16, 4, MCFGPTB_GPTDDR, MCFGPTB_GPTPORT, MCFGPTB_GPTPORT), + MCFGPS(QA, 24, 4, MCFQADC_DDRQA, MCFQADC_PORTQA, MCFQADC_PORTQA), + MCFGPS(QB, 32, 4, MCFQADC_DDRQB, MCFQADC_PORTQB, MCFQADC_PORTQB), + MCFGPF(A, 40, 8), + MCFGPF(B, 48, 8), + MCFGPF(C, 56, 8), + MCFGPF(D, 64, 8), + MCFGPF(E, 72, 8), + MCFGPF(F, 80, 8), + MCFGPF(G, 88, 8), + MCFGPF(H, 96, 8), + MCFGPF(J, 104, 8), + MCFGPF(DD, 112, 8), + MCFGPF(EH, 120, 8), + MCFGPF(EL, 128, 8), + MCFGPF(AS, 136, 6), + MCFGPF(QS, 144, 7), + MCFGPF(SD, 152, 6), + MCFGPF(TC, 160, 4), + MCFGPF(TD, 168, 4), + MCFGPF(UA, 176, 4), }; static int __init mcf_gpio_init(void) -- cgit v1.2.3 From f23c144d4265b9251a4146e057af668bcd7667cb Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 17 Apr 2012 13:25:38 +1000 Subject: m68knommu: make duplicated ColdFire GPIO init code common for all The code that adds each ColdFire platforms GPIO signals is duplicated in each platforms specific code. Remove it from each platforms code and put a single version in the existing ColdFire gpio subsystem init code. Signed-off-by: Greg Ungerer Acked-by: Steven King --- arch/m68k/include/asm/mcfgpio.h | 3 +++ arch/m68k/platform/5206/gpio.c | 12 ++---------- arch/m68k/platform/520x/gpio.c | 12 ++---------- arch/m68k/platform/523x/gpio.c | 12 ++---------- arch/m68k/platform/5249/gpio.c | 12 ++---------- arch/m68k/platform/5272/gpio.c | 12 ++---------- arch/m68k/platform/527x/gpio.c | 12 ++---------- arch/m68k/platform/528x/gpio.c | 12 ++---------- arch/m68k/platform/5307/gpio.c | 12 ++---------- arch/m68k/platform/532x/gpio.c | 12 ++---------- arch/m68k/platform/5407/gpio.c | 12 ++---------- arch/m68k/platform/54xx/config.c | 7 +++++++ arch/m68k/platform/coldfire/gpio.c | 4 ++++ 13 files changed, 34 insertions(+), 100 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h index 1bc877b45554..fe468eaa51e0 100644 --- a/arch/m68k/include/asm/mcfgpio.h +++ b/arch/m68k/include/asm/mcfgpio.h @@ -29,6 +29,9 @@ struct mcf_gpio_chip { const u8 *gpio_to_pinmux; }; +extern struct mcf_gpio_chip mcf_gpio_chips[]; +extern unsigned int mcf_gpio_chips_size; + int mcf_gpio_direction_input(struct gpio_chip *, unsigned); int mcf_gpio_get_value(struct gpio_chip *, unsigned); int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int); diff --git a/arch/m68k/platform/5206/gpio.c b/arch/m68k/platform/5206/gpio.c index 200a7acf0842..a652f8e550c6 100644 --- a/arch/m68k/platform/5206/gpio.c +++ b/arch/m68k/platform/5206/gpio.c @@ -20,16 +20,8 @@ #include #include -static struct mcf_gpio_chip mcf_gpio_chips[] = { +struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPS(PP, 0, 8, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), }; -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); diff --git a/arch/m68k/platform/520x/gpio.c b/arch/m68k/platform/520x/gpio.c index 96b368578baf..49387c34f0c4 100644 --- a/arch/m68k/platform/520x/gpio.c +++ b/arch/m68k/platform/520x/gpio.c @@ -20,7 +20,7 @@ #include #include -static struct mcf_gpio_chip mcf_gpio_chips[] = { +struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), MCFGPF(CS, 9, 3), MCFGPF(FECI2C, 16, 4), @@ -31,12 +31,4 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPF(FECL, 56, 8), }; -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); diff --git a/arch/m68k/platform/523x/gpio.c b/arch/m68k/platform/523x/gpio.c index 8e6e30e80361..07806eb34dd7 100644 --- a/arch/m68k/platform/523x/gpio.c +++ b/arch/m68k/platform/523x/gpio.c @@ -20,7 +20,7 @@ #include #include -static struct mcf_gpio_chip mcf_gpio_chips[] = { +struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), MCFGPF(ADDR, 13, 3), MCFGPF(DATAH, 16, 8), @@ -37,12 +37,4 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPF(ETPU, 104, 3), }; -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); diff --git a/arch/m68k/platform/5249/gpio.c b/arch/m68k/platform/5249/gpio.c index 775d618b9a44..422e45fe771d 100644 --- a/arch/m68k/platform/5249/gpio.c +++ b/arch/m68k/platform/5249/gpio.c @@ -20,17 +20,9 @@ #include #include -static struct mcf_gpio_chip mcf_gpio_chips[] = { +struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPS(GPIO0, 0, 32, MCFSIM2_GPIOENABLE, MCFSIM2_GPIOWRITE, MCFSIM2_GPIOREAD), MCFGPS(GPIO1, 32, 32, MCFSIM2_GPIO1ENABLE, MCFSIM2_GPIO1WRITE, MCFSIM2_GPIO1READ), }; -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); diff --git a/arch/m68k/platform/5272/gpio.c b/arch/m68k/platform/5272/gpio.c index 91358b830fc9..c029dab7baf3 100644 --- a/arch/m68k/platform/5272/gpio.c +++ b/arch/m68k/platform/5272/gpio.c @@ -20,18 +20,10 @@ #include #include -static struct mcf_gpio_chip mcf_gpio_chips[] = { +struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPS(PA, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), MCFGPS(PB, 16, 16, MCFSIM_PBDDR, MCFSIM_PBDAT, MCFSIM_PBDAT), MCFGPS(Pc, 32, 16, MCFSIM_PCDDR, MCFSIM_PCDAT, MCFSIM_PCDAT), }; -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); diff --git a/arch/m68k/platform/527x/gpio.c b/arch/m68k/platform/527x/gpio.c index b612a63b6c20..1c8633be71ab 100644 --- a/arch/m68k/platform/527x/gpio.c +++ b/arch/m68k/platform/527x/gpio.c @@ -20,7 +20,7 @@ #include #include -static struct mcf_gpio_chip mcf_gpio_chips[] = { +struct mcf_gpio_chip mcf_gpio_chips[] = { #if defined(CONFIG_M5271) MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), MCFGPF(ADDR, 13, 3), @@ -58,12 +58,4 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { #endif }; -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); diff --git a/arch/m68k/platform/528x/gpio.c b/arch/m68k/platform/528x/gpio.c index 81b161c8667f..79459acd8d36 100644 --- a/arch/m68k/platform/528x/gpio.c +++ b/arch/m68k/platform/528x/gpio.c @@ -20,7 +20,7 @@ #include #include -static struct mcf_gpio_chip mcf_gpio_chips[] = { +struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPS(NQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), MCFGPS(TA, 8, 4, MCFGPTA_GPTDDR, MCFGPTA_GPTPORT, MCFGPTB_GPTPORT), MCFGPS(TB, 16, 4, MCFGPTB_GPTDDR, MCFGPTB_GPTPORT, MCFGPTB_GPTPORT), @@ -46,12 +46,4 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPF(UA, 176, 4), }; -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); diff --git a/arch/m68k/platform/5307/gpio.c b/arch/m68k/platform/5307/gpio.c index 91d042030657..7bbbea7a8556 100644 --- a/arch/m68k/platform/5307/gpio.c +++ b/arch/m68k/platform/5307/gpio.c @@ -20,16 +20,8 @@ #include #include -static struct mcf_gpio_chip mcf_gpio_chips[] = { +struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), }; -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); diff --git a/arch/m68k/platform/532x/gpio.c b/arch/m68k/platform/532x/gpio.c index 9454c65e40ef..3e1b71dc7042 100644 --- a/arch/m68k/platform/532x/gpio.c +++ b/arch/m68k/platform/532x/gpio.c @@ -20,7 +20,7 @@ #include #include -static struct mcf_gpio_chip mcf_gpio_chips[] = { +struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), MCFGPF(FECH, 8, 8), MCFGPF(FECL, 16, 8), @@ -40,12 +40,4 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPF(LCDCTLL, 128, 8), }; -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); diff --git a/arch/m68k/platform/5407/gpio.c b/arch/m68k/platform/5407/gpio.c index 91d042030657..7bbbea7a8556 100644 --- a/arch/m68k/platform/5407/gpio.c +++ b/arch/m68k/platform/5407/gpio.c @@ -20,16 +20,8 @@ #include #include -static struct mcf_gpio_chip mcf_gpio_chips[] = { +struct mcf_gpio_chip mcf_gpio_chips[] = { MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), }; -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); diff --git a/arch/m68k/platform/54xx/config.c b/arch/m68k/platform/54xx/config.c index 2081c6cbb3de..20672dadb252 100644 --- a/arch/m68k/platform/54xx/config.c +++ b/arch/m68k/platform/54xx/config.c @@ -21,12 +21,19 @@ #include #include #include +#include #ifdef CONFIG_MMU #include #endif /***************************************************************************/ +struct mcf_gpio_chip mcf_gpio_chips[] = { }; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +/***************************************************************************/ + static void __init m54xx_uarts_init(void) { /* enable io pins */ diff --git a/arch/m68k/platform/coldfire/gpio.c b/arch/m68k/platform/coldfire/gpio.c index 292a1a5a2d7c..4c8c42450a4e 100644 --- a/arch/m68k/platform/coldfire/gpio.c +++ b/arch/m68k/platform/coldfire/gpio.c @@ -122,6 +122,10 @@ struct bus_type mcf_gpio_subsys = { static int __init mcf_gpio_sysinit(void) { + unsigned int i = 0; + + while (i < mcf_gpio_chips_size) + gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); return subsys_system_register(&mcf_gpio_subsys, NULL); } -- cgit v1.2.3 From 1744bd921cd1037f0415574e0f8a3611984ecc7c Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 2 May 2012 17:02:21 +1000 Subject: m68knommu: reorganize the no-MMU cache flushing to match m68k Introduce cache_push() and cache_clear() functions for the non-MMU m68k devices. With these in place we can more easily merge some of the common m68k arch code. In particular by reorganizing the __flush_cache_all() code and separating the cache push and clear functions it becomes trivial to implement the new cache_push() and cache_clear() functions. Signed-off-by: Greg Ungerer Acked-by: Geert Uytterhoeven --- arch/m68k/include/asm/cacheflush_no.h | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index cb88aa96c4f1..7cafb537d03c 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -30,11 +30,8 @@ void mcf_cache_push(void); -static inline void __flush_cache_all(void) +static inline void __clear_cache_all(void) { -#ifdef CACHE_PUSH - mcf_cache_push(); -#endif #ifdef CACHE_INVALIDATE __asm__ __volatile__ ( "movel %0, %%d0\n\t" @@ -44,6 +41,14 @@ static inline void __flush_cache_all(void) #endif } +static inline void __flush_cache_all(void) +{ +#ifdef CACHE_PUSH + mcf_cache_push(); +#endif + __clear_cache_all(); +} + /* * Some ColdFire parts implement separate instruction and data caches, * on those we should just flush the appropriate cache. If we don't need @@ -76,4 +81,23 @@ static inline void __flush_dcache_all(void) __asm__ __volatile__ ( "nop" ); #endif } + +/* + * Push cache entries at supplied address. We want to write back any dirty + * data and the invalidate the cache lines associated with this address. + */ +static inline void cache_push(unsigned long paddr, int len) +{ + __flush_cache_all(); +} + +/* + * Clear cache entries at supplied address (that is don't write back any + * dirty data). + */ +static inline void cache_clear(unsigned long paddr, int len) +{ + __clear_cache_all(); +} + #endif /* _M68KNOMMU_CACHEFLUSH_H */ -- cgit v1.2.3 From b2fb49bf2af013fa84d751ec02b0610571d67896 Mon Sep 17 00:00:00 2001 From: Luis Alves Date: Sun, 13 May 2012 17:39:42 +0100 Subject: m68knommu: unaligned.h fix for M68000 core This patch fixes unaligned memory access for the 68000 core based cpu's. Some time ago, my cpu (68000) was raising address/bus error's when mounting cifs shares (didn't bother to debug it at the time). After developing the MMC/SD card driver I was having the same issue when mounting the vfat fs. I've traced the issue down to the 'unaligned.h' file. (I guess nobody has ever used unaligned.h back in the 68328 'era'. Signed-off-by: Luis Alves Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/unaligned.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h index 019caa740c21..f4043ae63db1 100644 --- a/arch/m68k/include/asm/unaligned.h +++ b/arch/m68k/include/asm/unaligned.h @@ -2,7 +2,7 @@ #define _ASM_M68K_UNALIGNED_H -#ifdef CONFIG_COLDFIRE +#if defined(CONFIG_COLDFIRE) || defined(CONFIG_M68000) #include #include #include -- cgit v1.2.3