From 85744f2d938c5f3cfc44cb6533c157469634da93 Mon Sep 17 00:00:00 2001 From: Wan Jiabing Date: Sun, 17 Oct 2021 21:45:03 -0400 Subject: ARM: shmobile: rcar-gen2: Add missing of_node_put() Fix following coccicheck warning: ./arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c:156:1-33: Function for_each_matching_node_and_match should have of_node_put() before break and goto. Early exits from for_each_matching_node_and_match() should decrement the node reference counter. Signed-off-by: Wan Jiabing Link: https://lore.kernel.org/r/20211018014503.7598-1-wanjiabing@vivo.com Signed-off-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c index ee949255ced3..09ef73b99dd8 100644 --- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c +++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c @@ -154,8 +154,10 @@ static int __init rcar_gen2_regulator_quirk(void) return -ENODEV; for_each_matching_node_and_match(np, rcar_gen2_quirk_match, &id) { - if (!of_device_is_available(np)) + if (!of_device_is_available(np)) { + of_node_put(np); break; + } ret = of_property_read_u32(np, "reg", &addr); if (ret) /* Skip invalid entry and continue */ @@ -164,6 +166,7 @@ static int __init rcar_gen2_regulator_quirk(void) quirk = kzalloc(sizeof(*quirk), GFP_KERNEL); if (!quirk) { ret = -ENOMEM; + of_node_put(np); goto err_mem; } -- cgit v1.2.3 From 1ab0a62f28c9347a5abb9ff9ba544271deb45f87 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 14 Oct 2021 16:44:12 +0200 Subject: ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add missing camera regulators make dtbs_check: arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dt.yaml: ov5640@3c: 'AVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dt.yaml: ov5640@3c: 'DVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dt.yaml: ov5640@3c: 'DOVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml Fix this by describing the missing regulators. Signed-off-by: Geert Uytterhoeven Reviewed-by: Kieran Bingham Link: https://lore.kernel.org/r/300149c730931914b77e17df6bcce89b67c3005f.1634222546.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts | 16 ++++++++++++++++ .../boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi | 3 +++ 2 files changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts index 33db5938f2d4..3c8a7c8b1fdd 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -44,6 +44,22 @@ #clock-cells = <0>; clock-frequency = <26000000>; }; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p8v: 2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; }; &avb { diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi index 70c72ba4fe72..40cef0b1d1e6 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi @@ -17,6 +17,9 @@ reg = <0x3c>; clocks = <&MCLK_CAM>; clock-names = "xclk"; + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_2p8v>; + DVDD-supply = <®_1p8v>; status = "okay"; port { -- cgit v1.2.3 From 90dc0df9168b6c1ddb339481b440d7c13cc4417c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 11 Nov 2021 10:11:23 +0100 Subject: ARM: s3c: include header for prototype of s3c2410_modify_misccr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include the header with prototype of s3c2410_modify_misccr to fix W=1 warning: arch/arm/mach-s3c/gpio-samsung.c:1309:14: warning: no previous prototype for ‘s3c2410_modify_misccr’ [-Wmissing-prototypes] Reported-by: kernel test robot Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Acked-by: Arnd Bergmann Link: https://lore.kernel.org/r/20211111091123.50853-1-krzysztof.kozlowski@canonical.com --- arch/arm/mach-s3c/gpio-samsung.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c/gpio-samsung.c b/arch/arm/mach-s3c/gpio-samsung.c index 76ef415789f2..fda2c01f5a08 100644 --- a/arch/arm/mach-s3c/gpio-samsung.c +++ b/arch/arm/mach-s3c/gpio-samsung.c @@ -35,6 +35,7 @@ #include "gpio-core.h" #include "gpio-cfg.h" #include "gpio-cfg-helpers.h" +#include "hardware-s3c24xx.h" #include "pm.h" int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, -- cgit v1.2.3 From 9cb6de45a006a9799ec399bce60d64b6d4fcc4af Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 31 Oct 2021 23:41:36 +0000 Subject: ARM: dts: exynos: Fix BCM4330 Bluetooth reset polarity in I9100 The reset GPIO was marked active-high, which is against what's specified in the documentation. Mark the reset GPIO as active-low. With this change, Bluetooth can now be used on the i9100. Fixes: 8620cc2f99b7 ("ARM: dts: exynos: Add devicetree file for the Galaxy S2") Cc: stable@vger.kernel.org Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20211031234137.87070-1-paul@crapouillou.net Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-i9100.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 19bb7dc98b33..21b791150697 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -828,7 +828,7 @@ compatible = "brcm,bcm4330-bt"; shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpl1 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpl1 0 GPIO_ACTIVE_LOW>; device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; }; -- cgit v1.2.3 From 8e14b530f8c90346eab43c7b59b03ff9fec7d171 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 31 Oct 2021 23:41:37 +0000 Subject: ARM: dts: exynos: Use interrupt for BCM4330 host wakeup in I9100 Switch away from using the deprecated 'host-wakeup-gpios' property, and use a 'host-wakeup' interrupt instead, as suggested by the binding documentation. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20211031234137.87070-2-paul@crapouillou.net Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-i9100.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 21b791150697..33894054b8b0 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -830,7 +830,10 @@ shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpl1 0 GPIO_ACTIVE_LOW>; device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + + interrupt-parent = <&gpx2>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wakeup"; }; }; -- cgit v1.2.3 From aa67bacb482ae66bdb18b78ddccf7b9180441588 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 24 Oct 2021 10:45:35 +0200 Subject: arm: dts: mt6589: Add device tree for Fairphone 1 Add rudimentary support for the Fairphone 1, based on MT6589 to boot to UART console. The recently added SMP support needs to be disabled for this board as the kernel panics executing /init with it, even though the CPUs seem to start up fine - maybe a stability issue. [ 0.072010] smp: Bringing up secondary CPUs ... [ 0.131888] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [ 0.191889] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002 [ 0.251890] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003 [ 0.251982] smp: Brought up 1 node, 4 CPUs [ 0.254745] SMP: Total of 4 processors activated (7982.28 BogoMIPS). [ 0.255582] CPU: All CPU(s) started in SVC mode. [ 0.472039] Run /init as init process [ 0.473317] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004 Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20211024084535.30959-1-luca@z3ntu.xyz Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/mt6589-fairphone-fp1.dts | 30 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/mt6589.dtsi | 2 +- 3 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/mt6589-fairphone-fp1.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..8a2dfdf01ce3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1457,6 +1457,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt2701-evb.dtb \ mt6580-evbp1.dtb \ mt6589-aquaris5.dtb \ + mt6589-fairphone-fp1.dtb \ mt6592-evb.dtb \ mt7623a-rfb-emmc.dtb \ mt7623a-rfb-nand.dtb \ diff --git a/arch/arm/boot/dts/mt6589-fairphone-fp1.dts b/arch/arm/boot/dts/mt6589-fairphone-fp1.dts new file mode 100644 index 000000000000..c952347981de --- /dev/null +++ b/arch/arm/boot/dts/mt6589-fairphone-fp1.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Luca Weiss + */ + +/dts-v1/; +#include "mt6589.dtsi" + +/ { + model = "Fairphone 1"; + compatible = "fairphone,fp1", "mediatek,mt6589"; + + chosen { + stdout-path = &uart3; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&cpus { + /* SMP is not stable on this board, makes the kernel panic */ + /delete-property/ enable-method; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index 70df00a7bb26..c6babc8ad2ba 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -14,7 +14,7 @@ compatible = "mediatek,mt6589"; interrupt-parent = <&sysirq>; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; enable-method = "mediatek,mt6589-smp"; -- cgit v1.2.3 From 5f9cfe9e94a6eef576f89bbf5a946f8ae63c0f71 Mon Sep 17 00:00:00 2001 From: Matthew Hagan Date: Fri, 15 Oct 2021 23:50:22 +0100 Subject: ARM: dts: NSP: MX65: add qca8k falling-edge, PLL properties This patch enables two properties for the QCA8337 switches on the MX65. Set the SGMII transmit clock to falling edge "qca,sgmii-txclk-falling-edge" to conform to the OEM configuration [1]. The new explicit PLL enable option "qca,sgmii-enable-pll" is required [2]. [1] https://git.kernel.org/netdev/net-next/c/6c43809bf1be [2] https://git.kernel.org/netdev/net-next/c/bbc4799e8bb6 Signed-off-by: Matthew Hagan Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi index 102acd85fab2..ba01054a76cf 100644 --- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi +++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi @@ -118,6 +118,8 @@ reg = <0>; ethernet = <&sgmii1>; phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-txclk-falling-edge; fixed-link { speed = <1000>; full-duplex; @@ -194,6 +196,8 @@ reg = <0>; ethernet = <&sgmii0>; phy-mode = "sgmii"; + qca,sgmii-enable-pll; + qca,sgmii-txclk-falling-edge; fixed-link { speed = <1000>; full-duplex; -- cgit v1.2.3 From 8c9f00d4b05134164e462f27b21c8295255ffa64 Mon Sep 17 00:00:00 2001 From: Arınç ÜNAL Date: Wed, 27 Oct 2021 00:57:03 +0800 Subject: ARM: dts: BCM5301X: remove unnecessary address & size cells from Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the unnecessary #address-cells & #size-cells in the gpio-keys node from the device tree of Asus RT-AC88U. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 448060561cd0..b0cee1d87600 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -68,8 +68,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; wps { label = "WPS"; -- cgit v1.2.3 From 3d2d52a0d1835b56f6bd67d268f6c39df0e41692 Mon Sep 17 00:00:00 2001 From: Arınç ÜNAL Date: Wed, 27 Oct 2021 00:57:06 +0800 Subject: ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the Realtek RTL8365MB switch without interrupt support on the device tree of Asus RT-AC88U. Signed-off-by: Arınç ÜNAL Acked-by: Alvin Šipraga Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index b0cee1d87600..16dea851719f 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -93,6 +93,83 @@ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; }; + + switch { + compatible = "realtek,rtl8365mb"; + /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ + mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + realtek,disable-leds; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + phy-handle = <ðphy0>; + }; + + port@1 { + reg = <1>; + label = "lan6"; + phy-handle = <ðphy1>; + }; + + port@2 { + reg = <2>; + label = "lan7"; + phy-handle = <ðphy2>; + }; + + port@3 { + reg = <3>; + label = "lan8"; + phy-handle = <ðphy3>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&sw0_p5>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + compatible = "realtek,smi-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + }; + }; }; &srab { -- cgit v1.2.3 From de7880016665afe7fa7d40e1fafa859260d53ba1 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Thu, 28 Oct 2021 09:03:44 +0200 Subject: ARM: BCM53016: MR32: convert to Broadcom iProc I2C Driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit replaces the bit-banged i2c-gpio provided i2c functionality with the hardware in the SoC. During review of the MR32, Florian Fainelli pointed out that the SoC has a real I2C-controller. Furthermore, the connected pins (SDA and SCL) would line up perfectly for use. Back then I couldn't get it working though and I left it with i2c-gpio (which worked). Now we know the reason: the interrupt was incorrectly specified. (Hence, this patch depends on Florian Fainelli's "ARM: dts: BCM5301X: Fix I2C controller interrupt" patch). Cc: Florian Fainelli Cc: Rafał Miłecki Cc: Matthew Hagan Signed-off-by: Christian Lamparter Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 62 ++++++++++++++---------------- 1 file changed, 28 insertions(+), 34 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index 64f973e1ef12..66c64a6ec414 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -84,40 +84,6 @@ max-brightness = <255>; }; }; - - i2c { - /* - * The platform provided I2C does not budge. - * This is a replacement until I can figure - * out what are the missing bits... - */ - - compatible = "i2c-gpio"; - sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <10>; /* close to 100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - current_sense: ina219@45 { - compatible = "ti,ina219"; - reg = <0x45>; - shunt-resistor = <60000>; /* = 60 mOhms */ - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - mac_address: mac-address@66 { - reg = <0x66 0x6>; - }; - }; - }; }; &uart0 { @@ -228,3 +194,31 @@ }; }; }; + +&i2c0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_i2c>; + + clock-frequency = <100000>; + + current_sense: ina219@45 { + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <60000>; /* = 60 mOhms */ + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; + }; +}; -- cgit v1.2.3 From 31fd9b79dc580301c53a001482755ba7e88c2809 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Fri, 29 Oct 2021 18:05:23 +0200 Subject: ARM: dts: BCM5301X: update CRU block description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This describes CRU in a way matching documentation and fixes: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: cru@100: $nodename:0: 'cru@100' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /lib/python3.6/site-packages/dtschema/schemas/simple-bus.yaml Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index d4f355015e3c..e1cffef4935a 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -421,14 +421,14 @@ #address-cells = <1>; #size-cells = <1>; - cru@100 { - compatible = "simple-bus"; + cru-bus@100 { + compatible = "brcm,ns-cru", "simple-mfd"; reg = <0x100 0x1a4>; ranges; #address-cells = <1>; #size-cells = <1>; - lcpll0: lcpll0@100 { + lcpll0: clock-controller@100 { #clock-cells = <1>; compatible = "brcm,nsp-lcpll0"; reg = <0x100 0x14>; @@ -437,7 +437,7 @@ "sdio", "ddr_phy"; }; - genpll: genpll@140 { + genpll: clock-controller@140 { #clock-cells = <1>; compatible = "brcm,nsp-genpll"; reg = <0x140 0x24>; @@ -448,6 +448,11 @@ "sata1", "sata2"; }; + syscon@180 { + compatible = "brcm,cru-clkset", "syscon"; + reg = <0x180 0x4>; + }; + pinctrl: pin-controller@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; -- cgit v1.2.3 From 82099d76cb6ff6738306e90e816754a5d6b046ce Mon Sep 17 00:00:00 2001 From: Oskar Senft Date: Thu, 4 Nov 2021 23:29:10 -0400 Subject: ARM: dts: aspeed: tyan-s7106: Update nct7802 config This change updates the configuration for the nct7802 hardware monitor to correctly configure its temperature sensors. Signed-off-by: Oskar Senft Link: https://lore.kernel.org/r/20211105032910.446492-1-osk@google.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts index 68f332ee1886..60ac6d3f03b5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts +++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts @@ -213,6 +213,30 @@ nct7802@28 { compatible = "nuvoton,nct7802"; reg = <0x28>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* LTD */ + reg = <0>; + }; + + channel@1 { /* RTD1 */ + reg = <1>; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@2 { /* RTD2 */ + reg = <2>; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@3 { /* RTD3 */ + reg = <3>; + sensor-type = "temperature"; + }; }; /* Also connected to: -- cgit v1.2.3 From 8189162c66b7bc2d91224269b472aae57fc699e1 Mon Sep 17 00:00:00 2001 From: Quan Nguyen Date: Tue, 19 Oct 2021 13:01:54 +0700 Subject: ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices This commit adds configuration i2c busses for 24 NVMe slots and 2 M2 NVMe slots found on Mt.Jade hardware reference platform with Ampere's Altra processor family. Signed-off-by: Quan Nguyen Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20211019060155.945-3-quan@os.amperecomputing.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 258 +++++++++++++++++++++++++ 1 file changed, 258 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 3515d55bd312..723c7063c223 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -7,6 +7,50 @@ model = "Ampere Mt. Jade BMC"; compatible = "ampere,mtjade-bmc", "aspeed,ast2500"; + aliases { + /* + * i2c bus 50-57 assigned to NVMe slot 0-7 + */ + i2c50 = &nvmeslot_0; + i2c51 = &nvmeslot_1; + i2c52 = &nvmeslot_2; + i2c53 = &nvmeslot_3; + i2c54 = &nvmeslot_4; + i2c55 = &nvmeslot_5; + i2c56 = &nvmeslot_6; + i2c57 = &nvmeslot_7; + + /* + * i2c bus 60-67 assigned to NVMe slot 8-15 + */ + i2c60 = &nvmeslot_8; + i2c61 = &nvmeslot_9; + i2c62 = &nvmeslot_10; + i2c63 = &nvmeslot_11; + i2c64 = &nvmeslot_12; + i2c65 = &nvmeslot_13; + i2c66 = &nvmeslot_14; + i2c67 = &nvmeslot_15; + + /* + * i2c bus 70-77 assigned to NVMe slot 16-23 + */ + i2c70 = &nvmeslot_16; + i2c71 = &nvmeslot_17; + i2c72 = &nvmeslot_18; + i2c73 = &nvmeslot_19; + i2c74 = &nvmeslot_20; + i2c75 = &nvmeslot_21; + i2c76 = &nvmeslot_22; + i2c77 = &nvmeslot_23; + + /* + * i2c bus 80-81 assigned to NVMe M2 slot 0-1 + */ + i2c80 = &nvme_m2_0; + i2c81 = &nvme_m2_1; + }; + chosen { stdout-path = &uart5; bootargs = "console=ttyS4,115200 earlycon"; @@ -445,6 +489,220 @@ &i2c5 { status = "okay"; + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + nvmeslot_0_7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + }; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + nvmeslot_8_15: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + nvmeslot_16_23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + }; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72>; + i2c-mux-idle-disconnect; + + nvme_m2_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + nvme_m2_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + }; +}; + +&nvmeslot_0_7 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + + }; +}; + +&nvmeslot_8_15 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_8: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_9: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_10: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_11: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_12: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_13: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_14: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_15: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; +}; + +&nvmeslot_16_23 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; }; &i2c6 { -- cgit v1.2.3 From 16d6dc8d8030dfe88104616cd3dea4e055af506d Mon Sep 17 00:00:00 2001 From: Quan Nguyen Date: Tue, 19 Oct 2021 13:01:55 +0700 Subject: ARM: dts: aspeed: mtjade: Add uefi partition Add SPI NOR partition for uefi. Signed-off-by: Thang Q. Nguyen Signed-off-by: Quan Nguyen Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20211019060155.945-4-quan@os.amperecomputing.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 723c7063c223..4c3c3f1a12ea 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -374,6 +374,15 @@ m25p,fast-read; label = "pnor"; /* spi-max-frequency = <100000000>; */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + uefi@400000 { + reg = <0x400000 0x1C00000>; + label = "pnor-uefi"; + }; + }; }; }; -- cgit v1.2.3 From 7f9ec9b59c278f31b0c2c8fabcf564e6fc02d4d8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 16 Nov 2021 10:20:42 +0100 Subject: ARM: s3c: add one more "fallthrough" statement in Jive clang warns about one missing fallthrough that gcc ignores: arch/arm/mach-s3c/mach-jive.c:250:2: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough] Add it here as well. Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20211116092053.4042799-1-arnd@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-s3c/mach-jive.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c/mach-jive.c b/arch/arm/mach-s3c/mach-jive.c index 0785638a9069..285e1f0f4145 100644 --- a/arch/arm/mach-s3c/mach-jive.c +++ b/arch/arm/mach-s3c/mach-jive.c @@ -247,6 +247,7 @@ static int __init jive_mtdset(char *options) case 1: nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part); nand->partitions = jive_imageB_nand_part; + break; case 0: /* this is already setup in the nand info */ break; -- cgit v1.2.3 From ebf7f6f0a6cdcc17a3da52b81e4b3a98c4005028 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Fri, 5 Nov 2021 09:30:00 +0800 Subject: bpf: Change value of MAX_TAIL_CALL_CNT from 32 to 33 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In the current code, the actual max tail call count is 33 which is greater than MAX_TAIL_CALL_CNT (defined as 32). The actual limit is not consistent with the meaning of MAX_TAIL_CALL_CNT and thus confusing at first glance. We can see the historical evolution from commit 04fd61ab36ec ("bpf: allow bpf programs to tail-call other bpf programs") and commit f9dabe016b63 ("bpf: Undo off-by-one in interpreter tail call count limit"). In order to avoid changing existing behavior, the actual limit is 33 now, this is reasonable. After commit 874be05f525e ("bpf, tests: Add tail call test suite"), we can see there exists failed testcase. On all archs when CONFIG_BPF_JIT_ALWAYS_ON is not set: # echo 0 > /proc/sys/net/core/bpf_jit_enable # modprobe test_bpf # dmesg | grep -w FAIL Tail call error path, max count reached jited:0 ret 34 != 33 FAIL On some archs: # echo 1 > /proc/sys/net/core/bpf_jit_enable # modprobe test_bpf # dmesg | grep -w FAIL Tail call error path, max count reached jited:1 ret 34 != 33 FAIL Although the above failed testcase has been fixed in commit 18935a72eb25 ("bpf/tests: Fix error in tail call limit tests"), it would still be good to change the value of MAX_TAIL_CALL_CNT from 32 to 33 to make the code more readable. The 32-bit x86 JIT was using a limit of 32, just fix the wrong comments and limit to 33 tail calls as the constant MAX_TAIL_CALL_CNT updated. For the mips64 JIT, use "ori" instead of "addiu" as suggested by Johan Almbladh. For the riscv JIT, use RV_REG_TCC directly to save one register move as suggested by Björn Töpel. For the other implementations, no function changes, it does not change the current limit 33, the new value of MAX_TAIL_CALL_CNT can reflect the actual max tail call count, the related tail call testcases in test_bpf module and selftests can work well for the interpreter and the JIT. Here are the test results on x86_64: # uname -m x86_64 # echo 0 > /proc/sys/net/core/bpf_jit_enable # modprobe test_bpf test_suite=test_tail_calls # dmesg | tail -1 test_bpf: test_tail_calls: Summary: 8 PASSED, 0 FAILED, [0/8 JIT'ed] # rmmod test_bpf # echo 1 > /proc/sys/net/core/bpf_jit_enable # modprobe test_bpf test_suite=test_tail_calls # dmesg | tail -1 test_bpf: test_tail_calls: Summary: 8 PASSED, 0 FAILED, [8/8 JIT'ed] # rmmod test_bpf # ./test_progs -t tailcalls #142 tailcalls:OK Summary: 1/11 PASSED, 0 SKIPPED, 0 FAILED Signed-off-by: Tiezhu Yang Signed-off-by: Daniel Borkmann Tested-by: Johan Almbladh Tested-by: Ilya Leoshkevich Acked-by: Björn Töpel Acked-by: Johan Almbladh Acked-by: Ilya Leoshkevich Link: https://lore.kernel.org/bpf/1636075800-3264-1-git-send-email-yangtiezhu@loongson.cn --- arch/arm/net/bpf_jit_32.c | 5 +++-- arch/arm64/net/bpf_jit_comp.c | 5 +++-- arch/mips/net/bpf_jit_comp32.c | 3 +-- arch/mips/net/bpf_jit_comp64.c | 2 +- arch/powerpc/net/bpf_jit_comp32.c | 4 ++-- arch/powerpc/net/bpf_jit_comp64.c | 4 ++-- arch/riscv/net/bpf_jit_comp32.c | 6 ++---- arch/riscv/net/bpf_jit_comp64.c | 7 +++---- arch/s390/net/bpf_jit_comp.c | 6 +++--- arch/sparc/net/bpf_jit_comp_64.c | 2 +- arch/x86/net/bpf_jit_comp.c | 10 +++++----- arch/x86/net/bpf_jit_comp32.c | 4 ++-- include/linux/bpf.h | 2 +- include/uapi/linux/bpf.h | 2 +- kernel/bpf/core.c | 3 ++- lib/test_bpf.c | 4 ++-- tools/include/uapi/linux/bpf.h | 2 +- 17 files changed, 35 insertions(+), 36 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c index eeb6dc0ecf46..e59b41e9ab0c 100644 --- a/arch/arm/net/bpf_jit_32.c +++ b/arch/arm/net/bpf_jit_32.c @@ -1199,7 +1199,8 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx) /* tmp2[0] = array, tmp2[1] = index */ - /* if (tail_call_cnt > MAX_TAIL_CALL_CNT) + /* + * if (tail_call_cnt >= MAX_TAIL_CALL_CNT) * goto out; * tail_call_cnt++; */ @@ -1208,7 +1209,7 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx) tc = arm_bpf_get_reg64(tcc, tmp, ctx); emit(ARM_CMP_I(tc[0], hi), ctx); _emit(ARM_COND_EQ, ARM_CMP_I(tc[1], lo), ctx); - _emit(ARM_COND_HI, ARM_B(jmp_offset), ctx); + _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx); emit(ARM_ADDS_I(tc[1], tc[1], 1), ctx); emit(ARM_ADC_I(tc[0], tc[0], 0), ctx); arm_bpf_put_reg64(tcc, tmp, ctx); diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index 86c9dc0681cc..07c12c42b751 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -287,13 +287,14 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx) emit(A64_CMP(0, r3, tmp), ctx); emit(A64_B_(A64_COND_CS, jmp_offset), ctx); - /* if (tail_call_cnt > MAX_TAIL_CALL_CNT) + /* + * if (tail_call_cnt >= MAX_TAIL_CALL_CNT) * goto out; * tail_call_cnt++; */ emit_a64_mov_i64(tmp, MAX_TAIL_CALL_CNT, ctx); emit(A64_CMP(1, tcc, tmp), ctx); - emit(A64_B_(A64_COND_HI, jmp_offset), ctx); + emit(A64_B_(A64_COND_CS, jmp_offset), ctx); emit(A64_ADD_I(1, tcc, tcc, 1), ctx); /* prog = array->ptrs[index]; diff --git a/arch/mips/net/bpf_jit_comp32.c b/arch/mips/net/bpf_jit_comp32.c index bd996ede12f8..044b11b65bca 100644 --- a/arch/mips/net/bpf_jit_comp32.c +++ b/arch/mips/net/bpf_jit_comp32.c @@ -1381,8 +1381,7 @@ void build_prologue(struct jit_context *ctx) * 16-byte area in the parent's stack frame. On a tail call, the * calling function jumps into the prologue after these instructions. */ - emit(ctx, ori, MIPS_R_T9, MIPS_R_ZERO, - min(MAX_TAIL_CALL_CNT + 1, 0xffff)); + emit(ctx, ori, MIPS_R_T9, MIPS_R_ZERO, min(MAX_TAIL_CALL_CNT, 0xffff)); emit(ctx, sw, MIPS_R_T9, 0, MIPS_R_SP); /* diff --git a/arch/mips/net/bpf_jit_comp64.c b/arch/mips/net/bpf_jit_comp64.c index 815ade724227..6475828ffb36 100644 --- a/arch/mips/net/bpf_jit_comp64.c +++ b/arch/mips/net/bpf_jit_comp64.c @@ -552,7 +552,7 @@ void build_prologue(struct jit_context *ctx) * On a tail call, the calling function jumps into the prologue * after this instruction. */ - emit(ctx, addiu, tc, MIPS_R_ZERO, min(MAX_TAIL_CALL_CNT + 1, 0xffff)); + emit(ctx, ori, tc, MIPS_R_ZERO, min(MAX_TAIL_CALL_CNT, 0xffff)); /* === Entry-point for tail calls === */ diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c index 0da31d41d413..8a4faa05f9e4 100644 --- a/arch/powerpc/net/bpf_jit_comp32.c +++ b/arch/powerpc/net/bpf_jit_comp32.c @@ -221,13 +221,13 @@ static int bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 o PPC_BCC(COND_GE, out); /* - * if (tail_call_cnt > MAX_TAIL_CALL_CNT) + * if (tail_call_cnt >= MAX_TAIL_CALL_CNT) * goto out; */ EMIT(PPC_RAW_CMPLWI(_R0, MAX_TAIL_CALL_CNT)); /* tail_call_cnt++; */ EMIT(PPC_RAW_ADDIC(_R0, _R0, 1)); - PPC_BCC(COND_GT, out); + PPC_BCC(COND_GE, out); /* prog = array->ptrs[index]; */ EMIT(PPC_RAW_RLWINM(_R3, b2p_index, 2, 0, 29)); diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c index 8b5157ccfeba..8571aafcc9e1 100644 --- a/arch/powerpc/net/bpf_jit_comp64.c +++ b/arch/powerpc/net/bpf_jit_comp64.c @@ -228,12 +228,12 @@ static int bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 o PPC_BCC(COND_GE, out); /* - * if (tail_call_cnt > MAX_TAIL_CALL_CNT) + * if (tail_call_cnt >= MAX_TAIL_CALL_CNT) * goto out; */ PPC_BPF_LL(b2p[TMP_REG_1], 1, bpf_jit_stack_tailcallcnt(ctx)); EMIT(PPC_RAW_CMPLWI(b2p[TMP_REG_1], MAX_TAIL_CALL_CNT)); - PPC_BCC(COND_GT, out); + PPC_BCC(COND_GE, out); /* * tail_call_cnt++; diff --git a/arch/riscv/net/bpf_jit_comp32.c b/arch/riscv/net/bpf_jit_comp32.c index e6497424cbf6..529a83b85c1c 100644 --- a/arch/riscv/net/bpf_jit_comp32.c +++ b/arch/riscv/net/bpf_jit_comp32.c @@ -799,11 +799,10 @@ static int emit_bpf_tail_call(int insn, struct rv_jit_context *ctx) emit_bcc(BPF_JGE, lo(idx_reg), RV_REG_T1, off, ctx); /* - * temp_tcc = tcc - 1; - * if (tcc < 0) + * if (--tcc < 0) * goto out; */ - emit(rv_addi(RV_REG_T1, RV_REG_TCC, -1), ctx); + emit(rv_addi(RV_REG_TCC, RV_REG_TCC, -1), ctx); off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); emit_bcc(BPF_JSLT, RV_REG_TCC, RV_REG_ZERO, off, ctx); @@ -829,7 +828,6 @@ static int emit_bpf_tail_call(int insn, struct rv_jit_context *ctx) if (is_12b_check(off, insn)) return -1; emit(rv_lw(RV_REG_T0, off, RV_REG_T0), ctx); - emit(rv_addi(RV_REG_TCC, RV_REG_T1, 0), ctx); /* Epilogue jumps to *(t0 + 4). */ __build_epilogue(true, ctx); return 0; diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c index f2a779c7e225..603630b6f3c5 100644 --- a/arch/riscv/net/bpf_jit_comp64.c +++ b/arch/riscv/net/bpf_jit_comp64.c @@ -327,12 +327,12 @@ static int emit_bpf_tail_call(int insn, struct rv_jit_context *ctx) off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); emit_branch(BPF_JGE, RV_REG_A2, RV_REG_T1, off, ctx); - /* if (TCC-- < 0) + /* if (--TCC < 0) * goto out; */ - emit_addi(RV_REG_T1, tcc, -1, ctx); + emit_addi(RV_REG_TCC, tcc, -1, ctx); off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); - emit_branch(BPF_JSLT, tcc, RV_REG_ZERO, off, ctx); + emit_branch(BPF_JSLT, RV_REG_TCC, RV_REG_ZERO, off, ctx); /* prog = array->ptrs[index]; * if (!prog) @@ -352,7 +352,6 @@ static int emit_bpf_tail_call(int insn, struct rv_jit_context *ctx) if (is_12b_check(off, insn)) return -1; emit_ld(RV_REG_T3, off, RV_REG_T2, ctx); - emit_mv(RV_REG_TCC, RV_REG_T1, ctx); __build_epilogue(true, ctx); return 0; } diff --git a/arch/s390/net/bpf_jit_comp.c b/arch/s390/net/bpf_jit_comp.c index 233cc9bcd652..9ff2bd83aad7 100644 --- a/arch/s390/net/bpf_jit_comp.c +++ b/arch/s390/net/bpf_jit_comp.c @@ -1369,7 +1369,7 @@ static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, jit->prg); /* - * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT) + * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) * goto out; */ @@ -1381,9 +1381,9 @@ static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, EMIT4_IMM(0xa7080000, REG_W0, 1); /* laal %w1,%w0,off(%r15) */ EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off); - /* clij %w1,MAX_TAIL_CALL_CNT,0x2,out */ + /* clij %w1,MAX_TAIL_CALL_CNT-1,0x2,out */ patch_2_clij = jit->prg; - EMIT6_PCREL_RIEC(0xec000000, 0x007f, REG_W1, MAX_TAIL_CALL_CNT, + EMIT6_PCREL_RIEC(0xec000000, 0x007f, REG_W1, MAX_TAIL_CALL_CNT - 1, 2, jit->prg); /* diff --git a/arch/sparc/net/bpf_jit_comp_64.c b/arch/sparc/net/bpf_jit_comp_64.c index 9a2f20cbd48b..0bfe1c72a0c9 100644 --- a/arch/sparc/net/bpf_jit_comp_64.c +++ b/arch/sparc/net/bpf_jit_comp_64.c @@ -867,7 +867,7 @@ static void emit_tail_call(struct jit_ctx *ctx) emit(LD32 | IMMED | RS1(SP) | S13(off) | RD(tmp), ctx); emit_cmpi(tmp, MAX_TAIL_CALL_CNT, ctx); #define OFFSET2 13 - emit_branch(BGU, ctx->idx, ctx->idx + OFFSET2, ctx); + emit_branch(BGEU, ctx->idx, ctx->idx + OFFSET2, ctx); emit_nop(ctx); emit_alu_K(ADD, tmp, 1, ctx); diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index 726700fabca6..631847907786 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -412,7 +412,7 @@ static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip) * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ... * if (index >= array->map.max_entries) * goto out; - * if (++tail_call_cnt > MAX_TAIL_CALL_CNT) + * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) * goto out; * prog = array->ptrs[index]; * if (prog == NULL) @@ -446,14 +446,14 @@ static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used, EMIT2(X86_JBE, offset); /* jbe out */ /* - * if (tail_call_cnt > MAX_TAIL_CALL_CNT) + * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) * goto out; */ EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */ EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */ offset = ctx->tail_call_indirect_label - (prog + 2 - start); - EMIT2(X86_JA, offset); /* ja out */ + EMIT2(X86_JAE, offset); /* jae out */ EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */ EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */ @@ -504,14 +504,14 @@ static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke, int offset; /* - * if (tail_call_cnt > MAX_TAIL_CALL_CNT) + * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) * goto out; */ EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */ EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */ offset = ctx->tail_call_direct_label - (prog + 2 - start); - EMIT2(X86_JA, offset); /* ja out */ + EMIT2(X86_JAE, offset); /* jae out */ EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */ EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */ diff --git a/arch/x86/net/bpf_jit_comp32.c b/arch/x86/net/bpf_jit_comp32.c index da9b7cfa4632..429a89c5468b 100644 --- a/arch/x86/net/bpf_jit_comp32.c +++ b/arch/x86/net/bpf_jit_comp32.c @@ -1323,7 +1323,7 @@ static void emit_bpf_tail_call(u8 **pprog, u8 *ip) EMIT2(IA32_JBE, jmp_label(jmp_label1, 2)); /* - * if (tail_call_cnt > MAX_TAIL_CALL_CNT) + * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) * goto out; */ lo = (u32)MAX_TAIL_CALL_CNT; @@ -1337,7 +1337,7 @@ static void emit_bpf_tail_call(u8 **pprog, u8 *ip) /* cmp ecx,lo */ EMIT3(0x83, add_1reg(0xF8, IA32_ECX), lo); - /* ja out */ + /* jae out */ EMIT2(IA32_JAE, jmp_label(jmp_label1, 2)); /* add eax,0x1 */ diff --git a/include/linux/bpf.h b/include/linux/bpf.h index 56098c866704..cc7a0c36e7df 100644 --- a/include/linux/bpf.h +++ b/include/linux/bpf.h @@ -1081,7 +1081,7 @@ struct bpf_array { }; #define BPF_COMPLEXITY_LIMIT_INSNS 1000000 /* yes. 1M insns */ -#define MAX_TAIL_CALL_CNT 32 +#define MAX_TAIL_CALL_CNT 33 #define BPF_F_ACCESS_MASK (BPF_F_RDONLY | \ BPF_F_RDONLY_PROG | \ diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index 6297eafdc40f..a69e4b04ffeb 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -1744,7 +1744,7 @@ union bpf_attr { * if the maximum number of tail calls has been reached for this * chain of programs. This limit is defined in the kernel by the * macro **MAX_TAIL_CALL_CNT** (not accessible to user space), - * which is currently set to 32. + * which is currently set to 33. * Return * 0 on success, or a negative error in case of failure. * diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c index 2405e39d800f..b52dc845ecea 100644 --- a/kernel/bpf/core.c +++ b/kernel/bpf/core.c @@ -1574,7 +1574,8 @@ select_insn: if (unlikely(index >= array->map.max_entries)) goto out; - if (unlikely(tail_call_cnt > MAX_TAIL_CALL_CNT)) + + if (unlikely(tail_call_cnt >= MAX_TAIL_CALL_CNT)) goto out; tail_call_cnt++; diff --git a/lib/test_bpf.c b/lib/test_bpf.c index adae39567264..0c5cb2d6436a 100644 --- a/lib/test_bpf.c +++ b/lib/test_bpf.c @@ -14683,7 +14683,7 @@ static struct tail_call_test tail_call_tests[] = { BPF_EXIT_INSN(), }, .flags = FLAG_NEED_STATE | FLAG_RESULT_IN_STATE, - .result = (MAX_TAIL_CALL_CNT + 1 + 1) * MAX_TESTRUNS, + .result = (MAX_TAIL_CALL_CNT + 1) * MAX_TESTRUNS, }, { "Tail call count preserved across function calls", @@ -14705,7 +14705,7 @@ static struct tail_call_test tail_call_tests[] = { }, .stack_depth = 8, .flags = FLAG_NEED_STATE | FLAG_RESULT_IN_STATE, - .result = (MAX_TAIL_CALL_CNT + 1 + 1) * MAX_TESTRUNS, + .result = (MAX_TAIL_CALL_CNT + 1) * MAX_TESTRUNS, }, { "Tail call error path, NULL target", diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h index 6297eafdc40f..a69e4b04ffeb 100644 --- a/tools/include/uapi/linux/bpf.h +++ b/tools/include/uapi/linux/bpf.h @@ -1744,7 +1744,7 @@ union bpf_attr { * if the maximum number of tail calls has been reached for this * chain of programs. This limit is defined in the kernel by the * macro **MAX_TAIL_CALL_CNT** (not accessible to user space), - * which is currently set to 32. + * which is currently set to 33. * Return * 0 on success, or a negative error in case of failure. * -- cgit v1.2.3 From ff083a2d972f56bebfd82409ca62e5dfce950961 Mon Sep 17 00:00:00 2001 From: Sean Christopherson Date: Thu, 11 Nov 2021 02:07:22 +0000 Subject: perf: Protect perf_guest_cbs with RCU Protect perf_guest_cbs with RCU to fix multiple possible errors. Luckily, all paths that read perf_guest_cbs already require RCU protection, e.g. to protect the callback chains, so only the direct perf_guest_cbs touchpoints need to be modified. Bug #1 is a simple lack of WRITE_ONCE/READ_ONCE behavior to ensure perf_guest_cbs isn't reloaded between a !NULL check and a dereference. Fixed via the READ_ONCE() in rcu_dereference(). Bug #2 is that on weakly-ordered architectures, updates to the callbacks themselves are not guaranteed to be visible before the pointer is made visible to readers. Fixed by the smp_store_release() in rcu_assign_pointer() when the new pointer is non-NULL. Bug #3 is that, because the callbacks are global, it's possible for readers to run in parallel with an unregisters, and thus a module implementing the callbacks can be unloaded while readers are in flight, resulting in a use-after-free. Fixed by a synchronize_rcu() call when unregistering callbacks. Bug #1 escaped notice because it's extremely unlikely a compiler will reload perf_guest_cbs in this sequence. perf_guest_cbs does get reloaded for future derefs, e.g. for ->is_user_mode(), but the ->is_in_guest() guard all but guarantees the consumer will win the race, e.g. to nullify perf_guest_cbs, KVM has to completely exit the guest and teardown down all VMs before KVM start its module unload / unregister sequence. This also makes it all but impossible to encounter bug #3. Bug #2 has not been a problem because all architectures that register callbacks are strongly ordered and/or have a static set of callbacks. But with help, unloading kvm_intel can trigger bug #1 e.g. wrapping perf_guest_cbs with READ_ONCE in perf_misc_flags() while spamming kvm_intel module load/unload leads to: BUG: kernel NULL pointer dereference, address: 0000000000000000 #PF: supervisor read access in kernel mode #PF: error_code(0x0000) - not-present page PGD 0 P4D 0 Oops: 0000 [#1] PREEMPT SMP CPU: 6 PID: 1825 Comm: stress Not tainted 5.14.0-rc2+ #459 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 0.0.0 02/06/2015 RIP: 0010:perf_misc_flags+0x1c/0x70 Call Trace: perf_prepare_sample+0x53/0x6b0 perf_event_output_forward+0x67/0x160 __perf_event_overflow+0x52/0xf0 handle_pmi_common+0x207/0x300 intel_pmu_handle_irq+0xcf/0x410 perf_event_nmi_handler+0x28/0x50 nmi_handle+0xc7/0x260 default_do_nmi+0x6b/0x170 exc_nmi+0x103/0x130 asm_exc_nmi+0x76/0xbf Fixes: 39447b386c84 ("perf: Enhance perf to allow for guest statistic collection from host") Signed-off-by: Sean Christopherson Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Paolo Bonzini Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20211111020738.2512932-2-seanjc@google.com --- arch/arm/kernel/perf_callchain.c | 17 +++++++++++------ arch/arm64/kernel/perf_callchain.c | 18 ++++++++++++------ arch/csky/kernel/perf_callchain.c | 6 ++++-- arch/nds32/kernel/perf_event_cpu.c | 17 +++++++++++------ arch/riscv/kernel/perf_callchain.c | 7 +++++-- arch/x86/events/core.c | 17 +++++++++++------ arch/x86/events/intel/core.c | 9 ++++++--- include/linux/perf_event.h | 13 ++++++++++++- kernel/events/core.c | 13 ++++++++++--- 9 files changed, 82 insertions(+), 35 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/perf_callchain.c b/arch/arm/kernel/perf_callchain.c index 3b69a76d341e..1626dfc6f6ce 100644 --- a/arch/arm/kernel/perf_callchain.c +++ b/arch/arm/kernel/perf_callchain.c @@ -62,9 +62,10 @@ user_backtrace(struct frame_tail __user *tail, void perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); struct frame_tail __user *tail; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { + if (guest_cbs && guest_cbs->is_in_guest()) { /* We don't support guest os callchain now */ return; } @@ -98,9 +99,10 @@ callchain_trace(struct stackframe *fr, void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); struct stackframe fr; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { + if (guest_cbs && guest_cbs->is_in_guest()) { /* We don't support guest os callchain now */ return; } @@ -111,18 +113,21 @@ perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *re unsigned long perf_instruction_pointer(struct pt_regs *regs) { - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) - return perf_guest_cbs->get_guest_ip(); + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); + + if (guest_cbs && guest_cbs->is_in_guest()) + return guest_cbs->get_guest_ip(); return instruction_pointer(regs); } unsigned long perf_misc_flags(struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); int misc = 0; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { - if (perf_guest_cbs->is_user_mode()) + if (guest_cbs && guest_cbs->is_in_guest()) { + if (guest_cbs->is_user_mode()) misc |= PERF_RECORD_MISC_GUEST_USER; else misc |= PERF_RECORD_MISC_GUEST_KERNEL; diff --git a/arch/arm64/kernel/perf_callchain.c b/arch/arm64/kernel/perf_callchain.c index 4a72c2727309..86d9f2013172 100644 --- a/arch/arm64/kernel/perf_callchain.c +++ b/arch/arm64/kernel/perf_callchain.c @@ -102,7 +102,9 @@ compat_user_backtrace(struct compat_frame_tail __user *tail, void perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); + + if (guest_cbs && guest_cbs->is_in_guest()) { /* We don't support guest os callchain now */ return; } @@ -147,9 +149,10 @@ static bool callchain_trace(void *data, unsigned long pc) void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); struct stackframe frame; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { + if (guest_cbs && guest_cbs->is_in_guest()) { /* We don't support guest os callchain now */ return; } @@ -160,18 +163,21 @@ void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, unsigned long perf_instruction_pointer(struct pt_regs *regs) { - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) - return perf_guest_cbs->get_guest_ip(); + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); + + if (guest_cbs && guest_cbs->is_in_guest()) + return guest_cbs->get_guest_ip(); return instruction_pointer(regs); } unsigned long perf_misc_flags(struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); int misc = 0; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { - if (perf_guest_cbs->is_user_mode()) + if (guest_cbs && guest_cbs->is_in_guest()) { + if (guest_cbs->is_user_mode()) misc |= PERF_RECORD_MISC_GUEST_USER; else misc |= PERF_RECORD_MISC_GUEST_KERNEL; diff --git a/arch/csky/kernel/perf_callchain.c b/arch/csky/kernel/perf_callchain.c index ab55e98ee8f6..35318a635a5f 100644 --- a/arch/csky/kernel/perf_callchain.c +++ b/arch/csky/kernel/perf_callchain.c @@ -86,10 +86,11 @@ static unsigned long user_backtrace(struct perf_callchain_entry_ctx *entry, void perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); unsigned long fp = 0; /* C-SKY does not support virtualization. */ - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) + if (guest_cbs && guest_cbs->is_in_guest()) return; fp = regs->regs[4]; @@ -110,10 +111,11 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry, void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); struct stackframe fr; /* C-SKY does not support virtualization. */ - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { + if (guest_cbs && guest_cbs->is_in_guest()) { pr_warn("C-SKY does not support perf in guest mode!"); return; } diff --git a/arch/nds32/kernel/perf_event_cpu.c b/arch/nds32/kernel/perf_event_cpu.c index 0ce6f9f307e6..f38791960781 100644 --- a/arch/nds32/kernel/perf_event_cpu.c +++ b/arch/nds32/kernel/perf_event_cpu.c @@ -1363,6 +1363,7 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); unsigned long fp = 0; unsigned long gp = 0; unsigned long lp = 0; @@ -1371,7 +1372,7 @@ perf_callchain_user(struct perf_callchain_entry_ctx *entry, leaf_fp = 0; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { + if (guest_cbs && guest_cbs->is_in_guest()) { /* We don't support guest os callchain now */ return; } @@ -1479,9 +1480,10 @@ void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); struct stackframe fr; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { + if (guest_cbs && guest_cbs->is_in_guest()) { /* We don't support guest os callchain now */ return; } @@ -1493,20 +1495,23 @@ perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, unsigned long perf_instruction_pointer(struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); + /* However, NDS32 does not support virtualization */ - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) - return perf_guest_cbs->get_guest_ip(); + if (guest_cbs && guest_cbs->is_in_guest()) + return guest_cbs->get_guest_ip(); return instruction_pointer(regs); } unsigned long perf_misc_flags(struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); int misc = 0; /* However, NDS32 does not support virtualization */ - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { - if (perf_guest_cbs->is_user_mode()) + if (guest_cbs && guest_cbs->is_in_guest()) { + if (guest_cbs->is_user_mode()) misc |= PERF_RECORD_MISC_GUEST_USER; else misc |= PERF_RECORD_MISC_GUEST_KERNEL; diff --git a/arch/riscv/kernel/perf_callchain.c b/arch/riscv/kernel/perf_callchain.c index 0bb1854dce83..8ecfc4c128bc 100644 --- a/arch/riscv/kernel/perf_callchain.c +++ b/arch/riscv/kernel/perf_callchain.c @@ -56,10 +56,11 @@ static unsigned long user_backtrace(struct perf_callchain_entry_ctx *entry, void perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); unsigned long fp = 0; /* RISC-V does not support perf in guest mode. */ - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) + if (guest_cbs && guest_cbs->is_in_guest()) return; fp = regs->s0; @@ -78,8 +79,10 @@ static bool fill_callchain(void *entry, unsigned long pc) void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); + /* RISC-V does not support perf in guest mode. */ - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { + if (guest_cbs && guest_cbs->is_in_guest()) { pr_warn("RISC-V does not support perf in guest mode!"); return; } diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 38b2c779146f..32cec290d3ad 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2768,10 +2768,11 @@ static bool perf_hw_regs(struct pt_regs *regs) void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); struct unwind_state state; unsigned long addr; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { + if (guest_cbs && guest_cbs->is_in_guest()) { /* TODO: We don't support guest os callchain now */ return; } @@ -2871,10 +2872,11 @@ perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *ent void perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); struct stack_frame frame; const struct stack_frame __user *fp; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { + if (guest_cbs && guest_cbs->is_in_guest()) { /* TODO: We don't support guest os callchain now */ return; } @@ -2951,18 +2953,21 @@ static unsigned long code_segment_base(struct pt_regs *regs) unsigned long perf_instruction_pointer(struct pt_regs *regs) { - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) - return perf_guest_cbs->get_guest_ip(); + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); + + if (guest_cbs && guest_cbs->is_in_guest()) + return guest_cbs->get_guest_ip(); return regs->ip + code_segment_base(regs); } unsigned long perf_misc_flags(struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); int misc = 0; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { - if (perf_guest_cbs->is_user_mode()) + if (guest_cbs && guest_cbs->is_in_guest()) { + if (guest_cbs->is_user_mode()) misc |= PERF_RECORD_MISC_GUEST_USER; else misc |= PERF_RECORD_MISC_GUEST_KERNEL; diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 42cf01ecdd13..2258e02ca350 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2837,6 +2837,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) { struct perf_sample_data data; struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + struct perf_guest_info_callbacks *guest_cbs; int bit; int handled = 0; u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); @@ -2903,9 +2904,11 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) */ if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { handled++; - if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() && - perf_guest_cbs->handle_intel_pt_intr)) - perf_guest_cbs->handle_intel_pt_intr(); + + guest_cbs = perf_get_guest_cbs(); + if (unlikely(guest_cbs && guest_cbs->is_in_guest() && + guest_cbs->handle_intel_pt_intr)) + guest_cbs->handle_intel_pt_intr(); else intel_pt_interrupt(); } diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 0dcfd265beed..318c489b735b 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -1240,7 +1240,18 @@ extern void perf_event_bpf_event(struct bpf_prog *prog, enum perf_bpf_event_type type, u16 flags); -extern struct perf_guest_info_callbacks *perf_guest_cbs; +extern struct perf_guest_info_callbacks __rcu *perf_guest_cbs; +static inline struct perf_guest_info_callbacks *perf_get_guest_cbs(void) +{ + /* + * Callbacks are RCU-protected and must be READ_ONCE to avoid reloading + * the callbacks between a !NULL check and dereferences, to ensure + * pending stores/changes to the callback pointers are visible before a + * non-NULL perf_guest_cbs is visible to readers, and to prevent a + * module from unloading callbacks while readers are active. + */ + return rcu_dereference(perf_guest_cbs); +} extern int perf_register_guest_info_callbacks(struct perf_guest_info_callbacks *callbacks); extern int perf_unregister_guest_info_callbacks(struct perf_guest_info_callbacks *callbacks); diff --git a/kernel/events/core.c b/kernel/events/core.c index 523106a506ee..c552e1bfcaea 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -6526,18 +6526,25 @@ static void perf_pending_event(struct irq_work *entry) * Later on, we might change it to a list if there is * another virtualization implementation supporting the callbacks. */ -struct perf_guest_info_callbacks *perf_guest_cbs; +struct perf_guest_info_callbacks __rcu *perf_guest_cbs; int perf_register_guest_info_callbacks(struct perf_guest_info_callbacks *cbs) { - perf_guest_cbs = cbs; + if (WARN_ON_ONCE(rcu_access_pointer(perf_guest_cbs))) + return -EBUSY; + + rcu_assign_pointer(perf_guest_cbs, cbs); return 0; } EXPORT_SYMBOL_GPL(perf_register_guest_info_callbacks); int perf_unregister_guest_info_callbacks(struct perf_guest_info_callbacks *cbs) { - perf_guest_cbs = NULL; + if (WARN_ON_ONCE(rcu_access_pointer(perf_guest_cbs) != cbs)) + return -EINVAL; + + rcu_assign_pointer(perf_guest_cbs, NULL); + synchronize_rcu(); return 0; } EXPORT_SYMBOL_GPL(perf_unregister_guest_info_callbacks); -- cgit v1.2.3 From 84af21d850ee1ccc990df37dd47c13fdfe93be75 Mon Sep 17 00:00:00 2001 From: Sean Christopherson Date: Thu, 11 Nov 2021 02:07:26 +0000 Subject: perf: Drop dead and useless guest "support" from arm, csky, nds32 and riscv Drop "support" for guest callbacks from architectures that don't implement the guest callbacks. Future patches will convert the callbacks to static_call; rather than churn a bunch of arch code (that was presumably copy+pasted from x86), remove it wholesale as it's useless and at best wasting cycles. A future patch will also add a Kconfig to force architcture to opt into the callbacks to make it more difficult for uses "support" to sneak in in the future. No functional change intended. Signed-off-by: Sean Christopherson Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Paolo Bonzini Link: https://lore.kernel.org/r/20211111020738.2512932-6-seanjc@google.com --- arch/arm/kernel/perf_callchain.c | 33 ++++----------------------------- arch/csky/kernel/perf_callchain.c | 12 ------------ arch/nds32/kernel/perf_event_cpu.c | 34 ++++------------------------------ arch/riscv/kernel/perf_callchain.c | 13 ------------- 4 files changed, 8 insertions(+), 84 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/perf_callchain.c b/arch/arm/kernel/perf_callchain.c index 1626dfc6f6ce..bc6b246ab55e 100644 --- a/arch/arm/kernel/perf_callchain.c +++ b/arch/arm/kernel/perf_callchain.c @@ -62,14 +62,8 @@ user_backtrace(struct frame_tail __user *tail, void perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { - struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); struct frame_tail __user *tail; - if (guest_cbs && guest_cbs->is_in_guest()) { - /* We don't support guest os callchain now */ - return; - } - perf_callchain_store(entry, regs->ARM_pc); if (!current->mm) @@ -99,44 +93,25 @@ callchain_trace(struct stackframe *fr, void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { - struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); struct stackframe fr; - if (guest_cbs && guest_cbs->is_in_guest()) { - /* We don't support guest os callchain now */ - return; - } - arm_get_current_stackframe(regs, &fr); walk_stackframe(&fr, callchain_trace, entry); } unsigned long perf_instruction_pointer(struct pt_regs *regs) { - struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); - - if (guest_cbs && guest_cbs->is_in_guest()) - return guest_cbs->get_guest_ip(); - return instruction_pointer(regs); } unsigned long perf_misc_flags(struct pt_regs *regs) { - struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); int misc = 0; - if (guest_cbs && guest_cbs->is_in_guest()) { - if (guest_cbs->is_user_mode()) - misc |= PERF_RECORD_MISC_GUEST_USER; - else - misc |= PERF_RECORD_MISC_GUEST_KERNEL; - } else { - if (user_mode(regs)) - misc |= PERF_RECORD_MISC_USER; - else - misc |= PERF_RECORD_MISC_KERNEL; - } + if (user_mode(regs)) + misc |= PERF_RECORD_MISC_USER; + else + misc |= PERF_RECORD_MISC_KERNEL; return misc; } diff --git a/arch/csky/kernel/perf_callchain.c b/arch/csky/kernel/perf_callchain.c index 35318a635a5f..92057de08f4f 100644 --- a/arch/csky/kernel/perf_callchain.c +++ b/arch/csky/kernel/perf_callchain.c @@ -86,13 +86,8 @@ static unsigned long user_backtrace(struct perf_callchain_entry_ctx *entry, void perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { - struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); unsigned long fp = 0; - /* C-SKY does not support virtualization. */ - if (guest_cbs && guest_cbs->is_in_guest()) - return; - fp = regs->regs[4]; perf_callchain_store(entry, regs->pc); @@ -111,15 +106,8 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry, void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { - struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); struct stackframe fr; - /* C-SKY does not support virtualization. */ - if (guest_cbs && guest_cbs->is_in_guest()) { - pr_warn("C-SKY does not support perf in guest mode!"); - return; - } - fr.fp = regs->regs[4]; fr.lr = regs->lr; walk_stackframe(&fr, entry); diff --git a/arch/nds32/kernel/perf_event_cpu.c b/arch/nds32/kernel/perf_event_cpu.c index f38791960781..a78a879e7ef1 100644 --- a/arch/nds32/kernel/perf_event_cpu.c +++ b/arch/nds32/kernel/perf_event_cpu.c @@ -1363,7 +1363,6 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { - struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); unsigned long fp = 0; unsigned long gp = 0; unsigned long lp = 0; @@ -1372,11 +1371,6 @@ perf_callchain_user(struct perf_callchain_entry_ctx *entry, leaf_fp = 0; - if (guest_cbs && guest_cbs->is_in_guest()) { - /* We don't support guest os callchain now */ - return; - } - perf_callchain_store(entry, regs->ipc); fp = regs->fp; gp = regs->gp; @@ -1480,13 +1474,8 @@ void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { - struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); struct stackframe fr; - if (guest_cbs && guest_cbs->is_in_guest()) { - /* We don't support guest os callchain now */ - return; - } fr.fp = regs->fp; fr.lp = regs->lp; fr.sp = regs->sp; @@ -1495,32 +1484,17 @@ perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, unsigned long perf_instruction_pointer(struct pt_regs *regs) { - struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); - - /* However, NDS32 does not support virtualization */ - if (guest_cbs && guest_cbs->is_in_guest()) - return guest_cbs->get_guest_ip(); - return instruction_pointer(regs); } unsigned long perf_misc_flags(struct pt_regs *regs) { - struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); int misc = 0; - /* However, NDS32 does not support virtualization */ - if (guest_cbs && guest_cbs->is_in_guest()) { - if (guest_cbs->is_user_mode()) - misc |= PERF_RECORD_MISC_GUEST_USER; - else - misc |= PERF_RECORD_MISC_GUEST_KERNEL; - } else { - if (user_mode(regs)) - misc |= PERF_RECORD_MISC_USER; - else - misc |= PERF_RECORD_MISC_KERNEL; - } + if (user_mode(regs)) + misc |= PERF_RECORD_MISC_USER; + else + misc |= PERF_RECORD_MISC_KERNEL; return misc; } diff --git a/arch/riscv/kernel/perf_callchain.c b/arch/riscv/kernel/perf_callchain.c index 8ecfc4c128bc..1fc075b8f764 100644 --- a/arch/riscv/kernel/perf_callchain.c +++ b/arch/riscv/kernel/perf_callchain.c @@ -56,13 +56,8 @@ static unsigned long user_backtrace(struct perf_callchain_entry_ctx *entry, void perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { - struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); unsigned long fp = 0; - /* RISC-V does not support perf in guest mode. */ - if (guest_cbs && guest_cbs->is_in_guest()) - return; - fp = regs->s0; perf_callchain_store(entry, regs->epc); @@ -79,13 +74,5 @@ static bool fill_callchain(void *entry, unsigned long pc) void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { - struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); - - /* RISC-V does not support perf in guest mode. */ - if (guest_cbs && guest_cbs->is_in_guest()) { - pr_warn("RISC-V does not support perf in guest mode!"); - return; - } - walk_stackframe(NULL, regs, fill_callchain, entry); } -- cgit v1.2.3 From 801cd261718e44adeb033c428390761adc03e2fc Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 29 Oct 2021 12:33:39 +0200 Subject: ARM: dts: qcom: update USB nodes with new platform specific compatible To match dwc3 documentation, add compatible for platform. Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211029103340.26828-2-david@ixit.cz --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++-- arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index ff1bdb10ad19..7dec0553636e 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -637,7 +637,7 @@ }; usb3: usb3@8af8800 { - compatible = "qcom,dwc3"; + compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; reg = <0x8af8800 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -669,7 +669,7 @@ }; usb2: usb2@60f8800 { - compatible = "qcom,dwc3"; + compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; reg = <0x60f8800 0x100>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 11481313bdb6..996f4458d9fc 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -1080,7 +1080,7 @@ }; usb3_0: usb3@100f8800 { - compatible = "qcom,dwc3", "syscon"; + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; #address-cells = <1>; #size-cells = <1>; reg = <0x100f8800 0x8000>; @@ -1122,7 +1122,7 @@ }; usb3_1: usb3@110f8800 { - compatible = "qcom,dwc3", "syscon"; + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; #address-cells = <1>; #size-cells = <1>; reg = <0x110f8800 0x8000>; -- cgit v1.2.3 From f9d3b807daa69728e59a5171e8e7b40cfa848383 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Wed, 20 Oct 2021 16:50:13 +0100 Subject: ARM: dts: vf610-zii-dev-rev-b: correct phy-mode for 6185 dsa link DT currently lists the port mode for the 88E6352 switch 1 to 88E6185 switch 2 as "rgmii-id" but referring to the schematics, it is in fact a serdes link. The 88E6352 is configured with P5_MODE=6, S_SEL=1 and S_MODE=1, which means port 5 is configured as 1000BASE-X. This is confirmed by the value in the 88E6352 port 5 status register, 0x4e09, where C_MODE=9 meaning 1000BASE-X. It is also confirmed by the 88E6185 port 9 status register, 0x5e8c, where C_MODE=4 meaning cross-chip SERDES mode is selected. Signed-off-by: Russell King (Oracle) Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 043ddd70372f..80698e98dafe 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -149,7 +149,7 @@ reg = <5>; label = "dsa"; link = <&switch2port9>; - phy-mode = "rgmii-txid"; + phy-mode = "1000base-x"; fixed-link { speed = <1000>; @@ -252,7 +252,7 @@ switch2port9: port@9 { reg = <9>; label = "dsa"; - phy-mode = "rgmii-txid"; + phy-mode = "1000base-x"; link = <&switch1port5 &switch0port5>; -- cgit v1.2.3 From 52c612692848bbe6ae2feb31706911641b17afc9 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Tue, 26 Oct 2021 10:34:23 +0100 Subject: ARM: dts: vf610-zii-dev-rev-b: specify phy-mode for external PHYs Specify the phy-mode for the external PHYs on the third switch on the ZII development rev B board so phylink and phylib knows what mode these interfaces are configured for. Signed-off-by: Russell King (Oracle) Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 80698e98dafe..1f9686c33a84 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -211,12 +211,14 @@ reg = <0>; label = "lan6"; phy-handle = <&switch2phy0>; + phy-mode = "sgmii"; }; port@1 { reg = <1>; label = "lan7"; phy-handle = <&switch2phy1>; + phy-mode = "sgmii"; }; port@2 { -- cgit v1.2.3 From efe33befc2ffc94248159978902a374c7b2882d0 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Thu, 28 Oct 2021 16:19:32 +0200 Subject: ARM: imx: remove dead left-over from i.MX{27,31,35} removal The commits: commit 879c0e5e0ac7 ("ARM: imx: Remove i.MX27 board files") commit c93197b0041d ("ARM: imx: Remove i.MX31 board files") commit e1324ece2af4 ("ARM: imx: Remove i.MX35 board files") remove the config MACH_MX27_3DS, MACH_MX31_3DS and MACH_MX35_3DS. Commit a542fc18168c ("ARM: imx31: Remove remaining i.MX31 board code") further removes arch/arm/mach-imx/3ds_debugboard.{c,h}. So, only some dead left-over in Kconfig and Makefile remains. Remove this remaining left-over. This issue was identified with ./scripts/checkkconfigsymbols.py, which warns on references to the non-existing configs MACH_MX{27,31,35}_3DS in ./arch/arm/mach-imx/Kconfig. Signed-off-by: Lukas Bulwahn Reviewed-by: Arnd Bergmann Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Kconfig | 12 ------------ arch/arm/mach-imx/Makefile | 2 -- 2 files changed, 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index b407b024dde3..f296bac467c8 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -21,18 +21,6 @@ config MXC_TZIC config MXC_AVIC bool -config MXC_DEBUG_BOARD - bool "Enable MXC debug board(for 3-stack)" - depends on MACH_MX27_3DS || MACH_MX31_3DS || MACH_MX35_3DS - help - The debug board is an integral part of the MXC 3-stack(PDK) - platforms, it can be attached or removed from the peripheral - board. On debug board, several debug devices(ethernet, UART, - buttons, LEDs and JTAG) are implemented. Between the MCU and - these devices, a CPLD is added as a bridge which performs - data/address de-multiplexing and decode, signal level shift, - interrupt control and various board functions. - config HAVE_IMX_ANATOP bool diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index d1506ef7a537..d5291ed9186a 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -14,8 +14,6 @@ obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o $(imx5-pm-y) obj-$(CONFIG_MXC_TZIC) += tzic.o obj-$(CONFIG_MXC_AVIC) += avic.o -obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o - ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o -- cgit v1.2.3 From b0100bce4ff82ec1ccd3c1f3d339fd2df6a81784 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Thu, 28 Oct 2021 16:19:33 +0200 Subject: ARM: imx: rename DEBUG_IMX21_IMX27_UART to DEBUG_IMX27_UART Since commit 4b563a066611 ("ARM: imx: Remove imx21 support"), the config DEBUG_IMX21_IMX27_UART is really only debug support for IMX27. So, rename this option to DEBUG_IMX27_UART and adjust dependencies in Kconfig and rename the definitions to IMX27 as further clean-up. This issue was discovered with ./scripts/checkkconfigsymbols.py, which reported that DEBUG_IMX21_IMX27_UART depends on the non-existing config SOC_IMX21. Signed-off-by: Lukas Bulwahn Reviewed-by: Arnd Bergmann Signed-off-by: Shawn Guo --- arch/arm/Kconfig.debug | 14 +++++++------- arch/arm/include/debug/imx-uart.h | 18 +++++++++--------- 2 files changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 98436702e0c7..644875d73ba1 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -410,12 +410,12 @@ choice Say Y here if you want kernel low-level debugging support on i.MX25. - config DEBUG_IMX21_IMX27_UART - bool "i.MX21 and i.MX27 Debug UART" - depends on SOC_IMX21 || SOC_IMX27 + config DEBUG_IMX27_UART + bool "i.MX27 Debug UART" + depends on SOC_IMX27 help Say Y here if you want kernel low-level debugging support - on i.MX21 or i.MX27. + on i.MX27. config DEBUG_IMX28_UART bool "i.MX28 Debug UART" @@ -1481,7 +1481,7 @@ config DEBUG_IMX_UART_PORT int "i.MX Debug UART Port Selection" depends on DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ - DEBUG_IMX21_IMX27_UART || \ + DEBUG_IMX27_UART || \ DEBUG_IMX31_UART || \ DEBUG_IMX35_UART || \ DEBUG_IMX50_UART || \ @@ -1540,12 +1540,12 @@ config DEBUG_LL_INCLUDE default "debug/icedcc.S" if DEBUG_ICEDCC default "debug/imx.S" if DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ - DEBUG_IMX21_IMX27_UART || \ + DEBUG_IMX27_UART || \ DEBUG_IMX31_UART || \ DEBUG_IMX35_UART || \ DEBUG_IMX50_UART || \ DEBUG_IMX51_UART || \ - DEBUG_IMX53_UART ||\ + DEBUG_IMX53_UART || \ DEBUG_IMX6Q_UART || \ DEBUG_IMX6SL_UART || \ DEBUG_IMX6SX_UART || \ diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h index c8eb83d4b896..3edbb3c5b42b 100644 --- a/arch/arm/include/debug/imx-uart.h +++ b/arch/arm/include/debug/imx-uart.h @@ -11,13 +11,6 @@ #define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR #define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n) -#define IMX21_UART1_BASE_ADDR 0x1000a000 -#define IMX21_UART2_BASE_ADDR 0x1000b000 -#define IMX21_UART3_BASE_ADDR 0x1000c000 -#define IMX21_UART4_BASE_ADDR 0x1000d000 -#define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR -#define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n) - #define IMX25_UART1_BASE_ADDR 0x43f90000 #define IMX25_UART2_BASE_ADDR 0x43f94000 #define IMX25_UART3_BASE_ADDR 0x5000c000 @@ -26,6 +19,13 @@ #define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR #define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n) +#define IMX27_UART1_BASE_ADDR 0x1000a000 +#define IMX27_UART2_BASE_ADDR 0x1000b000 +#define IMX27_UART3_BASE_ADDR 0x1000c000 +#define IMX27_UART4_BASE_ADDR 0x1000d000 +#define IMX27_UART_BASE_ADDR(n) IMX27_UART##n##_BASE_ADDR +#define IMX27_UART_BASE(n) IMX27_UART_BASE_ADDR(n) + #define IMX31_UART1_BASE_ADDR 0x43f90000 #define IMX31_UART2_BASE_ADDR 0x43f94000 #define IMX31_UART3_BASE_ADDR 0x5000c000 @@ -112,10 +112,10 @@ #ifdef CONFIG_DEBUG_IMX1_UART #define UART_PADDR IMX_DEBUG_UART_BASE(IMX1) -#elif defined(CONFIG_DEBUG_IMX21_IMX27_UART) -#define UART_PADDR IMX_DEBUG_UART_BASE(IMX21) #elif defined(CONFIG_DEBUG_IMX25_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX25) +#elif defined(CONFIG_DEBUG_IMX27_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX27) #elif defined(CONFIG_DEBUG_IMX31_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX31) #elif defined(CONFIG_DEBUG_IMX35_UART) -- cgit v1.2.3 From 3ac5f9db26bb7a227ccbf160c36a5567b5394299 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Sun, 21 Nov 2021 17:05:58 +0200 Subject: ARM: samsung: Remove HAVE_S3C2410_I2C and use direct dependencies A separate Kconfig option HAVE_S3C2410_I2C for Samsung SoCs is not really needed and the i2c-s3c24xx driver can depend on Samsung ARM architectures instead. This also enables i2c-s3c2410 for arm64 Exynos SoCs, which is required for example by Exynos850. This is basically continuation of work made in following commits: - commit d96890fca9fd ("rtc: s3c: remove HAVE_S3C_RTC in favor of direct dependencies") - commit 7dd3cae90d85 ("ARM: samsung: remove HAVE_S3C2410_WATCHDOG and use direct dependencies") Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211121150558.21801-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/Kconfig | 1 - arch/arm/mach-exynos/Kconfig | 1 - arch/arm/mach-s3c/Kconfig.s3c64xx | 1 - arch/arm/mach-s5pv210/Kconfig | 1 - drivers/i2c/busses/Kconfig | 10 ++-------- 5 files changed, 2 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0f9e8bec83a..391f07c17096 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -479,7 +479,6 @@ config ARCH_S3C24XX select GPIO_SAMSUNG select GPIOLIB select GENERIC_IRQ_MULTI_HANDLER - select HAVE_S3C2410_I2C if I2C select NEED_MACH_IO_H select S3C2410_WATCHDOG select SAMSUNG_ATAGS diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index dd1ae5571f43..f7d993628cb7 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -20,7 +20,6 @@ menuconfig ARCH_EXYNOS select GPIOLIB select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5 select HAVE_ARM_SCU if SMP - select HAVE_S3C2410_I2C if I2C select PINCTRL select PINCTRL_EXYNOS select PM_GENERIC_DOMAINS if PM diff --git a/arch/arm/mach-s3c/Kconfig.s3c64xx b/arch/arm/mach-s3c/Kconfig.s3c64xx index f3fcb570edf5..af01675d8769 100644 --- a/arch/arm/mach-s3c/Kconfig.s3c64xx +++ b/arch/arm/mach-s3c/Kconfig.s3c64xx @@ -12,7 +12,6 @@ menuconfig ARCH_S3C64XX select COMMON_CLK_SAMSUNG select GPIO_SAMSUNG if ATAGS select GPIOLIB - select HAVE_S3C2410_I2C if I2C select HAVE_TCM select PLAT_SAMSUNG select PM_GENERIC_DOMAINS if PM diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 5a96099af991..055de578b57f 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -12,7 +12,6 @@ config ARCH_S5PV210 select CLKSRC_SAMSUNG_PWM select COMMON_CLK_SAMSUNG select GPIOLIB - select HAVE_S3C2410_I2C if I2C select PINCTRL select PINCTRL_EXYNOS select SOC_SAMSUNG diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index dce392839017..c6b854a9e476 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -963,16 +963,10 @@ config I2C_RK3X This driver can also be built as a module. If so, the module will be called i2c-rk3x. -config HAVE_S3C2410_I2C - bool - help - This will include I2C support for Samsung SoCs. If you want to - include I2C support for any machine, kindly select this in the - respective Kconfig file. - config I2C_S3C2410 tristate "S3C/Exynos I2C Driver" - depends on HAVE_S3C2410_I2C || COMPILE_TEST + depends on ARCH_EXYNOS || ARCH_S3C24XX || ARCH_S3C64XX || \ + ARCH_S5PV210 || COMPILE_TEST help Say Y here to include support for I2C controller in the Samsung SoCs (S3C, S5Pv210, Exynos). -- cgit v1.2.3 From 725bc607aa02d570c35c5f21c3eadc3342bf4e06 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 21 Nov 2021 08:03:21 +0100 Subject: ARM: dts: sun8i: h3: beelink-x2: Sort nodes Nodes are not sorted alphabetically. Do it. There is no functional change. Signed-off-by: Jernej Skrabec Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211121070321.601659-1-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index f0e591e1c771..9dfd1a86b6c6 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -87,11 +87,15 @@ }; }; - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; + r-gpio-keys { + compatible = "gpio-keys"; + + power { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; }; sound_spdif { @@ -112,15 +116,11 @@ compatible = "linux,spdif-dit"; }; - r-gpio-keys { - compatible = "gpio-keys"; - - power { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; }; -- cgit v1.2.3 From 38df5750962c61b96d4e53358f31955fe310d4f5 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 20 Nov 2021 08:34:48 +0100 Subject: ARM: dts: sunxi: Add CEC clock to DW-HDMI Experimentation determined that HDMI CEC controller inside DW HDMI block depends on 32k clock from RTC. If this clock is tampered with, HDMI CEC communication starts or stops working, depending on situation. SoC user manual doesn't say anything about CEC, so this was overlooked. Fix this by adding dependency to RTC 32k clock. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211120073448.32480-3-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-r40.dtsi | 4 ++-- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 1d87fc0c24ee..f10436b7869c 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -1212,8 +1212,8 @@ reg-io-width = <1>; interrupts = ; clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; + <&ccu CLK_HDMI>, <&rtc 0>; + clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index c7428df9469e..d1e974886fdf 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -813,8 +813,8 @@ reg-io-width = <1>; interrupts = ; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; + <&ccu CLK_HDMI>, <&rtc 0>; + clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; -- cgit v1.2.3 From bbdde16e5d7ebfd2e04bc41f800ebbd5468336b1 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 20 Nov 2021 11:20:24 +0100 Subject: ARM: dts: sun8i: h3: beelink-x2: Add GPIO CEC node Beelink X2 doesn't use HW CEC controller found in DW HDMI core. It has dedicated GPIO pin for that purpose. Add a node for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211120102024.439456-1-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index 9dfd1a86b6c6..cd9f655e4f92 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -57,6 +57,12 @@ ethernet1 = &sdiowifi; }; + cec-gpio { + compatible = "cec-gpio"; + cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */ + hdmi-phandle = <&hdmi>; + }; + chosen { stdout-path = "serial0:115200n8"; }; -- cgit v1.2.3 From 8e0150fe5cf5b86df55257d800258e57d7d34202 Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Mon, 15 Nov 2021 18:30:53 +0900 Subject: ARM: dts: milbeaut: add a clock node for M10V Add a clock node for the platform of the Milbeaut M10V. Signed-off-by: Sugaya Taichi Link: https://lore.kernel.org/r/1636968656-14033-2-git-send-email-sugaya.taichi@socionext.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/milbeaut-m10v.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi index aa7c6caeb750..28aee25d939e 100644 --- a/arch/arm/boot/dts/milbeaut-m10v.dtsi +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -65,6 +65,13 @@ <0x1d002000 0x1000>; /* CPU I/f base and size */ }; + clk: clock-ctrl@1d021000 { + compatible = "socionext,milbeaut-m10v-ccu"; + #clock-cells = <1>; + reg = <0x1d021000 0x1000>; + clocks = <&uclk40xi>; + }; + timer@1e000050 { /* 32-bit Reload Timers */ compatible = "socionext,milbeaut-timer"; reg = <0x1e000050 0x20>; -- cgit v1.2.3 From 2fc4dfc294eef022889e56ebcd4f0c6c6e34e3c5 Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Mon, 15 Nov 2021 18:30:54 +0900 Subject: ARM: dts: milbeaut: set clock phandle to timer node Set clock phandle to timer node for Milbeaut M10V support. Signed-off-by: Sugaya Taichi Link: https://lore.kernel.org/r/1636968656-14033-3-git-send-email-sugaya.taichi@socionext.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/milbeaut-m10v.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi index 28aee25d939e..9f70784bad0c 100644 --- a/arch/arm/boot/dts/milbeaut-m10v.dtsi +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -76,6 +76,7 @@ compatible = "socionext,milbeaut-timer"; reg = <0x1e000050 0x20>; interrupts = <0 91 4>; + clocks = <&clk 4>; }; uart1: serial@1e700010 { /* PE4, PE5 */ -- cgit v1.2.3 From 69a25d34f377b5602d188a05827f6173c26ff0de Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Mon, 15 Nov 2021 18:30:55 +0900 Subject: ARM: dts: milbeaut: set clock phandle to uart node Set clock phandle to uart node for Milbeaut M10V support. Signed-off-by: Sugaya Taichi Link: https://lore.kernel.org/r/1636968656-14033-4-git-send-email-sugaya.taichi@socionext.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/milbeaut-m10v.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi index 9f70784bad0c..75f0c0af2270 100644 --- a/arch/arm/boot/dts/milbeaut-m10v.dtsi +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -85,6 +85,7 @@ reg = <0x1e700010 0x10>; interrupts = <0 141 0x4>, <0 149 0x4>; interrupt-names = "rx", "tx"; + clocks = <&clk 2>; }; }; -- cgit v1.2.3 From c214f124161d446b340597e7c968e0a2dc149142 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Tue, 9 Nov 2021 19:57:10 +0000 Subject: arch_topology: Introduce thermal pressure update function The thermal pressure is a mechanism which is used for providing information about reduced CPU performance to the scheduler. Usually code has to convert the value from frequency units into capacity units, which are understandable by the scheduler. Create a common conversion code which can be just used via a handy API. Internally, the topology_update_thermal_pressure() operates on frequency in MHz and max CPU frequency is taken from 'freq_factor' (per-cpu). Signed-off-by: Lukasz Luba Reviewed-by: Thara Gopinath Signed-off-by: Viresh Kumar --- arch/arm/include/asm/topology.h | 1 + arch/arm64/include/asm/topology.h | 1 + drivers/base/arch_topology.c | 43 ++++++++++++++++++++++++++++++++++++++- include/linux/arch_topology.h | 3 +++ include/linux/sched/topology.h | 7 +++++++ 5 files changed, 54 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h index 470299ee2fba..f1eafacc9a30 100644 --- a/arch/arm/include/asm/topology.h +++ b/arch/arm/include/asm/topology.h @@ -24,6 +24,7 @@ /* Replace task scheduler's default thermal pressure API */ #define arch_scale_thermal_pressure topology_get_thermal_pressure #define arch_set_thermal_pressure topology_set_thermal_pressure +#define arch_update_thermal_pressure topology_update_thermal_pressure #else diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index ec2db3419c41..7a421cbc99ed 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -33,6 +33,7 @@ void update_freq_counters_refs(void); /* Replace task scheduler's default thermal pressure API */ #define arch_scale_thermal_pressure topology_get_thermal_pressure #define arch_set_thermal_pressure topology_set_thermal_pressure +#define arch_update_thermal_pressure topology_update_thermal_pressure #include diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index ff16a36a908b..a3ae0b4eea09 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -22,6 +22,7 @@ static DEFINE_PER_CPU(struct scale_freq_data __rcu *, sft_data); static struct cpumask scale_freq_counters_mask; static bool scale_freq_invariant; +static DEFINE_PER_CPU(u32, freq_factor) = 1; static bool supports_scale_freq_counters(const struct cpumask *cpus) { @@ -165,6 +166,47 @@ void topology_set_thermal_pressure(const struct cpumask *cpus, } EXPORT_SYMBOL_GPL(topology_set_thermal_pressure); +/** + * topology_update_thermal_pressure() - Update thermal pressure for CPUs + * @cpus : The related CPUs for which capacity has been reduced + * @capped_freq : The maximum allowed frequency that CPUs can run at + * + * Update the value of thermal pressure for all @cpus in the mask. The + * cpumask should include all (online+offline) affected CPUs, to avoid + * operating on stale data when hot-plug is used for some CPUs. The + * @capped_freq reflects the currently allowed max CPUs frequency due to + * thermal capping. It might be also a boost frequency value, which is bigger + * than the internal 'freq_factor' max frequency. In such case the pressure + * value should simply be removed, since this is an indication that there is + * no thermal throttling. The @capped_freq must be provided in kHz. + */ +void topology_update_thermal_pressure(const struct cpumask *cpus, + unsigned long capped_freq) +{ + unsigned long max_capacity, capacity; + u32 max_freq; + int cpu; + + cpu = cpumask_first(cpus); + max_capacity = arch_scale_cpu_capacity(cpu); + max_freq = per_cpu(freq_factor, cpu); + + /* Convert to MHz scale which is used in 'freq_factor' */ + capped_freq /= 1000; + + /* + * Handle properly the boost frequencies, which should simply clean + * the thermal pressure value. + */ + if (max_freq <= capped_freq) + capacity = max_capacity; + else + capacity = mult_frac(max_capacity, capped_freq, max_freq); + + arch_set_thermal_pressure(cpus, max_capacity - capacity); +} +EXPORT_SYMBOL_GPL(topology_update_thermal_pressure); + static ssize_t cpu_capacity_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -217,7 +259,6 @@ static void update_topology_flags_workfn(struct work_struct *work) update_topology = 0; } -static DEFINE_PER_CPU(u32, freq_factor) = 1; static u32 *raw_capacity; static int free_raw_capacity(void) diff --git a/include/linux/arch_topology.h b/include/linux/arch_topology.h index b97cea83b25e..ace1e5dcf773 100644 --- a/include/linux/arch_topology.h +++ b/include/linux/arch_topology.h @@ -59,6 +59,9 @@ static inline unsigned long topology_get_thermal_pressure(int cpu) void topology_set_thermal_pressure(const struct cpumask *cpus, unsigned long th_pressure); +void topology_update_thermal_pressure(const struct cpumask *cpus, + unsigned long capped_freq); + struct cpu_topology { int thread_id; int core_id; diff --git a/include/linux/sched/topology.h b/include/linux/sched/topology.h index c07bfa2d80f2..6e89a8e43aa7 100644 --- a/include/linux/sched/topology.h +++ b/include/linux/sched/topology.h @@ -273,6 +273,13 @@ void arch_set_thermal_pressure(const struct cpumask *cpus, { } #endif +#ifndef arch_update_thermal_pressure +static __always_inline +void arch_update_thermal_pressure(const struct cpumask *cpus, + unsigned long capped_frequency) +{ } +#endif + static inline int task_node(const struct task_struct *p) { return cpu_to_node(task_cpu(p)); -- cgit v1.2.3 From 7e97b3dc2556743dd02612c92a8de7026e8d7dc9 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Tue, 9 Nov 2021 19:57:14 +0000 Subject: arch_topology: Remove unused topology_set_thermal_pressure() and related There is no need of this function (and related) since code has been converted to use the new arch_update_thermal_pressure() API. The old code can be removed. Signed-off-by: Lukasz Luba Signed-off-by: Viresh Kumar --- arch/arm/include/asm/topology.h | 1 - arch/arm64/include/asm/topology.h | 1 - drivers/base/arch_topology.c | 17 +++++------------ include/linux/arch_topology.h | 3 --- include/linux/sched/topology.h | 7 ------- init/Kconfig | 2 +- 6 files changed, 6 insertions(+), 25 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h index f1eafacc9a30..c7d2510e5a78 100644 --- a/arch/arm/include/asm/topology.h +++ b/arch/arm/include/asm/topology.h @@ -23,7 +23,6 @@ /* Replace task scheduler's default thermal pressure API */ #define arch_scale_thermal_pressure topology_get_thermal_pressure -#define arch_set_thermal_pressure topology_set_thermal_pressure #define arch_update_thermal_pressure topology_update_thermal_pressure #else diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index 7a421cbc99ed..f386b90a79c8 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -32,7 +32,6 @@ void update_freq_counters_refs(void); /* Replace task scheduler's default thermal pressure API */ #define arch_scale_thermal_pressure topology_get_thermal_pressure -#define arch_set_thermal_pressure topology_set_thermal_pressure #define arch_update_thermal_pressure topology_update_thermal_pressure #include diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index a3ae0b4eea09..976154140f0b 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -156,16 +156,6 @@ void topology_set_cpu_scale(unsigned int cpu, unsigned long capacity) DEFINE_PER_CPU(unsigned long, thermal_pressure); -void topology_set_thermal_pressure(const struct cpumask *cpus, - unsigned long th_pressure) -{ - int cpu; - - for_each_cpu(cpu, cpus) - WRITE_ONCE(per_cpu(thermal_pressure, cpu), th_pressure); -} -EXPORT_SYMBOL_GPL(topology_set_thermal_pressure); - /** * topology_update_thermal_pressure() - Update thermal pressure for CPUs * @cpus : The related CPUs for which capacity has been reduced @@ -183,7 +173,7 @@ EXPORT_SYMBOL_GPL(topology_set_thermal_pressure); void topology_update_thermal_pressure(const struct cpumask *cpus, unsigned long capped_freq) { - unsigned long max_capacity, capacity; + unsigned long max_capacity, capacity, th_pressure; u32 max_freq; int cpu; @@ -203,7 +193,10 @@ void topology_update_thermal_pressure(const struct cpumask *cpus, else capacity = mult_frac(max_capacity, capped_freq, max_freq); - arch_set_thermal_pressure(cpus, max_capacity - capacity); + th_pressure = max_capacity - capacity; + + for_each_cpu(cpu, cpus) + WRITE_ONCE(per_cpu(thermal_pressure, cpu), th_pressure); } EXPORT_SYMBOL_GPL(topology_update_thermal_pressure); diff --git a/include/linux/arch_topology.h b/include/linux/arch_topology.h index ace1e5dcf773..cce6136b300a 100644 --- a/include/linux/arch_topology.h +++ b/include/linux/arch_topology.h @@ -56,9 +56,6 @@ static inline unsigned long topology_get_thermal_pressure(int cpu) return per_cpu(thermal_pressure, cpu); } -void topology_set_thermal_pressure(const struct cpumask *cpus, - unsigned long th_pressure); - void topology_update_thermal_pressure(const struct cpumask *cpus, unsigned long capped_freq); diff --git a/include/linux/sched/topology.h b/include/linux/sched/topology.h index 6e89a8e43aa7..8054641c0a7b 100644 --- a/include/linux/sched/topology.h +++ b/include/linux/sched/topology.h @@ -266,13 +266,6 @@ unsigned long arch_scale_thermal_pressure(int cpu) } #endif -#ifndef arch_set_thermal_pressure -static __always_inline -void arch_set_thermal_pressure(const struct cpumask *cpus, - unsigned long th_pressure) -{ } -#endif - #ifndef arch_update_thermal_pressure static __always_inline void arch_update_thermal_pressure(const struct cpumask *cpus, diff --git a/init/Kconfig b/init/Kconfig index 036b750e8d8a..086fd11348e0 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -550,7 +550,7 @@ config SCHED_THERMAL_PRESSURE i.e. put less load on throttled CPUs than on non/less throttled ones. This requires the architecture to implement - arch_set_thermal_pressure() and arch_scale_thermal_pressure(). + arch_update_thermal_pressure() and arch_scale_thermal_pressure(). config BSD_PROCESS_ACCT bool "BSD Process Accounting" -- cgit v1.2.3 From 95f04048325cb808f4ca98f0a4d075bbb23576f8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 20 Jun 2021 00:42:59 +0200 Subject: ARM: dts: ux500: Add reset lines to IP blocks The new reset controller makes is possible to add reset lines to a host of IP blocks in the DB8500/U8500. Cc: Ulf Hansson Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 68607e4ad80c..dc0bcc7020f1 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -300,6 +301,10 @@ #clock-cells = <2>; }; + prcc_reset: prcc-reset-controller { + #reset-cells = <2>; + }; + rtc_clk: rtc32k-clock { #clock-cells = <0>; }; @@ -662,6 +667,7 @@ clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>; status = "disabled"; }; @@ -680,6 +686,7 @@ clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>; status = "disabled"; }; @@ -698,6 +705,7 @@ clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>; status = "disabled"; }; @@ -716,6 +724,7 @@ clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>; status = "disabled"; }; @@ -734,6 +743,7 @@ clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; clock-names = "i2cclk", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>; status = "disabled"; }; @@ -750,6 +760,7 @@ <&dma 8 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>; status = "disabled"; }; @@ -766,6 +777,7 @@ <&dma 9 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>; status = "disabled"; }; @@ -834,6 +846,7 @@ <&dma 40 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>; status = "disabled"; }; @@ -849,6 +862,7 @@ clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; clock-names = "uart", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>; status = "disabled"; }; @@ -864,6 +878,7 @@ clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; clock-names = "uart", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>; status = "disabled"; }; @@ -879,6 +894,7 @@ clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; clock-names = "uart", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>; status = "disabled"; }; @@ -895,6 +911,7 @@ clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>; status = "disabled"; }; @@ -911,6 +928,7 @@ clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>; status = "disabled"; }; @@ -927,6 +945,7 @@ clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>; status = "disabled"; }; @@ -943,6 +962,7 @@ clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>; status = "disabled"; }; @@ -959,6 +979,7 @@ clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>; status = "disabled"; }; @@ -975,6 +996,7 @@ clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; clock-names = "sdi", "apb_pclk"; power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>; status = "disabled"; }; @@ -996,6 +1018,7 @@ clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>; status = "disabled"; }; @@ -1012,6 +1035,7 @@ clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>; status = "disabled"; }; @@ -1030,6 +1054,7 @@ clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>; status = "disabled"; }; @@ -1046,6 +1071,7 @@ clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; clock-names = "msp", "apb_pclk"; + resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>; status = "disabled"; }; -- cgit v1.2.3 From c8f7b50785ca3a8b81f615da6e2f4e7b6380b20a Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:39 -0600 Subject: ARM: dts: sunxi: h3/h5: Update MBUS node In order to support memory dynamic frequency scaling (MDFS), the MBUS binding now requires enumerating more resources. Provide them in the device tree. Since the H3 and H5 have different clock divider limits, they need separate compatibles. Reviewed-by: Chanwoo Choi Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-5-samuel@sholland.org --- arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 11 ++++++++--- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ++++ 3 files changed, 16 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index ae4f933abb89..845f25235407 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -282,6 +282,10 @@ compatible = "allwinner,sun8i-h3-de2-clk"; }; +&mbus { + compatible = "allwinner,sun8i-h3-mbus"; +}; + &mmc0 { compatible = "allwinner,sun7i-a20-mmc"; clocks = <&ccu CLK_BUS_MMC0>, diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index d1e974886fdf..4aeca9e7e30d 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -568,9 +568,14 @@ }; mbus: dram-controller@1c62000 { - compatible = "allwinner,sun8i-h3-mbus"; - reg = <0x01c62000 0x1000>; - clocks = <&ccu CLK_MBUS>; + /* compatible is in per SoC .dtsi file */ + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0xc0000000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index 9988e87ea7b3..a56fae761a1f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -233,6 +233,10 @@ compatible = "allwinner,sun50i-h5-de2-clk"; }; +&mbus { + compatible = "allwinner,sun50i-h5-mbus"; +}; + &mmc0 { compatible = "allwinner,sun50i-h5-mmc", "allwinner,sun50i-a64-mmc"; -- cgit v1.2.3 From 1aa590c85ae4a66bd686146392708704828691a2 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Sat, 13 Nov 2021 11:21:56 +0800 Subject: ARM: dts: imx: Fix typo in pinfunc comments Remove the repeated `configurable' in some comments in imx1-pinfunc.h and imx27-pinfunc.h. Signed-off-by: Jason Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx1-pinfunc.h | 6 +++--- arch/arm/boot/dts/imx27-pinfunc.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx1-pinfunc.h b/arch/arm/boot/dts/imx1-pinfunc.h index 050a1fc46a77..bd2e679cb26c 100644 --- a/arch/arm/boot/dts/imx1-pinfunc.h +++ b/arch/arm/boot/dts/imx1-pinfunc.h @@ -26,9 +26,9 @@ * 2 - 0 * 3 - 1 * - * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable - * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin - * number on the specific port (between 0 and 31). + * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is + * the pin number on the specific port (between 0 and 31). */ #define MX1_PAD_A24__A24 0x00 0x004 diff --git a/arch/arm/boot/dts/imx27-pinfunc.h b/arch/arm/boot/dts/imx27-pinfunc.h index 1514d80a3112..75aea0c701d4 100644 --- a/arch/arm/boot/dts/imx27-pinfunc.h +++ b/arch/arm/boot/dts/imx27-pinfunc.h @@ -26,9 +26,9 @@ * 2 - 0 * 3 - 1 * - * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable - * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin - * number on the specific port (between 0 and 31). + * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is + * the pin number on the specific port (between 0 and 31). */ #define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000 -- cgit v1.2.3 From 11611eecb8aa1ab07f78e9bf0f2d8c40188e7826 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 23 Nov 2021 11:23:11 +0100 Subject: ARM: dts: ux500: Fixup Gavini magnetometer The Gavini device tree had the wrong magnetometer specified, this should be a YAS530. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-gavini.dts | 39 +++++++++++++------------- 1 file changed, 19 insertions(+), 20 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts index 47bbf5ab267f..1c0e5cfeddac 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts @@ -232,19 +232,18 @@ #address-cells = <1>; #size-cells = <0>; - /* TODO: Memsic MMC328 magnetometer */ - magnetometer@30 { - compatible = "memsic,mmc328"; - reg = <0x30>; - /* TODO: if you have the schematic, check if both voltages come from AUX2 */ - /* VDA 1.8 V */ - vda-supply = <&ab8500_ldo_aux2_reg>; - /* VDD 1.8V */ - vdd-supply = <&ab8500_ldo_aux2_reg>; - /* GPIO204 */ + /* Yamaha YAS530 magnetometer */ + magnetometer@2e { + compatible = "yamaha,yas530"; + reg = <0x2e>; + /* VDD 3V */ + vdd-supply = <&ab8500_ldo_aux1_reg>; + /* IOVDD 1.8V */ + iovdd-supply = <&ab8500_ldo_aux2_reg>; + /* GPIO204 COMPASS_RST_N */ reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&mmc328_default>; + pinctrl-0 = <&yas530_default>; }; /* TODO: this should also be used by the NCP6914 Camera power management unit */ }; @@ -645,6 +644,15 @@ }; }; }; + /* Reset line for the Yamaha YAS530 magnetometer */ + yas530 { + yas530_default: yas530_janice { + janice_cfg1 { + pins = "GPIO204_AF23"; + ste,config = <&gpio_out_hi>; + }; + }; + }; /* Flash and torch */ flash { gpio_flash_default_mode: flash_default { @@ -747,15 +755,6 @@ }; }; }; - /* Reset line for the Memsic MMC328 magnetometer */ - mmc328 { - mmc328_default: mmc328_gavini { - gavini_cfg1 { - pins = "GPIO204_AF23"; - ste,config = <&gpio_out_hi>; - }; - }; - }; /* Interrupt line for Invensense MPU3050 gyroscope */ mpu3050 { mpu3050_default: mpu3050 { -- cgit v1.2.3 From 1a46061a2a4130a08841941ce6dcaa32be2ce312 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 23 Nov 2021 10:03:33 +0100 Subject: ARM: dts: BCM5301X: use non-deprecated USB 2.0 PHY binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The new binding covers a single reg and uses syscon to reference shared register. References: 55b9b741712d ("dt-bindings: phy: brcm,ns-usb2-phy: bind just a PHY block") Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index e1cffef4935a..588e57db6859 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -148,15 +148,6 @@ }; }; - usb2_phy: usb2-phy@1800c000 { - compatible = "brcm,ns-usb2-phy"; - reg = <0x1800c000 0x1000>; - reg-names = "dmu"; - #phy-cells = <0>; - clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; - clock-names = "phy-ref-clk"; - }; - axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; @@ -448,7 +439,16 @@ "sata1", "sata2"; }; - syscon@180 { + usb2_phy: phy@164 { + compatible = "brcm,ns-usb2-phy"; + reg = <0x164 0x4>; + brcm,syscon-clkset = <&cru_clkset>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + #phy-cells = <0>; + }; + + cru_clkset: syscon@180 { compatible = "brcm,cru-clkset", "syscon"; reg = <0x180 0x4>; }; -- cgit v1.2.3 From 3297481d688a5cc2973ea58bd78e66b8639748b1 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 26 Oct 2021 12:03:48 +0200 Subject: futex: Remove futex_cmpxchg detection Now that all architectures have a working futex implementation in any configuration, remove the runtime detection code. Signed-off-by: Arnd Bergmann Signed-off-by: Thomas Gleixner Reviewed-by: Russell King (Oracle) Acked-by: Vineet Gupta Acked-by: Max Filippov Acked-by: Christian Borntraeger Link: https://lore.kernel.org/r/20211026100432.1730393-2-arnd@kernel.org --- arch/arc/Kconfig | 1 - arch/arm/Kconfig | 1 - arch/arm64/Kconfig | 1 - arch/csky/Kconfig | 1 - arch/m68k/Kconfig | 1 - arch/riscv/Kconfig | 1 - arch/s390/Kconfig | 1 - arch/sh/Kconfig | 1 - arch/um/Kconfig | 1 - arch/um/kernel/skas/uaccess.c | 1 - arch/xtensa/Kconfig | 1 - init/Kconfig | 8 -------- kernel/futex/core.c | 35 ----------------------------------- kernel/futex/futex.h | 6 ------ kernel/futex/syscalls.c | 22 ---------------------- 15 files changed, 82 deletions(-) (limited to 'arch/arm') diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index b4ae6058902a..f74d9860a442 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -32,7 +32,6 @@ config ARC select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4 select HAVE_DEBUG_STACKOVERFLOW select HAVE_DEBUG_KMEMLEAK - select HAVE_FUTEX_CMPXCHG if FUTEX select HAVE_IOREMAP_PROT select HAVE_KERNEL_GZIP select HAVE_KERNEL_LZMA diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0f9e8bec83a..2948487346dc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -92,7 +92,6 @@ config ARM select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG select HAVE_FUNCTION_TRACER if !XIP_KERNEL && !(THUMB2_KERNEL && CC_IS_CLANG) - select HAVE_FUTEX_CMPXCHG if FUTEX select HAVE_GCC_PLUGINS select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) select HAVE_IRQ_TIME_ACCOUNTING diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c4207cf9bb17..5e2dfef78956 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -194,7 +194,6 @@ config ARM64 select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_POSIX_CPU_TIMERS_TASK_WORK select HAVE_FUNCTION_ARG_ACCESS_API - select HAVE_FUTEX_CMPXCHG if FUTEX select MMU_GATHER_RCU_TABLE_FREE select HAVE_RSEQ select HAVE_STACKPROTECTOR diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig index aed2b3e734ee..132f43f12dd8 100644 --- a/arch/csky/Kconfig +++ b/arch/csky/Kconfig @@ -52,7 +52,6 @@ config CSKY select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FUNCTION_ERROR_INJECTION - select HAVE_FUTEX_CMPXCHG if FUTEX && SMP select HAVE_FTRACE_MCOUNT_RECORD select HAVE_KERNEL_GZIP select HAVE_KERNEL_LZO diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 0b50da08a9c5..15a793c5b2dc 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -20,7 +20,6 @@ config M68K select HAVE_ASM_MODVERSIONS select HAVE_DEBUG_BUGVERBOSE select HAVE_EFFICIENT_UNALIGNED_ACCESS if !CPU_HAS_NO_UNALIGNED - select HAVE_FUTEX_CMPXCHG if MMU && FUTEX select HAVE_MOD_ARCH_SPECIFIC select HAVE_UID16 select MMU_GATHER_NO_RANGE if MMU diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 821252b65f89..09abf62ae0ad 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -83,7 +83,6 @@ config RISCV select HAVE_DMA_CONTIGUOUS if MMU select HAVE_EBPF_JIT if MMU select HAVE_FUNCTION_ERROR_INJECTION - select HAVE_FUTEX_CMPXCHG if FUTEX select HAVE_GCC_PLUGINS select HAVE_GENERIC_VDSO if MMU && 64BIT select HAVE_IRQ_TIME_ACCOUNTING diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 8857ec3b97eb..f614562d74f0 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -165,7 +165,6 @@ config S390 select HAVE_FUNCTION_ERROR_INJECTION select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FUNCTION_TRACER - select HAVE_FUTEX_CMPXCHG if FUTEX select HAVE_GCC_PLUGINS select HAVE_GENERIC_VDSO select HAVE_IOREMAP_PROT if PCI diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 70afb30e0b32..2474a04ceac4 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -34,7 +34,6 @@ config SUPERH select HAVE_FAST_GUP if MMU select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FUNCTION_TRACER - select HAVE_FUTEX_CMPXCHG if FUTEX select HAVE_FTRACE_MCOUNT_RECORD select HAVE_HW_BREAKPOINT select HAVE_IOREMAP_PROT if MMU && !X2TLB diff --git a/arch/um/Kconfig b/arch/um/Kconfig index c18b45f75d41..c906250d4970 100644 --- a/arch/um/Kconfig +++ b/arch/um/Kconfig @@ -14,7 +14,6 @@ config UML select HAVE_ARCH_SECCOMP_FILTER select HAVE_ASM_MODVERSIONS select HAVE_UID16 - select HAVE_FUTEX_CMPXCHG if FUTEX select HAVE_DEBUG_KMEMLEAK select HAVE_DEBUG_BUGVERBOSE select NO_DMA if !UML_DMA_EMULATION diff --git a/arch/um/kernel/skas/uaccess.c b/arch/um/kernel/skas/uaccess.c index a509be911026..9e37a7c05990 100644 --- a/arch/um/kernel/skas/uaccess.c +++ b/arch/um/kernel/skas/uaccess.c @@ -348,7 +348,6 @@ EXPORT_SYMBOL(arch_futex_atomic_op_inuser); * 0 - On success * -EFAULT - User access resulted in a page fault * -EAGAIN - Atomic operation was unable to complete due to contention - * -ENOSYS - Function not implemented (only if !HAVE_FUTEX_CMPXCHG) */ int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 0e56bad058fa..8ac599aa6d99 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -31,7 +31,6 @@ config XTENSA select HAVE_DMA_CONTIGUOUS select HAVE_EXIT_THREAD select HAVE_FUNCTION_TRACER - select HAVE_FUTEX_CMPXCHG if !MMU && FUTEX select HAVE_HW_BREAKPOINT if PERF_EVENTS select HAVE_IRQ_TIME_ACCOUNTING select HAVE_PCI diff --git a/init/Kconfig b/init/Kconfig index 3f5aa5063f55..76d89db5657b 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -1592,14 +1592,6 @@ config FUTEX_PI depends on FUTEX && RT_MUTEXES default y -config HAVE_FUTEX_CMPXCHG - bool - depends on FUTEX - help - Architectures should select this if futex_atomic_cmpxchg_inatomic() - is implemented and always working. This removes a couple of runtime - checks. - config EPOLL bool "Enable eventpoll support" if EXPERT default y diff --git a/kernel/futex/core.c b/kernel/futex/core.c index 25d8a88b32e5..926c2bb752bc 100644 --- a/kernel/futex/core.c +++ b/kernel/futex/core.c @@ -41,11 +41,6 @@ #include "futex.h" #include "../locking/rtmutex_common.h" -#ifndef CONFIG_HAVE_FUTEX_CMPXCHG -int __read_mostly futex_cmpxchg_enabled; -#endif - - /* * The base of the bucket array and its size are always used together * (after initialization only in futex_hash()), so ensure that they @@ -776,9 +771,6 @@ static void exit_robust_list(struct task_struct *curr) unsigned long futex_offset; int rc; - if (!futex_cmpxchg_enabled) - return; - /* * Fetch the list head (which was registered earlier, via * sys_set_robust_list()): @@ -874,9 +866,6 @@ static void compat_exit_robust_list(struct task_struct *curr) compat_long_t futex_offset; int rc; - if (!futex_cmpxchg_enabled) - return; - /* * Fetch the list head (which was registered earlier, via * sys_set_robust_list()): @@ -950,8 +939,6 @@ static void exit_pi_state_list(struct task_struct *curr) struct futex_hash_bucket *hb; union futex_key key = FUTEX_KEY_INIT; - if (!futex_cmpxchg_enabled) - return; /* * We are a ZOMBIE and nobody can enqueue itself on * pi_state_list anymore, but we have to be careful @@ -1125,26 +1112,6 @@ void futex_exit_release(struct task_struct *tsk) futex_cleanup_end(tsk, FUTEX_STATE_DEAD); } -static void __init futex_detect_cmpxchg(void) -{ -#ifndef CONFIG_HAVE_FUTEX_CMPXCHG - u32 curval; - - /* - * This will fail and we want it. Some arch implementations do - * runtime detection of the futex_atomic_cmpxchg_inatomic() - * functionality. We want to know that before we call in any - * of the complex code paths. Also we want to prevent - * registration of robust lists in that case. NULL is - * guaranteed to fault and we get -EFAULT on functional - * implementation, the non-functional ones will return - * -ENOSYS. - */ - if (futex_cmpxchg_value_locked(&curval, NULL, 0, 0) == -EFAULT) - futex_cmpxchg_enabled = 1; -#endif -} - static int __init futex_init(void) { unsigned int futex_shift; @@ -1163,8 +1130,6 @@ static int __init futex_init(void) futex_hashsize, futex_hashsize); futex_hashsize = 1UL << futex_shift; - futex_detect_cmpxchg(); - for (i = 0; i < futex_hashsize; i++) { atomic_set(&futex_queues[i].waiters, 0); plist_head_init(&futex_queues[i].chain); diff --git a/kernel/futex/futex.h b/kernel/futex/futex.h index 040ae4277cb0..c264cbeab71c 100644 --- a/kernel/futex/futex.h +++ b/kernel/futex/futex.h @@ -27,12 +27,6 @@ #define FLAGS_CLOCKRT 0x02 #define FLAGS_HAS_TIMEOUT 0x04 -#ifdef CONFIG_HAVE_FUTEX_CMPXCHG -#define futex_cmpxchg_enabled 1 -#else -extern int __read_mostly futex_cmpxchg_enabled; -#endif - #ifdef CONFIG_FAIL_FUTEX extern bool should_fail_futex(bool fshared); #else diff --git a/kernel/futex/syscalls.c b/kernel/futex/syscalls.c index 6f91a07a6a83..086a22d1adb7 100644 --- a/kernel/futex/syscalls.c +++ b/kernel/futex/syscalls.c @@ -29,8 +29,6 @@ SYSCALL_DEFINE2(set_robust_list, struct robust_list_head __user *, head, size_t, len) { - if (!futex_cmpxchg_enabled) - return -ENOSYS; /* * The kernel knows only one size for now: */ @@ -56,9 +54,6 @@ SYSCALL_DEFINE3(get_robust_list, int, pid, unsigned long ret; struct task_struct *p; - if (!futex_cmpxchg_enabled) - return -ENOSYS; - rcu_read_lock(); ret = -ESRCH; @@ -103,17 +98,6 @@ long do_futex(u32 __user *uaddr, int op, u32 val, ktime_t *timeout, return -ENOSYS; } - switch (cmd) { - case FUTEX_LOCK_PI: - case FUTEX_LOCK_PI2: - case FUTEX_UNLOCK_PI: - case FUTEX_TRYLOCK_PI: - case FUTEX_WAIT_REQUEUE_PI: - case FUTEX_CMP_REQUEUE_PI: - if (!futex_cmpxchg_enabled) - return -ENOSYS; - } - switch (cmd) { case FUTEX_WAIT: val3 = FUTEX_BITSET_MATCH_ANY; @@ -323,9 +307,6 @@ COMPAT_SYSCALL_DEFINE2(set_robust_list, struct compat_robust_list_head __user *, head, compat_size_t, len) { - if (!futex_cmpxchg_enabled) - return -ENOSYS; - if (unlikely(len != sizeof(*head))) return -EINVAL; @@ -342,9 +323,6 @@ COMPAT_SYSCALL_DEFINE3(get_robust_list, int, pid, unsigned long ret; struct task_struct *p; - if (!futex_cmpxchg_enabled) - return -ENOSYS; - rcu_read_lock(); ret = -ESRCH; -- cgit v1.2.3 From b046049e59dca5e5830dc75ed16acf7657a95161 Mon Sep 17 00:00:00 2001 From: Dillon Min Date: Sat, 24 Jul 2021 11:44:02 +0800 Subject: ARM: dts: stm32: fix dtbs_check warning on ili9341 dts binding on stm32f429 disco Since the compatible string defined from ilitek,ili9341.yaml is "st,sf-tc240t-9370-t", "ilitek,ili9341" so, append "ilitek,ili9341" to avoid the below dtbs_check warning. arch/arm/boot/dts/stm32f429-disco.dt.yaml: display@1: compatible: ['st,sf-tc240t-9370-t'] is too short Fixes: a726e2f000ec ("ARM: dts: stm32: enable ltdc binding with ili9341, gyro l3gd20 on stm32429-disco board") Signed-off-by: Dillon Min Reported-by: kernel test robot Reviewed-by: Linus Walleij Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429-disco.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 075ac57d0bf4..6435e099c632 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -192,7 +192,7 @@ display: display@1{ /* Connect panel-ilitek-9341 to ltdc */ - compatible = "st,sf-tc240t-9370-t"; + compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341"; reg = <1>; spi-3wire; spi-max-frequency = <10000000>; -- cgit v1.2.3 From 958b18a404152a982b511bc251768ca969a87630 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Wed, 20 Oct 2021 17:03:11 +0200 Subject: ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins on STM32MP15 DKx boards Add pull-up to USART3 and UART7 RX pins to allow loop tests between USART3 and UART7 on stm32mp15 DKx boards. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 2ebafe27a865..1c413a04ba9c 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1816,7 +1816,7 @@ }; pins2 { pinmux = ; /* UART7_RX */ - bias-disable; + bias-pull-up; }; }; @@ -1826,7 +1826,7 @@ }; pins2 { pinmux = ; /* UART7_RX */ - bias-disable; + bias-pull-up; }; }; @@ -1971,7 +1971,7 @@ pins2 { pinmux = , /* USART3_RX */ ; /* USART3_CTS_NSS */ - bias-disable; + bias-pull-up; }; }; @@ -1988,7 +1988,7 @@ }; pins3 { pinmux = ; /* USART3_RX */ - bias-disable; + bias-pull-up; }; }; @@ -2012,7 +2012,7 @@ pins2 { pinmux = , /* USART3_RX */ ; /* USART3_CTS_NSS */ - bias-disable; + bias-pull-up; }; }; @@ -2029,7 +2029,7 @@ }; pins3 { pinmux = ; /* USART3_RX */ - bias-disable; + bias-pull-up; }; }; -- cgit v1.2.3 From a2368f89660728284b749cc14537d7628e3fc318 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Wed, 20 Oct 2021 17:02:30 +0200 Subject: ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15 Clean useless spaces in uart4_idle_pins_a node. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 1c413a04ba9c..5f060feaf639 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1737,20 +1737,20 @@ }; uart4_idle_pins_a: uart4-idle-0 { - pins1 { - pinmux = ; /* UART4_TX */ - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; }; uart4_sleep_pins_a: uart4-sleep-0 { - pins { + pins { pinmux = , /* UART4_TX */ ; /* UART4_RX */ - }; + }; }; uart4_pins_b: uart4-1 { -- cgit v1.2.3 From 2312a6e7b301f43f02fb30b1dee932df5a87a7d0 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 25 Oct 2021 17:17:49 +0200 Subject: ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx This patch adds phy tuning parameters for usbphyc port0 (USBH controller) and usbphyc port1 (OTG controller). Phy tuning parameters are used to adjust the phy settings to compensate parasitics, which can be due to USB receptacle, routing, and ESD protection component. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 48beed0f1f30..6caeb448c190 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -694,10 +694,26 @@ &usbphyc_port0 { phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; }; &usbphyc_port1 { phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; }; &vrefbuf { -- cgit v1.2.3 From 28f645fc9424bf455528cb92bd6a7120281bca45 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Mon, 25 Oct 2021 17:17:50 +0200 Subject: ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1 This patch adds phy tuning parameters for usbphyc port0 (USBH controller) and usbphyc port1 (OTG controller). Phy tuning parameters are used to adjust the phy settings to compensate parasitics, which can be due to USB receptacle, routing, and ESD protection component. Signed-off-by: Amelie Delaunay Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 5c5b1ddf7bfd..e222d2d2cb44 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -375,3 +375,25 @@ &usbphyc { status = "okay"; }; + +&usbphyc_port0 { + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; -- cgit v1.2.3 From 635e4172bd0a43af943fb164799965fc9a9a705d Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Tue, 2 Nov 2021 07:38:10 +0100 Subject: arm: remove zte zx platform left-over Commit 89d4f98ae90d ("ARM: remove zte zx platform") missed to remove some definitions for this platform's debug and serial, e.g., code dependent on the config DEBUG_ZTE_ZX. Fortunately, ./scripts/checkkconfigsymbols.py detects this and warns: DEBUG_ZTE_ZX Referencing files: arch/arm/include/debug/pl01x.S Further review by Arnd Bergmann identified even more dead code in the amba serial driver. Remove all this left-over from the zte zx platform. Reviewed-by: Arnd Bergmann Signed-off-by: Lukas Bulwahn Link: https://lore.kernel.org/r/20211102063810.932-1-lukas.bulwahn@gmail.com Signed-off-by: Greg Kroah-Hartman --- arch/arm/include/debug/pl01x.S | 7 ------- drivers/tty/serial/amba-pl011.c | 37 ------------------------------------- include/linux/amba/bus.h | 6 ------ 3 files changed, 50 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/debug/pl01x.S b/arch/arm/include/debug/pl01x.S index 0c7bfa4c10db..c7e02d0628bf 100644 --- a/arch/arm/include/debug/pl01x.S +++ b/arch/arm/include/debug/pl01x.S @@ -8,13 +8,6 @@ */ #include -#ifdef CONFIG_DEBUG_ZTE_ZX -#undef UART01x_DR -#undef UART01x_FR -#define UART01x_DR 0x04 -#define UART01x_FR 0x14 -#endif - #ifdef CONFIG_DEBUG_UART_PHYS .macro addruart, rp, rv, tmp ldr \rp, =CONFIG_DEBUG_UART_PHYS diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index d361cd84ff8c..c9534e229166 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -188,38 +188,6 @@ static struct vendor_data vendor_st = { .get_fifosize = get_fifosize_st, }; -static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = { - [REG_DR] = ZX_UART011_DR, - [REG_FR] = ZX_UART011_FR, - [REG_LCRH_RX] = ZX_UART011_LCRH, - [REG_LCRH_TX] = ZX_UART011_LCRH, - [REG_IBRD] = ZX_UART011_IBRD, - [REG_FBRD] = ZX_UART011_FBRD, - [REG_CR] = ZX_UART011_CR, - [REG_IFLS] = ZX_UART011_IFLS, - [REG_IMSC] = ZX_UART011_IMSC, - [REG_RIS] = ZX_UART011_RIS, - [REG_MIS] = ZX_UART011_MIS, - [REG_ICR] = ZX_UART011_ICR, - [REG_DMACR] = ZX_UART011_DMACR, -}; - -static unsigned int get_fifosize_zte(struct amba_device *dev) -{ - return 16; -} - -static struct vendor_data vendor_zte = { - .reg_offset = pl011_zte_offsets, - .access_32b = true, - .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, - .fr_busy = ZX_UART01x_FR_BUSY, - .fr_dsr = ZX_UART01x_FR_DSR, - .fr_cts = ZX_UART01x_FR_CTS, - .fr_ri = ZX_UART011_FR_RI, - .get_fifosize = get_fifosize_zte, -}; - /* Deals with DMA transactions */ struct pl011_sgbuf { @@ -2974,11 +2942,6 @@ static const struct amba_id pl011_ids[] = { .mask = 0x00ffffff, .data = &vendor_st, }, - { - .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe), - .mask = 0x00ffffff, - .data = &vendor_zte, - }, { 0, 0 }, }; diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index edfcf7a14dcd..6c7f47846971 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -90,14 +90,8 @@ enum amba_vendor { AMBA_VENDOR_ST = 0x80, AMBA_VENDOR_QCOM = 0x51, AMBA_VENDOR_LSI = 0xb6, - AMBA_VENDOR_LINUX = 0xfe, /* This value is not official */ }; -/* This is used to generate pseudo-ID for AMBA device */ -#define AMBA_LINUX_ID(conf, rev, part) \ - (((conf) & 0xff) << 24 | ((rev) & 0xf) << 20 | \ - AMBA_VENDOR_LINUX << 12 | ((part) & 0xfff)) - extern struct bus_type amba_bustype; #define to_amba_device(d) container_of(d, struct amba_device, dev) -- cgit v1.2.3 From 342e3ce0f6f4691b31b1c7c9c3ae37160c4a82d2 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 23 Nov 2021 21:27:21 +0200 Subject: ARM: pxa/lubbock: Replace custom ->cs_control() by GPIO lookup table SPI PXA2xx driver supports GPIO chipselect by querying for known GPIO connection ID. Replace custom ->cs_control() by GPIO table, so the driver will use generic approach on this platform. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211123192723.44537-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown --- arch/arm/mach-pxa/lubbock.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 742d18a1f7dc..e2411971422d 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -211,16 +211,17 @@ static struct ads7846_platform_data ads_info = { // .y_plate_ohms = 500, /* GUESS! */ }; -static void ads7846_cs(u32 command) -{ - static const unsigned TS_nCS = 1 << 11; - lubbock_set_misc_wr(TS_nCS, (command == PXA2XX_CS_ASSERT) ? 0 : TS_nCS); -} +static struct gpiod_lookup_table ads7846_cs_gpios = { + .dev_id = "ads7846", + .table = { + GPIO_LOOKUP("lubbock", 11, "cs", GPIO_ACTIVE_LOW), + {} + }, +}; static struct pxa2xx_spi_chip ads_hw = { .tx_threshold = 1, .rx_threshold = 2, - .cs_control = ads7846_cs, }; static struct spi_board_info spi_board_info[] __initdata = { { @@ -512,6 +513,8 @@ static void __init lubbock_init(void) lubbock_flash_data[flashboot].name = "boot-rom"; (void) platform_add_devices(devices, ARRAY_SIZE(devices)); + gpiod_add_lookup_table(&ads7846_cs_gpios); + pxa2xx_set_spi_info(1, &pxa_ssp_master_info); spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); } -- cgit v1.2.3 From a9c8f68ce2c37ced2f7a8667eda71b7753ede398 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 23 Nov 2021 21:27:22 +0200 Subject: spi: pxa2xx: Get rid of unused ->cs_control() Since the last user of the custom ->cs_control() gone, we may get rid of this legacy API completely. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211123192723.44537-2-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown --- Documentation/spi/pxa2xx.rst | 29 +++-------------------------- arch/arm/mach-pxa/stargate2.c | 2 +- drivers/spi/spi-pxa2xx.c | 18 ------------------ drivers/spi/spi-pxa2xx.h | 3 --- include/linux/spi/pxa2xx_spi.h | 4 ---- 5 files changed, 4 insertions(+), 52 deletions(-) (limited to 'arch/arm') diff --git a/Documentation/spi/pxa2xx.rst b/Documentation/spi/pxa2xx.rst index 6312968acfe9..dfc7673ed15d 100644 --- a/Documentation/spi/pxa2xx.rst +++ b/Documentation/spi/pxa2xx.rst @@ -102,7 +102,7 @@ device. All fields are optional. u8 dma_burst_size; u32 timeout; u8 enable_loopback; - void (*cs_control)(u32 command); + int gpio_cs; }; The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are @@ -133,11 +133,6 @@ into internal loopback mode. In this mode the SSP controller internally connects the SSPTX pin to the SSPRX pin. This is useful for initial setup testing. -The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific -function for asserting/deasserting a slave device chip select. If the field is -NULL, the pxa2xx_spi master controller driver assumes that the SSP port is -configured to use GPIO or SSPFRM instead. - NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the chipselect is dropped after each spi_transfer. Most devices need chip select asserted around the complete message. Use SSPFRM as a GPIO (through a descriptor) @@ -152,30 +147,12 @@ field. Below is a sample configuration using the PXA255 NSSP. :: - /* Chip Select control for the CS8415A SPI slave device */ - static void cs8415a_cs_control(u32 command) - { - if (command & PXA2XX_CS_ASSERT) - GPCR(2) = GPIO_bit(2); - else - GPSR(2) = GPIO_bit(2); - } - - /* Chip Select control for the CS8405A SPI slave device */ - static void cs8405a_cs_control(u32 command) - { - if (command & PXA2XX_CS_ASSERT) - GPCR(3) = GPIO_bit(3); - else - GPSR(3) = GPIO_bit(3); - } - static struct pxa2xx_spi_chip cs8415a_chip_info = { .tx_threshold = 8, /* SSP hardward FIFO threshold */ .rx_threshold = 8, /* SSP hardward FIFO threshold */ .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ .timeout = 235, /* See Intel documentation */ - .cs_control = cs8415a_cs_control, /* Use external chip select */ + .gpio_cs = 2, /* Use external chip select */ }; static struct pxa2xx_spi_chip cs8405a_chip_info = { @@ -183,7 +160,7 @@ field. Below is a sample configuration using the PXA255 NSSP. .rx_threshold = 8, /* SSP hardward FIFO threshold */ .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ .timeout = 235, /* See Intel documentation */ - .cs_control = cs8405a_cs_control, /* Use external chip select */ + .gpio_cs = 3, /* Use external chip select */ }; static struct spi_board_info streetracer_spi_board_info[] __initdata = { diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 7ad627465768..8ca02ec1d44c 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -347,7 +347,7 @@ static struct pxa2xx_spi_controller pxa_ssp_master_2_info = { }; /* An upcoming kernel change will scrap SFRM usage so these - * drivers have been moved to use gpio's via cs_control */ + * drivers have been moved to use GPIOs */ static struct pxa2xx_spi_chip staccel_chip_info = { .tx_threshold = 8, .rx_threshold = 8, diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index ee3297dd532e..24196156c609 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -427,7 +427,6 @@ static void lpss_ssp_cs_control(struct spi_device *spi, bool enable) static void cs_assert(struct spi_device *spi) { - struct chip_data *chip = spi_get_ctldata(spi); struct driver_data *drv_data = spi_controller_get_devdata(spi->controller); @@ -436,18 +435,12 @@ static void cs_assert(struct spi_device *spi) return; } - if (chip->cs_control) { - chip->cs_control(PXA2XX_CS_ASSERT); - return; - } - if (is_lpss_ssp(drv_data)) lpss_ssp_cs_control(spi, true); } static void cs_deassert(struct spi_device *spi) { - struct chip_data *chip = spi_get_ctldata(spi); struct driver_data *drv_data = spi_controller_get_devdata(spi->controller); unsigned long timeout; @@ -461,11 +454,6 @@ static void cs_deassert(struct spi_device *spi) !time_after(jiffies, timeout)) cpu_relax(); - if (chip->cs_control) { - chip->cs_control(PXA2XX_CS_DEASSERT); - return; - } - if (is_lpss_ssp(drv_data)) lpss_ssp_cs_control(spi, false); } @@ -1204,12 +1192,6 @@ static int setup_cs(struct spi_device *spi, struct chip_data *chip, */ cleanup_cs(spi); - /* If ->cs_control() is provided, ignore GPIO chip select */ - if (chip_info->cs_control) { - chip->cs_control = chip_info->cs_control; - return 0; - } - if (gpio_is_valid(chip_info->gpio_cs)) { int gpio = chip_info->gpio_cs; int err; diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h index 4d77f4de6eda..45cdbbc71c4b 100644 --- a/drivers/spi/spi-pxa2xx.h +++ b/drivers/spi/spi-pxa2xx.h @@ -49,7 +49,6 @@ struct driver_data { int (*write)(struct driver_data *drv_data); int (*read)(struct driver_data *drv_data); irqreturn_t (*transfer_handler)(struct driver_data *drv_data); - void (*cs_control)(u32 command); void __iomem *lpss_base; @@ -67,8 +66,6 @@ struct chip_data { u32 threshold; u16 lpss_rx_threshold; u16 lpss_tx_threshold; - - void (*cs_control)(u32 command); }; static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg) diff --git a/include/linux/spi/pxa2xx_spi.h b/include/linux/spi/pxa2xx_spi.h index eaab121ee575..42e06bfbc2a4 100644 --- a/include/linux/spi/pxa2xx_spi.h +++ b/include/linux/spi/pxa2xx_spi.h @@ -9,9 +9,6 @@ #include -#define PXA2XX_CS_ASSERT (0x01) -#define PXA2XX_CS_DEASSERT (0x02) - struct dma_chan; /* @@ -47,7 +44,6 @@ struct pxa2xx_spi_chip { u32 timeout; u8 enable_loopback; int gpio_cs; - void (*cs_control)(u32 command); }; #if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP) -- cgit v1.2.3 From 1149ccc5e89145a344cfdd8832d83bcc919dc1ed Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 26 Nov 2021 12:33:40 +0100 Subject: ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk A pinctrl handle is used to setup a pull-up on the stusb1600 IRQ pin (that is open drain). When in ANALOG state, no pull-up can be applied in the GPIO HW controller, still the setting is done into the register. The pull-up is effective currently, only when the GPIO IRQ is requested. The correct setting is to use directly the GPIO, instead of ANALOG state. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 5f060feaf639..3b65130affec 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1718,7 +1718,7 @@ stusb1600_pins_a: stusb1600-0 { pins { - pinmux = ; + pinmux = ; bias-pull-up; }; }; -- cgit v1.2.3 From bc02973a06a6c74374edeb6d73ed4bde99b37456 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 24 Nov 2021 16:41:12 +0100 Subject: arm: ioremap: Implement standard PCI function pci_remap_iospace() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit pci_remap_iospace() is standard PCI core function. Architecture code can reimplement default core implementation if needs custom arch specific functionality. ARM needs custom implementation due to pci_ioremap_set_mem_type() hook which allows ARM platforms to change mem type for iospace. Implement this pci_remap_iospace() function for ARM architecture to correctly handle pci_ioremap_set_mem_type() hook, which allows usage of this standard PCI core function also for platforms which needs different mem type (e.g. Marvell Armada 375, 38x and 39x). Link: https://lore.kernel.org/r/20211124154116.916-2-pali@kernel.org Signed-off-by: Pali Rohár Signed-off-by: Lorenzo Pieralisi Reviewed-by: Russell King (Oracle) --- arch/arm/include/asm/io.h | 5 +++++ arch/arm/mm/ioremap.c | 15 +++++++++++++++ 2 files changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index c576fa7d9bf8..12eca75bdee9 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -182,6 +182,11 @@ static inline void pci_ioremap_set_mem_type(int mem_type) {} extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); +struct resource; + +#define pci_remap_iospace pci_remap_iospace +int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); + /* * PCI configuration space mapping function. * diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 6e830b9418c9..fa3bde48d6a7 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -459,6 +459,21 @@ void pci_ioremap_set_mem_type(int mem_type) pci_ioremap_mem_type = mem_type; } +int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) +{ + unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; + + if (!(res->flags & IORESOURCE_IO)) + return -EINVAL; + + if (res->end > IO_SPACE_LIMIT) + return -EINVAL; + + return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, + __pgprot(get_mem_type(pci_ioremap_mem_type)->prot_pte)); +} +EXPORT_SYMBOL(pci_remap_iospace); + int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr) { BUG_ON(offset + SZ_64K - 1 > IO_SPACE_LIMIT); -- cgit v1.2.3 From 06edc59c1fd7aababc8361655b20f4cc9870aef2 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 19 Nov 2021 17:32:13 +0100 Subject: bpf, docs: Prune all references to "internal BPF" The eBPF name has completely taken over from eBPF in general usage for the actual eBPF representation, or BPF for any general in-kernel use. Prune all remaining references to "internal BPF". Signed-off-by: Christoph Hellwig Signed-off-by: Alexei Starovoitov Acked-by: Song Liu Link: https://lore.kernel.org/bpf/20211119163215.971383-4-hch@lst.de --- Documentation/networking/filter.rst | 22 +++++++++++----------- arch/arm/net/bpf_jit_32.c | 2 +- arch/arm64/net/bpf_jit_comp.c | 2 +- arch/sparc/net/bpf_jit_comp_64.c | 2 +- kernel/bpf/core.c | 2 +- net/core/filter.c | 11 +++++------ 6 files changed, 20 insertions(+), 21 deletions(-) (limited to 'arch/arm') diff --git a/Documentation/networking/filter.rst b/Documentation/networking/filter.rst index ce2b8e8bb9ab..83ffcaa5b91a 100644 --- a/Documentation/networking/filter.rst +++ b/Documentation/networking/filter.rst @@ -617,7 +617,7 @@ format with similar underlying principles from BPF described in previous paragraphs is being used. However, the instruction set format is modelled closer to the underlying architecture to mimic native instruction sets, so that a better performance can be achieved (more details later). This new -ISA is called 'eBPF' or 'internal BPF' interchangeably. (Note: eBPF which +ISA is called 'eBPF'. (Note: eBPF which originates from [e]xtended BPF is not the same as BPF extensions! While eBPF is an ISA, BPF extensions date back to classic BPF's 'overloading' of BPF_LD | BPF_{B,H,W} | BPF_ABS instruction.) @@ -690,7 +690,7 @@ Some core changes of the new internal format: That behavior maps directly to x86_64 and arm64 subregister definition, but makes other JITs more difficult. - 32-bit architectures run 64-bit internal BPF programs via interpreter. + 32-bit architectures run 64-bit eBPF programs via interpreter. Their JITs may convert BPF programs that only use 32-bit subregisters into native instruction set and let the rest being interpreted. @@ -711,7 +711,7 @@ Some core changes of the new internal format: - Introduces bpf_call insn and register passing convention for zero overhead calls from/to other kernel functions: - Before an in-kernel function call, the internal BPF program needs to + Before an in-kernel function call, the eBPF program needs to place function arguments into R1 to R5 registers to satisfy calling convention, then the interpreter will take them from registers and pass to in-kernel function. If R1 - R5 registers are mapped to CPU registers @@ -780,7 +780,7 @@ Some core changes of the new internal format: ... since x86_64 ABI mandates rdi, rsi, rdx, rcx, r8, r9 for argument passing and rbx, r12 - r15 are callee saved. - Then the following internal BPF pseudo-program:: + Then the following eBPF pseudo-program:: bpf_mov R6, R1 /* save ctx */ bpf_mov R2, 2 @@ -846,7 +846,7 @@ Some core changes of the new internal format: bpf_exit After the call the registers R1-R5 contain junk values and cannot be read. - An in-kernel eBPF verifier is used to validate internal BPF programs. + An in-kernel eBPF verifier is used to validate eBPF programs. Also in the new design, eBPF is limited to 4096 insns, which means that any program will terminate quickly and will only call a fixed number of kernel @@ -861,23 +861,23 @@ A program, that is translated internally consists of the following elements:: op:16, jt:8, jf:8, k:32 ==> op:8, dst_reg:4, src_reg:4, off:16, imm:32 -So far 87 internal BPF instructions were implemented. 8-bit 'op' opcode field +So far 87 eBPF instructions were implemented. 8-bit 'op' opcode field has room for new instructions. Some of them may use 16/24/32 byte encoding. New instructions must be multiple of 8 bytes to preserve backward compatibility. -Internal BPF is a general purpose RISC instruction set. Not every register and +eBPF is a general purpose RISC instruction set. Not every register and every instruction are used during translation from original BPF to new format. For example, socket filters are not using ``exclusive add`` instruction, but tracing filters may do to maintain counters of events, for example. Register R9 is not used by socket filters either, but more complex filters may be running out of registers and would have to resort to spill/fill to stack. -Internal BPF can be used as a generic assembler for last step performance +eBPF can be used as a generic assembler for last step performance optimizations, socket filters and seccomp are using it as assembler. Tracing filters may use it as assembler to generate code from kernel. In kernel usage -may not be bounded by security considerations, since generated internal BPF code +may not be bounded by security considerations, since generated eBPF code may be optimizing internal code path and not being exposed to the user space. -Safety of internal BPF can come from a verifier (TBD). In such use cases as +Safety of eBPF can come from a verifier (TBD). In such use cases as described, it may be used as safe instruction set. Just like the original BPF, the new format runs within a controlled environment, @@ -1675,7 +1675,7 @@ Testing ------- Next to the BPF toolchain, the kernel also ships a test module that contains -various test cases for classic and internal BPF that can be executed against +various test cases for classic and eBPF that can be executed against the BPF interpreter and JIT compiler. It can be found in lib/test_bpf.c and enabled via Kconfig:: diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c index e59b41e9ab0c..10ceebb7530b 100644 --- a/arch/arm/net/bpf_jit_32.c +++ b/arch/arm/net/bpf_jit_32.c @@ -163,7 +163,7 @@ static const s8 bpf2a32[][2] = { [BPF_REG_9] = {STACK_OFFSET(BPF_R9_HI), STACK_OFFSET(BPF_R9_LO)}, /* Read only Frame Pointer to access Stack */ [BPF_REG_FP] = {STACK_OFFSET(BPF_FP_HI), STACK_OFFSET(BPF_FP_LO)}, - /* Temporary Register for internal BPF JIT, can be used + /* Temporary Register for BPF JIT, can be used * for constant blindings and others. */ [TMP_REG_1] = {ARM_R7, ARM_R6}, diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index 07c12c42b751..07aad85848fa 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -44,7 +44,7 @@ static const int bpf2a64[] = { [BPF_REG_9] = A64_R(22), /* read-only frame pointer to access stack */ [BPF_REG_FP] = A64_R(25), - /* temporary registers for internal BPF JIT */ + /* temporary registers for BPF JIT */ [TMP_REG_1] = A64_R(10), [TMP_REG_2] = A64_R(11), [TMP_REG_3] = A64_R(12), diff --git a/arch/sparc/net/bpf_jit_comp_64.c b/arch/sparc/net/bpf_jit_comp_64.c index 0bfe1c72a0c9..b1e38784eb23 100644 --- a/arch/sparc/net/bpf_jit_comp_64.c +++ b/arch/sparc/net/bpf_jit_comp_64.c @@ -227,7 +227,7 @@ static const int bpf2sparc[] = { [BPF_REG_AX] = G7, - /* temporary register for internal BPF JIT */ + /* temporary register for BPF JIT */ [TMP_REG_1] = G1, [TMP_REG_2] = G2, [TMP_REG_3] = G3, diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c index 189d85d64bf1..de3e5bc6781f 100644 --- a/kernel/bpf/core.c +++ b/kernel/bpf/core.c @@ -1892,7 +1892,7 @@ static void bpf_prog_select_func(struct bpf_prog *fp) /** * bpf_prog_select_runtime - select exec runtime for BPF program - * @fp: bpf_prog populated with internal BPF program + * @fp: bpf_prog populated with BPF program * @err: pointer to error variable * * Try to JIT eBPF program, if JIT is not available, use interpreter. diff --git a/net/core/filter.c b/net/core/filter.c index 26e0276aa00d..fe27c91e3758 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -1242,10 +1242,9 @@ static struct bpf_prog *bpf_migrate_filter(struct bpf_prog *fp) int err, new_len, old_len = fp->len; bool seen_ld_abs = false; - /* We are free to overwrite insns et al right here as it - * won't be used at this point in time anymore internally - * after the migration to the internal BPF instruction - * representation. + /* We are free to overwrite insns et al right here as it won't be used at + * this point in time anymore internally after the migration to the eBPF + * instruction representation. */ BUILD_BUG_ON(sizeof(struct sock_filter) != sizeof(struct bpf_insn)); @@ -1336,8 +1335,8 @@ static struct bpf_prog *bpf_prepare_filter(struct bpf_prog *fp, */ bpf_jit_compile(fp); - /* JIT compiler couldn't process this filter, so do the - * internal BPF translation for the optimized interpreter. + /* JIT compiler couldn't process this filter, so do the eBPF translation + * for the optimized interpreter. */ if (!fp->jited) fp = bpf_migrate_filter(fp); -- cgit v1.2.3 From 050e22bfc4f450d342dbb7eaea470858ad567bce Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Mon, 29 Nov 2021 13:06:47 +0000 Subject: ARM: Snapshot thread flags Some thread flags can be set remotely, and so even when IRQs are disabled, the flags can change under our feet. Generally this is unlikely to cause a problem in practice, but it is somewhat unsound, and KCSAN will legitimately warn that there is a data race. To avoid such issues, a snapshot of the flags has to be taken prior to using them. Some places already use READ_ONCE() for that, others do not. Convert them all to the new flag accessor helpers. Signed-off-by: Mark Rutland Signed-off-by: Thomas Gleixner Acked-by: Paul E. McKenney Cc: Russell King Link: https://lore.kernel.org/r/20211129130653.2037928-6-mark.rutland@arm.com --- arch/arm/kernel/signal.c | 2 +- arch/arm/mm/alignment.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index a41e27ace391..c532a6041066 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -631,7 +631,7 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall) } } local_irq_disable(); - thread_flags = current_thread_info()->flags; + thread_flags = read_thread_flags(); } while (thread_flags & _TIF_WORK_MASK); return 0; } diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index ea81e89e7740..adbb3817d0be 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -990,7 +990,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) * there is no work pending for this thread. */ raw_local_irq_disable(); - if (!(current_thread_info()->flags & _TIF_WORK_MASK)) + if (!(read_thread_flags() & _TIF_WORK_MASK)) set_cr(cr_no_alignment); } -- cgit v1.2.3 From 254a27585eb135f35887579ebc7d0e02b9788b92 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:15 +0530 Subject: ARM: dts: qcom: sdx55: Add support for PCIe PHY Add devicetree support for PCIe PHY used in SDX55 platform. This PHY is used by the PCIe EP controller. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-2-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 44526ad9d210..16995782dfdf 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -309,6 +309,41 @@ status = "disabled"; }; + pcie0_phy: phy@1c07000 { + compatible = "qcom,sdx55-qmp-pcie-phy"; + reg = <0x01c07000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06000 { + reg = <0x01c06000 0x104>, /* tx0 */ + <0x01c06200 0x328>, /* rx0 */ + <0x01c07200 0x1e8>, /* pcs */ + <0x01c06800 0x104>, /* tx1 */ + <0x01c06a00 0x328>, /* rx1 */ + <0x01c07600 0x800>; /* pcs_misc */ + clocks = <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + }; + }; + ipa: ipa@1e40000 { compatible = "qcom,sdx55-ipa"; -- cgit v1.2.3 From a5a2661287b450f2b1f751ae7b4da4f39976571b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:16 +0530 Subject: ARM: dts: qcom: sdx55-fn980: Enable PCIE0 PHY Enable PCIE0 PHY on Telit FN980 TLB for PCIE EP. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-3-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index 80c40da79604..e8b5327afbe7 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -236,6 +236,13 @@ status = "ok"; }; +&pcie0_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1e_bb_1p2>; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; +}; + &qpic_bam { status = "ok"; }; -- cgit v1.2.3 From e6b69813283f9babc6892c1324d2c3bd2a577d9c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:17 +0530 Subject: ARM: dts: qcom: sdx55: Add support for PCIe EP Add support for PCIe Endpoint controller on the Qualcomm SDX55 platform. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-4-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 45 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 16995782dfdf..5d769b3f2d35 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -391,6 +392,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fcb000 { + compatible = "syscon"; + reg = <0x01fc0000 0x1000>; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; @@ -403,6 +409,45 @@ status = "disabled"; }; + pcie_ep: pcie-ep@40000000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40002000 0x10000>, + <0x01c03000 0x3000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie0_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; -- cgit v1.2.3 From 7cecfb53cad8e9f564fdf11e56502c7d8607b3a3 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:18 +0530 Subject: ARM: dts: qcom: sdx55-fn980: Enable PCIe EP Enable PCIe Endpoint controller on the Telit FN980 TLB board based on Qualcomm SDX55 platform. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-5-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 46 ++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index e8b5327afbe7..01ac91738f34 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -243,6 +243,14 @@ vdda-pll-supply = <&vreg_l4e_bb_0p875>; }; +&pcie_ep { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; +}; + &qpic_bam { status = "ok"; }; @@ -267,6 +275,44 @@ memory-region = <&mpss_adsp_mem>; }; +&tlmm { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + config { + pins = "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; +}; + &usb_hsphy { status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; -- cgit v1.2.3 From e1fb17ee85bc85808eeb103afa63581d065c7328 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:19 +0530 Subject: ARM: dts: qcom: sdx55-fn980: Enable IPA Enable IP Accelerator (IPA) on Telit FN980 TLB for getting data connectivity from modem. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-6-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index 01ac91738f34..a4fa468a095f 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -236,6 +236,12 @@ status = "ok"; }; +&ipa { + status = "okay"; + + memory-region = <&ipa_fw_mem>; +}; + &pcie0_phy { status = "okay"; -- cgit v1.2.3 From 1f7fe79d03b2ac0991c8a229ca50a9f45b71df80 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 26 Nov 2021 12:35:20 +0530 Subject: ARM: dts: qcom: sdx55-t55: Enable IPA Enable IP Accelerator (IPA) on Thundercomm T55 board for getting data connectivity from modem. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211126070520.28979-7-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index 2ffcd085904d..7ed8feb99afb 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -236,6 +236,12 @@ status = "ok"; }; +&ipa { + status = "okay"; + + memory-region = <&ipa_fw_mem>; +}; + &qpic_bam { status = "ok"; }; -- cgit v1.2.3 From 145988cff2a10ec8c720eccdcfc94748f497cd8d Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 29 Nov 2021 17:55:10 +0100 Subject: ARM: dts: sun8i: Adjust power key nodes Several H3 and one H2+ board have power key nodes, which are slightly off. Some are missing wakeup-source property and some have BTN_0 code assigned instead of KEY_POWER. Adjust them, so they can function as intended by designer. Co-developed-by: Michael Klein Signed-off-by: Michael Klein Signed-off-by: Jernej Skrabec Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211129165510.370717-1-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 3 ++- arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 1 + arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 3 ++- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 3 ++- arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 3 ++- arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi | 1 + 6 files changed, 10 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index 8e8634ff2f9d..d5c7b7984d85 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -52,8 +52,9 @@ sw4 { label = "power"; - linux,code = ; + linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index c7c3e7d8b3c8..fc45d5aaa67f 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -81,6 +81,7 @@ label = "k1"; linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 597c425d08ec..9daffd90c12f 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -99,8 +99,9 @@ sw4 { label = "sw4"; - linux,code = ; + linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index 5aff8ecc66cb..90f75fa85e68 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -91,8 +91,9 @@ sw4 { label = "sw4"; - linux,code = ; + linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; }; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi index 7a6af54dd342..d03f5853ef7b 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi @@ -82,8 +82,9 @@ sw4 { label = "power"; - linux,code = ; + linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi index c44fd726945a..9e14fe5fdcde 100644 --- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi +++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi @@ -49,6 +49,7 @@ label = "power"; linux,code = ; gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + wakeup-source; }; }; -- cgit v1.2.3 From e1ab4182ca113f9a14e3aefc15cf7652b8446991 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Mon, 29 Nov 2021 09:58:01 -0700 Subject: Revert "ARM: 9070/1: Make UNWINDER_ARM depend on ld.bfd or ld.lld 11.0.0+" This reverts commit 7411cfc3c91a08a884463bbc7623087ecc2efdd8. The minimum supported version of LLVM has been raised to 11.0.0, meaning this check is always true, so it can be dropped. Signed-off-by: Nathan Chancellor Reviewed-by: Miguel Ojeda Reviewed-by: Mark Brown Reviewed-by: Nick Desaulniers Reviewed-by: Kees Cook Signed-off-by: Masahiro Yamada --- arch/arm/Kconfig.debug | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 98436702e0c7..cd2d74b625c1 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -66,8 +66,6 @@ config UNWINDER_FRAME_POINTER config UNWINDER_ARM bool "ARM EABI stack unwinder" depends on AEABI && !FUNCTION_GRAPH_TRACER - # https://github.com/ClangBuiltLinux/linux/issues/732 - depends on !LD_IS_LLD || LLD_VERSION >= 110000 select ARM_UNWIND help This option enables stack unwinding support in the kernel -- cgit v1.2.3 From 2db0624b78c42abe1bcada7dd62068ef978e1e35 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 22 Nov 2021 11:19:17 +0100 Subject: ARM: dts: add JOZ Access Point JOZ Access Point is imx6ull based device designed for agricultural cleaning machines. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6ull-jozacp.dts | 456 +++++++++++++++++++++++++++++++++++ 2 files changed, 457 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-jozacp.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..9753faf0f1aa 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -688,6 +688,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-colibri-emmc-eval-v3.dtb \ imx6ull-colibri-eval-v3.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ + imx6ull-jozacp.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-opos6uldev.dtb \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-jozacp.dts b/arch/arm/boot/dts/imx6ull-jozacp.dts new file mode 100644 index 000000000000..a152eeb78e88 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-jozacp.dts @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; + +#include +#include +#include "imx6ull.dtsi" + +/ { + model = "JOZ Access Point"; + compatible = "joz,jozacp", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + /* On board name LED_RGB1 */ + led-controller-1 { + compatible = "pwm-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <0>; + pwms = <&pwm1 0 10000000 0>; + max-brightness = <255>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + pwms = <&pwm3 0 10000000 0>; + max-brightness = <255>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + pwms = <&pwm5 0 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* On board name LED_RGB2 */ + led-controller-2 { + compatible = "pwm-leds"; + + led-3 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + pwms = <&pwm2 0 10000000 0>; + max-brightness = <255>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <4>; + pwms = <&pwm4 0 10000000 0>; + max-brightness = <255>; + }; + + led-5 { + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <5>; + pwms = <&pwm6 0 10000000 0>; + max-brightness = <255>; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_5v0>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vbus: regulator-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vbus>; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v0>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&cpu0 { + clock-frequency = <792000000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + interrupts-extended = <&gpio1 29 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + dtr-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + vbus-supply = <®_vbus>; + dr_mode = "host"; + over-current-active-low; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vmmc-supply = <®_3v3>; + bus-width = <8>; + no-1-8-v; + non-removable; + cap-mmc-hw-reset; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sd; + non-removable; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x038b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x170b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* HW Revision */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 + + /* HW ID */ + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 + + /* Digital inputs */ + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x11000 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x11000 + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x11000 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x11000 + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x11000 + + /* Isolated outputs */ + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x01020 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x01020 + MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x01020 + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x01020 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x01020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001f8b1 + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b1 + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x01010 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x01010 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x01010 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x01010 + >; + }; + + pinctrl_pwm5: pwm5grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x01010 + >; + }; + + pinctrl_pwm6: pwm6grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x01010 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b0 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b0 + MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x1b0b0 + MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x1b0b0 + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x1b0b0 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x17099 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1f099 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10099 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17099 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17099 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17099 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17099 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17099 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17099 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17099 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17099 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9 + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_vbus: vbus0grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x030b0 + >; + }; + + pinctrl_wifi_npd: wifigrp { + fsl,pins = < + /* WL_REG_ON */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x03020 + >; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_hog>; + + pinctrl_snvs_hog: snvs-hog-grp { + fsl,pins = < + /* Digital outputs */ + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x00020 + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x00020 + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x00020 + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x00020 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x00020 + + /* Digital outputs fault feedback */ + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17000 + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17000 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x17000 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17000 + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17000 + >; + }; +}; -- cgit v1.2.3 From 2439d70c52c51f991b00b0ae5644e96033bd8165 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 22 Nov 2021 12:37:39 +0100 Subject: ARM: dts: imx6qdl-tqma6: add ERR006687 hardware workaround for "a" variant The TQMa6x "a" has a workaround for ERR006687 implemented in hardware. Add the required pinmuxing and related setup to make use of this. As board DTS files based on the TQMa6x SoMs will define their own pinmuxing for the FEC ethernet controller as well, we can't apply this pin group unconditionally; instead, it is the responsibility of the board DTs derived from imx6qdl-tqma6a.dtsi to include this group. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-tqma6a.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi index b679bec78e6c..bfb67da64b96 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi @@ -4,6 +4,12 @@ * Copyright 2013-2017 Markus Niebel */ +&fec { + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; @@ -26,3 +32,17 @@ pagesize = <32>; }; }; + +&iomuxc { + /* + * This pinmuxing is required for the ERR006687 workaround. Board + * DTS files that enable the FEC controller with + * fsl,err006687-workaround-present must include this group. + */ + pinctrl_enet_fix: enetfixgrp { + fsl,pins = < + /* ENET ping patch */ + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; +}; -- cgit v1.2.3 From ef3846247b41391434c23fcd9560daa57d14bb7a Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 22 Nov 2021 12:37:40 +0100 Subject: ARM: dts: imx6qdl: add TQ-Systems MBa6x device trees Add device trees for the MBa6x mainboard with TQMa6Q/QP/DL SoMs. As discussed, all new files are added with GPL-2.0-only license, as they are too tightly intertwined with the SoC DTSIs imx6dl.dtsi and imx6q.dtsi, which are GPL-2.0. Signed-off-by: Markus Niebel Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 5 + arch/arm/boot/dts/imx6dl-mba6.dtsi | 22 ++ arch/arm/boot/dts/imx6dl-mba6a.dts | 21 ++ arch/arm/boot/dts/imx6dl-mba6b.dts | 21 ++ arch/arm/boot/dts/imx6q-mba6.dtsi | 44 +++ arch/arm/boot/dts/imx6q-mba6a.dts | 20 ++ arch/arm/boot/dts/imx6q-mba6b.dts | 20 ++ arch/arm/boot/dts/imx6qdl-mba6.dtsi | 526 +++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-mba6a.dtsi | 36 +++ arch/arm/boot/dts/imx6qdl-mba6b.dtsi | 52 ++++ arch/arm/boot/dts/imx6qp-mba6b.dts | 18 ++ 11 files changed, 785 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-mba6.dtsi create mode 100644 arch/arm/boot/dts/imx6dl-mba6a.dts create mode 100644 arch/arm/boot/dts/imx6dl-mba6b.dts create mode 100644 arch/arm/boot/dts/imx6q-mba6.dtsi create mode 100644 arch/arm/boot/dts/imx6q-mba6a.dts create mode 100644 arch/arm/boot/dts/imx6q-mba6b.dts create mode 100644 arch/arm/boot/dts/imx6qdl-mba6.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-mba6a.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-mba6b.dtsi create mode 100644 arch/arm/boot/dts/imx6qp-mba6b.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9753faf0f1aa..e462dbe75f6a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -483,6 +483,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-icore-rqs.dtb \ imx6dl-lanmcu.dtb \ imx6dl-mamoj.dtb \ + imx6dl-mba6a.dtb \ + imx6dl-mba6b.dtb \ imx6dl-nit6xlite.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-phytec-mira-rdk-nand.dtb \ @@ -584,6 +586,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-kp-tpc.dtb \ imx6q-logicpd.dtb \ imx6q-marsboard.dtb \ + imx6q-mba6a.dtb \ + imx6q-mba6b.dtb \ imx6q-mccmon6.dtb \ imx6q-nitrogen6x.dtb \ imx6q-nitrogen6_max.dtb \ @@ -629,6 +633,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-wandboard-revb1.dtb \ imx6q-wandboard-revd1.dtb \ imx6q-zii-rdu2.dtb \ + imx6qp-mba6b.dtb \ imx6qp-nitrogen6_max.dtb \ imx6qp-nitrogen6_som2.dtb \ imx6qp-phytec-mira-rdk-nand.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-mba6.dtsi b/arch/arm/boot/dts/imx6dl-mba6.dtsi new file mode 100644 index 000000000000..b749b424bbd6 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-mba6.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +ðphy { + rxdv-skew-ps = <180>; + txen-skew-ps = <0>; + rxd3-skew-ps = <180>; + rxd2-skew-ps = <180>; + rxd1-skew-ps = <180>; + rxd0-skew-ps = <180>; + txd3-skew-ps = <120>; + txd2-skew-ps = <0>; + txd1-skew-ps = <300>; + txd0-skew-ps = <120>; + txc-skew-ps = <1860>; + rxc-skew-ps = <1860>; +}; diff --git a/arch/arm/boot/dts/imx6dl-mba6a.dts b/arch/arm/boot/dts/imx6dl-mba6a.dts new file mode 100644 index 000000000000..df0a96b28af0 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-mba6a.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include +#include "imx6dl-tqma6a.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6a.dtsi" +#include "imx6dl-mba6.dtsi" + +/ { + model = "TQ TQMa6S/DL on MBa6x"; + compatible = "tq,imx6dl-mba6x-a", "tq,mba6a", + "tq,imx6dl-tqma6dl-a", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-mba6b.dts b/arch/arm/boot/dts/imx6dl-mba6b.dts new file mode 100644 index 000000000000..610b19d2db0f --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-mba6b.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include +#include "imx6dl-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6dl-mba6.dtsi" + +/ { + model = "TQ TQMa6S/DL on MBa6x"; + compatible = "tq,imx6dl-mba6x-b", "tq,mba6b", + "tq,imx6dl-tqma6dl-b", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6q-mba6.dtsi b/arch/arm/boot/dts/imx6q-mba6.dtsi new file mode 100644 index 000000000000..0d7be4567291 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-mba6.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +&ecspi5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5_mba6x>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; +}; + +ðphy { + rxdv-skew-ps = <180>; + txen-skew-ps = <120>; + rxd3-skew-ps = <180>; + rxd2-skew-ps = <180>; + rxd1-skew-ps = <180>; + rxd0-skew-ps = <180>; + txd3-skew-ps = <120>; + txd2-skew-ps = <0>; + txd1-skew-ps = <180>; + txd0-skew-ps = <360>; + txc-skew-ps = <1860>; + rxc-skew-ps = <1860>; +}; + +&sata { + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi5_mba6x: ecspi5grp-mba6x { + fsl,pins = < + /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b099 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0xb099 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0xb099 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0xb099 /* eCSPI5 SS0 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-mba6a.dts b/arch/arm/boot/dts/imx6q-mba6a.dts new file mode 100644 index 000000000000..349a08605a5e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-mba6a.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6q-tqma6a.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6a.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6Q on MBa6x"; + compatible = "tq,imx6q-mba6x-a", "tq,mba6a", + "tq,imx6q-tqma6q-a", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-mba6b.dts b/arch/arm/boot/dts/imx6q-mba6b.dts new file mode 100644 index 000000000000..02c9f3e91b8f --- /dev/null +++ b/arch/arm/boot/dts/imx6q-mba6b.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6q-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6Q on MBa6x"; + compatible = "tq,imx6q-mba6x-b", "tq,mba6b", + "tq,imx6q-tqma6q-b", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/imx6qdl-mba6.dtsi new file mode 100644 index 000000000000..daf76345b179 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-mba6.dtsi @@ -0,0 +1,526 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include +#include +#include +#include + +/ { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + /delete-property/ mmc2; + /delete-property/ mmc3; + }; + + chosen { + stdout-path = &uart2; + }; + + beeper: gpio-beeper { + compatible = "gpio-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobeeper>; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + }; + + gpio_buttons: gpio-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobuttons>; + + button1 { + label = "s6"; + linux,code = ; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + }; + + button2 { + label = "s7"; + linux,code = ; + gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + }; + + button3 { + label = "s8"; + linux,code = ; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led1 { + label = "led1"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_mba6_3p3v: regulator-mba6-3p3v { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6-3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "supply-pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* PCIE.PWR_EN */ + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_mba6_3p3v>; + }; + + reg_vcc3v3_audio: regulator-vcc3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3-audio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_mba6_3p3v>; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&ssi1>; + audio-codec = <&tlv320aic32x4>; + audio-asrc = <&asrc>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + status = "okay"; + + ssi0 { + fsl,audmux-port = ; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) + >; + }; + + aud3 { + fsl,audmux-port = ; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0) + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>; + cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>; +}; + +&fec { + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <100000>; + micrel,force-master; + max-speed = <1000>; + }; + }; +}; + +&i2c1 { + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + ldoin-supply = <®_vcc3v3_audio>; + iov-supply = <®_mba6_3p3v>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + power-active-high; + over-current-active-low; + srp-disable; + hnp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +/* SD card slot */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_mba6_3p3v>; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + /* does not work on unmodified starter kit */ + /* fsl,ext-reset-output; */ + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099 + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */ + >; + }; + + pinctrl_ecspi1_mba6: ecspimba6grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* FEC phy IRQ */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008 + /* FEC phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099 + /* DSE = 100, 100k up, SPEED = MED */ + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0 + /* DSE = 111, pull 100k up */ + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038 + /* DSE = 111, pull external */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038 + /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0 + >; + }; + + pinctrl_gpiobeeper: gpiobeepergrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099 + >; + }; + + pinctrl_gpiobuttons: gpiobuttongrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099 + >; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 + + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099 + + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099 + + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099 + + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099 + + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099 + + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */ + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */ + /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */ + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071 + /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059 + + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059 + MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + /* Watchdog out */ + MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi new file mode 100644 index 000000000000..a61f2705a340 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/ { + aliases { + rtc0 = &rtc0; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>; +}; + +&i2c1 { + lm75: temperature-sensor@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + m24c64_57: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi new file mode 100644 index 000000000000..9f9f7037c9e4 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * Copyright 2013-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/ { + aliases { + rtc0 = &rtc0; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c3 { + lm75: temperature-sensor@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + m24c64_57: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-mba6b.dts b/arch/arm/boot/dts/imx6qp-mba6b.dts new file mode 100644 index 000000000000..eee2e09d6e94 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-mba6b.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2015-2021 TQ-Systems GmbH + * Author: Markus Niebel + */ +/dts-v1/; + +#include +#include "imx6qp-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6QP on MBa6x"; + compatible = "tq,imx6qp-mba6x-b", "tq,mba6b", + "tq,imx6qp-tqma6qp-b", "fsl,imx6qp"; +}; -- cgit v1.2.3 From c25b80c560b8a2bb9ca60155553abff6223c73a8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 22 Nov 2021 11:22:28 +0100 Subject: ARM: dts: Add FSG3 system controller and LEDs This adds the system controller on CS2 and the LEDs on it. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts | 59 ++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts index 598586fc0862..b740403b05a9 100644 --- a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts +++ b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts @@ -97,6 +97,65 @@ fis-index-block = <0x1f>; }; }; + + /* Small syscon with some LEDs at CS2 */ + syscon@2,0 { + compatible = "freecom,fsg-cs2-system-controller", "syscon"; + reg = <2 0x0 0x200>; + reg-io-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <2 0x0 0x0 0x200>; + + led@0,0 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x01>; + label = "fsg:blue:wlan"; + linux,default-trigger = "wlan"; + default-state = "on"; + }; + led@0,1 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x02>; + label = "fsg:blue:wan"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,2 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x04>; + label = "fsg:blue:sata"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,3 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x04>; + label = "fsg:blue:usb"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,4 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x08>; + label = "fsg:blue:sync"; + linux,default-trigger = ""; + default-state = "on"; + }; + led@0,5 { + compatible = "register-bit-led"; + reg = <0x00 0x02>; + mask = <0x10>; + label = "fsg:blue:ring"; + linux,default-trigger = ""; + default-state = "on"; + }; + }; }; pci@c0000000 { -- cgit v1.2.3 From 65248dde81528d7f6cdd091e397d2d6e0b49dae1 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 29 Jul 2021 01:34:39 +0200 Subject: ARM: dts: Add Goramo MultiLink device tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds a device tree for the Goramo MultiLink IXP425-based WAN router. Cc: Krzysztof Hałasa Cc: openwrt-devel@lists.openwrt.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/intel-ixp42x-goramo-multilink.dts | 180 +++++++++++++++++++++ arch/arm/boot/dts/intel-ixp4xx.dtsi | 17 ++ 3 files changed, 198 insertions(+) create mode 100644 arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..4084535c6489 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -263,6 +263,7 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp46x-ixdp465.dtb \ intel-ixp42x-adi-coyote.dtb \ intel-ixp42x-ixdpg425.dtb \ + intel-ixp42x-goramo-multilink.dtb \ intel-ixp42x-iomega-nas100d.dtb \ intel-ixp42x-dlink-dsm-g600.dtb \ intel-ixp42x-gateworks-gw2348.dtb \ diff --git a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts new file mode 100644 index 000000000000..f80388b17a9e --- /dev/null +++ b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Goramo MultiLink Router + * There are two variants: + * - MultiLink Basic (a box) + * - MultiLink Max (19" rack mount) + * This device tree supports MultiLink Basic. + * This machine is based on IXP425. + * This is one of the few devices supporting the IXP4xx High-Speed Serial + * (HSS) link for a V.35 WAN interface. + * The hardware originates in Poland. + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Goramo MultiLink Router"; + compatible = "goramo,multilink-router", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* + * 64 MB of RAM according to the manual. The MultiLink + * Max has 128 MB. + */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + /* + * 74HC4094 which is used as a rudimentary GPIO expander + * FIXME: + * - Create device tree bindings for this as GPIO expander + * - Write a pure DT GPIO driver using these bindings + * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different) + */ + gpio_74: gpio-74hc4094 { + compatible = "nxp,74hc4094"; + cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + /* oe-gpios is optional */ + gpio-controller; + #gpio-cells = <2>; + /* We are not cascaded */ + registers-number = <1>; + gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N", + "CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET", + "CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N"; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* 16 MB of Flash mapped in at CS0 */ + reg = <0 0x00000000 0x1000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x0fe0000 */ + fis-index-block = <0x7f>; + }; + }; + }; + + pci@c0000000 { + status = "ok"; + + /* + * The device has 4 slots (IDSEL) with one dedicated IRQ per slot. + * The slots have Ethernet, Ethernet, NEC and MPCI. + * The IDSELs are 11, 12, 13, 14. + */ + interrupt-map = + /* IDSEL 11 - Ethernet A */ + <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */ + <0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */ + <0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */ + <0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */ + /* IDSEL 12 - Ethernet B */ + <0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */ + <0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */ + <0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */ + <0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */ + /* IDSEL 13 - MPCI */ + <0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */ + <0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */ + <0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */ + <0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */ + /* IDSEL 14 - NEC */ + <0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */ + <0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */ + <0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */ + <0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */ + }; + + /* HSS links */ + npe@c8006000 { + hss@0 { + status = "okay"; + intel,queue-chl-rxtrig = <&qmgr 12>; + intel,queue-chl-txready = <&qmgr 34>; + intel,queue-pkt-rx = <&qmgr 13>; + intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>; + intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>; + intel,queue-pkt-txdone = <&qmgr 22>; + /* The Goramo GPIO-based clock etc control */ + cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>; + clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>; + }; + hss@1 { + status = "okay"; + intel,queue-chl-rxtrig = <&qmgr 10>; + intel,queue-chl-txready = <&qmgr 35>; + intel,queue-pkt-rx = <&qmgr 0>; + intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>; + intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>; + intel,queue-pkt-txdone = <&qmgr 9>; + /* The Goramo GPIO-based clock etc control */ + cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>; + clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>; + }; + }; + + /* EthB */ + ethernet@c8009000 { + status = "ok"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 32>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + /* EthC */ + ethernet@c800a000 { + status = "ok"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 33>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi index 46fede021476..51a716c59669 100644 --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi @@ -139,6 +139,23 @@ npe: npe@c8006000 { compatible = "intel,ixp4xx-network-processing-engine"; reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + /* NPE-A contains two high-speed serial links */ + hss@0 { + compatible = "intel,ixp4xx-hss"; + reg = <0>; + intel,npe-handle = <&npe 0>; + status = "disabled"; + }; + + hss@1 { + compatible = "intel,ixp4xx-hss"; + reg = <1>; + intel,npe-handle = <&npe 0>; + status = "disabled"; + }; /* NPE-C contains a crypto accelerator */ crypto { -- cgit v1.2.3 From 6786e78d6b7a7236df7ded9ae0e09fa1cba950fb Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Thu, 28 Oct 2021 16:19:31 +0200 Subject: ARM: ixp4xx: remove dead configs CPU_IXP43X and CPU_IXP46X Commit 73d04ca5f4ac ("ARM: ixp4xx: Delete Intel reference design boardfiles") removes the definition of the configs MACH_IXDP465 and MACH_KIXRP435, but misses to remove the configs CPU_IXP43X and CPU_IXP46X that depend on those removed configs, and hence are dead now. Fortunately, ./scripts/checkkconfigsymbols.py warns: MACH_IXDP465 Referencing files: arch/arm/mach-ixp4xx/Kconfig MACH_KIXRP435 Referencing files: arch/arm/mach-ixp4xx/Kconfig Remove the dead configs CPU_IXP43X and CPU_IXP46X. A further quick grep for the name of those two symbols did not show any use of the two config symbols; so, there are no further clean-up activities beyond this config removal needed. Signed-off-by: Lukas Bulwahn Reviewed-by: Arnd Bergmann Signed-off-by: Linus Walleij --- arch/arm/mach-ixp4xx/Kconfig | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 365a5853d310..4c787b4be62b 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -39,19 +39,6 @@ config ARCH_PRPMC1100 PrPCM1100 Processor Mezanine Module. For more information on this platform, see . -# -# Certain registers and IRQs are only enabled if supporting IXP465 CPUs -# -config CPU_IXP46X - bool - depends on MACH_IXDP465 - default y - -config CPU_IXP43X - bool - depends on MACH_KIXRP435 - default y - comment "IXP4xx Options" config IXP4XX_PCI_LEGACY -- cgit v1.2.3 From 29bf0ff5ae18ad1a6dd183569cc097e578052c57 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Sat, 4 Dec 2021 23:58:19 +0200 Subject: ARM: dts: exynos: Rename hsi2c nodes to i2c for Exynos5260 In Device Tree specification it's recommended to use "i2c" name for I2C nodes. Now that i2c-exynos5 dt-schema binding was added, it shows some warnings like this when validating HS-I2C nodes: hsi2c@xxxxxxxxx: $nodename:0: 'hsi2c@xxxxxxxx' does not match '^i2c(@.*)?' From schema: Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Rename hsi2c@* to i2c@* to fix those warnings. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211204215820.17378-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5260.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 52fa211525ce..524d244050e0 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -368,7 +368,7 @@ status = "disabled"; }; - hsi2c_0: hsi2c@12da0000 { + hsi2c_0: i2c@12da0000 { compatible = "samsung,exynos5260-hsi2c"; reg = <0x12DA0000 0x1000>; interrupts = ; @@ -381,7 +381,7 @@ status = "disabled"; }; - hsi2c_1: hsi2c@12db0000 { + hsi2c_1: i2c@12db0000 { compatible = "samsung,exynos5260-hsi2c"; reg = <0x12DB0000 0x1000>; interrupts = ; @@ -394,7 +394,7 @@ status = "disabled"; }; - hsi2c_2: hsi2c@12dc0000 { + hsi2c_2: i2c@12dc0000 { compatible = "samsung,exynos5260-hsi2c"; reg = <0x12DC0000 0x1000>; interrupts = ; @@ -407,7 +407,7 @@ status = "disabled"; }; - hsi2c_3: hsi2c@12dd0000 { + hsi2c_3: i2c@12dd0000 { compatible = "samsung,exynos5260-hsi2c"; reg = <0x12DD0000 0x1000>; interrupts = ; -- cgit v1.2.3 From 856732adc1acbfdf457ec7a875a252d6fb039294 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 3 Dec 2021 22:24:33 +0530 Subject: ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit has plugged with 7" LVDS panel. Engicam i.Core STM32MP1 SoM has SN65DSI84 DSI to LVDS bridge. This patch adds a display pipeline to connect DSI to SN65DSI84 to 7" LVDS panel. Signed-off-by: Jagan Teki Signed-off-by: Alexandre Torgue --- .../dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 85 ++++++++++++++++++++++ 1 file changed, 85 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts index ec9f1d1cd50f..a797eaa917b7 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -24,6 +24,91 @@ chosen { stdout-path = "serial0:115200n8"; }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + default-on; + }; + + panel { + compatible = "yes-optoelectronics,ytc700tlag-05-201c"; + backlight = <&backlight>; + power-supply = <&v3v3>; + + port { + panel_out_bridge: endpoint { + remote-endpoint = <&bridge_out_panel>; + }; + }; + }; +}; + +&dsi { + status = "okay"; + phy-dsi-supply = <®18>; + + ports { + port@0 { + reg = <0>; + dsi_in_ltdc: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out_bridge: endpoint { + remote-endpoint = <&bridge_in_dsi>; + }; + }; + }; +}; + +&i2c6 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_a>; + pinctrl-1 = <&i2c6_sleep_pins_a>; + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in_dsi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + data-lanes = <1 2>; + }; + }; + + port@2 { + reg = <2>; + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_out_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in_ltdc>; + }; + }; }; &sdmmc1 { -- cgit v1.2.3 From 3ff0810ffc4793bfde454a452837484d0815aa14 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 3 Dec 2021 22:24:35 +0530 Subject: ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - 10" LVDS Panel (SN65DSI84 DSI-LVDS bridge on SoM) i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0 10.1" Open Frame board. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + .../stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 132 +++++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..641220e970e8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1140,6 +1140,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ stm32mp157a-icore-stm32mp1-ctouch2.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \ stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts new file mode 100644 index 000000000000..2a2829283456 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-icore-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1\" Open Frame"; + compatible = "engicam,icore-stm32mp1-ctouch2-of10", + "engicam,icore-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + default-on; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + panel { + compatible = "ampire,am-1280800n3tzqw-t00h"; + backlight = <&backlight>; + power-supply = <&v3v3>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; +}; + +&dsi { + status = "okay"; + phy-dsi-supply = <®18>; + + ports { + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&i2c6 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_a>; + pinctrl-1 = <&i2c6_sleep_pins_a>; + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <1 2>; + }; + }; + + port@2 { + reg = <2>; + bridge_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; -- cgit v1.2.3 From 67ac01d03862b274d4ca3fa76092e96b00f478af Mon Sep 17 00:00:00 2001 From: Andrei Kartashev Date: Fri, 19 Nov 2021 15:00:57 +0300 Subject: ARM: dts: aspeed: add device tree for YADRO VEGMAN BMC YADRO VEGMAN is x86 based servers family with ASPEED AST2500-based BMC. Currently there are three models: * VEGMAN N110 * VEGMAN S220/320 * VEGMAN R120/220 The dts files provides configuration for BMC system. Signed-off-by: Andrei Kartashev Link: https://lore.kernel.org/r/20211119120057.12118-3-a.kartashev@yadro.com Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 5 +- arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts | 149 +++++++++++++ arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts | 255 ++++++++++++++++++++++ arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts | 154 +++++++++++++ arch/arm/boot/dts/aspeed-bmc-vegman.dtsi | 311 +++++++++++++++++++++++++++ 5 files changed, 873 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-vegman.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..78b71e02624c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1519,4 +1519,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-quanta-q71l.dtb \ aspeed-bmc-supermicro-x11spi.dtb \ aspeed-bmc-inventec-transformers.dtb \ - aspeed-bmc-tyan-s7106.dtb + aspeed-bmc-tyan-s7106.dtb \ + aspeed-bmc-vegman-n110.dtb \ + aspeed-bmc-vegman-rx20.dtb \ + aspeed-bmc-vegman-sx20.dtb diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts b/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts new file mode 100644 index 000000000000..24319267d550 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO +/dts-v1/; + +#include "aspeed-bmc-vegman.dtsi" + +/ { + model = "YADRO VEGMAN N110 BMC"; + compatible = "yadro,vegman-n110-bmc", "aspeed,ast2500"; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", + /*F0-F7*/ "NMI_OUT","PCIE_NIC_ALERT","","","SKT0_FAULT_LED","","RST_RGMII_PHYRST_DNP","", + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", + /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", + /*AA0-AA7*/ "","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpio { + ngpios = <80>; + bus-frequency = <2000000>; + status = "okay"; + /* SGPIO lines. even: input, odd: output */ + gpio-line-names = + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", + /*D0-D7*/ "","","","","","","","","","","","","","","","", + /*E0-E7*/ "","","","","","","","","","","","","","","","", + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", + /*H0-H7*/ "","","","","","","","","","","","","","","","", + /*I0-I7*/ "","","","","","","","","","","","","","","","", + /*J0-J7*/ "","","","","","","","","","","","","","","",""; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "", "", "", "", "", "", "PE_PCH_SCR_CLKREQ", "", + /*IO1.0-1.7*/ "", "PE_PCH_MEZ_PRSNT", "PE_PCH_MEZ_PRSNT_", "NIC_4_PE_PRSNT", "NIC_3_PE_PRSNT", "NIC_2_PE_PRSNT", "NIC_1_PE_PRSNT", ""; + }; + gpio@27 { + compatible = "nxp,pca9698"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "", "", "", + /*IO3.0-3.7*/ "", "", "", "", "", "", "", "", + /*IO4.0-4.7*/ "", "", "", "", "", "", "", ""; + }; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + mux-expa@73 { + compatible = "nxp,pca9545"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; + mux-sata@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + mux-expb@71 { + compatible = "nxp,pca9545"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x06>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts b/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts new file mode 100644 index 000000000000..ebbb68b55559 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO +/dts-v1/; + +#include "aspeed-bmc-vegman.dtsi" + +/ { + model = "YADRO VEGMAN Rx20 BMC"; + compatible = "yadro,vegman-rx20-bmc", "aspeed,ast2500"; + + leds { + compatible = "gpio-leds"; + + temp_alarm { + label = "temp:red:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 4) GPIO_ACTIVE_LOW>; + }; + + temp_ok { + label = "temp:green:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; + }; + + psu_fault { + label = "psu:red:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_LOW>; + }; + + psu_ok { + label = "psu:green:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "CASE_OPEN_DNP","CASE_OPEN_FAULT_RST_DNP","BEZEL_ON_PWR_P3V3","PWM_PWRGD_EXP_EN","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","LED_TEMP_STATUS_R","LED_TEMP_STATUS_G","LED_PWR_STATUS_R","LED_PWR_STATUS_G", + /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED_DNP","SKT1_FAULT_LED_DNP","RST_RGMII_PHYRST_DNP","", + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","SPI_BMC_BOOT_HD","IRQ_NMI_EVENT","SPI_BMC_BOOT_WP","SPI_BMC_BOOT_WP1","", + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "SEL_FLASH_SOFT","STATUS_SEL_BMC","","","BMC_WDT_P","ID_BUTTON","PS_PWROK","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","SPI_BIOS_ACTIVE_FLASH_SEL","STATUS_SEL_BIOS", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "_SPI_BMC_BOOT_CS1","","","","","","","", + /*S0-S7*/ "_SPI2_BMC_CS1","RSR_A_SMBEXP_RST_INT","RSR_B_SMBEXP_RST_INT","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", + /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","BMC_WDT_RST1","BMC_WDT_RST2","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpio { + ngpios = <80>; + bus-frequency = <2000000>; + status = "okay"; + /* SGPIO lines. even: input, odd: output */ + gpio-line-names = + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", + /*D0-D7*/ "","","","","","","","","","","","","","","","", + /*E0-E7*/ "","","","","","","","","","","","","","","","", + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", + /*H0-H7*/ "","","","","","","","","","","","","","","","", + /*I0-I7*/ "","","","","","","","","","","","","","","","", + /*J0-J7*/ "","","","","","","","","","","","","","","",""; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "ETH3_CLK_REQ", "ETH2_CLK_REQ", "RSR_A_PCIE_X16_2_PRSNT", "RSR_B_PCIE_X16_2_PRSNT", "", "RSR_B_PCIE_X8_3_PRSNT", "RSR_B_PCIE_X8_4_PRSNT", "RSR_B_PCIE_X16_PRSNT_N", + /*IO1.0-1.7*/ "RSR_B_PCIE_X8_2_PRSNT", "RSR_B_PCIE_X8_1_PRSNT", "NIC_1_PE_BUF_PRSNT", "RSR_A_PCIE_X16_PRSNT", "RSR_A_PCIE_X8_3_PRSNT", "RSR_A_PCIE_X8_2_PRSNT", "RSR_A_PCIE_X8_1_PRSNT_N", ""; + }; + gpio@23 { + compatible = "nxp,pcal9535"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "", "", "", + /*IO1.0-1.7*/ "", "", "", "", "", "", "", ""; + }; + gpio@27 { + compatible = "nxp,pca9698"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", + /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", + /*IO4.0-4.7*/ "PCH_PWR_RESET_N", "FM_BOARD_SKU_ID0", "FM_BOARD_SKU_ID1", "FM_BOARD_SKU_ID2", "FM_BOARD_SKU_ID3", "FM_BOARD_SKU_ID4", "FM_BOARD_REV_ID0", "FM_BOARD_REV_ID1"; + }; + gpio@39 { + compatible = "nxp,pca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "FAN_FAULT_0", "FAN_FAULT_1", "FAN_FAULT_2", "FAN_FAULT_3", "FAN_FAULT_4", "FAN_FAULT_5", "FAN_FAULT_6", ""; + }; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + mux-expa@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + rsra-mux@72 { + compatible = "nxp,pca9548"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + }; + }; + }; + }; + mux-sata@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + mux-expb@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rsrb-mux@72 { + compatible = "nxp,pca9548"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + }; + }; + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + }; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x07>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0C>; + }; + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0D>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts b/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts new file mode 100644 index 000000000000..e36ee4704994 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO +/dts-v1/; + +#include "aspeed-bmc-vegman.dtsi" + +/ { + model = "YADRO VEGMAN Sx20 BMC"; + compatible = "yadro,vegman-sx20-bmc", "aspeed,ast2500"; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", + /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED","SKT1_FAULT_LED","RST_RGMII_PHYRST_DNP","", + /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", + /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","BMC_GPU_RISER_ID1","BMC_GPU_RISER_ID0","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", + /*P0-P7*/ "","P12V_HDDS_A_EN","P12V_HDDS_B_EN","P5V_HDDS_A_EN","PWRGD_P5V_HDDS_A","P5V_HDDS_B_EN","PWRGD_P5V_HDDS_B","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", + /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", + /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", + /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", + /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpio { + ngpios = <80>; + bus-frequency = <2000000>; + status = "okay"; + /* SGPIO lines. even: input, odd: output */ + gpio-line-names = + /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", + /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", + /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", + /*D0-D7*/ "","","","","","","","","","","","","","","","", + /*E0-E7*/ "","","","","","","","","","","","","","","","", + /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", + /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", + /*H0-H7*/ "","","","","","","","","","","","","","","","", + /*I0-I7*/ "","","","","","","","","","","","","","","","", + /*J0-J7*/ "","","","","","","","","","","","","","","",""; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "", "", "CPU1_PE3_0_SLOT_PRSNT", "", "CPU1_PE1_GPU_PRSNT", "CPU1_PE3_1_SLOT_PRSNT", "PE_PCH_MEZ_PRSNT", "CPU0_PE3_1_SLOT_PRSNT", + /*IO1.0-1.7*/ "CPU0_PE1_GPU_PRSNT", "CPU0_PE2_NVME2_PRSNT", "CPU1_PE2_NVME3_PRSNT", "CPU1_PE2_SLOT_PRSNT", "CPU1_PE2_NVME4_PRSNT", "", "CPU0_PE2_NVME1_PRSNT", "CPU0_PE3_0_RAID_PRSNT"; + }; + gpio@27 { + compatible = "nxp,pca9698"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", + /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", + /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1", + /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1", + /*IO4.0-4.7*/ "PWRGD_P5V_HDDS_A_R", "PWRGD_P5V_HDDS_B_R", "", "", "", "", "", ""; + }; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + mux-expa@73 { + compatible = "nxp,pca9545"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; + mux-sata@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + mux-expb@71 { + compatible = "nxp,pca9545"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi b/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi new file mode 100644 index 000000000000..1a5b25b2ea29 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 YADRO + +#include "aspeed-g5.dtsi" +#include + +/ { + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + ramoops@9eff0000{ + compatible = "ramoops"; + reg = <0x9eff0000 0x10000>; + record-size = <0x2000>; + console-size = <0x2000>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; + + leds { + compatible = "gpio-leds"; + + identify { + label = "platform:blue:indicator"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; + }; + + status_amber { + label = "platform:red:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(S, 5) GPIO_ACTIVE_LOW>; + }; + + status_green { + label = "platform:green:status"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(S, 4) GPIO_ACTIVE_LOW>; + }; + + power_fault { + label = "platform:red:power"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>; + }; + + power_ok { + label = "platform:green:power"; + default-state = "off"; + gpios = <&gpio ASPEED_GPIO(AA, 5) GPIO_ACTIVE_LOW>; + }; + }; + + beeper { + compatible = "pwm-beeper"; + pwms = <&timer 5 1000000 0>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2ck_default + &pinctrl_spi2miso_default + &pinctrl_spi2mosi_default + &pinctrl_spi2cs0_default>; + flash@0 { + status = "okay"; + label = "bios"; + m25p,fast-read; + }; +}; + +&mac0 { + status = "okay"; + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; + + phy-mode = "rgmii"; + phy-handle = <&phy>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + /* KSZ9131 */ + compatible = "ethernet-phy-id0022.1640"; + reg = <1>; + + micrel,led-mode = <0>; + }; + }; +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&sdmmc { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_default>; + disable-wp; +}; + +&timer { + fttmr010,pwm-outputs = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_timer5_default>; + #pwm-cells = <3>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xCA2>; + status = "okay"; +}; + +&kcs4 { + aspeed,lpc-io-reg = <0xCA4>; + status = "okay"; +}; + +&lpc_snoop { + snoop-ports = <0x80>; + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; +}; + +&i2c0 { + /* SMB_IPMB_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c1 { + /* SMB_CHASSENSOR_STBY_LVC3 */ + status = "okay"; +}; + +&i2c2 { + /* SMB_PCIE_STBY_LVC3 */ + status = "okay"; +}; + +&i2c3 { + /* SMB_HOST_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c4 { + /* BMC_PMBUS2_STBY */ + status = "okay"; +}; + +&i2c5 { + /* SMB_SMLINK0_STBY_LVC3 */ + bus-frequency = <1000000>; + multi-master; + status = "okay"; +}; + +&i2c6 { + /* SMB_TEMPSENSOR_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c7 { + /* SMB_SM_PMB1_SML1_STBY_LVC3 */ + multi-master; + status = "okay"; +}; + +&i2c9 { + /* SMB_BMC_ETH3_LVC3 */ + status = "okay"; +}; + +&i2c10 { + /* SMB_BMC_ETH2_LVC3 */ + status = "okay"; +}; + +&i2c11 { + /* SMB_BMC_MGMT_LVC3 */ + status = "okay"; + + at24@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; +}; + +&i2c12 { + /* SMB_BMC_FAULT_EXP_LVC3 */ + status = "okay"; +}; + +&i2c13 { + /* SMB_PCIE2_STBY_LVC3 */ + status = "okay"; +}; -- cgit v1.2.3 From 77993b595ada5731e513eb06a0f4bf4b9f1e9532 Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Mon, 29 Nov 2021 18:46:54 +0100 Subject: locking: Allow to include asm/spinlock_types.h from linux/spinlock_types_raw.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The printk header file includes ratelimit_types.h for its __ratelimit() based usage. It is required for the static initializer used in printk_ratelimited(). It uses a raw_spinlock_t and includes the spinlock_types.h. PREEMPT_RT substitutes spinlock_t with a rtmutex based implementation and so its spinlock_t implmentation (provided by spinlock_rt.h) includes rtmutex.h and atomic.h which leads to recursive includes where defines are missing. By including only the raw_spinlock_t defines it avoids the atomic.h related includes at this stage. An example on powerpc: | CALL scripts/atomic/check-atomics.sh |In file included from include/linux/bug.h:5, | from include/linux/page-flags.h:10, | from kernel/bounds.c:10: |arch/powerpc/include/asm/page_32.h: In function ‘clear_page’: |arch/powerpc/include/asm/bug.h:87:4: error: implicit declaration of function â=80=98__WARNâ=80=99 [-Werror=3Dimplicit-function-declaration] | 87 | __WARN(); \ | | ^~~~~~ |arch/powerpc/include/asm/page_32.h:48:2: note: in expansion of macro ‘WARN_ONâ€=99 | 48 | WARN_ON((unsigned long)addr & (L1_CACHE_BYTES - 1)); | | ^~~~~~~ |arch/powerpc/include/asm/bug.h:58:17: error: invalid application of ‘sizeofâ€=99 to incomplete type ‘struct bug_entryâ€=99 | 58 | "i" (sizeof(struct bug_entry)), \ | | ^~~~~~ |arch/powerpc/include/asm/bug.h:89:3: note: in expansion of macro ‘BUG_ENTRYâ€=99 | 89 | BUG_ENTRY(PPC_TLNEI " %4, 0", \ | | ^~~~~~~~~ |arch/powerpc/include/asm/page_32.h:48:2: note: in expansion of macro ‘WARN_ONâ€=99 | 48 | WARN_ON((unsigned long)addr & (L1_CACHE_BYTES - 1)); | | ^~~~~~~ |In file included from arch/powerpc/include/asm/ptrace.h:298, | from arch/powerpc/include/asm/hw_irq.h:12, | from arch/powerpc/include/asm/irqflags.h:12, | from include/linux/irqflags.h:16, | from include/asm-generic/cmpxchg-local.h:6, | from arch/powerpc/include/asm/cmpxchg.h:526, | from arch/powerpc/include/asm/atomic.h:11, | from include/linux/atomic.h:7, | from include/linux/rwbase_rt.h:6, | from include/linux/rwlock_types.h:55, | from include/linux/spinlock_types.h:74, | from include/linux/ratelimit_types.h:7, | from include/linux/printk.h:10, | from include/asm-generic/bug.h:22, | from arch/powerpc/include/asm/bug.h:109, | from include/linux/bug.h:5, | from include/linux/page-flags.h:10, | from kernel/bounds.c:10: |include/linux/thread_info.h: In function â=80=98copy_overflowâ=80=99: |include/linux/thread_info.h:210:2: error: implicit declaration of function â=80=98WARNâ=80=99 [-Werror=3Dimplicit-function-declaration] | 210 | WARN(1, "Buffer overflow detected (%d < %lu)!\n", size, count); | | ^~~~ The WARN / BUG include pulls in printk.h and then ptrace.h expects WARN (from bug.h) which is not yet complete. Even hw_irq.h has WARN_ON() statements. On POWERPC64 there are missing atomic64 defines while building 32bit VDSO: | VDSO32C arch/powerpc/kernel/vdso32/vgettimeofday.o |In file included from include/linux/atomic.h:80, | from include/linux/rwbase_rt.h:6, | from include/linux/rwlock_types.h:55, | from include/linux/spinlock_types.h:74, | from include/linux/ratelimit_types.h:7, | from include/linux/printk.h:10, | from include/linux/kernel.h:19, | from arch/powerpc/include/asm/page.h:11, | from arch/powerpc/include/asm/vdso/gettimeofday.h:5, | from include/vdso/datapage.h:137, | from lib/vdso/gettimeofday.c:5, | from : |include/linux/atomic-arch-fallback.h: In function ‘arch_atomic64_incâ€=99: |include/linux/atomic-arch-fallback.h:1447:2: error: implicit declaration of function ‘arch_atomic64_add’; did you mean ‘arch_atomic_add’? [-Werror=3Dimpl |icit-function-declaration] | 1447 | arch_atomic64_add(1, v); | | ^~~~~~~~~~~~~~~~~ | | arch_atomic_add The generic fallback is not included, atomics itself are not used. If kernel.h does not include printk.h then it comes later from the bug.h include. Allow asm/spinlock_types.h to be included from linux/spinlock_types_raw.h. Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20211129174654.668506-12-bigeasy@linutronix.de --- arch/alpha/include/asm/spinlock_types.h | 2 +- arch/arm/include/asm/spinlock_types.h | 2 +- arch/arm64/include/asm/spinlock_types.h | 2 +- arch/csky/include/asm/spinlock_types.h | 2 +- arch/hexagon/include/asm/spinlock_types.h | 2 +- arch/ia64/include/asm/spinlock_types.h | 2 +- arch/powerpc/include/asm/simple_spinlock_types.h | 2 +- arch/powerpc/include/asm/spinlock_types.h | 2 +- arch/riscv/include/asm/spinlock_types.h | 2 +- arch/s390/include/asm/spinlock_types.h | 2 +- arch/sh/include/asm/spinlock_types.h | 2 +- arch/xtensa/include/asm/spinlock_types.h | 2 +- include/linux/ratelimit_types.h | 2 +- include/linux/spinlock_types_up.h | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/include/asm/spinlock_types.h b/arch/alpha/include/asm/spinlock_types.h index 1d5716bc060b..2526fd3be5fd 100644 --- a/arch/alpha/include/asm/spinlock_types.h +++ b/arch/alpha/include/asm/spinlock_types.h @@ -2,7 +2,7 @@ #ifndef _ALPHA_SPINLOCK_TYPES_H #define _ALPHA_SPINLOCK_TYPES_H -#ifndef __LINUX_SPINLOCK_TYPES_H +#ifndef __LINUX_SPINLOCK_TYPES_RAW_H # error "please don't include this file directly" #endif diff --git a/arch/arm/include/asm/spinlock_types.h b/arch/arm/include/asm/spinlock_types.h index 5976958647fe..0c14b36ef101 100644 --- a/arch/arm/include/asm/spinlock_types.h +++ b/arch/arm/include/asm/spinlock_types.h @@ -2,7 +2,7 @@ #ifndef __ASM_SPINLOCK_TYPES_H #define __ASM_SPINLOCK_TYPES_H -#ifndef __LINUX_SPINLOCK_TYPES_H +#ifndef __LINUX_SPINLOCK_TYPES_RAW_H # error "please don't include this file directly" #endif diff --git a/arch/arm64/include/asm/spinlock_types.h b/arch/arm64/include/asm/spinlock_types.h index 18782f0c4721..11ab1c077697 100644 --- a/arch/arm64/include/asm/spinlock_types.h +++ b/arch/arm64/include/asm/spinlock_types.h @@ -5,7 +5,7 @@ #ifndef __ASM_SPINLOCK_TYPES_H #define __ASM_SPINLOCK_TYPES_H -#if !defined(__LINUX_SPINLOCK_TYPES_H) && !defined(__ASM_SPINLOCK_H) +#if !defined(__LINUX_SPINLOCK_TYPES_RAW_H) && !defined(__ASM_SPINLOCK_H) # error "please don't include this file directly" #endif diff --git a/arch/csky/include/asm/spinlock_types.h b/arch/csky/include/asm/spinlock_types.h index 8ff0f6ff3a00..db87a12c3827 100644 --- a/arch/csky/include/asm/spinlock_types.h +++ b/arch/csky/include/asm/spinlock_types.h @@ -3,7 +3,7 @@ #ifndef __ASM_CSKY_SPINLOCK_TYPES_H #define __ASM_CSKY_SPINLOCK_TYPES_H -#ifndef __LINUX_SPINLOCK_TYPES_H +#ifndef __LINUX_SPINLOCK_TYPES_RAW_H # error "please don't include this file directly" #endif diff --git a/arch/hexagon/include/asm/spinlock_types.h b/arch/hexagon/include/asm/spinlock_types.h index 19d233497ba5..d5f66495b670 100644 --- a/arch/hexagon/include/asm/spinlock_types.h +++ b/arch/hexagon/include/asm/spinlock_types.h @@ -8,7 +8,7 @@ #ifndef _ASM_SPINLOCK_TYPES_H #define _ASM_SPINLOCK_TYPES_H -#ifndef __LINUX_SPINLOCK_TYPES_H +#ifndef __LINUX_SPINLOCK_TYPES_RAW_H # error "please don't include this file directly" #endif diff --git a/arch/ia64/include/asm/spinlock_types.h b/arch/ia64/include/asm/spinlock_types.h index 6e345fefcdca..14b8a161c165 100644 --- a/arch/ia64/include/asm/spinlock_types.h +++ b/arch/ia64/include/asm/spinlock_types.h @@ -2,7 +2,7 @@ #ifndef _ASM_IA64_SPINLOCK_TYPES_H #define _ASM_IA64_SPINLOCK_TYPES_H -#ifndef __LINUX_SPINLOCK_TYPES_H +#ifndef __LINUX_SPINLOCK_TYPES_RAW_H # error "please don't include this file directly" #endif diff --git a/arch/powerpc/include/asm/simple_spinlock_types.h b/arch/powerpc/include/asm/simple_spinlock_types.h index 0f3cdd8faa95..08243338069d 100644 --- a/arch/powerpc/include/asm/simple_spinlock_types.h +++ b/arch/powerpc/include/asm/simple_spinlock_types.h @@ -2,7 +2,7 @@ #ifndef _ASM_POWERPC_SIMPLE_SPINLOCK_TYPES_H #define _ASM_POWERPC_SIMPLE_SPINLOCK_TYPES_H -#ifndef __LINUX_SPINLOCK_TYPES_H +#ifndef __LINUX_SPINLOCK_TYPES_RAW_H # error "please don't include this file directly" #endif diff --git a/arch/powerpc/include/asm/spinlock_types.h b/arch/powerpc/include/asm/spinlock_types.h index c5d742f18021..d5f8a74ed2e8 100644 --- a/arch/powerpc/include/asm/spinlock_types.h +++ b/arch/powerpc/include/asm/spinlock_types.h @@ -2,7 +2,7 @@ #ifndef _ASM_POWERPC_SPINLOCK_TYPES_H #define _ASM_POWERPC_SPINLOCK_TYPES_H -#ifndef __LINUX_SPINLOCK_TYPES_H +#ifndef __LINUX_SPINLOCK_TYPES_RAW_H # error "please don't include this file directly" #endif diff --git a/arch/riscv/include/asm/spinlock_types.h b/arch/riscv/include/asm/spinlock_types.h index f398e7638dd6..5a35a49505da 100644 --- a/arch/riscv/include/asm/spinlock_types.h +++ b/arch/riscv/include/asm/spinlock_types.h @@ -6,7 +6,7 @@ #ifndef _ASM_RISCV_SPINLOCK_TYPES_H #define _ASM_RISCV_SPINLOCK_TYPES_H -#ifndef __LINUX_SPINLOCK_TYPES_H +#ifndef __LINUX_SPINLOCK_TYPES_RAW_H # error "please don't include this file directly" #endif diff --git a/arch/s390/include/asm/spinlock_types.h b/arch/s390/include/asm/spinlock_types.h index a2bbfd7df85f..b69695e39957 100644 --- a/arch/s390/include/asm/spinlock_types.h +++ b/arch/s390/include/asm/spinlock_types.h @@ -2,7 +2,7 @@ #ifndef __ASM_SPINLOCK_TYPES_H #define __ASM_SPINLOCK_TYPES_H -#ifndef __LINUX_SPINLOCK_TYPES_H +#ifndef __LINUX_SPINLOCK_TYPES_RAW_H # error "please don't include this file directly" #endif diff --git a/arch/sh/include/asm/spinlock_types.h b/arch/sh/include/asm/spinlock_types.h index e82369f286a2..907bda4b1619 100644 --- a/arch/sh/include/asm/spinlock_types.h +++ b/arch/sh/include/asm/spinlock_types.h @@ -2,7 +2,7 @@ #ifndef __ASM_SH_SPINLOCK_TYPES_H #define __ASM_SH_SPINLOCK_TYPES_H -#ifndef __LINUX_SPINLOCK_TYPES_H +#ifndef __LINUX_SPINLOCK_TYPES_RAW_H # error "please don't include this file directly" #endif diff --git a/arch/xtensa/include/asm/spinlock_types.h b/arch/xtensa/include/asm/spinlock_types.h index 64c9389254f1..797aed7df3dd 100644 --- a/arch/xtensa/include/asm/spinlock_types.h +++ b/arch/xtensa/include/asm/spinlock_types.h @@ -2,7 +2,7 @@ #ifndef __ASM_SPINLOCK_TYPES_H #define __ASM_SPINLOCK_TYPES_H -#if !defined(__LINUX_SPINLOCK_TYPES_H) && !defined(__ASM_SPINLOCK_H) +#if !defined(__LINUX_SPINLOCK_TYPES_RAW_H) && !defined(__ASM_SPINLOCK_H) # error "please don't include this file directly" #endif diff --git a/include/linux/ratelimit_types.h b/include/linux/ratelimit_types.h index b676aa419eef..c21c7f8103e2 100644 --- a/include/linux/ratelimit_types.h +++ b/include/linux/ratelimit_types.h @@ -4,7 +4,7 @@ #include #include -#include +#include #define DEFAULT_RATELIMIT_INTERVAL (5 * HZ) #define DEFAULT_RATELIMIT_BURST 10 diff --git a/include/linux/spinlock_types_up.h b/include/linux/spinlock_types_up.h index c09b6407ae1b..7f86a2016ac5 100644 --- a/include/linux/spinlock_types_up.h +++ b/include/linux/spinlock_types_up.h @@ -1,7 +1,7 @@ #ifndef __LINUX_SPINLOCK_TYPES_UP_H #define __LINUX_SPINLOCK_TYPES_UP_H -#ifndef __LINUX_SPINLOCK_TYPES_H +#ifndef __LINUX_SPINLOCK_TYPES_RAW_H # error "please don't include this file directly" #endif -- cgit v1.2.3 From 6198461ef509356e7f0fe5b04e88009aa698a065 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 24 Nov 2021 16:41:15 +0100 Subject: arm: ioremap: Replace pci_ioremap_io() usage by pci_remap_iospace() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace all usage of ARM specific pci_ioremap_io() function by standard PCI core API function pci_remap_iospace() in all drivers and ARM mach code. Link: https://lore.kernel.org/r/20211124154116.916-5-pali@kernel.org Signed-off-by: Pali Rohár Signed-off-by: Lorenzo Pieralisi Reviewed-by: Russell King (Oracle) Reviewed-by: Alexandre Belloni --- arch/arm/mach-dove/pcie.c | 9 +++++---- arch/arm/mach-iop32x/pci.c | 5 ++++- arch/arm/mach-mv78xx0/pcie.c | 5 ++++- arch/arm/mach-orion5x/pci.c | 10 ++++++++-- drivers/pcmcia/at91_cf.c | 6 +++++- 5 files changed, 26 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c index ee91ac6b5ebf..2a493bdfffc6 100644 --- a/arch/arm/mach-dove/pcie.c +++ b/arch/arm/mach-dove/pcie.c @@ -38,6 +38,7 @@ static int num_pcie_ports; static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) { struct pcie_port *pp; + struct resource realio; if (nr >= num_pcie_ports) return 0; @@ -53,10 +54,10 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) orion_pcie_setup(pp->base); - if (pp->index == 0) - pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE); - else - pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE); + realio.start = sys->busnr * SZ_64K; + realio.end = realio.start + SZ_64K - 1; + pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE : + DOVE_PCIE1_IO_PHYS_BASE); /* * IORESOURCE_MEM diff --git a/arch/arm/mach-iop32x/pci.c b/arch/arm/mach-iop32x/pci.c index ab0010dc3145..7a215d2ee7e2 100644 --- a/arch/arm/mach-iop32x/pci.c +++ b/arch/arm/mach-iop32x/pci.c @@ -185,6 +185,7 @@ iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) { struct resource *res; + struct resource realio; if (nr != 0) return 0; @@ -206,7 +207,9 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) pci_add_resource_offset(&sys->resources, res, sys->mem_offset); - pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA); + realio.start = 0; + realio.end = realio.start + SZ_64K - 1; + pci_remap_iospace(&realio, IOP3XX_PCI_LOWER_IO_PA); return 1; } diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index 636d84b40466..e15646af7f26 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -101,6 +101,7 @@ static void __init mv78xx0_pcie_preinit(void) static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) { struct pcie_port *pp; + struct resource realio; if (nr >= num_pcie_ports) return 0; @@ -115,7 +116,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) orion_pcie_set_local_bus_nr(pp->base, sys->busnr); orion_pcie_setup(pp->base); - pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr)); + realio.start = nr * SZ_64K; + realio.end = realio.start + SZ_64K - 1; + pci_remap_iospace(&realio, MV78XX0_PCIE_IO_PHYS_BASE(nr)); pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 76951bfbacf5..92e938bba20d 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -142,6 +142,7 @@ static struct pci_ops pcie_ops = { static int __init pcie_setup(struct pci_sys_data *sys) { struct resource *res; + struct resource realio; int dev; /* @@ -164,7 +165,9 @@ static int __init pcie_setup(struct pci_sys_data *sys) pcie_ops.read = pcie_rd_conf_wa; } - pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE); + realio.start = sys->busnr * SZ_64K; + realio.end = realio.start + SZ_64K - 1; + pci_remap_iospace(&realio, ORION5X_PCIE_IO_PHYS_BASE); /* * Request resources. @@ -466,6 +469,7 @@ static void __init orion5x_setup_pci_wins(void) static int __init pci_setup(struct pci_sys_data *sys) { struct resource *res; + struct resource realio; /* * Point PCI unit MBUS decode windows to DRAM space. @@ -482,7 +486,9 @@ static int __init pci_setup(struct pci_sys_data *sys) */ orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); - pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE); + realio.start = sys->busnr * SZ_64K; + realio.end = realio.start + SZ_64K - 1; + pci_remap_iospace(&realio, ORION5X_PCI_IO_PHYS_BASE); /* * Request resources diff --git a/drivers/pcmcia/at91_cf.c b/drivers/pcmcia/at91_cf.c index 6b1edfc890a3..92df2c2c5d07 100644 --- a/drivers/pcmcia/at91_cf.c +++ b/drivers/pcmcia/at91_cf.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -230,6 +231,7 @@ static int at91_cf_probe(struct platform_device *pdev) struct at91_cf_socket *cf; struct at91_cf_data *board; struct resource *io; + struct resource realio; int status; board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL); @@ -307,7 +309,9 @@ static int at91_cf_probe(struct platform_device *pdev) * io_offset is set to 0x10000 to avoid the check in static_find_io(). * */ cf->socket.io_offset = 0x10000; - status = pci_ioremap_io(0x10000, cf->phys_baseaddr + CF_IO_PHYS); + realio.start = cf->socket.io_offset; + realio.end = realio.start + SZ_64K - 1; + status = pci_remap_iospace(&realio, cf->phys_baseaddr + CF_IO_PHYS); if (status) goto fail0a; -- cgit v1.2.3 From 600b790309864fcc311b5dc701f8dc5c3b81374c Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 24 Nov 2021 16:41:16 +0100 Subject: arm: ioremap: Remove unused ARM-specific function pci_ioremap_io() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This function is not used by any driver anymore. So completely remove it. Link: https://lore.kernel.org/r/20211124154116.916-6-pali@kernel.org Signed-off-by: Pali Rohár Signed-off-by: Lorenzo Pieralisi Reviewed-by: Russell King (Oracle) --- arch/arm/include/asm/io.h | 2 -- arch/arm/mm/ioremap.c | 11 ----------- 2 files changed, 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 12eca75bdee9..0c70eb688a00 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -180,8 +180,6 @@ void pci_ioremap_set_mem_type(int mem_type); static inline void pci_ioremap_set_mem_type(int mem_type) {} #endif -extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); - struct resource; #define pci_remap_iospace pci_remap_iospace diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index fa3bde48d6a7..197f8eb3a775 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -474,17 +474,6 @@ int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) } EXPORT_SYMBOL(pci_remap_iospace); -int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr) -{ - BUG_ON(offset + SZ_64K - 1 > IO_SPACE_LIMIT); - - return ioremap_page_range(PCI_IO_VIRT_BASE + offset, - PCI_IO_VIRT_BASE + offset + SZ_64K, - phys_addr, - __pgprot(get_mem_type(pci_ioremap_mem_type)->prot_pte)); -} -EXPORT_SYMBOL_GPL(pci_ioremap_io); - void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size) { return arch_ioremap_caller(res_cookie, size, MT_UNCACHED, -- cgit v1.2.3 From 671f852c1bee9bd7138a5c4ad2c88d379cd0a6cb Mon Sep 17 00:00:00 2001 From: Evgeny Boger Date: Mon, 22 Nov 2021 13:46:16 +0300 Subject: ARM: dts: sun8i: r40: add node for CAN controller Allwinner R40 (also known as A40i, T3, V40) has a CAN controller. The controller is the same as in earlier A10 and A20 SoCs, but needs reset line to be deasserted before use. This patch adds a CAN node and the corresponding pinctrl descriptions. Link: https://lore.kernel.org/all/20211122104616.537156-4-boger@wirenboard.com Signed-off-by: Evgeny Boger Signed-off-by: Marc Kleine-Budde --- arch/arm/boot/dts/sun8i-r40.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 1d87fc0c24ee..c99c92f008a0 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -511,6 +511,16 @@ #interrupt-cells = <3>; #gpio-cells = <3>; + can_ph_pins: can-ph-pins { + pins = "PH20", "PH21"; + function = "can"; + }; + + can_pa_pins: can-pa-pins { + pins = "PA16", "PA17"; + function = "can"; + }; + clk_out_a_pin: clk-out-a-pin { pins = "PI12"; function = "clk_out_a"; @@ -926,6 +936,15 @@ #size-cells = <0>; }; + can0: can@1c2bc00 { + compatible = "allwinner,sun8i-r40-can"; + reg = <0x01c2bc00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_CAN>; + resets = <&ccu RST_BUS_CAN>; + status = "disabled"; + }; + i2c4: i2c@1c2c000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2c000 0x400>; -- cgit v1.2.3 From 12f332d2dd3187472f595b678246adb10d886bd0 Mon Sep 17 00:00:00 2001 From: Hari Prasath Date: Wed, 8 Dec 2021 12:05:53 +0530 Subject: ARM: dts: at91: update alternate function of signal PD20 The alternate function of PD20 is 4 as per the datasheet of sama7g5 and not 5 as defined earlier. Signed-off-by: Hari Prasath Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Cc: # v5.15+ Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211208063553.19807-1-Hari.PrasathGE@microchip.com --- arch/arm/boot/dts/sama7g5-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama7g5-pinfunc.h b/arch/arm/boot/dts/sama7g5-pinfunc.h index 22fe9e522a97..4eb30445d205 100644 --- a/arch/arm/boot/dts/sama7g5-pinfunc.h +++ b/arch/arm/boot/dts/sama7g5-pinfunc.h @@ -765,7 +765,7 @@ #define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) #define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) #define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) -#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 5, 2) +#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 4, 2) #define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) #define PIN_PD21 117 #define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) -- cgit v1.2.3 From 0de4ab81ab26f09d4dbf8142a881b4607070d01f Mon Sep 17 00:00:00 2001 From: Michal Vokáč Date: Mon, 22 Nov 2021 17:25:20 +0100 Subject: ARM: dts: imx6dl-yapp4: Add Y Soft IOTA Crux/Crux+ board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devicetrees for the new boards in the Y Soft IOTA family. These boards are based on Orion but use Quad/QuadPlus SoC instead of DualLite. Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 ++ arch/arm/boot/dts/imx6q-yapp4-crux.dts | 54 ++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts | 54 ++++++++++++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-yapp4-crux.dts create mode 100644 arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e462dbe75f6a..51a6dd687191 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -632,6 +632,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-wandboard.dtb \ imx6q-wandboard-revb1.dtb \ imx6q-wandboard-revd1.dtb \ + imx6q-yapp4-crux.dtb \ imx6q-zii-rdu2.dtb \ imx6qp-mba6b.dtb \ imx6qp-nitrogen6_max.dtb \ @@ -646,6 +647,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6qp-tx6qp-8137-mb7.dtb \ imx6qp-vicutp.dtb \ imx6qp-wandboard-revd1.dtb \ + imx6qp-yapp4-crux-plus.dtb \ imx6qp-zii-rdu2.dtb \ imx6s-dhcom-drc02.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ diff --git a/arch/arm/boot/dts/imx6q-yapp4-crux.dts b/arch/arm/boot/dts/imx6q-yapp4-crux.dts new file mode 100644 index 000000000000..15f4824a5142 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-yapp4-crux.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Crux i.MX6Quad board"; + compatible = "ysoft,imx6q-yapp4-crux", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts b/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts new file mode 100644 index 000000000000..cea165f2161a --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6qp.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Crux+ i.MX6QuadPlus board"; + compatible = "ysoft,imx6qp-yapp4-crux-plus", "fsl,imx6qp"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; -- cgit v1.2.3 From bb29e4091079dd7ef5bd488bd7625965cdfd2c12 Mon Sep 17 00:00:00 2001 From: Wan Jiabing Date: Thu, 14 Oct 2021 04:45:55 -0400 Subject: ARM: at91: pm: Add of_node_put() before goto Fix following coccicheck warning: ./arch/arm/mach-at91/pm.c:643:1-33: WARNING: Function for_each_matching_node_and_match should have of_node_put() before goto Early exits from for_each_matching_node_and_match should decrement the node reference counter. Signed-off-by: Wan Jiabing Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211014084555.21422-1-wanjiabing@vivo.com --- arch/arm/mach-at91/pm.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 8711d6824c1f..dd6f4ce3f766 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -645,6 +645,7 @@ static __init int at91_dt_ramc(bool phy_mandatory) if (!soc_pm.data.ramc[idx]) { pr_err("unable to map ramc[%d] cpu registers\n", idx); ret = -ENOMEM; + of_node_put(np); goto unmap_ramc; } @@ -670,6 +671,7 @@ static __init int at91_dt_ramc(bool phy_mandatory) if (!soc_pm.data.ramc_phy) { pr_err("unable to map ramc phy cpu registers\n"); ret = -ENOMEM; + of_node_put(np); goto unmap_ramc; } } -- cgit v1.2.3 From 6d4518a086b2cce1f7935eb5a88a7f03e241f640 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Tue, 26 Oct 2021 16:20:34 +0300 Subject: ARM: dts: at91: sama5d2_xplained: remove PA11__SDMMC0_VDDSEL from pinctrl I/O voltage for eMMC is always 3.3V because PA11__SDMMC0_VDDSEL is tied with 10K resistor to GND. U13 switch S1 is always selected as voltage rail of 3.3V for VCCQ power pin from MPU controller and eMMC flash. Removing PA11 from pinctrl because it remains unused. Signed-off-by: Mihai Sain Reviewed-by: Eugen Hristev Signed-off-by: Eugen Hristev Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211026132034.678655-1-eugen.hristev@microchip.com --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index b1e854f658de..9bf2ec0ba3e2 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -66,7 +66,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc0_default>; non-removable; - mmc-ddr-1_8v; + mmc-ddr-3_3v; status = "okay"; }; @@ -619,10 +619,9 @@ bias-disable; }; - ck_cd_rstn_vddsel { + ck_cd_rstn { pinmux = , , - , ; bias-disable; }; -- cgit v1.2.3 From b3111fe15df5e420f5251bad612fcf6915392c92 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Thu, 11 Nov 2021 09:10:45 +0100 Subject: ARM: dts: at91: add Microchip EVB-KSZ9477 board Add KSZ9477 managed switch evaluation kit with SAMA5D36 MPU: https://www.microchip.com/en-us/development-tool/evb-ksz9477 Signed-off-by: Oleksij Rempel Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211111081045.711323-1-o.rempel@pengutronix.de --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts | 209 +++++++++++++++++++++++++ 2 files changed, 210 insertions(+) create mode 100644 arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..f79585f6e80b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -61,6 +61,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d2_icp.dtb \ at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ + at91-sama5d3_ksz9477_evb.dtb \ at91-sama5d3_xplained.dtb \ at91-dvk_som60.dtb \ at91-gatwick.dtb \ diff --git a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts new file mode 100644 index 000000000000..443e8b022897 --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 Oleksij Rempel , Pengutronix + */ +/dts-v1/; +#include "sama5d36.dtsi" + +/ { + model = "EVB-KSZ9477"; + compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36", + "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = &dbgu; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vcc_mmc0: regulator-mmc0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcc0_vcc>; + regulator-name = "mmc0-vcc"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + }; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; +}; + +&macb0 { + phy-mode = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&mmc0 { + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <®_vcc_mmc0>; + vqmmc-supply = <®_3v3>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&spi0 { + cs-gpios = <&pioD 13 GPIO_ACTIVE_LOW>, <0>, <0>, + <&pioD 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&pinctrl_spi_ksz>; + cs-gpios = <&pioC 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + switch@0 { + compatible = "microchip,ksz9477"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpha; + spi-cpol; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "lan5"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&macb0>; + phy-mode = "rgmii-txid"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + board { + pinctrl_i2c0_pu: i2c0-pu { + atmel,pins = + , + ; + }; + + pinctrl_mmc0_cd: mmc0-cd { + atmel,pins = ; + }; + + pinctrl_mcc0_vcc: mmc0-vcc { + atmel,pins = ; + }; + + pinctrl_spi_ksz: spi-ksz { + atmel,pins = + < + /* SPI1_MISO */ + AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + /* SPI1_MOSI */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE + /* SPI1_SPCK */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE + + /* SPI CS */ + AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + /* switch IRQ */ + AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH + /* switch PME_N, SoC IN */ + AT91_PIOC 30 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP + /* switch RST */ + AT91_PIOC 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH + >; + }; + + pinctrl_usba_vbus: usba-vbus { + atmel,pins = + ; + }; + }; +}; -- cgit v1.2.3 From 36b88b209593f6e103fdc4df369fcdedc7f2f1c9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 20 Oct 2021 02:40:59 +0300 Subject: ARM: dts: elpida_ecb240abacn: Change Elpida compatible Vendor prefix shouldn't start with capital letter. The Elpida Memory compatible was never used in practice, hence just correct the compatible. Signed-off-by: Dmitry Osipenko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi index d87ee4794f83..9698801cbcfb 100644 --- a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi +++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi @@ -5,7 +5,7 @@ / { elpida_ECB240ABACN: lpddr2 { - compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; + compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4"; density = <2048>; io-width = <32>; -- cgit v1.2.3 From f3499b1329c9af605874df0664ee0e245687b72b Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 18 Oct 2021 15:00:19 -0700 Subject: ARM: dts: am335x-boneblack-common: move system-power-controller Move the rtc node system-power-controller property from am335x-boneblack-common.dtsi to am335x-bone-common.dtsi. am335x-boneblack-common.dtsi is included by am335x-boneblack.dts, am335x-boneblack-wireless.dts, am335x-sancloud-bbe.dts and am335x-sancloud-bbe-lite.dts. All of these dts files also include am335x-bone-common.dtsi and thus will retain the rtc node system-power-controller property. am335x-bone-common.dtsi is also included by am335x-bone.dts [1], am335x-bonegreen.dts [2] and am335x-bonegreen-wireless.dts [3]. These boards will now have the rtc node system-power-controller property too. This is valid as they also have PMIC_POWR_EN (ZCZ C6) connected to PWR_EN on the TPS65217B PMIC. Based on commit 15c7be47fb7c ("ARM: dts: am335x: Add rtc node as system-power-controller") by Keerthy in ti-linux-5.4.y branch [4]. [1] https://beagleboard.org/static/beaglebone/BEAGLEBONE_SCHEM_A3.pdf [2] https://github.com/SeeedDocument/BeagleBone_Green/blob/master/resources/BEAGLEBONE_GREEN_V1.pdf [3] https://github.com/SeeedDocument/BeagleBone_Green_Wireless/blob/master/resources/BeagleBone_Green%20Wireless_V1.0_SCH_20160314.pdf [4] git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git Cc: Jason Kridner Cc: Dave Gerlach Cc: Keerthy Link: https://lore.kernel.org/linux-omap/20211012191311.879838-1-dfustini@baylibre.com/ Suggested-by: Johan Hovold Reviewed-by: Johan Hovold Signed-off-by: Drew Fustini Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone-common.dtsi | 1 + arch/arm/boot/dts/am335x-boneblack-common.dtsi | 4 ---- 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 0ccdc7cd463b..56ae5095a5b8 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -399,6 +399,7 @@ &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; + system-power-controller; }; &pruss_tm { diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/am335x-boneblack-common.dtsi index 10494c4431b9..a7a8c61ef9b2 100644 --- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi +++ b/arch/arm/boot/dts/am335x-boneblack-common.dtsi @@ -22,10 +22,6 @@ non-removable; }; -&rtc { - system-power-controller; -}; - / { memory@80000000 { device_type = "memory"; -- cgit v1.2.3 From 1e72c64eb75e99cfcd62c2678f4c465d1213170c Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 18 Oct 2021 15:00:20 -0700 Subject: ARM: dts: am335x-icev2: Add system-power-controller to RTC node On the am335x-icev2 board [1], AM3359 PMIC_PWR_EN (ZCZ ball C6) is connected to PWRHOLD (pin 1) on the TPS65910A3 PMIC. The addition of system-power-controller to the rtc node will enable the capability of the RTC driver to poweroff the board. Based on commit 15c7be47fb7c ("ARM: dts: am335x: Add rtc node as system-power-controller") by Keerthy in ti-linux-5.4.y branch [2]. [1] https://www.ti.com/tool/TMDSICE3359 [2] git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git Cc: Dave Gerlach Cc: Keerthy Link: https://lore.kernel.org/linux-omap/20211012191311.879838-1-dfustini@baylibre.com/ Suggested-by: Johan Hovold Signed-off-by: Drew Fustini Reviewed-by: Johan Hovold Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-icev2.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index e5ce89c8f54d..5835c0cdda50 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -512,3 +512,7 @@ &pruss_tm { status = "okay"; }; + +&rtc { + system-power-controller; +}; -- cgit v1.2.3 From d2e8a6c43bbf61200e5fcb3199efc2680af32bc1 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 26 Nov 2021 15:24:11 +0100 Subject: ARM: dts: am437x-cm-t43: Use a correctly spelled DT property Back in 2014 a property got misspelled "ti,coordiante-readouts" instead of "ti,coordinate-readouts". The year after it got fixed but both are still supported, although this is not a reason to continue using this old deprecated property. Signed-off-by: Miquel Raynal Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-cm-t43.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index 5ce8e684e7d3..3e3354780db8 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -399,7 +399,7 @@ tsc { ti,wires = <4>; ti,x-plate-resistance = <200>; - ti,coordiante-readouts = <5>; + ti,coordinate-readouts = <5>; ti,wire-config = <0x00 0x11 0x22 0x33>; }; -- cgit v1.2.3 From 6c06a9f55b5fc9f48950bedfe8d5b74748a21e76 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 26 Nov 2021 15:24:12 +0100 Subject: ARM: dts: am43xx: Describe the magnetic reader/ADC1 hardware module This hardware module is close to the am33xx ADC module but instead of featuring a touchscreen it has a magnetic reader capability. Signed-off-by: Miquel Raynal Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 31 +++++++++++++++++++++++++++++-- arch/arm/boot/dts/am43xx-clocks.dtsi | 7 +++++++ 2 files changed, 36 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index ba58e6b0da1d..8f2268c02778 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -2378,11 +2378,38 @@ }; target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4c000 0x4>, + <0x4c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + clocks = <&l3s_clkctrl AM4_L3S_ADC1_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4c000 0x2000>; + + magadc: magadc@0 { + compatible = "ti,am4372-magadc"; + reg = <0x0 0x2000>; + interrupts = ; + clocks = <&adc_mag_fck>; + clock-names = "fck"; + dmas = <&edma 54 0>, <&edma 55 0>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + mag { + compatible = "ti,am4372-mag"; + }; + + adc { + #io-channel-cells = <1>; + compatible ="ti,am4372-adc"; + }; + }; }; target-module@80000 { /* 0x48380000, ap 123 42.0 */ diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 314fc5975acb..66e892fa3398 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -444,6 +444,13 @@ reg = <0x422c>; }; + adc_mag_fck: adc_mag_fck@424c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_per_m2_ck>; + reg = <0x424c>; + }; + l3_gclk: l3_gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; -- cgit v1.2.3 From 6fde719b19af7e82671c352c69981c75ca9909c2 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 26 Nov 2021 15:24:13 +0100 Subject: ARM: dts: am437x-gp-evm: enable ADC1 ADC0 and ADC1 pins are available on external connector J22. Enable ADC1 which was missing. Signed-off-by: Miquel Raynal Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index c2e4896076e7..4416ddb559e4 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -775,6 +775,14 @@ }; }; +&magadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + &ecap0 { status = "okay"; pinctrl-names = "default"; -- cgit v1.2.3 From 7ebe6e99f7702dad342486e5b30d989a0a6499af Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 3 Dec 2021 15:10:43 +0100 Subject: ARM: dts: motorola-mapphone: Drop second ti,wlcore compatible value The TI wlcore DT bindings specify using a single compatible value for each variant, and the Linux kernel driver matches against the first compatible value since commit 078b30da3f074f2e ("wlcore: add wl1285 compatible") in v4.13. Signed-off-by: Geert Uytterhoeven Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/motorola-mapphone-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index a4423ff0df39..c7a1f3ffc48c 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -310,7 +310,7 @@ #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { - compatible = "ti,wl1285", "ti,wl1283"; + compatible = "ti,wl1285"; reg = <2>; /* gpio_100 with gpmc_wait2 pad as wakeirq */ interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>, -- cgit v1.2.3 From fa0fdb78cb5d4cde00430ec481f09fbe7c029376 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 15:48:02 +0100 Subject: ARM: dts: am335x: Use correct vendor prefix for Asahi Kasei Corp. The old "ak" vendor prefix that was never officially accepted was still being used in some device trees. Convert to the correct vendor prefix (i.e. "asahi-kasei"). Signed-off-by: Thierry Reding Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblue.dts | 2 +- arch/arm/boot/dts/am335x-osd3358-sm-red.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index c6bb325ead33..147c00de3795 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -341,7 +341,7 @@ #address-cells = <1>; #size-cells = <0>; ax8975@c { - compatible = "ak,ak8975"; + compatible = "asahi-kasei,ak8975"; reg = <0x0c>; }; }; diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts index 605b2a436edf..b2846cd220f0 100644 --- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts +++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts @@ -84,7 +84,7 @@ #address-cells = <1>; #size-cells = <0>; ax8975@c { - compatible = "ak,ak8975"; + compatible = "asahi-kasei,ak8975"; reg = <0x0c>; }; }; -- cgit v1.2.3 From 7b9eb6cfdb784ad713024a3f8f202620ad40ba70 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sun, 12 Dec 2021 18:49:40 +0100 Subject: ARM: dts: ixp4xx: Add devicetree for Gateway 7001 This adds a device tree for the Gateway 7001 AP, based on Intel IXP422. Cc: Imre Kaloz Signed-off-by: Zoltan HERPAI Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts | 111 ++++++++++++++++++++++++ 2 files changed, 113 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4084535c6489..7dfda6be2916 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -269,7 +269,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp42x-gateworks-gw2348.dtb \ intel-ixp43x-gateworks-gw2358.dtb \ intel-ixp42x-netgear-wg302v2.dtb \ - intel-ixp42x-arcom-vulcan.dtb + intel-ixp42x-arcom-vulcan.dtb \ + intel-ixp42x-gateway-7001.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += \ keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ diff --git a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts new file mode 100644 index 000000000000..a1c03c965f17 --- /dev/null +++ b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Gateway 7001 AP + * Derived from boardfiles written by Imre Kaloz + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model = "Gateway 7001 AP"; + compatible = "gateway,7001", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 32 MB SDRAM */ + device_type = "memory"; + reg = <0x00000000 0x2000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart1:115200n8"; + }; + + aliases { + /* second UART is the primary console */ + serial0 = &uart1; + serial1 = &uart0; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 8 MB of flash + */ + reg = <0 0x00000000 0x800000>; + + /* Configure expansion bus to allow writes */ + intel,ixp4xx-eb-write-enable = <1>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; + }; + }; + }; + + pci@c0000000 { + status = "ok"; + + /* + * Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c) + * We have slots (IDSEL) 1 and 2 with one assigned IRQ + * each handling all IRQs. + */ + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 11 */ + <0x0800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 11 */ + <0x0800 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 11 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */ + <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */ + <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */ + }; + + ethernet@c8009000 { + status = "ok"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + ethernet@c800a000 { + status = "ok"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy2>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + }; + }; + }; +}; -- cgit v1.2.3 From 5e8c1bf1a0a5c728cee2b6c2162348a9dfddf1bf Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 30 Nov 2021 17:11:47 +0100 Subject: ARM: dts: bcm2711-rpi-4-b: Add gpio offsets to line name array MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this helps human readers considerably to determine the line name for a given offset or vice versa. Signed-off-by: Uwe Kleine-König [ nsaenz: corrected patch title ] Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/20211130161147.317653-1-u.kleine-koenig@pengutronix.de --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 631dd5baf68d..4432412044de 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -65,12 +65,12 @@ }; &expgpio { - gpio-line-names = "BT_ON", + gpio-line-names = "BT_ON", /* 0 */ "WL_ON", "PWR_LED_OFF", "GLOBAL_RESET", "VDD_SD_IO_SEL", - "CAM_GPIO", + "CAM_GPIO", /* 5 */ "SD_PWR_ON", ""; }; @@ -84,66 +84,66 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "ID_SDA", + gpio-line-names = "ID_SDA", /* 0 */ "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", - "GPIO5", + "GPIO5", /* 5 */ "GPIO6", "SPI_CE1_N", "SPI_CE0_N", "SPI_MISO", - "SPI_MOSI", + "SPI_MOSI", /* 10 */ "SPI_SCLK", "GPIO12", "GPIO13", /* Serial port */ "TXD1", - "RXD1", + "RXD1", /* 15 */ "GPIO16", "GPIO17", "GPIO18", "GPIO19", - "GPIO20", + "GPIO20", /* 20 */ "GPIO21", "GPIO22", "GPIO23", "GPIO24", - "GPIO25", + "GPIO25", /* 25 */ "GPIO26", "GPIO27", "RGMII_MDIO", "RGMIO_MDC", /* Used by BT module */ - "CTS0", + "CTS0", /* 30 */ "RTS0", "TXD0", "RXD0", /* Used by Wifi */ "SD1_CLK", - "SD1_CMD", + "SD1_CMD", /* 35 */ "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* Shared with SPI flash */ - "PWM0_MISO", + "PWM0_MISO", /* 40 */ "PWM1_MOSI", "STATUS_LED_G_CLK", "SPIFLASH_CE_N", "SDA0", - "SCL0", + "SCL0", /* 45 */ "RGMII_RXCLK", "RGMII_RXCTL", "RGMII_RXD0", "RGMII_RXD1", - "RGMII_RXD2", + "RGMII_RXD2", /* 50 */ "RGMII_RXD3", "RGMII_TXCLK", "RGMII_TXCTL", "RGMII_TXD0", - "RGMII_TXD1", + "RGMII_TXD1", /* 55 */ "RGMII_TXD2", "RGMII_TXD3"; }; -- cgit v1.2.3 From c0d6316c238b1bd743108bd4b08eda364f47c7c9 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Fri, 10 Dec 2021 16:31:22 -0600 Subject: ARM: dts: qcom: sdx55: fix IPA interconnect definitions The first two interconnects defined for IPA on the SDX55 SoC are really two parts of what should be represented as a single path between IPA and system memory. Fix this by combining the "memory-a" and "memory-b" interconnects into a single "memory" interconnect. Reported-by: David Heidelberg Tested-by: Manivannan Sadhasivam Signed-off-by: Alex Elder Signed-off-by: David S. Miller --- arch/arm/boot/dts/qcom-sdx55.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 44526ad9d210..eee2f63b9bba 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -333,12 +333,10 @@ clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; - interconnects = <&system_noc MASTER_IPA &system_noc SLAVE_SNOC_MEM_NOC_GC>, - <&mem_noc MASTER_SNOC_GC_MEM_NOC &mc_virt SLAVE_EBI_CH0>, + interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>, <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>; - interconnect-names = "memory-a", - "memory-b", + interconnect-names = "memory", "imem", "config"; -- cgit v1.2.3 From cf4060f1bb643495742f3630ab98a7b44fc5c0fd Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 12:25:42 +0200 Subject: ARM: dts: at91: sama5d2: Name the qspi clock Naming clocks is a good practice. The atmel-quadspi driver supports an unnamed clock for the peripheral clock in order to be backward compatible with old DTs, but it is recommended to name the clocks on new DTs. The driver's bindings file requires the clock-names property, so name the clock. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209102542.254153-1-tudor.ambarus@microchip.com --- arch/arm/boot/dts/sama5d2.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 801969c113d6..09c741e8ecb8 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -288,6 +288,7 @@ reg-names = "qspi_base", "qspi_mmap"; interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; + clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -299,6 +300,7 @@ reg-names = "qspi_base", "qspi_mmap"; interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; + clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit v1.2.3 From 0081a525ceef14e950172def4af14c3f652fb4a2 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 14:36:42 +0200 Subject: ARM: dts: at91: sama7g5: Add QSPI nodes sama7g5 embedds 2 instances of QSPI controller: 1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported. 2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209123643.341892-1-tudor.ambarus@microchip.com --- arch/arm/boot/dts/sama7g5.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 7039311bf678..eddcfbf4d223 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -181,6 +181,36 @@ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; + qspi0: spi@e080c000 { + compatible = "microchip,sama7g5-ospi"; + reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, + <&dma0 AT91_XDMAC_DT_PERID(40)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; + clock-names = "pclk", "gclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi1: spi@e0810000 { + compatible = "microchip,sama7g5-qspi"; + reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, + <&dma0 AT91_XDMAC_DT_PERID(42)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; + clock-names = "pclk", "gclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + adc: adc@e1000000 { compatible = "microchip,sama7g5-adc"; reg = <0xe1000000 0x200>; -- cgit v1.2.3 From 078c2a0e8e60bb3fe78cf50b5da1620a4e13e0cd Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 14:36:43 +0200 Subject: ARM: dts: at91: sama7g5ek: Add QSPI0 node QSPI0 comunicates with a MX66LM1G45G SPI NOR flash. Enable the controller and describe the flash. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209123643.341892-2-tudor.ambarus@microchip.com --- arch/arm/boot/dts/at91-sama7g5ek.dts | 73 ++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 0e1975c6812e..ccf9e224da78 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -13,6 +13,7 @@ #include "sama7g5.dtsi" #include #include +#include / { model = "Microchip SAMA7G5-EK"; @@ -134,6 +135,59 @@ cpu-supply = <&vddcpu>; }; +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + m25p,fast-read; + + at91bootstrap@0 { + label = "ospi: at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "ospi: bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "ospi: bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "ospi: bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "ospi: device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "ospi: kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "ospi: rootfs"; + reg = <0x800000 0x7800000>; + }; + + }; +}; + &dma0 { status = "okay"; }; @@ -555,6 +609,25 @@ bias-disable; }; + pinctrl_qspi: qspi { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + slew-rate = <0>; + atmel,drive-strength = ; + }; + pinctrl_sdmmc0_default: sdmmc0_default { cmd_data { pinmux = , -- cgit v1.2.3 From 5d7248e956e68f257b46cdfcee465792086e2c01 Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Thu, 2 Dec 2021 10:52:53 +0100 Subject: ARM: dts: spear3xx: Use plgpio regmap in SPEAr310 and SPEAr320 Resources used by plgpio and pinmux are conflicting on SPEAr310 and SPEAr320. Use the newly introduced regmap property in plgpio node to use pinmux resources from plgpio and so avoid the conflict. Signed-off-by: Herve Codina Link: https://lore.kernel.org/r/20211202095255.165797-5-herve.codina@bootlin.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/spear310.dtsi | 1 + arch/arm/boot/dts/spear320.dtsi | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi index 8ce751a1376d..77570833d46b 100644 --- a/arch/arm/boot/dts/spear310.dtsi +++ b/arch/arm/boot/dts/spear310.dtsi @@ -92,6 +92,7 @@ gpiopinctrl: gpio@b4000000 { compatible = "st,spear-plgpio"; reg = <0xb4000000 0x1000>; + regmap = <&pinmux>; #interrupt-cells = <1>; interrupt-controller; gpio-controller; diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi index 3bc1e93a0a55..47ac4474ed96 100644 --- a/arch/arm/boot/dts/spear320.dtsi +++ b/arch/arm/boot/dts/spear320.dtsi @@ -120,6 +120,7 @@ gpiopinctrl: gpio@b3000000 { compatible = "st,spear-plgpio"; reg = <0xb3000000 0x1000>; + regmap = <&pinmux>; #interrupt-cells = <1>; interrupt-controller; gpio-controller; -- cgit v1.2.3 From 7cf4cc3e8524989f9f1619ba49726576a46ee32d Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Thu, 2 Dec 2021 10:52:55 +0100 Subject: ARM: dts: spear3xx: Add spear320s dtsi The SPEAr320s SOC is a SPEAr320 SOC variant. Mostly identical to the SPEAr320 SOC variant, it has a new interrupt routing for PL_PGIOs. Add spear320s.dtsi to handle SPEAr320s SOC Signed-off-by: Herve Codina Link: https://lore.kernel.org/r/20211202095255.165797-7-herve.codina@bootlin.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/spear320s.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 arch/arm/boot/dts/spear320s.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/spear320s.dtsi b/arch/arm/boot/dts/spear320s.dtsi new file mode 100644 index 000000000000..133236dc190d --- /dev/null +++ b/arch/arm/boot/dts/spear320s.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DTS file for SPEAr320s SoC + * + * Copyright 2021 Herve Codina + */ + +/include/ "spear320.dtsi" + +/ { + ahb { + apb { + gpiopinctrl: gpio@b3000000 { + /* + * The "RM0321 SPEAr320s address and map + * registers" document mentions interrupt 6 + * (NPGIO_INTR) for the PL_GPIO interrupt. + */ + interrupts = <6>; + interrupt-parent = <&shirq>; + }; + }; + }; +}; -- cgit v1.2.3 From 0e25498f8cd43c1b5aa327f373dd094e9a006da7 Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Mon, 28 Jun 2021 14:52:01 -0500 Subject: exit: Add and use make_task_dead. There are two big uses of do_exit. The first is it's design use to be the guts of the exit(2) system call. The second use is to terminate a task after something catastrophic has happened like a NULL pointer in kernel code. Add a function make_task_dead that is initialy exactly the same as do_exit to cover the cases where do_exit is called to handle catastrophic failure. In time this can probably be reduced to just a light wrapper around do_task_dead. For now keep it exactly the same so that there will be no behavioral differences introducing this new concept. Replace all of the uses of do_exit that use it for catastraphic task cleanup with make_task_dead to make it clear what the code is doing. As part of this rename rewind_stack_do_exit rewind_stack_and_make_dead. Signed-off-by: "Eric W. Biederman" --- arch/alpha/kernel/traps.c | 6 +++--- arch/alpha/mm/fault.c | 2 +- arch/arm/kernel/traps.c | 2 +- arch/arm/mm/fault.c | 2 +- arch/arm64/kernel/traps.c | 2 +- arch/arm64/mm/fault.c | 2 +- arch/csky/abiv1/alignment.c | 2 +- arch/csky/kernel/traps.c | 2 +- arch/csky/mm/fault.c | 2 +- arch/h8300/kernel/traps.c | 2 +- arch/h8300/mm/fault.c | 2 +- arch/hexagon/kernel/traps.c | 2 +- arch/ia64/kernel/mca_drv.c | 2 +- arch/ia64/kernel/traps.c | 2 +- arch/ia64/mm/fault.c | 2 +- arch/m68k/kernel/traps.c | 2 +- arch/m68k/mm/fault.c | 2 +- arch/microblaze/kernel/exceptions.c | 4 ++-- arch/mips/kernel/traps.c | 2 +- arch/nds32/kernel/fpu.c | 2 +- arch/nds32/kernel/traps.c | 8 ++++---- arch/nios2/kernel/traps.c | 4 ++-- arch/openrisc/kernel/traps.c | 2 +- arch/parisc/kernel/traps.c | 2 +- arch/powerpc/kernel/traps.c | 8 ++++---- arch/riscv/kernel/traps.c | 2 +- arch/riscv/mm/fault.c | 2 +- arch/s390/kernel/dumpstack.c | 2 +- arch/s390/kernel/nmi.c | 2 +- arch/sh/kernel/traps.c | 2 +- arch/sparc/kernel/traps_32.c | 4 +--- arch/sparc/kernel/traps_64.c | 4 +--- arch/x86/entry/entry_32.S | 6 +++--- arch/x86/entry/entry_64.S | 6 +++--- arch/x86/kernel/dumpstack.c | 4 ++-- arch/xtensa/kernel/traps.c | 2 +- include/linux/sched/task.h | 1 + kernel/exit.c | 9 +++++++++ tools/objtool/check.c | 3 ++- 39 files changed, 63 insertions(+), 56 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c index 2ae34702456c..8a66fe544c69 100644 --- a/arch/alpha/kernel/traps.c +++ b/arch/alpha/kernel/traps.c @@ -190,7 +190,7 @@ die_if_kernel(char * str, struct pt_regs *regs, long err, unsigned long *r9_15) local_irq_enable(); while (1); } - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); } #ifndef CONFIG_MATHEMU @@ -575,7 +575,7 @@ do_entUna(void * va, unsigned long opcode, unsigned long reg, printk("Bad unaligned kernel access at %016lx: %p %lx %lu\n", pc, va, opcode, reg); - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); got_exception: /* Ok, we caught the exception, but we don't want it. Is there @@ -630,7 +630,7 @@ got_exception: local_irq_enable(); while (1); } - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); } /* diff --git a/arch/alpha/mm/fault.c b/arch/alpha/mm/fault.c index eee5102c3d88..e9193d52222e 100644 --- a/arch/alpha/mm/fault.c +++ b/arch/alpha/mm/fault.c @@ -204,7 +204,7 @@ retry: printk(KERN_ALERT "Unable to handle kernel paging request at " "virtual address %016lx\n", address); die_if_kernel("Oops", regs, cause, (unsigned long*)regs - 16); - do_exit(SIGKILL); + make_task_dead(SIGKILL); /* We ran out of memory, or some other thing happened to us that made us unable to handle the page fault gracefully. */ diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 195dff58bafc..b4bd2e5f17c1 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -333,7 +333,7 @@ static void oops_end(unsigned long flags, struct pt_regs *regs, int signr) if (panic_on_oops) panic("Fatal exception"); if (signr) - do_exit(signr); + make_task_dead(signr); } /* diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index bc8779d54a64..bf1a0c618c49 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -111,7 +111,7 @@ static void die_kernel_fault(const char *msg, struct mm_struct *mm, show_pte(KERN_ALERT, mm, addr); die("Oops", regs, fsr); bust_spinlocks(0); - do_exit(SIGKILL); + make_task_dead(SIGKILL); } /* diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 7b21213a570f..bdd456e4e7f4 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -235,7 +235,7 @@ void die(const char *str, struct pt_regs *regs, int err) raw_spin_unlock_irqrestore(&die_lock, flags); if (ret != NOTIFY_STOP) - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); } static void arm64_show_signal(int signo, const char *str) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 9ae24e3b72be..11a28cace2d2 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -302,7 +302,7 @@ static void die_kernel_fault(const char *msg, unsigned long addr, show_pte(addr); die("Oops", regs, esr); bust_spinlocks(0); - do_exit(SIGKILL); + make_task_dead(SIGKILL); } #ifdef CONFIG_KASAN_HW_TAGS diff --git a/arch/csky/abiv1/alignment.c b/arch/csky/abiv1/alignment.c index cb2a0d94a144..5e2fb45d605c 100644 --- a/arch/csky/abiv1/alignment.c +++ b/arch/csky/abiv1/alignment.c @@ -294,7 +294,7 @@ bad_area: __func__, opcode, rz, rx, imm, addr); show_regs(regs); bust_spinlocks(0); - do_exit(SIGKILL); + make_dead_task(SIGKILL); } force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)addr); diff --git a/arch/csky/kernel/traps.c b/arch/csky/kernel/traps.c index e5fbf8653a21..88a47035b925 100644 --- a/arch/csky/kernel/traps.c +++ b/arch/csky/kernel/traps.c @@ -109,7 +109,7 @@ void die(struct pt_regs *regs, const char *str) if (panic_on_oops) panic("Fatal exception"); if (ret != NOTIFY_STOP) - do_exit(SIGSEGV); + make_dead_task(SIGSEGV); } void do_trap(struct pt_regs *regs, int signo, int code, unsigned long addr) diff --git a/arch/csky/mm/fault.c b/arch/csky/mm/fault.c index 466ad949818a..7215a46b6b8e 100644 --- a/arch/csky/mm/fault.c +++ b/arch/csky/mm/fault.c @@ -67,7 +67,7 @@ static inline void no_context(struct pt_regs *regs, unsigned long addr) pr_alert("Unable to handle kernel paging request at virtual " "addr 0x%08lx, pc: 0x%08lx\n", addr, regs->pc); die(regs, "Oops"); - do_exit(SIGKILL); + make_task_dead(SIGKILL); } static inline void mm_fault_error(struct pt_regs *regs, unsigned long addr, vm_fault_t fault) diff --git a/arch/h8300/kernel/traps.c b/arch/h8300/kernel/traps.c index bdbe988d8dbc..3d4e0bde37ae 100644 --- a/arch/h8300/kernel/traps.c +++ b/arch/h8300/kernel/traps.c @@ -106,7 +106,7 @@ void die(const char *str, struct pt_regs *fp, unsigned long err) dump(fp); spin_unlock_irq(&die_lock); - do_exit(SIGSEGV); + make_dead_task(SIGSEGV); } static int kstack_depth_to_print = 24; diff --git a/arch/h8300/mm/fault.c b/arch/h8300/mm/fault.c index d4bc9c16f2df..0223528565dd 100644 --- a/arch/h8300/mm/fault.c +++ b/arch/h8300/mm/fault.c @@ -51,7 +51,7 @@ asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, printk(" at virtual address %08lx\n", address); if (!user_mode(regs)) die("Oops", regs, error_code); - do_exit(SIGKILL); + make_dead_task(SIGKILL); return 1; } diff --git a/arch/hexagon/kernel/traps.c b/arch/hexagon/kernel/traps.c index edfc35dafeb1..6dd6cf0ab711 100644 --- a/arch/hexagon/kernel/traps.c +++ b/arch/hexagon/kernel/traps.c @@ -214,7 +214,7 @@ int die(const char *str, struct pt_regs *regs, long err) panic("Fatal exception"); oops_exit(); - do_exit(err); + make_dead_task(err); return 0; } diff --git a/arch/ia64/kernel/mca_drv.c b/arch/ia64/kernel/mca_drv.c index 5bfc79be4cef..23c203639a96 100644 --- a/arch/ia64/kernel/mca_drv.c +++ b/arch/ia64/kernel/mca_drv.c @@ -176,7 +176,7 @@ mca_handler_bh(unsigned long paddr, void *iip, unsigned long ipsr) spin_unlock(&mca_bh_lock); /* This process is about to be killed itself */ - do_exit(SIGKILL); + make_task_dead(SIGKILL); } /** diff --git a/arch/ia64/kernel/traps.c b/arch/ia64/kernel/traps.c index e13cb905930f..753642366e12 100644 --- a/arch/ia64/kernel/traps.c +++ b/arch/ia64/kernel/traps.c @@ -85,7 +85,7 @@ die (const char *str, struct pt_regs *regs, long err) if (panic_on_oops) panic("Fatal exception"); - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); return 0; } diff --git a/arch/ia64/mm/fault.c b/arch/ia64/mm/fault.c index 02de2e70c587..4796cccbf74f 100644 --- a/arch/ia64/mm/fault.c +++ b/arch/ia64/mm/fault.c @@ -259,7 +259,7 @@ retry: regs = NULL; bust_spinlocks(0); if (regs) - do_exit(SIGKILL); + make_task_dead(SIGKILL); return; out_of_memory: diff --git a/arch/m68k/kernel/traps.c b/arch/m68k/kernel/traps.c index 34d6458340b0..59fc63feb0dc 100644 --- a/arch/m68k/kernel/traps.c +++ b/arch/m68k/kernel/traps.c @@ -1131,7 +1131,7 @@ void die_if_kernel (char *str, struct pt_regs *fp, int nr) pr_crit("%s: %08x\n", str, nr); show_registers(fp); add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); } asmlinkage void set_esp0(unsigned long ssp) diff --git a/arch/m68k/mm/fault.c b/arch/m68k/mm/fault.c index ef46e77e97a5..fcb3a0d8421c 100644 --- a/arch/m68k/mm/fault.c +++ b/arch/m68k/mm/fault.c @@ -48,7 +48,7 @@ int send_fault_sig(struct pt_regs *regs) pr_alert("Unable to handle kernel access"); pr_cont(" at virtual address %p\n", addr); die_if_kernel("Oops", regs, 0 /*error_code*/); - do_exit(SIGKILL); + make_task_dead(SIGKILL); } return 1; diff --git a/arch/microblaze/kernel/exceptions.c b/arch/microblaze/kernel/exceptions.c index 908788497b28..fd153d5fab98 100644 --- a/arch/microblaze/kernel/exceptions.c +++ b/arch/microblaze/kernel/exceptions.c @@ -44,10 +44,10 @@ void die(const char *str, struct pt_regs *fp, long err) pr_warn("Oops: %s, sig: %ld\n", str, err); show_regs(fp); spin_unlock_irq(&die_lock); - /* do_exit() should take care of panic'ing from an interrupt + /* make_task_dead() should take care of panic'ing from an interrupt * context so we don't handle it here */ - do_exit(err); + make_task_dead(err); } /* for user application debugging */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index d26b0fb8ea06..a486486b2355 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -422,7 +422,7 @@ void __noreturn die(const char *str, struct pt_regs *regs) if (regs && kexec_should_crash(current)) crash_kexec(regs); - do_exit(sig); + make_task_dead(sig); } extern struct exception_table_entry __start___dbe_table[]; diff --git a/arch/nds32/kernel/fpu.c b/arch/nds32/kernel/fpu.c index 9edd7ed7d7bf..701c09a668de 100644 --- a/arch/nds32/kernel/fpu.c +++ b/arch/nds32/kernel/fpu.c @@ -223,7 +223,7 @@ inline void handle_fpu_exception(struct pt_regs *regs) } } else if (fpcsr & FPCSR_mskRIT) { if (!user_mode(regs)) - do_exit(SIGILL); + make_task_dead(SIGILL); si_signo = SIGILL; } diff --git a/arch/nds32/kernel/traps.c b/arch/nds32/kernel/traps.c index ca75d475eda4..c0a8f3344fb9 100644 --- a/arch/nds32/kernel/traps.c +++ b/arch/nds32/kernel/traps.c @@ -141,7 +141,7 @@ void __noreturn die(const char *str, struct pt_regs *regs, int err) bust_spinlocks(0); spin_unlock_irq(&die_lock); - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); } EXPORT_SYMBOL(die); @@ -240,7 +240,7 @@ void unhandled_interruption(struct pt_regs *regs) pr_emerg("unhandled_interruption\n"); show_regs(regs); if (!user_mode(regs)) - do_exit(SIGKILL); + make_task_dead(SIGKILL); force_sig(SIGKILL); } @@ -251,7 +251,7 @@ void unhandled_exceptions(unsigned long entry, unsigned long addr, addr, type); show_regs(regs); if (!user_mode(regs)) - do_exit(SIGKILL); + make_task_dead(SIGKILL); force_sig(SIGKILL); } @@ -278,7 +278,7 @@ void do_revinsn(struct pt_regs *regs) pr_emerg("Reserved Instruction\n"); show_regs(regs); if (!user_mode(regs)) - do_exit(SIGILL); + make_task_dead(SIGILL); force_sig(SIGILL); } diff --git a/arch/nios2/kernel/traps.c b/arch/nios2/kernel/traps.c index 596986a74a26..85ac49d64cf7 100644 --- a/arch/nios2/kernel/traps.c +++ b/arch/nios2/kernel/traps.c @@ -37,10 +37,10 @@ void die(const char *str, struct pt_regs *regs, long err) show_regs(regs); spin_unlock_irq(&die_lock); /* - * do_exit() should take care of panic'ing from an interrupt + * make_task_dead() should take care of panic'ing from an interrupt * context so we don't handle it here */ - do_exit(err); + make_task_dead(err); } void _exception(int signo, struct pt_regs *regs, int code, unsigned long addr) diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c index 0898cb159fac..0446a3c34372 100644 --- a/arch/openrisc/kernel/traps.c +++ b/arch/openrisc/kernel/traps.c @@ -212,7 +212,7 @@ void __noreturn die(const char *str, struct pt_regs *regs, long err) __asm__ __volatile__("l.nop 1"); do {} while (1); #endif - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); } /* This is normally the 'Oops' routine */ diff --git a/arch/parisc/kernel/traps.c b/arch/parisc/kernel/traps.c index b11fb26ce299..df2122c50d78 100644 --- a/arch/parisc/kernel/traps.c +++ b/arch/parisc/kernel/traps.c @@ -269,7 +269,7 @@ void die_if_kernel(char *str, struct pt_regs *regs, long err) panic("Fatal exception"); oops_exit(); - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); } /* gdb uses break 4,8 */ diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 11741703d26e..a08bb7cefdc5 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -245,7 +245,7 @@ static void oops_end(unsigned long flags, struct pt_regs *regs, if (panic_on_oops) panic("Fatal exception"); - do_exit(signr); + make_task_dead(signr); } NOKPROBE_SYMBOL(oops_end); @@ -792,9 +792,9 @@ int machine_check_generic(struct pt_regs *regs) void die_mce(const char *str, struct pt_regs *regs, long err) { /* - * The machine check wants to kill the interrupted context, but - * do_exit() checks for in_interrupt() and panics in that case, so - * exit the irq/nmi before calling die. + * The machine check wants to kill the interrupted context, + * but make_task_dead() checks for in_interrupt() and panics + * in that case, so exit the irq/nmi before calling die. */ if (in_nmi()) nmi_exit(); diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 0daaa3e4630d..fe92e119e6a3 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -54,7 +54,7 @@ void die(struct pt_regs *regs, const char *str) if (panic_on_oops) panic("Fatal exception"); if (ret != NOTIFY_STOP) - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); } void do_trap(struct pt_regs *regs, int signo, int code, unsigned long addr) diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index aa08dd2f8fae..42118bc728f9 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -31,7 +31,7 @@ static void die_kernel_fault(const char *msg, unsigned long addr, bust_spinlocks(0); die(regs, "Oops"); - do_exit(SIGKILL); + make_task_dead(SIGKILL); } static inline void no_context(struct pt_regs *regs, unsigned long addr) diff --git a/arch/s390/kernel/dumpstack.c b/arch/s390/kernel/dumpstack.c index 0681c55e831d..1e3233eb510a 100644 --- a/arch/s390/kernel/dumpstack.c +++ b/arch/s390/kernel/dumpstack.c @@ -224,5 +224,5 @@ void __noreturn die(struct pt_regs *regs, const char *str) if (panic_on_oops) panic("Fatal exception: panic_on_oops"); oops_exit(); - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); } diff --git a/arch/s390/kernel/nmi.c b/arch/s390/kernel/nmi.c index 20f8e1868853..a4d8c058dd27 100644 --- a/arch/s390/kernel/nmi.c +++ b/arch/s390/kernel/nmi.c @@ -175,7 +175,7 @@ void __s390_handle_mcck(void) "malfunction (code 0x%016lx).\n", mcck.mcck_code); printk(KERN_EMERG "mcck: task: %s, pid: %d.\n", current->comm, current->pid); - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); } } diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c index cbe3201d4f21..01884054aeb2 100644 --- a/arch/sh/kernel/traps.c +++ b/arch/sh/kernel/traps.c @@ -57,7 +57,7 @@ void __noreturn die(const char *str, struct pt_regs *regs, long err) if (panic_on_oops) panic("Fatal exception"); - do_exit(SIGSEGV); + make_task_dead(SIGSEGV); } void die_if_kernel(const char *str, struct pt_regs *regs, long err) diff --git a/arch/sparc/kernel/traps_32.c b/arch/sparc/kernel/traps_32.c index 5630e5a395e0..179aabfa712e 100644 --- a/arch/sparc/kernel/traps_32.c +++ b/arch/sparc/kernel/traps_32.c @@ -86,9 +86,7 @@ void __noreturn die_if_kernel(char *str, struct pt_regs *regs) } printk("Instruction DUMP:"); instruction_dump ((unsigned long *) regs->pc); - if(regs->psr & PSR_PS) - do_exit(SIGKILL); - do_exit(SIGSEGV); + make_task_dead((regs->psr & PSR_PS) ? SIGKILL : SIGSEGV); } void do_hw_interrupt(struct pt_regs *regs, unsigned long type) diff --git a/arch/sparc/kernel/traps_64.c b/arch/sparc/kernel/traps_64.c index 6863025ed56d..21077821f427 100644 --- a/arch/sparc/kernel/traps_64.c +++ b/arch/sparc/kernel/traps_64.c @@ -2559,9 +2559,7 @@ void __noreturn die_if_kernel(char *str, struct pt_regs *regs) } if (panic_on_oops) panic("Fatal exception"); - if (regs->tstate & TSTATE_PRIV) - do_exit(SIGKILL); - do_exit(SIGSEGV); + make_task_dead((regs->tstate & TSTATE_PRIV)? SIGKILL : SIGSEGV); } EXPORT_SYMBOL(die_if_kernel); diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S index ccb9d32768f3..7738fad6a85e 100644 --- a/arch/x86/entry/entry_32.S +++ b/arch/x86/entry/entry_32.S @@ -1248,14 +1248,14 @@ SYM_CODE_START(asm_exc_nmi) SYM_CODE_END(asm_exc_nmi) .pushsection .text, "ax" -SYM_CODE_START(rewind_stack_do_exit) +SYM_CODE_START(rewind_stack_and_make_dead) /* Prevent any naive code from trying to unwind to our caller. */ xorl %ebp, %ebp movl PER_CPU_VAR(cpu_current_top_of_stack), %esi leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp - call do_exit + call make_task_dead 1: jmp 1b -SYM_CODE_END(rewind_stack_do_exit) +SYM_CODE_END(rewind_stack_and_make_dead) .popsection diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index e38a4cf795d9..f09276457942 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -1429,7 +1429,7 @@ SYM_CODE_END(ignore_sysret) #endif .pushsection .text, "ax" -SYM_CODE_START(rewind_stack_do_exit) +SYM_CODE_START(rewind_stack_and_make_dead) UNWIND_HINT_FUNC /* Prevent any naive code from trying to unwind to our caller. */ xorl %ebp, %ebp @@ -1438,6 +1438,6 @@ SYM_CODE_START(rewind_stack_do_exit) leaq -PTREGS_SIZE(%rax), %rsp UNWIND_HINT_REGS - call do_exit -SYM_CODE_END(rewind_stack_do_exit) + call make_task_dead +SYM_CODE_END(rewind_stack_and_make_dead) .popsection diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index ea4fe192189d..53de044e5654 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -351,7 +351,7 @@ unsigned long oops_begin(void) } NOKPROBE_SYMBOL(oops_begin); -void __noreturn rewind_stack_do_exit(int signr); +void __noreturn rewind_stack_and_make_dead(int signr); void oops_end(unsigned long flags, struct pt_regs *regs, int signr) { @@ -386,7 +386,7 @@ void oops_end(unsigned long flags, struct pt_regs *regs, int signr) * reuse the task stack and that existing poisons are invalid. */ kasan_unpoison_task_stack(current); - rewind_stack_do_exit(signr); + rewind_stack_and_make_dead(signr); } NOKPROBE_SYMBOL(oops_end); diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index 4b4dbeb2d612..9345007d474d 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c @@ -552,5 +552,5 @@ void __noreturn die(const char * str, struct pt_regs * regs, long err) if (panic_on_oops) panic("Fatal exception"); - do_exit(err); + make_task_dead(err); } diff --git a/include/linux/sched/task.h b/include/linux/sched/task.h index ba88a6987400..2d4bbd9c3278 100644 --- a/include/linux/sched/task.h +++ b/include/linux/sched/task.h @@ -59,6 +59,7 @@ extern void sched_post_fork(struct task_struct *p, extern void sched_dead(struct task_struct *p); void __noreturn do_task_dead(void); +void __noreturn make_task_dead(int signr); extern void proc_caches_init(void); diff --git a/kernel/exit.c b/kernel/exit.c index f702a6a63686..bfa513c5b227 100644 --- a/kernel/exit.c +++ b/kernel/exit.c @@ -884,6 +884,15 @@ void __noreturn do_exit(long code) } EXPORT_SYMBOL_GPL(do_exit); +void __noreturn make_task_dead(int signr) +{ + /* + * Take the task off the cpu after something catastrophic has + * happened. + */ + do_exit(signr); +} + void complete_and_exit(struct completion *comp, long code) { if (comp) diff --git a/tools/objtool/check.c b/tools/objtool/check.c index 21735829b860..e6ab5687770b 100644 --- a/tools/objtool/check.c +++ b/tools/objtool/check.c @@ -168,6 +168,7 @@ static bool __dead_end_function(struct objtool_file *file, struct symbol *func, "panic", "do_exit", "do_task_dead", + "make_task_dead", "__module_put_and_exit", "complete_and_exit", "__reiserfs_panic", @@ -175,7 +176,7 @@ static bool __dead_end_function(struct objtool_file *file, struct symbol *func, "fortify_panic", "usercopy_abort", "machine_real_restart", - "rewind_stack_do_exit", + "rewind_stack_and_make_dead" "kunit_try_catch_throw", "xen_start_kernel", "cpu_bringup_and_idle", -- cgit v1.2.3 From 4754eab7e5a78bdefe7a960c5c260c95ebbb5fa6 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Mon, 6 Dec 2021 01:43:34 +0100 Subject: ARM: dts: gemini: NAS4220-B: fis-index-block with 128 KiB sectors Steven Maddox reported in the OpenWrt bugzilla, that his RaidSonic IB-NAS4220-B was no longer booting with the new OpenWrt 21.02 (uses linux 5.10's device-tree). However, it was working with the previous OpenWrt 19.07 series (uses 4.14). |[ 5.548038] No RedBoot partition table detected in 30000000.flash |[ 5.618553] Searching for RedBoot partition table in 30000000.flash at offset 0x0 |[ 5.739093] No RedBoot partition table detected in 30000000.flash |... |[ 7.039504] Waiting for root device /dev/mtdblock3... The provided bootlog shows that the RedBoot partition parser was looking for the partition table "at offset 0x0". Which is strange since the comment in the device-tree says it should be at 0xfe0000. Further digging on the internet led to a review site that took some useful PCB pictures of their review unit back in February 2009. Their picture shows a Spansion S29GL128N11TFI01 flash chip. >From Spansion's Datasheet: "S29GL128N: One hundred twenty-eight 64 Kword (128 Kbyte) sectors" Steven also provided a "cat /sys/class/mtd/mtd0/erasesize" from his unit: "131072". With the 128 KiB Sector/Erasesize in mind. This patch changes the fis-index-block property to (0xfe0000 / 0x20000) = 0x7f. Fixes: b5a923f8c739 ("ARM: dts: gemini: Switch to redboot partition parsing") Reported-by: Steven Maddox Signed-off-by: Christian Lamparter Signed-off-by: Linus Walleij Tested-by: Steven Maddox Link: https://lore.kernel.org/r/20211206004334.4169408-1-linus.walleij@linaro.org' Bugzilla: https://bugs.openwrt.org/index.php?do=details&task_id=4137 Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/gemini-nas4220b.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts index 13112a8a5dd8..6544c730340f 100644 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini-nas4220b.dts @@ -84,7 +84,7 @@ partitions { compatible = "redboot-fis"; /* Eraseblock at 0xfe0000 */ - fis-index-block = <0x1fc>; + fis-index-block = <0x7f>; }; }; -- cgit v1.2.3 From a6839c42fe7c21173eb6f5db67d944e0f076be2a Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 13 Dec 2021 12:32:49 +0100 Subject: ARM: dts: qcom: Build apq8016-sbc/DragonBoard 410c DTB on ARM32 The DragonBoard 410c is a convenient device for testing and debugging. Since there is support for using ARM32 kernels on MSM8916 now, also build the DB410c DTB on ARM32 so it can be used for testing. ARM64 is still the main supported architecture for DB410c but it actually works great on ARM32 as well. The "apq8016-sbc.dts" is simply included as-is from ARM64 similar to the approach used for Raspberry Pi (e.g. bcm2711-rpi-4-b.dts). Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213113250.4249-1-stephan@gerhold.net --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-apq8016-sbc.dts | 2 ++ 2 files changed, 3 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-apq8016-sbc.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..bba17ee51e29 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -954,6 +954,7 @@ dtb-$(CONFIG_ARCH_OXNAS) += \ ox810se-wd-mbwe.dtb \ ox820-cloudengines-pogoplug-series-3.dtb dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8016-sbc.dtb \ qcom-apq8026-lg-lenok.dtb \ qcom-apq8060-dragonboard.dtb \ qcom-apq8064-cm-qs600.dtb \ diff --git a/arch/arm/boot/dts/qcom-apq8016-sbc.dts b/arch/arm/boot/dts/qcom-apq8016-sbc.dts new file mode 100644 index 000000000000..4ccd2dca74a2 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8016-sbc.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/apq8016-sbc.dts" -- cgit v1.2.3 From b357ffd8604ae45ec4bb1ebec072cd4ca4ce839c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 2 Dec 2021 08:38:27 -0600 Subject: ARM: dts: imx: Change spba to spba-bus With the updated dt-bindings for the spba-bus, rename spba@xxxx to spba-bus@xxxx. There are no functional changes. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 2 +- arch/arm/boot/dts/imx31.dtsi | 2 +- arch/arm/boot/dts/imx50.dtsi | 2 +- arch/arm/boot/dts/imx51.dtsi | 2 +- arch/arm/boot/dts/imx53.dtsi | 2 +- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index fdcca82c9986..83278b390c70 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -200,7 +200,7 @@ }; }; - spba@50000000 { + spba-bus@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 948d2a543f8d..2adb923c0b27 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -166,7 +166,7 @@ }; }; - spba@50000000 { + spba-bus@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index a969f335b240..a31e3694fa2b 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -108,7 +108,7 @@ reg = <0x50000000 0x10000000>; ranges; - spba@50000000 { + spba-bus@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 01cfcbe5928e..ba496fdfe8cb 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -178,7 +178,7 @@ reg = <0x70000000 0x10000000>; ranges; - spba@70000000 { + spba-bus@70000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 2cf3909cca2f..6082cd347124 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -229,7 +229,7 @@ reg = <0x50000000 0x10000000>; ranges; - spba@50000000 { + spba-bus@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index f5de5def876d..6dc1b970bcad 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -481,7 +481,7 @@ status = "okay"; }; - spba@203c000 { + spba-bus@203c000 { reg = <0x0203c000 0x4000>; }; }; -- cgit v1.2.3 From 74092acd6eab63b1f1e0c293400ef3b1bb7af6f8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 3 Dec 2021 00:19:01 +0200 Subject: ARM: dts: imx7s-warp: Drop undefined property in mipi_csi node The fsl,csis-hs-settle property isn't defined by the nxp,imx7-mipi-csi2.yaml binding, and isn't parsed by the corresponding driver. Drop it. Signed-off-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 569bbd84e371..614d252f029f 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -248,7 +248,6 @@ &mipi_csi { clock-frequency = <166000000>; - fsl,csis-hs-settle = <3>; status = "okay"; port@0 { -- cgit v1.2.3 From 473d06b9093ddc6b9fd2927893819f43e830bde5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 3 Dec 2021 00:19:02 +0200 Subject: ARM: dts: imx7: Drop reset-names property for mipi_csi node The reset-names property isn't defined by the nxp,imx7-mipi-csi2.yaml binding, and isn't used by the corresponding driver as it acquires the reset with a NULL ID. Drop it. Signed-off-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 1843fc053870..7e6b99ece7e9 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -819,7 +819,6 @@ power-domains = <&pgc_mipi_phy>; phy-supply = <®_1p0d>; resets = <&src IMX7_RESET_MIPI_PHY_MRST>; - reset-names = "mrst"; status = "disabled"; port@0 { -- cgit v1.2.3 From 3f8b6cf82088e0423b755f9a9dc79b8650bd1e25 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 3 Dec 2021 00:19:03 +0200 Subject: ARM: dts: imx7: Group mipi_csi 'port' children in a 'ports' node The nxp,imx7-mipi-csi2.yaml binding requires ports to be grouped in a ports node, as multiple ports are present. Fix imx7s.dtsi and the only board file that references the mipi_csi ports. Signed-off-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 13 +++++++------ arch/arm/boot/dts/imx7s.dtsi | 21 ++++++++++++--------- 2 files changed, 19 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 614d252f029f..4f1edef06c92 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -250,14 +250,15 @@ clock-frequency = <166000000>; status = "okay"; - port@0 { - reg = <0>; + ports { + port@0 { + reg = <0>; - mipi_from_sensor: endpoint { - remote-endpoint = <&ov2680_to_mipi>; - data-lanes = <1>; + mipi_from_sensor: endpoint { + remote-endpoint = <&ov2680_to_mipi>; + data-lanes = <1>; + }; }; - }; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 7e6b99ece7e9..52a9aeecdbb2 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -809,8 +809,6 @@ mipi_csi: mipi-csi@30750000 { compatible = "fsl,imx7-mipi-csi2"; reg = <0x30750000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; interrupts = ; clocks = <&clks IMX7D_IPG_ROOT_CLK>, <&clks IMX7D_MIPI_CSI_ROOT_CLK>, @@ -821,15 +819,20 @@ resets = <&src IMX7_RESET_MIPI_PHY_MRST>; status = "disabled"; - port@0 { - reg = <0>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@1 { - reg = <1>; + port@0 { + reg = <0>; + }; - mipi_vc0_to_csi_mux: endpoint { - remote-endpoint = <&csi_mux_from_mipi_vc0>; + port@1 { + reg = <1>; + + mipi_vc0_to_csi_mux: endpoint { + remote-endpoint = <&csi_mux_from_mipi_vc0>; + }; }; }; }; -- cgit v1.2.3 From 05be8e7472cdce0b006aa5fc995ec199f91979f5 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:23 +0100 Subject: ARM: dts: imx1: drop "fsl,imx-clk32" "fsl,imx-clk32" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi index 9b940987864c..e312f1e74e2f 100644 --- a/arch/arm/boot/dts/imx1.dtsi +++ b/arch/arm/boot/dts/imx1.dtsi @@ -55,7 +55,7 @@ clocks { clk32 { - compatible = "fsl,imx-clk32", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32000>; }; -- cgit v1.2.3 From 9a68c8ec9ac9f097c75d6a02f12ddcd29379622d Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:24 +0100 Subject: ARM: dts: imx25: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 83278b390c70..fa8044c21cb8 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -62,7 +62,7 @@ clocks { osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; -- cgit v1.2.3 From 20adb4921cd6d8db90efd466a1547af047160a0a Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:25 +0100 Subject: ARM: dts: imx50: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index a31e3694fa2b..d61c24846eef 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -80,7 +80,7 @@ }; osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; -- cgit v1.2.3 From c5e526a9c3d5d8be8829ab2c4530a063a9aef983 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:26 +0100 Subject: ARM: dts: imx50: drop "fsl,imx-ckil" "fsl,imx-ckil" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index d61c24846eef..af748ea4c1a5 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -62,7 +62,7 @@ clocks { ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; -- cgit v1.2.3 From c522683be5b56a2366bbe896bae2180a6d22e95e Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:27 +0100 Subject: ARM: dts: imx50: drop "fsl,imx-ckih1" "fsl,imx-ckih1" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index af748ea4c1a5..682880e9e485 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -68,7 +68,7 @@ }; ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <22579200>; }; -- cgit v1.2.3 From f6bc4a7c037f07bb338dde5171c64d191e65dfff Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:28 +0100 Subject: ARM: dts: imx50: drop "fsl,imx-ckih2" "fsl,imx-ckih2" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 682880e9e485..be0de0fd31f9 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -74,7 +74,7 @@ }; ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; -- cgit v1.2.3 From 73cda7c63a59609fa53ab91c1167f55692140a1f Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:29 +0100 Subject: ARM: dts: imx51: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index ba496fdfe8cb..090223321b3b 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -66,7 +66,7 @@ }; osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; -- cgit v1.2.3 From 929bdb7b0afb19c6f640b96859554d0d0010c3b3 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:30 +0100 Subject: ARM: dts: imx51: drop "fsl,imx-ckil" "fsl,imx-ckil" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 090223321b3b..7840489fcd6c 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -48,7 +48,7 @@ clocks { ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; -- cgit v1.2.3 From 58cd720f3f5a19c8cacff81b652018358c0105ea Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:31 +0100 Subject: ARM: dts: imx51: drop "fsl,imx-ckih1" "fsl,imx-ckih1" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 7840489fcd6c..e973f3c58052 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -54,7 +54,7 @@ }; ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; -- cgit v1.2.3 From 0dee2e69efc250410f1c0d756117d6b4506f54ef Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:32 +0100 Subject: ARM: dts: imx51: drop "fsl,imx-ckih2" "fsl,imx-ckih2" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index e973f3c58052..56c8d87864c3 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -60,7 +60,7 @@ }; ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; -- cgit v1.2.3 From 39cd25fe2e1d10a5b319a73a6e2bf97ecba86a9c Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:33 +0100 Subject: ARM: dts: imx53: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 6082cd347124..9e51ea3dd739 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -104,7 +104,7 @@ }; osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; -- cgit v1.2.3 From ac0894359ecfd80f260aa42b283c88bf02387e4e Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:34 +0100 Subject: ARM: dts: imx53: drop "fsl,imx-ckil" "fsl,imx-ckil" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 9e51ea3dd739..dd5cf147a7a4 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -86,7 +86,7 @@ clocks { ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; -- cgit v1.2.3 From 917fee9c6f7b7d4110730c2ab5f5fe8cdd7df534 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:35 +0100 Subject: ARM: dts: imx53: drop "fsl,imx-ckih1" "fsl,imx-ckih1" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index dd5cf147a7a4..3efa3d6d87c5 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -92,7 +92,7 @@ }; ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <22579200>; }; -- cgit v1.2.3 From 4ce956128d43527c5c917309257f2c4e927425d6 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:36 +0100 Subject: ARM: dts: imx53: drop "fsl,imx-ckih2" "fsl,imx-ckih2" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 3efa3d6d87c5..67487f3caee1 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -98,7 +98,7 @@ }; ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; -- cgit v1.2.3 From 36b85fdaa36ac19ec6bd77ad5d44050747265c28 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:37 +0100 Subject: ARM: dts: imx6qdl: drop "fsl,imx-osc" "fsl,imx-osc" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 6dc1b970bcad..6dcb3756597b 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -67,7 +67,7 @@ }; osc { - compatible = "fsl,imx-osc", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; -- cgit v1.2.3 From 5368f930cc655d0906574e9841960ee380bf4351 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:38 +0100 Subject: ARM: dts: imx6qdl: drop "fsl,imx-ckil" "fsl,imx-ckil" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 6dcb3756597b..5d4557d15d03 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -55,7 +55,7 @@ clocks { ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; -- cgit v1.2.3 From bca46d8e5fede9cf4491be27dba9d09721b80f71 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 01:40:39 +0100 Subject: ARM: dts: imx6qdl: drop "fsl,imx-ckih1" "fsl,imx-ckih1" is useless since no driver deals with it, so let's drop it. Signed-off-by: Giulio Benetti Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 5d4557d15d03..d27beb47f9a3 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -61,7 +61,7 @@ }; ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; -- cgit v1.2.3 From e7ed6ba0239df1e2aca3f9b2d77da4de180cdbe0 Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Wed, 8 Dec 2021 16:05:43 +0100 Subject: ARM: dts: imx6qdl-dhcom: Align PHY reset timing with other DHCOM SoMs According to datasheet Microchip LAN8710A/LAN8710Ai DS00002164B [1] the reset should stay asserted for at least 100uS and software should wait at least 200nS. On other DHCOM SoMs with the SMSC LAN8710Ai PHY both reset delays are 500us. This should be plenty and for consistency, the i.MX6 SoM should also use these delays. [1] https://ww1.microchip.com/downloads/en/DeviceDoc/00002164B.pdf Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi index 5d10c40313cb..e71687061161 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi @@ -138,8 +138,8 @@ pinctrl-0 = <&pinctrl_ethphy0>; pinctrl-names = "default"; reg = <0>; - reset-assert-us = <1000>; - reset-deassert-us = <1000>; + reset-assert-us = <500>; + reset-deassert-us = <500>; reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; smsc,disable-energy-detect; /* Make plugin detection reliable */ }; -- cgit v1.2.3 From cbcf2b40a7cf40da02e08e4485118a3b4fce54ce Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Wed, 8 Dec 2021 16:07:26 +0100 Subject: ARM: dts: imx6qdl-dhcom: Identify the PHY by ethernet-phy-id0007.c0f0 Identify the PHY by its compatible ID value. In some cases during boot, the PHY needs to be reset to be accessible, but this is only possible if the PHY is recognized. In that case, the automatic detection of the PHY does not work and a static compatible ID value is need. Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi index e71687061161..b2b7daf43ede 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi @@ -132,7 +132,8 @@ #size-cells = <0>; ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ - compatible = "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0007.c0f0", + "ethernet-phy-ieee802.3-c22"; interrupt-parent = <&gpio4>; interrupts = <15 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pinctrl_ethphy0>; -- cgit v1.2.3 From 0714ccb54c38826f942848813cb06bc50d148e37 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 18 Dec 2019 13:49:14 +0100 Subject: ARM: tegra: Clean up external memory controller nodes The external memory controller should be sorted after the memory controller to keep the ordering by unit-address intact. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 432 +- arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 2602 +++--- arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 11310 ++++++++++++----------- arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 750 +- 4 files changed, 7576 insertions(+), 7518 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index a7ac805eeed5..25c1006a2c5a 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -15,66 +15,77 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-924000000 { clock-frequency = <924000000>; nvidia,parent-clock-frequency = <924000000>; @@ -84,6 +95,216 @@ }; }; + memory-controller@70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 0x8000000a + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x77e30303 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 0x80000012 + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x76230303 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 0x80000017 + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x74a30303 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 0x8000001e + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x74230403 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 0x80000026 + 0x00000001 0x00000001 + 0x00000003 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0503 + 0x73c30504 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 0x80000040 + 0x00000001 0x00000001 + 0x00000004 0x00000002 + 0x00000003 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000004 0x00000006 + 0x06040203 0x000a0504 + 0x73840a05 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 0x80000040 + 0x00000001 0x00000002 + 0x00000007 0x00000004 + 0x00000004 0x00000001 + 0x00000002 0x00000007 + 0x00000002 0x00000002 + 0x00000004 0x00000006 + 0x06040202 0x000b0607 + 0x77450e08 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 0x80000040 + 0x00000001 0x00000002 + 0x00000009 0x00000005 + 0x00000006 0x00000001 + 0x00000002 0x00000008 + 0x00000002 0x00000002 + 0x00000004 0x00000006 + 0x06040202 0x000d0709 + 0x7586120a 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 0x80000040 + 0x00000002 0x00000003 + 0x0000000c 0x00000007 + 0x00000008 0x00000001 + 0x00000002 0x00000009 + 0x00000002 0x00000002 + 0x00000005 0x00000006 + 0x06050202 0x0010090c + 0x7428180d 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 0x80000040 + 0x00000003 0x00000004 + 0x0000000e 0x00000009 + 0x0000000a 0x00000001 + 0x00000003 0x0000000b + 0x00000002 0x00000002 + 0x00000005 0x00000007 + 0x07050202 0x00130b0e + 0x73a91b0f 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b 0x80000040 + 0x00000004 0x00000005 + 0x00000013 0x0000000c + 0x0000000d 0x00000002 + 0x00000003 0x0000000c + 0x00000002 0x00000002 + 0x00000006 0x00000008 + 0x08060202 0x00170e13 + 0x736c2414 0x70000f02 + 0x001f0000 + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < + 0x0e00000d 0x80000040 + 0x00000005 0x00000006 + 0x00000016 0x0000000e + 0x0000000f 0x00000002 + 0x00000004 0x0000000e + 0x00000002 0x00000002 + 0x00000006 0x00000009 + 0x09060202 0x001a1016 + 0x734e2a17 0x70000f02 + 0x001f0000 + >; + }; + }; + }; + external-memory-controller@7001b000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -1251,217 +1472,6 @@ 0x00000011 >; }; - - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 0x8000000a - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x77e30303 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 0x80000012 - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x76230303 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 0x80000017 - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x74a30303 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 0x8000001e - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x74230403 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 0x80000026 - 0x00000001 0x00000001 - 0x00000003 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0503 - 0x73c30504 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 0x80000040 - 0x00000001 0x00000001 - 0x00000004 0x00000002 - 0x00000003 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000004 0x00000006 - 0x06040203 0x000a0504 - 0x73840a05 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 0x80000040 - 0x00000001 0x00000002 - 0x00000007 0x00000004 - 0x00000004 0x00000001 - 0x00000002 0x00000007 - 0x00000002 0x00000002 - 0x00000004 0x00000006 - 0x06040202 0x000b0607 - 0x77450e08 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 0x80000040 - 0x00000001 0x00000002 - 0x00000009 0x00000005 - 0x00000006 0x00000001 - 0x00000002 0x00000008 - 0x00000002 0x00000002 - 0x00000004 0x00000006 - 0x06040202 0x000d0709 - 0x7586120a 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 0x80000040 - 0x00000002 0x00000003 - 0x0000000c 0x00000007 - 0x00000008 0x00000001 - 0x00000002 0x00000009 - 0x00000002 0x00000002 - 0x00000005 0x00000006 - 0x06050202 0x0010090c - 0x7428180d 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 0x80000040 - 0x00000003 0x00000004 - 0x0000000e 0x00000009 - 0x0000000a 0x00000001 - 0x00000003 0x0000000b - 0x00000002 0x00000002 - 0x00000005 0x00000007 - 0x07050202 0x00130b0e - 0x73a91b0f 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b 0x80000040 - 0x00000004 0x00000005 - 0x00000013 0x0000000c - 0x0000000d 0x00000002 - 0x00000003 0x0000000c - 0x00000002 0x00000002 - 0x00000006 0x00000008 - 0x08060202 0x00170e13 - 0x736c2414 0x70000f02 - 0x001f0000 - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emem-configuration = < - 0x0e00000d 0x80000040 - 0x00000005 0x00000006 - 0x00000016 0x0000000e - 0x0000000f 0x00000002 - 0x00000004 0x0000000e - 0x00000002 0x00000002 - 0x00000006 0x00000009 - 0x09060202 0x001a1016 - 0x734e2a17 0x70000f02 - 0x001f0000 - >; - }; }; }; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index df4e463afbd1..3ad2e02c7d3a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -10,66 +10,77 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-924000000 { clock-frequency = <924000000>; nvidia,parent-clock-frequency = <924000000>; @@ -79,516 +90,330 @@ }; }; - external-memory-controller@7001b000 { + memory-controller@70019000 { emc-timings-3 { nvidia,ram-code = <3>; timing-12750000 { clock-frequency = <12750000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 0x00000000 + 0x00000002 + 0x00000001 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 + 0x00000008 0x00000003 + 0x00000002 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 0x00000006 + 0x06030203 + 0x000a0502 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 0x00000002 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000060 - 0x00000000 - 0x00000018 - 0x00000002 0x00000002 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000005 - 0x00000005 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000064 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000007 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 - 0x800001c5 - 0x0000000a + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x76230303 + 0x70000f03 + 0x001f0000 >; }; - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; + timing-40800000 { + clock-frequency = <40800000>; - nvidia,emc-configuration = < - 0x00000000 - 0x00000005 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 + 0x00000002 0x00000000 + 0x00000002 + 0x00000001 0x00000003 + 0x00000008 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x0000009a - 0x00000000 - 0x00000026 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 0x00000002 + 0x00000000 0x00000002 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000006 - 0x00000006 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x000000a0 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x0000000b - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 - 0x8000023a - 0x0000000a + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0502 + 0x74230403 + 0x70000f03 + 0x001f0000 >; }; - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; + timing-102000000 { + clock-frequency = <102000000>; - nvidia,emc-configuration = < + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 0x00000001 - 0x0000000a - 0x00000000 0x00000001 + 0x00000003 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 + 0x00000002 + 0x00000001 0x00000003 + 0x00000008 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 + 0x00000006 + 0x06030203 + 0x000a0503 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000134 - 0x00000000 - 0x0000004d - 0x00000002 0x00000002 + 0x00000003 0x00000001 - 0x00000000 + 0x00000003 0x00000008 - 0x0000000f - 0x0000000c - 0x0000000c + 0x00000003 + 0x00000002 0x00000004 - 0x00000005 + 0x00000006 + 0x06040203 + 0x000a0504 + 0x73840a05 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000007 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000013f - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000015 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 + 0x00000004 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000005 + 0x00000006 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 0x00000003 - 0x0000f2f3 - 0x80000370 + 0x0000000c + 0x00000007 + 0x00000008 + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090c + 0x7428180d + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 0x0000000a + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 >; }; - timing-68000000 { - clock-frequency = <68000000>; + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000d + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00170e13 + 0x736c2414 + 0x70000f02 + 0x001f0000 + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < + 0x0e00000d + 0x80000040 + 0x00000005 + 0x00000006 + 0x00000016 + 0x0000000e + 0x0000000f + 0x00000002 + 0x00000004 + 0x0000000e + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000009 + 0x09060202 + 0x001a1016 + 0x734e2a17 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; + + external-memory-controller@7001b000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; @@ -609,10 +434,10 @@ nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < + 0x00000000 0x00000003 - 0x00000011 0x00000000 - 0x00000002 + 0x00000000 0x00000000 0x00000004 0x0000000a @@ -640,25 +465,25 @@ 0x0000000c 0x0000000d 0x0000000f - 0x00000202 + 0x00000060 0x00000000 - 0x00000080 + 0x00000018 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f - 0x0000000f - 0x00000013 - 0x00000013 + 0x00000005 + 0x00000005 0x00000004 0x00000005 0x00000004 - 0x00000001 + 0x00000000 0x00000000 0x00000005 0x00000005 - 0x00000213 + 0x00000064 0x00000000 0x00000000 0x00000000 @@ -743,21 +568,21 @@ 0x00514514 0x51451400 0x0000003f - 0x00000022 + 0x00000007 0x00000000 0x00000042 0x000e000e 0x00000000 0x00000003 0x0000f2f3 - 0x8000050e + 0x800001c5 0x0000000a >; }; - timing-102000000 { - clock-frequency = <102000000>; - + timing-20400000 { + clock-frequency = <20400000>; + nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; @@ -777,17 +602,17 @@ nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000004 - 0x0000001a 0x00000000 - 0x00000003 - 0x00000001 + 0x00000005 + 0x00000000 + 0x00000000 + 0x00000000 0x00000004 0x0000000a 0x00000005 0x0000000b - 0x00000001 - 0x00000001 + 0x00000000 + 0x00000000 0x00000003 0x00000003 0x00000000 @@ -808,25 +633,25 @@ 0x0000000c 0x0000000d 0x0000000f - 0x00000304 + 0x0000009a 0x00000000 - 0x000000c1 + 0x00000026 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000018 + 0x00000007 0x0000000f - 0x0000001c - 0x0000001c + 0x00000006 + 0x00000006 0x00000004 0x00000005 0x00000004 - 0x00000002 + 0x00000000 0x00000000 0x00000005 0x00000005 - 0x0000031c + 0x000000a0 0x00000000 0x00000000 0x00000000 @@ -911,20 +736,20 @@ 0x00514514 0x51451400 0x0000003f - 0x00000033 + 0x0000000b 0x00000000 0x00000042 0x000e000e 0x00000000 0x00000003 0x0000f2f3 - 0x80000713 + 0x8000023a 0x0000000a >; }; - timing-204000000 { - clock-frequency = <204000000>; + timing-40800000 { + clock-frequency = <40800000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; @@ -932,7 +757,7 @@ nvidia,emc-auto-cal-interval = <0x001fffff>; nvidia,emc-bgbias-ctl0 = <0x00000008>; nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008cd>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; nvidia,emc-mode-1 = <0x80100003>; nvidia,emc-mode-2 = <0x80200008>; @@ -942,59 +767,59 @@ nvidia,emc-sel-dpd-ctrl = <0x00040128>; nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000009 - 0x00000035 + 0x00000001 + 0x0000000a 0x00000000 - 0x00000006 - 0x00000002 - 0x00000005 + 0x00000001 + 0x00000000 + 0x00000004 0x0000000a 0x00000005 0x0000000b - 0x00000002 - 0x00000002 + 0x00000000 + 0x00000000 0x00000003 0x00000003 0x00000000 - 0x00000005 - 0x00000005 + 0x00000006 + 0x00000006 0x00000006 0x00000002 0x00000000 - 0x00000004 - 0x00000006 + 0x00000005 + 0x00000005 0x00010000 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000003 + 0x00000004 + 0x0000000c 0x0000000d 0x0000000f - 0x00000011 - 0x00000607 + 0x00000134 0x00000000 - 0x00000181 + 0x0000004d 0x00000002 0x00000002 0x00000001 0x00000000 - 0x00000032 + 0x00000008 0x0000000f - 0x00000038 - 0x00000038 + 0x0000000c + 0x0000000c 0x00000004 0x00000005 0x00000004 - 0x00000006 + 0x00000000 0x00000000 0x00000005 0x00000005 - 0x00000638 + 0x0000013f 0x00000000 0x00000000 0x00000000 @@ -1027,10 +852,8 @@ 0x00000000 0x00000000 0x00000000 - 0x00008000 0x00000000 0x00000000 - 0x00008000 0x00000000 0x00000000 0x00000000 @@ -1055,21 +878,23 @@ 0x00000000 0x00000000 0x00000000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x00009000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 0x10000280 0x00000000 0x00111111 0x00000000 0x00000000 0x77ffc081 - 0x00000707 + 0x00000e0e 0x81f1f108 0x07070004 0x0000003f @@ -1079,112 +904,112 @@ 0x00514514 0x51451400 0x0000003f - 0x00000066 + 0x00000015 0x00000000 - 0x00000100 + 0x00000042 0x000e000e 0x00000000 0x00000003 - 0x0000d2b3 - 0x80000d22 + 0x0000f2f3 + 0x80000370 0x0000000a >; }; - timing-300000000 { - clock-frequency = <300000000>; + timing-68000000 { + clock-frequency = <68000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0173000e>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x0000000d - 0x0000004d - 0x00000000 - 0x00000009 - 0x00000003 - 0x00000004 - 0x00000008 - 0x00000002 - 0x00000009 0x00000003 - 0x00000003 - 0x00000002 + 0x00000011 + 0x00000000 0x00000002 0x00000000 + 0x00000004 + 0x0000000a + 0x00000005 + 0x0000000b + 0x00000000 + 0x00000000 0x00000003 0x00000003 - 0x00000005 - 0x00000002 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 0x00000002 - 0x00000007 - 0x00020000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000001 - 0x0000000e - 0x00000010 - 0x00000012 - 0x000008e4 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000202 0x00000000 - 0x00000239 - 0x00000001 - 0x00000008 + 0x00000080 + 0x00000002 + 0x00000002 0x00000001 0x00000000 - 0x0000004b - 0x0000000e - 0x00000052 - 0x00000200 + 0x0000000f + 0x0000000f + 0x00000013 + 0x00000013 0x00000004 0x00000005 0x00000004 - 0x00000008 + 0x00000001 0x00000000 0x00000005 0x00000005 - 0x00000924 + 0x00000213 0x00000000 0x00000000 0x00000000 - 0x104ab098 + 0x106aa298 0x002c00a0 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 @@ -1193,11 +1018,7 @@ 0x00000000 0x00000000 0x00000000 - 0x00098000 - 0x00098000 0x00000000 - 0x00098000 - 0x00098000 0x00000000 0x00000000 0x00000000 @@ -1223,136 +1044,140 @@ 0x00000000 0x00000000 0x00000000 - 0x00050000 - 0x00050000 - 0x00050000 - 0x00050000 - 0x00005000 - 0x00005000 - 0x00005000 - 0x00005000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 0x10000280 0x00000000 0x00111111 0x00000000 0x00000000 0x77ffc081 - 0x00000505 + 0x00000e0e 0x81f1f108 0x07070004 - 0x00000000 + 0x0000003f 0x016eeeee - 0x51451420 + 0x51451400 0x00514514 0x00514514 0x51451400 0x0000003f - 0x00000096 + 0x00000022 0x00000000 - 0x00000100 - 0x0173000e + 0x00000042 + 0x000e000e 0x00000000 0x00000003 - 0x000052a3 - 0x800012d7 - 0x00000009 + 0x0000f2f3 + 0x8000050e + 0x0000000a >; }; - timing-396000000 { - clock-frequency = <396000000>; + timing-102000000 { + clock-frequency = <102000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000011 - 0x00000066 - 0x00000000 - 0x0000000c 0x00000004 + 0x0000001a + 0x00000000 + 0x00000003 + 0x00000001 0x00000004 - 0x00000008 - 0x00000002 0x0000000a - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000002 - 0x00000000 + 0x00000005 + 0x0000000b + 0x00000001 + 0x00000001 0x00000003 0x00000003 - 0x00000005 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 0x00000002 0x00000000 - 0x00000001 - 0x00000008 - 0x00020000 + 0x00000005 + 0x00000005 + 0x00010000 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d 0x0000000f - 0x00000010 - 0x00000012 - 0x00000bd1 + 0x00000304 0x00000000 - 0x000002f4 - 0x00000001 - 0x00000008 + 0x000000c1 + 0x00000002 + 0x00000002 0x00000001 0x00000000 - 0x00000063 + 0x00000018 0x0000000f - 0x0000006c - 0x00000200 + 0x0000001c + 0x0000001c 0x00000004 0x00000005 0x00000004 - 0x0000000b + 0x00000002 0x00000000 0x00000005 0x00000005 - 0x00000c11 + 0x0000031c 0x00000000 0x00000000 0x00000000 - 0x104ab098 + 0x106aa298 0x002c00a0 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 @@ -1361,11 +1186,7 @@ 0x00000000 0x00000000 0x00000000 - 0x00070000 - 0x00070000 0x00000000 - 0x00070000 - 0x00070000 0x00000000 0x00000000 0x00000000 @@ -1391,136 +1212,140 @@ 0x00000000 0x00000000 0x00000000 - 0x00038000 - 0x00038000 - 0x00038000 - 0x00038000 - 0x00003800 - 0x00003800 - 0x00003800 - 0x00003800 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x000fc000 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 + 0x0000fc00 0x10000280 0x00000000 0x00111111 0x00000000 0x00000000 0x77ffc081 - 0x00000505 + 0x00000e0e 0x81f1f108 0x07070004 - 0x00000000 + 0x0000003f 0x016eeeee - 0x51451420 + 0x51451400 0x00514514 0x00514514 0x51451400 0x0000003f - 0x000000c6 + 0x00000033 0x00000000 - 0x00000100 - 0x015b000e + 0x00000042 + 0x000e000e 0x00000000 0x00000003 - 0x000052a3 - 0x8000188b - 0x00000009 + 0x0000f2f3 + 0x80000713 + 0x0000000a >; }; - timing-528000000 { - clock-frequency = <528000000>; + timing-204000000 { + clock-frequency = <204000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008cd>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-1 = <0x80100003>; nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x0139000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x00000018 - 0x00000088 + 0x00000009 + 0x00000035 0x00000000 - 0x00000010 0x00000006 - 0x00000006 - 0x00000009 0x00000002 - 0x0000000d - 0x00000006 - 0x00000006 + 0x00000005 + 0x0000000a + 0x00000005 + 0x0000000b 0x00000002 0x00000002 - 0x00000000 0x00000003 0x00000003 + 0x00000000 + 0x00000005 + 0x00000005 0x00000006 0x00000002 0x00000000 - 0x00000001 - 0x00000009 - 0x00030000 + 0x00000004 + 0x00000006 + 0x00010000 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000003 + 0x0000000d + 0x0000000f + 0x00000011 + 0x00000607 0x00000000 - 0x00000010 - 0x00000012 - 0x00000014 - 0x00000fd6 - 0x00000000 - 0x000003f5 + 0x00000181 + 0x00000002 0x00000002 - 0x0000000b 0x00000001 0x00000000 - 0x00000085 - 0x00000012 - 0x00000090 - 0x00000200 + 0x00000032 + 0x0000000f + 0x00000038 + 0x00000038 0x00000004 0x00000005 0x00000004 - 0x00000010 - 0x00000000 - 0x00000006 0x00000006 - 0x00001017 0x00000000 + 0x00000005 + 0x00000005 + 0x00000638 0x00000000 0x00000000 - 0x104ab098 - 0xe01200b1 + 0x00000000 + 0x106aa298 + 0x002c00a0 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 @@ -1529,14 +1354,12 @@ 0x00000000 0x00000000 0x00000000 - 0x00054000 - 0x00054000 0x00000000 - 0x00054000 - 0x00054000 0x00000000 + 0x00008000 0x00000000 0x00000000 + 0x00008000 0x00000000 0x00000000 0x00000000 @@ -1559,136 +1382,138 @@ 0x00000000 0x00000000 0x00000000 - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x100002a0 + 0x00000000 + 0x00000000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00090000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x00009000 + 0x10000280 0x00000000 0x00111111 0x00000000 0x00000000 - 0x77ffc085 - 0x00000505 + 0x77ffc081 + 0x00000707 0x81f1f108 0x07070004 - 0x00000000 + 0x0000003f 0x016eeeee - 0x51451420 + 0x51451400 0x00514514 0x00514514 0x51451400 - 0x0606003f - 0x00000000 + 0x0000003f + 0x00000066 0x00000000 0x00000100 - 0x0139000e + 0x000e000e 0x00000000 0x00000003 - 0x000042a0 - 0x80002062 + 0x0000d2b3 + 0x80000d22 0x0000000a >; }; - timing-600000000 { - clock-frequency = <600000000>; + timing-300000000 { + clock-frequency = <300000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-2 = <0x80200000>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0127000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0173000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; nvidia,emc-zcal-cnt-long = <0x00000042>; nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x0000001b - 0x0000009b + 0x0000000d + 0x0000004d 0x00000000 - 0x00000013 - 0x00000007 - 0x00000007 - 0x0000000b + 0x00000009 + 0x00000003 + 0x00000004 + 0x00000008 + 0x00000002 + 0x00000009 + 0x00000003 0x00000003 - 0x00000010 - 0x00000007 - 0x00000007 0x00000002 0x00000002 0x00000000 + 0x00000003 + 0x00000003 0x00000005 - 0x00000005 - 0x0000000a 0x00000002 0x00000000 - 0x00000003 - 0x0000000b - 0x00070000 + 0x00000002 + 0x00000007 + 0x00020000 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000002 + 0x00000001 + 0x0000000e + 0x00000010 0x00000012 - 0x00000016 - 0x00000018 - 0x00001208 + 0x000008e4 0x00000000 - 0x00000482 - 0x00000002 - 0x0000000d + 0x00000239 + 0x00000001 + 0x00000008 0x00000001 0x00000000 - 0x00000097 - 0x00000015 - 0x000000a3 + 0x0000004b + 0x0000000e + 0x00000052 0x00000200 0x00000004 0x00000005 0x00000004 - 0x00000013 + 0x00000008 0x00000000 - 0x00000006 - 0x00000006 - 0x00001248 + 0x00000005 + 0x00000005 + 0x00000924 0x00000000 0x00000000 0x00000000 0x104ab098 - 0xe00e00b1 + 0x002c00a0 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 0x00000000 0x00000000 0x00000000 @@ -1697,11 +1522,11 @@ 0x00000000 0x00000000 0x00000000 - 0x00048000 - 0x00048000 + 0x00098000 + 0x00098000 0x00000000 - 0x00048000 - 0x00048000 + 0x00098000 + 0x00098000 0x00000000 0x00000000 0x00000000 @@ -1727,20 +1552,20 @@ 0x00000000 0x00000000 0x00000000 - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x100002a0 + 0x00050000 + 0x00050000 + 0x00050000 + 0x00050000 + 0x00005000 + 0x00005000 + 0x00005000 + 0x00005000 + 0x10000280 0x00000000 0x00111111 0x00000000 0x00000000 - 0x77ffc085 + 0x77ffc081 0x00000505 0x81f1f108 0x07070004 @@ -1750,113 +1575,113 @@ 0x00514514 0x00514514 0x51451400 - 0x0606003f - 0x00000000 + 0x0000003f + 0x00000096 0x00000000 0x00000100 - 0x0127000e + 0x0173000e 0x00000000 0x00000003 - 0x000040a0 - 0x800024aa - 0x0000000e + 0x000052a3 + 0x800012d7 + 0x00000009 >; }; - timing-792000000 { - clock-frequency = <792000000>; + timing-396000000 { + clock-frequency = <396000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; nvidia,emc-ctt-term-ctrl = <0x00000802>; nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-2 = <0x80200000>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f7000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; nvidia,emc-zcal-cnt-long = <0x00000042>; nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x00000024 - 0x000000cd + 0x00000011 + 0x00000066 0x00000000 - 0x00000019 - 0x0000000a - 0x00000008 - 0x0000000d + 0x0000000c 0x00000004 - 0x00000013 - 0x0000000a + 0x00000004 + 0x00000008 + 0x00000002 0x0000000a 0x00000004 + 0x00000004 0x00000002 - 0x00000000 - 0x00000006 - 0x00000006 - 0x0000000b 0x00000002 0x00000000 + 0x00000003 + 0x00000003 + 0x00000005 0x00000002 - 0x0000000d - 0x00080000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 0x00000000 0x00000001 - 0x00000014 - 0x00000018 - 0x0000001a - 0x000017e2 - 0x00000000 - 0x000005f8 + 0x00000008 + 0x00020000 0x00000003 - 0x00000011 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000f + 0x00000010 + 0x00000012 + 0x00000bd1 + 0x00000000 + 0x000002f4 + 0x00000001 + 0x00000008 0x00000001 0x00000000 - 0x000000c7 - 0x00000018 - 0x000000d7 + 0x00000063 + 0x0000000f + 0x0000006c 0x00000200 + 0x00000004 0x00000005 - 0x00000006 - 0x00000005 - 0x00000019 + 0x00000004 + 0x0000000b 0x00000000 - 0x00000008 - 0x00000008 - 0x00001822 + 0x00000005 + 0x00000005 + 0x00000c11 0x00000000 0x00000000 0x00000000 0x104ab098 - 0xe00700b1 + 0x002c00a0 0x00008000 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 + 0x00030000 0x00000000 0x00000000 0x00000000 @@ -1865,11 +1690,11 @@ 0x00000000 0x00000000 0x00000000 - 0x00034000 - 0x00034000 + 0x00070000 + 0x00070000 0x00000000 - 0x00034000 - 0x00034000 + 0x00070000 + 0x00070000 0x00000000 0x00000000 0x00000000 @@ -1879,62 +1704,62 @@ 0x00000000 0x00000000 0x00000000 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x100002a0 0x00000000 - 0x00111111 0x00000000 0x00000000 - 0x77ffc085 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00038000 + 0x00038000 + 0x00038000 + 0x00038000 + 0x00003800 + 0x00003800 + 0x00003800 + 0x00003800 + 0x10000280 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc081 + 0x00000505 0x81f1f108 0x07070004 0x00000000 0x016eeeee - 0x61861820 + 0x51451420 0x00514514 0x00514514 - 0x61861800 - 0x0606003f - 0x00000000 + 0x51451400 + 0x0000003f + 0x000000c6 0x00000000 0x00000100 - 0x00f7000e + 0x015b000e 0x00000000 - 0x00000004 - 0x00004080 - 0x80003012 - 0x0000000f + 0x00000003 + 0x000052a3 + 0x8000188b + 0x00000009 >; }; - timing-924000000 { - clock-frequency = <924000000>; + timing-528000000 { + clock-frequency = <528000000>; - nvidia,emc-auto-cal-config = <0xa1430303>; + nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; @@ -1943,101 +1768,104 @@ nvidia,emc-cfg-2 = <0x0000089d>; nvidia,emc-ctt-term-ctrl = <0x00000802>; nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200020>; + nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000f15>; - nvidia,emc-mrs-wait-cnt = <0x00cd000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x0000004c>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x0139000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x0000002b - 0x000000f0 + 0x00000018 + 0x00000088 0x00000000 - 0x0000001e - 0x0000000b + 0x00000010 + 0x00000006 + 0x00000006 0x00000009 - 0x0000000f - 0x00000005 - 0x00000016 - 0x0000000b - 0x0000000b - 0x00000004 0x00000002 - 0x00000000 - 0x00000007 - 0x00000007 0x0000000d + 0x00000006 + 0x00000006 + 0x00000002 0x00000002 0x00000000 + 0x00000003 + 0x00000003 + 0x00000006 0x00000002 - 0x0000000f - 0x000a0000 - 0x00000004 0x00000000 + 0x00000001 + 0x00000009 + 0x00030000 + 0x00000003 0x00000000 0x00000000 0x00000000 - 0x00000001 - 0x00000016 - 0x0000001a - 0x0000001c - 0x00001be7 0x00000000 - 0x000006f9 - 0x00000004 - 0x00000015 + 0x00000000 + 0x00000010 + 0x00000012 + 0x00000014 + 0x00000fd6 + 0x00000000 + 0x000003f5 + 0x00000002 + 0x0000000b 0x00000001 0x00000000 - 0x000000e7 - 0x0000001b - 0x000000fb + 0x00000085 + 0x00000012 + 0x00000090 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000010 + 0x00000000 0x00000006 - 0x00000007 0x00000006 - 0x0000001e + 0x00001017 + 0x00000000 0x00000000 + 0x00000000 + 0x104ab098 + 0xe01200b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a 0x0000000a 0x0000000a - 0x00001c28 0x00000000 0x00000000 0x00000000 - 0x104ab898 - 0xe00400b1 - 0x00008000 - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00054000 + 0x00054000 0x00000000 + 0x00054000 + 0x00054000 0x00000000 0x00000000 - 0x0002c000 - 0x0002c000 0x00000000 - 0x0002c000 - 0x0002c000 0x00000000 0x00000000 0x00000000 @@ -2047,374 +1875,556 @@ 0x00000000 0x00000000 0x00000000 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c + 0x0000000c 0x100002a0 0x00000000 0x00111111 0x00000000 0x00000000 0x77ffc085 - 0x00000000 + 0x00000505 0x81f1f108 0x07070004 0x00000000 0x016eeeee - 0x5d75d720 + 0x51451420 0x00514514 0x00514514 - 0x5d75d700 + 0x51451400 0x0606003f 0x00000000 0x00000000 - 0x00000128 - 0x00cd000e + 0x00000100 + 0x0139000e 0x00000000 - 0x00000004 - 0x00004080 - 0x800037ea - 0x00000011 + 0x00000003 + 0x000042a0 + 0x80002062 + 0x0000000a >; }; - }; - }; - - memory-controller@70019000 { - emc-timings-3 { - nvidia,ram-code = <3>; + timing-600000000 { + clock-frequency = <600000000>; - timing-12750000 { - clock-frequency = <12750000>; + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0127000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 + nvidia,emc-configuration = < + 0x0000001b + 0x0000009b 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 + 0x00000013 + 0x00000007 + 0x00000007 + 0x0000000b 0x00000003 + 0x00000010 + 0x00000007 + 0x00000007 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 0x00000002 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 + 0x00000005 + 0x00000005 + 0x0000000a 0x00000002 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 0x00000003 - 0x00000002 + 0x0000000b + 0x00070000 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 + 0x00000000 + 0x00000000 + 0x00000000 0x00000000 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 + 0x00000012 + 0x00000016 + 0x00000018 + 0x00001208 0x00000000 + 0x00000482 0x00000002 + 0x0000000d 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 + 0x00000000 + 0x00000097 + 0x00000015 + 0x000000a3 + 0x00000200 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000013 + 0x00000000 0x00000006 - 0x06030203 - 0x000a0503 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000004 - 0x00000002 - 0x00000003 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 0x00000006 - 0x06040203 - 0x000a0504 - 0x73840a05 - 0x70000f03 - 0x001f0000 + 0x00001248 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00e00b1 + 0x00008000 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00048000 + 0x00048000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x0000000d + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000505 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x51451420 + 0x00514514 + 0x00514514 + 0x51451400 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x0127000e + 0x00000000 + 0x00000003 + 0x000040a0 + 0x800024aa + 0x0000000e >; }; - timing-300000000 { - clock-frequency = <300000000>; + timing-792000000 { + clock-frequency = <792000000>; - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f7000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000024 + 0x000000cd + 0x00000000 + 0x00000019 + 0x0000000a + 0x00000008 + 0x0000000d 0x00000004 + 0x00000013 + 0x0000000a + 0x0000000a 0x00000004 - 0x00000001 - 0x00000002 - 0x00000007 0x00000002 - 0x00000002 - 0x00000004 + 0x00000000 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 0x00000006 - 0x00000001 - 0x00000002 - 0x00000008 + 0x0000000b 0x00000002 + 0x00000000 0x00000002 + 0x0000000d + 0x00080000 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 - 0x80000040 - 0x00000002 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000014 + 0x00000018 + 0x0000001a + 0x000017e2 + 0x00000000 + 0x000005f8 0x00000003 - 0x0000000c - 0x00000007 - 0x00000008 + 0x00000011 0x00000001 - 0x00000002 - 0x00000009 - 0x00000002 - 0x00000002 + 0x00000000 + 0x000000c7 + 0x00000018 + 0x000000d7 + 0x00000200 0x00000005 0x00000006 - 0x06050202 - 0x0010090c - 0x7428180d - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000a - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000d - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 + 0x00000019 + 0x00000000 0x00000008 - 0x08060202 - 0x00170e13 - 0x736c2414 - 0x70000f02 - 0x001f0000 + 0x00000008 + 0x00001822 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab098 + 0xe00700b1 + 0x00008000 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x007fc008 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00034000 + 0x00034000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x00000005 + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x0000000a + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000000 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x61861820 + 0x00514514 + 0x00514514 + 0x61861800 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000100 + 0x00f7000e + 0x00000000 + 0x00000004 + 0x00004080 + 0x80003012 + 0x0000000f >; }; timing-924000000 { clock-frequency = <924000000>; - nvidia,emem-configuration = < - 0x0e00000d - 0x80000040 + nvidia,emc-auto-cal-config = <0xa1430303>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200020>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000f15>; + nvidia,emc-mrs-wait-cnt = <0x00cd000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x0000004c>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000002b + 0x000000f0 + 0x00000000 + 0x0000001e + 0x0000000b + 0x00000009 + 0x0000000f 0x00000005 - 0x00000006 0x00000016 - 0x0000000e - 0x0000000f - 0x00000002 + 0x0000000b + 0x0000000b 0x00000004 - 0x0000000e 0x00000002 + 0x00000000 + 0x00000007 + 0x00000007 + 0x0000000d + 0x00000002 + 0x00000000 0x00000002 + 0x0000000f + 0x000a0000 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000016 + 0x0000001a + 0x0000001c + 0x00001be7 + 0x00000000 + 0x000006f9 + 0x00000004 + 0x00000015 + 0x00000001 + 0x00000000 + 0x000000e7 + 0x0000001b + 0x000000fb + 0x00000200 0x00000006 - 0x00000009 - 0x09060202 - 0x001a1016 - 0x734e2a17 - 0x70000f02 - 0x001f0000 + 0x00000007 + 0x00000006 + 0x0000001e + 0x00000000 + 0x0000000a + 0x0000000a + 0x00001c28 + 0x00000000 + 0x00000000 + 0x00000000 + 0x104ab898 + 0xe00400b1 + 0x00008000 + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x007f800a + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x0002c000 + 0x0002c000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000004 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x00000008 + 0x100002a0 + 0x00000000 + 0x00111111 + 0x00000000 + 0x00000000 + 0x77ffc085 + 0x00000000 + 0x81f1f108 + 0x07070004 + 0x00000000 + 0x016eeeee + 0x5d75d720 + 0x00514514 + 0x00514514 + 0x5d75d700 + 0x0606003f + 0x00000000 + 0x00000000 + 0x00000128 + 0x00cd000e + 0x00000000 + 0x00000004 + 0x00004080 + 0x800037ea + 0x00000011 >; }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index a0f56cc9da5c..49a6d6afc633 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -14,60 +14,70 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; @@ -85,60 +95,70 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; @@ -156,60 +176,70 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + timing-528000000 { clock-frequency = <528000000>; nvidia,parent-clock-frequency = <528000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; clock-names = "emc-parent"; }; + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; @@ -219,3707 +249,583 @@ }; }; - external-memory-controller@7001b000 { + memory-controller@70019000 { emc-timings-1 { nvidia,ram-code = <1>; timing-12750000 { clock-frequency = <12750000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000003 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; timing-20400000 { clock-frequency = <20400000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x76230303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000005 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x0000009a /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000006 /* EMC_TXSR */ - 0x00000006 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000a0 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x0000000a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000134 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000c /* EMC_TXSR */ - 0x0000000c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000013f /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000015 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 /* EMC_RC */ - 0x00000011 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000002 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000202 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000013 /* EMC_TXSR */ - 0x00000013 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000213 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000022 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000304 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000018 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000033 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000004 /* EMC_EINPUT */ - 0x00000006 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000003 /* EMC_QRST */ - 0x0000000d /* EMC_QSAFE */ - 0x0000000f /* EMC_RDV */ - 0x00000011 /* EMC_RDV_MASK */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000032 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000007 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00090000 /* EMC_DLL_XFORM_DQ0 */ - 0x00090000 /* EMC_DLL_XFORM_DQ1 */ - 0x00094000 /* EMC_DLL_XFORM_DQ2 */ - 0x00094000 /* EMC_DLL_XFORM_DQ3 */ - 0x00009400 /* EMC_DLL_XFORM_DQ4 */ - 0x00009000 /* EMC_DLL_XFORM_DQ5 */ - 0x00009000 /* EMC_DLL_XFORM_DQ6 */ - 0x00009000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000066 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000d2b3 /* EMC_CFG_PIPE */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0174000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d /* EMC_RC */ - 0x0000004c /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000009 /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000007 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x0000000e /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x000008e4 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000004a /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x00000051 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000924 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00060000 /* EMC_DLL_XFORM_DQ0 */ - 0x00060000 /* EMC_DLL_XFORM_DQ1 */ - 0x00060000 /* EMC_DLL_XFORM_DQ2 */ - 0x00060000 /* EMC_DLL_XFORM_DQ3 */ - 0x00006000 /* EMC_DLL_XFORM_DQ4 */ - 0x00006000 /* EMC_DLL_XFORM_DQ5 */ - 0x00006000 /* EMC_DLL_XFORM_DQ6 */ - 0x00006000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000096 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0174000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000065 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000001 /* EMC_EINPUT */ - 0x00000008 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000000 /* EMC_QRST */ - 0x0000000f /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x00000bd1 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000063 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006b /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x0000000d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c11 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x00004800 /* EMC_DLL_XFORM_DQ4 */ - 0x00004800 /* EMC_DLL_XFORM_DQ5 */ - 0x00004800 /* EMC_DLL_XFORM_DQ6 */ - 0x00004800 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x000000c6 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x015b000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x013a000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 /* EMC_RC */ - 0x00000088 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000011 /* EMC_RAS */ - 0x00000006 /* EMC_RP */ - 0x00000006 /* EMC_R2W */ - 0x00000009 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000d /* EMC_W2P */ - 0x00000006 /* EMC_RD_RCD */ - 0x00000006 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000007 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000009 /* EMC_EINPUT_DURATION */ - 0x00040000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000010 /* EMC_QSAFE */ - 0x00000013 /* EMC_RDV */ - 0x00000015 /* EMC_RDV_MASK */ - 0x00000fd6 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000b /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000084 /* EMC_AR2PDEN */ - 0x00000012 /* EMC_RW2PDEN */ - 0x0000008f /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000013 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001017 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe01200b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x013a000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000042a0 /* EMC_CFG_PIPE */ - 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b /* EMC_QPOP */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0128000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001c /* EMC_RC */ - 0x0000009a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000013 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000007 /* EMC_R2W */ - 0x0000000b /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000010 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x0000000a /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000003 /* EMC_EINPUT */ - 0x0000000b /* EMC_EINPUT_DURATION */ - 0x00070000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000002 /* EMC_QRST */ - 0x00000012 /* EMC_QSAFE */ - 0x00000016 /* EMC_RDV */ - 0x00000018 /* EMC_RDV_MASK */ - 0x00001208 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000d /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000096 /* EMC_AR2PDEN */ - 0x00000015 /* EMC_RW2PDEN */ - 0x000000a2 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001249 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe00e00b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0128000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000040a0 /* EMC_CFG_PIPE */ - 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000e /* EMC_QPOP */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200418>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f8000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000cc /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000008 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x0000000b /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x0000000d /* EMC_EINPUT_DURATION */ - 0x00080000 /* EMC_PUTERM_EXTRA */ - 0x00000004 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000014 /* EMC_QSAFE */ - 0x00000018 /* EMC_RDV */ - 0x0000001a /* EMC_RDV_MASK */ - 0x000017e2 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000011 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000c6 /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d6 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000006 /* EMC_TCKESR */ - 0x00000005 /* EMC_TPD */ - 0x0000001d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000008 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001822 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x80000005 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab198 /* EMC_FBIO_CFG5 */ - 0xe00700b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000005 /* EMC_DLL_XFORM_DQS0 */ - 0x00000005 /* EMC_DLL_XFORM_DQS1 */ - 0x00000005 /* EMC_DLL_XFORM_DQS2 */ - 0x00000005 /* EMC_DLL_XFORM_DQS3 */ - 0x00000005 /* EMC_DLL_XFORM_DQS4 */ - 0x00000005 /* EMC_DLL_XFORM_DQS5 */ - 0x00000005 /* EMC_DLL_XFORM_DQS6 */ - 0x00000005 /* EMC_DLL_XFORM_DQS7 */ - 0x00000005 /* EMC_DLL_XFORM_DQS8 */ - 0x00000005 /* EMC_DLL_XFORM_DQS9 */ - 0x00000005 /* EMC_DLL_XFORM_DQS10 */ - 0x00000005 /* EMC_DLL_XFORM_DQS11 */ - 0x00000005 /* EMC_DLL_XFORM_DQS12 */ - 0x00000005 /* EMC_DLL_XFORM_DQS13 */ - 0x00000005 /* EMC_DLL_XFORM_DQS14 */ - 0x00000005 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x0000000a /* EMC_DLL_XFORM_DQ4 */ - 0x0000000a /* EMC_DLL_XFORM_DQ5 */ - 0x0000000a /* EMC_DLL_XFORM_DQ6 */ - 0x0000000a /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x61861820 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x61861800 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000007 /* EMC_CTT */ - 0x00000004 /* EMC_CTT_DURATION */ - 0x00004080 /* EMC_CFG_PIPE */ - 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000f /* EMC_QPOP */ - >; - }; - }; - - emc-timings-4 { - nvidia,ram-code = <4>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000004 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000007 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x0000009a /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000008 /* EMC_TXSR */ - 0x00000008 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000a0 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x0000000e /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000134 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000c /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000f /* EMC_TXSR */ - 0x0000000f /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000013f /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000015 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 /* EMC_RC */ - 0x00000017 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000002 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000202 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000015 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000019 /* EMC_TXSR */ - 0x00000019 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000213 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000022 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x00000023 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000304 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000021 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000025 /* EMC_TXSR */ - 0x00000025 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000033 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000047 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000006 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000004 /* EMC_EINPUT */ - 0x00000006 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000003 /* EMC_QRST */ - 0x0000000d /* EMC_QSAFE */ - 0x0000000f /* EMC_RDV */ - 0x00000011 /* EMC_RDV_MASK */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000044 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000004a /* EMC_TXSR */ - 0x0000004a /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000007 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00090000 /* EMC_DLL_XFORM_DQ0 */ - 0x00090000 /* EMC_DLL_XFORM_DQ1 */ - 0x00094000 /* EMC_DLL_XFORM_DQ2 */ - 0x00094000 /* EMC_DLL_XFORM_DQ3 */ - 0x00009400 /* EMC_DLL_XFORM_DQ4 */ - 0x00009000 /* EMC_DLL_XFORM_DQ5 */ - 0x00009000 /* EMC_DLL_XFORM_DQ6 */ - 0x00009000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000066 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000d2b3 /* EMC_CFG_PIPE */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000321>; - nvidia,emc-mrs-wait-cnt = <0x0117000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + timing-68000000 { + clock-frequency = <68000000>; - nvidia,emc-configuration = < - 0x0000000d /* EMC_RC */ - 0x00000067 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000009 /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000007 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x0000000e /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x000008e4 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000065 /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x0000006c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000924 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00060000 /* EMC_DLL_XFORM_DQ0 */ - 0x00060000 /* EMC_DLL_XFORM_DQ1 */ - 0x00060000 /* EMC_DLL_XFORM_DQ2 */ - 0x00060000 /* EMC_DLL_XFORM_DQ3 */ - 0x00006000 /* EMC_DLL_XFORM_DQ4 */ - 0x00006000 /* EMC_DLL_XFORM_DQ5 */ - 0x00006000 /* EMC_DLL_XFORM_DQ6 */ - 0x00006000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000096 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0117000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74230403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; timing-396000000 { clock-frequency = <396000000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000521>; - nvidia,emc-mrs-wait-cnt = <0x00f5000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000011 /* EMC_RC */ - 0x00000089 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000001 /* EMC_EINPUT */ - 0x00000008 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000000 /* EMC_QRST */ - 0x0000000f /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x00000bd1 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000087 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000008f /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x0000000d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c11 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x00004800 /* EMC_DLL_XFORM_DQ4 */ - 0x00004800 /* EMC_DLL_XFORM_DQ5 */ - 0x00004800 /* EMC_DLL_XFORM_DQ6 */ - 0x00004800 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x000000c6 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f5000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; timing-528000000 { clock-frequency = <528000000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000941>; - nvidia,emc-mrs-wait-cnt = <0x00c8000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ + 0x7428180e /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x00000018 /* EMC_RC */ - 0x000000b7 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000010 /* EMC_RAS */ - 0x00000006 /* EMC_RP */ - 0x00000006 /* EMC_R2W */ - 0x00000009 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000d /* EMC_W2P */ - 0x00000006 /* EMC_RD_RCD */ - 0x00000006 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000007 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000009 /* EMC_EINPUT_DURATION */ - 0x00040000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000010 /* EMC_QSAFE */ - 0x00000013 /* EMC_RDV */ - 0x00000015 /* EMC_RDV_MASK */ - 0x00000fd6 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000b /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000b4 /* EMC_AR2PDEN */ - 0x00000012 /* EMC_RW2PDEN */ - 0x000000bf /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000013 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001017 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe01200b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00c8000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000042a0 /* EMC_CFG_PIPE */ - 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b /* EMC_QPOP */ + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x734c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-4 { + nvidia,ram-code = <4>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; - timing-600000000 { - clock-frequency = <600000000>; + timing-20400000 { + clock-frequency = <20400000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000b61>; - nvidia,emc-mrs-wait-cnt = <0x00b0000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x77430303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x0000001b /* EMC_RC */ - 0x000000d0 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000013 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000007 /* EMC_R2W */ - 0x0000000b /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000010 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x0000000a /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000003 /* EMC_EINPUT */ - 0x0000000b /* EMC_EINPUT_DURATION */ - 0x00070000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000002 /* EMC_QRST */ - 0x00000012 /* EMC_QSAFE */ - 0x00000016 /* EMC_RDV */ - 0x00000018 /* EMC_RDV_MASK */ - 0x00001208 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000d /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000cc /* EMC_AR2PDEN */ - 0x00000015 /* EMC_RW2PDEN */ - 0x000000d8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001249 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe00e00b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00b0000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000040a0 /* EMC_CFG_PIPE */ - 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000e /* EMC_QPOP */ + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75430403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; - timing-792000000 { - clock-frequency = <792000000>; + timing-102000000 { + clock-frequency = <102000000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200418>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000d71>; - nvidia,emc-mrs-wait-cnt = <0x006f000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x74e30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x00000024 /* EMC_RC */ - 0x00000114 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000019 /* EMC_RAS */ - 0x0000000a /* EMC_RP */ - 0x00000008 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x0000000a /* EMC_RD_RCD */ - 0x0000000a /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x0000000b /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x0000000d /* EMC_EINPUT_DURATION */ - 0x00080000 /* EMC_PUTERM_EXTRA */ - 0x00000004 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000014 /* EMC_QSAFE */ - 0x00000018 /* EMC_RDV */ - 0x0000001a /* EMC_RDV_MASK */ - 0x000017e2 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000011 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000010d /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x0000011e /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000006 /* EMC_TCKESR */ - 0x00000005 /* EMC_TPD */ - 0x0000001d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000008 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001822 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x80000005 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab198 /* EMC_FBIO_CFG5 */ - 0xe00700b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x007fc007 /* EMC_DLL_XFORM_DQS0 */ - 0x007fc008 /* EMC_DLL_XFORM_DQS1 */ - 0x007f400c /* EMC_DLL_XFORM_DQS2 */ - 0x007fc007 /* EMC_DLL_XFORM_DQS3 */ - 0x007f4006 /* EMC_DLL_XFORM_DQS4 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS5 */ - 0x007f8005 /* EMC_DLL_XFORM_DQS6 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS7 */ - 0x007fc007 /* EMC_DLL_XFORM_DQS8 */ - 0x007fc008 /* EMC_DLL_XFORM_DQS9 */ - 0x007f400c /* EMC_DLL_XFORM_DQS10 */ - 0x007fc007 /* EMC_DLL_XFORM_DQS11 */ - 0x007f4006 /* EMC_DLL_XFORM_DQS12 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS13 */ - 0x007f8005 /* EMC_DLL_XFORM_DQS14 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x61861820 /* EMC_XM2DQSPADCTRL3 */ - 0x00492492 /* EMC_XM2DQSPADCTRL4 */ - 0x00492492 /* EMC_XM2DQSPADCTRL5 */ - 0x61861800 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x006f000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000007 /* EMC_CTT */ - 0x00000004 /* EMC_CTT_DURATION */ - 0x00004080 /* EMC_CFG_PIPE */ - 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000f /* EMC_QPOP */ + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0504 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a40a05 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RC */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090c /* MC_EMEM_ARB_DA_COVERS */ + 0x7488180d /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x74691b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00170e13 /* MC_EMEM_ARB_DA_COVERS */ + 0x746c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; }; @@ -3930,677 +836,297 @@ timing-12750000 { clock-frequency = <12750000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000003 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; timing-20400000 { clock-frequency = <20400000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x76230303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000005 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x0000009a /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000006 /* EMC_TXSR */ - 0x00000006 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000a0 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74230403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; - timing-40800000 { - clock-frequency = <40800000>; + timing-204000000 { + clock-frequency = <204000000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x0000000a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000134 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000c /* EMC_TXSR */ - 0x0000000c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000013f /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000015 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ + 0x7428180e /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; - timing-68000000 { - clock-frequency = <68000000>; + timing-600000000 { + clock-frequency = <600000000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; - nvidia,emc-configuration = < - 0x00000003 /* EMC_RC */ - 0x00000011 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000002 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000202 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000013 /* EMC_TXSR */ - 0x00000013 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000213 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000022 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x734c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; + }; + }; - timing-102000000 { - clock-frequency = <102000000>; + external-memory-controller@7001b000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; @@ -4621,17 +1147,17 @@ nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ 0x00000000 /* EMC_RFC_SLR */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ 0x00000004 /* EMC_R2W */ 0x0000000a /* EMC_W2R */ 0x00000003 /* EMC_R2P */ 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ 0x00000003 /* EMC_RRD */ 0x00000003 /* EMC_REXT */ 0x00000000 /* EMC_WEXT */ @@ -4652,25 +1178,25 @@ 0x0000000c /* EMC_QSAFE */ 0x0000000d /* EMC_RDV */ 0x0000000f /* EMC_RDV_MASK */ - 0x00000304 /* EMC_REFRESH */ + 0x00000060 /* EMC_REFRESH */ 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002 /* EMC_PDEX2WR */ 0x00000002 /* EMC_PDEX2RD */ 0x00000001 /* EMC_PCHG2PDEN */ 0x00000000 /* EMC_ACT2PDEN */ - 0x00000018 /* EMC_AR2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ 0x00000004 /* EMC_TCKE */ 0x00000005 /* EMC_TCKESR */ 0x00000004 /* EMC_TPD */ - 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TFAW */ 0x00000000 /* EMC_TRPAB */ 0x00000005 /* EMC_TCLKSTABLE */ 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ + 0x00000064 /* EMC_TREFBW */ 0x00000000 /* EMC_FBIO_CFG6 */ 0x00000000 /* EMC_ODT_WRITE */ 0x00000000 /* EMC_ODT_READ */ @@ -4755,20 +1281,20 @@ 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 0x51451400 /* EMC_XM2DQSPADCTRL6 */ 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000033 /* EMC_TXDSRVTTGEN */ + 0x00000007 /* EMC_TXDSRVTTGEN */ 0x00000000 /* EMC_FBIO_SPARE */ 0x00000042 /* EMC_ZCAL_WAIT_CNT */ 0x000c000c /* EMC_MRS_WAIT_CNT2 */ 0x00000000 /* EMC_CTT */ 0x00000003 /* EMC_CTT_DURATION */ 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ 0x0000000a /* EMC_QPOP */ >; }; - timing-204000000 { - clock-frequency = <204000000>; + timing-20400000 { + clock-frequency = <20400000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; @@ -4776,69 +1302,69 @@ nvidia,emc-auto-cal-interval = <0x001fffff>; nvidia,emc-bgbias-ctl0 = <0x00000008>; nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; nvidia,emc-mode-1 = <0x80100003>; nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; nvidia,emc-mode-reset = <0x80001221>; nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ + 0x00000000 /* EMC_RC */ + 0x00000005 /* EMC_RFC */ 0x00000000 /* EMC_RFC_SLR */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ 0x0000000a /* EMC_W2R */ 0x00000003 /* EMC_R2P */ 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ 0x00000003 /* EMC_RRD */ 0x00000003 /* EMC_REXT */ 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ 0x00000006 /* EMC_QUSE */ 0x00000002 /* EMC_QUSE_WIDTH */ 0x00000000 /* EMC_IBDLY */ - 0x00000004 /* EMC_EINPUT */ - 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ 0x00010000 /* EMC_PUTERM_EXTRA */ 0x00000003 /* EMC_PUTERM_WIDTH */ 0x00000000 /* EMC_PUTERM_ADJ */ 0x00000000 /* EMC_CDB_CNTL_1 */ 0x00000000 /* EMC_CDB_CNTL_2 */ 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000003 /* EMC_QRST */ - 0x0000000d /* EMC_QSAFE */ - 0x0000000f /* EMC_RDV */ - 0x00000011 /* EMC_RDV_MASK */ - 0x00000607 /* EMC_REFRESH */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x0000009a /* EMC_REFRESH */ 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002 /* EMC_PDEX2WR */ 0x00000002 /* EMC_PDEX2RD */ 0x00000001 /* EMC_PCHG2PDEN */ 0x00000000 /* EMC_ACT2PDEN */ - 0x00000032 /* EMC_AR2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ + 0x00000006 /* EMC_TXSR */ + 0x00000006 /* EMC_TXSRDLL */ 0x00000004 /* EMC_TCKE */ 0x00000005 /* EMC_TCKESR */ 0x00000004 /* EMC_TPD */ - 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TFAW */ 0x00000000 /* EMC_TRPAB */ 0x00000005 /* EMC_TCLKSTABLE */ 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ + 0x000000a0 /* EMC_TREFBW */ 0x00000000 /* EMC_FBIO_CFG6 */ 0x00000000 /* EMC_ODT_WRITE */ 0x00000000 /* EMC_ODT_READ */ @@ -4899,14 +1425,14 @@ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00090000 /* EMC_DLL_XFORM_DQ0 */ - 0x00090000 /* EMC_DLL_XFORM_DQ1 */ - 0x00094000 /* EMC_DLL_XFORM_DQ2 */ - 0x00094000 /* EMC_DLL_XFORM_DQ3 */ - 0x00009400 /* EMC_DLL_XFORM_DQ4 */ - 0x00009000 /* EMC_DLL_XFORM_DQ5 */ - 0x00009000 /* EMC_DLL_XFORM_DQ6 */ - 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ 0x10000280 /* EMC_XM2CMDPADCTRL */ 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 0x00111111 /* EMC_XM2CMDPADCTRL5 */ @@ -4923,280 +1449,112 @@ 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 0x51451400 /* EMC_XM2DQSPADCTRL6 */ 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000066 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000d2b3 /* EMC_CFG_PIPE */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0174000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d /* EMC_RC */ - 0x0000004c /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000009 /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000007 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x0000000e /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x000008e4 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000004a /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x00000051 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000924 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00060000 /* EMC_DLL_XFORM_DQ0 */ - 0x00060000 /* EMC_DLL_XFORM_DQ1 */ - 0x00060000 /* EMC_DLL_XFORM_DQ2 */ - 0x00060000 /* EMC_DLL_XFORM_DQ3 */ - 0x00006000 /* EMC_DLL_XFORM_DQ4 */ - 0x00006000 /* EMC_DLL_XFORM_DQ5 */ - 0x00006000 /* EMC_DLL_XFORM_DQ6 */ - 0x00006000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x0000000b /* EMC_TXDSRVTTGEN */ 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0174000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ 0x00000000 /* EMC_CTT */ 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; - timing-396000000 { - clock-frequency = <396000000>; + timing-40800000 { + clock-frequency = <40800000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000065 /* EMC_RFC */ + 0x00000001 /* EMC_RC */ + 0x0000000a /* EMC_RFC */ 0x00000000 /* EMC_RFC_SLR */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ 0x00000002 /* EMC_QUSE_WIDTH */ 0x00000000 /* EMC_IBDLY */ - 0x00000001 /* EMC_EINPUT */ - 0x00000008 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ 0x00000003 /* EMC_PUTERM_WIDTH */ 0x00000000 /* EMC_PUTERM_ADJ */ 0x00000000 /* EMC_CDB_CNTL_1 */ 0x00000000 /* EMC_CDB_CNTL_2 */ 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000000 /* EMC_QRST */ - 0x0000000f /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x00000bd1 /* EMC_REFRESH */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000134 /* EMC_REFRESH */ 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ + 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ 0x00000001 /* EMC_PCHG2PDEN */ 0x00000000 /* EMC_ACT2PDEN */ - 0x00000063 /* EMC_AR2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ 0x0000000f /* EMC_RW2PDEN */ - 0x0000006b /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ + 0x0000000c /* EMC_TXSR */ + 0x0000000c /* EMC_TXSRDLL */ 0x00000004 /* EMC_TCKE */ 0x00000005 /* EMC_TCKESR */ 0x00000004 /* EMC_TPD */ - 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TFAW */ 0x00000000 /* EMC_TRPAB */ 0x00000005 /* EMC_TCLKSTABLE */ 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c11 /* EMC_TREFBW */ + 0x0000013f /* EMC_TREFBW */ 0x00000000 /* EMC_FBIO_CFG6 */ 0x00000000 /* EMC_ODT_WRITE */ 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x106aa298 /* EMC_FBIO_CFG5 */ 0x002c00a0 /* EMC_CFG_DIG_DLL */ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ @@ -5205,12 +1563,12 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ @@ -5235,136 +1593,136 @@ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x00004800 /* EMC_DLL_XFORM_DQ4 */ - 0x00004800 /* EMC_DLL_XFORM_DQ5 */ - 0x00004800 /* EMC_DLL_XFORM_DQ6 */ - 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ 0x10000280 /* EMC_XM2CMDPADCTRL */ 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 0x00111111 /* EMC_XM2CMDPADCTRL5 */ 0x00000000 /* EMC_XM2DQPADCTRL2 */ 0x00000000 /* EMC_XM2DQPADCTRL3 */ 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ 0x81f1f108 /* EMC_XM2COMPPADCTRL */ 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ 0x00514514 /* EMC_XM2DQSPADCTRL4 */ 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 0x51451400 /* EMC_XM2DQSPADCTRL6 */ 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000015 /* EMC_TXDSRVTTGEN */ 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x015b000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ 0x00000000 /* EMC_CTT */ 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; - timing-528000000 { - clock-frequency = <528000000>; + timing-68000000 { + clock-frequency = <68000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-1 = <0x80100003>; nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x013a000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000018 /* EMC_RC */ - 0x00000088 /* EMC_RFC */ + 0x00000003 /* EMC_RC */ + 0x00000011 /* EMC_RFC */ 0x00000000 /* EMC_RFC_SLR */ - 0x00000011 /* EMC_RAS */ - 0x00000006 /* EMC_RP */ - 0x00000006 /* EMC_R2W */ - 0x00000009 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000d /* EMC_W2P */ - 0x00000006 /* EMC_RD_RCD */ - 0x00000006 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ + 0x00000002 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000007 /* EMC_QUSE */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ 0x00000002 /* EMC_QUSE_WIDTH */ 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000009 /* EMC_EINPUT_DURATION */ - 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ 0x00000003 /* EMC_PUTERM_WIDTH */ 0x00000000 /* EMC_PUTERM_ADJ */ 0x00000000 /* EMC_CDB_CNTL_1 */ 0x00000000 /* EMC_CDB_CNTL_2 */ 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000010 /* EMC_QSAFE */ - 0x00000013 /* EMC_RDV */ - 0x00000015 /* EMC_RDV_MASK */ - 0x00000fd6 /* EMC_REFRESH */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000202 /* EMC_REFRESH */ 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002 /* EMC_PDEX2WR */ - 0x0000000b /* EMC_PDEX2RD */ + 0x00000002 /* EMC_PDEX2RD */ 0x00000001 /* EMC_PCHG2PDEN */ 0x00000000 /* EMC_ACT2PDEN */ - 0x00000084 /* EMC_AR2PDEN */ - 0x00000012 /* EMC_RW2PDEN */ - 0x0000008f /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ + 0x0000000f /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000013 /* EMC_TXSR */ + 0x00000013 /* EMC_TXSRDLL */ 0x00000004 /* EMC_TCKE */ 0x00000005 /* EMC_TCKESR */ 0x00000004 /* EMC_TPD */ - 0x00000013 /* EMC_TFAW */ + 0x00000001 /* EMC_TFAW */ 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001017 /* EMC_TREFBW */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000213 /* EMC_TREFBW */ 0x00000000 /* EMC_FBIO_CFG6 */ 0x00000000 /* EMC_ODT_WRITE */ 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ @@ -5373,12 +1731,12 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ @@ -5387,152 +1745,152 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 0x00111111 /* EMC_XM2CMDPADCTRL5 */ 0x00000000 /* EMC_XM2DQPADCTRL2 */ 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ 0x81f1f108 /* EMC_XM2COMPPADCTRL */ 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ 0x00514514 /* EMC_XM2DQSPADCTRL4 */ 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000022 /* EMC_TXDSRVTTGEN */ 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x013a000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ 0x00000000 /* EMC_CTT */ 0x00000003 /* EMC_CTT_DURATION */ - 0x000042a0 /* EMC_CFG_PIPE */ - 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b /* EMC_QPOP */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; - timing-600000000 { - clock-frequency = <600000000>; + timing-102000000 { + clock-frequency = <102000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0128000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x0000001c /* EMC_RC */ - 0x0000009a /* EMC_RFC */ + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ 0x00000000 /* EMC_RFC_SLR */ - 0x00000013 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000007 /* EMC_R2W */ - 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ 0x00000003 /* EMC_R2P */ - 0x00000010 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ 0x00000003 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ + 0x00000003 /* EMC_REXT */ 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x0000000a /* EMC_QUSE */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ 0x00000002 /* EMC_QUSE_WIDTH */ 0x00000000 /* EMC_IBDLY */ - 0x00000003 /* EMC_EINPUT */ - 0x0000000b /* EMC_EINPUT_DURATION */ - 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ 0x00000003 /* EMC_PUTERM_WIDTH */ 0x00000000 /* EMC_PUTERM_ADJ */ 0x00000000 /* EMC_CDB_CNTL_1 */ 0x00000000 /* EMC_CDB_CNTL_2 */ 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000002 /* EMC_QRST */ - 0x00000012 /* EMC_QSAFE */ - 0x00000016 /* EMC_RDV */ - 0x00000018 /* EMC_RDV_MASK */ - 0x00001208 /* EMC_REFRESH */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000304 /* EMC_REFRESH */ 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002 /* EMC_PDEX2WR */ - 0x0000000d /* EMC_PDEX2RD */ + 0x00000002 /* EMC_PDEX2RD */ 0x00000001 /* EMC_PCHG2PDEN */ 0x00000000 /* EMC_ACT2PDEN */ - 0x00000096 /* EMC_AR2PDEN */ - 0x00000015 /* EMC_RW2PDEN */ - 0x000000a2 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ + 0x00000018 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ 0x00000004 /* EMC_TCKE */ 0x00000005 /* EMC_TCKESR */ 0x00000004 /* EMC_TPD */ - 0x00000015 /* EMC_TFAW */ + 0x00000003 /* EMC_TFAW */ 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001249 /* EMC_TREFBW */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ 0x00000000 /* EMC_FBIO_CFG6 */ 0x00000000 /* EMC_ODT_WRITE */ 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ @@ -5541,12 +1899,12 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ @@ -5555,152 +1913,152 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 0x00111111 /* EMC_XM2CMDPADCTRL5 */ 0x00000000 /* EMC_XM2DQPADCTRL2 */ 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ 0x81f1f108 /* EMC_XM2COMPPADCTRL */ 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ 0x00514514 /* EMC_XM2DQSPADCTRL4 */ 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000033 /* EMC_TXDSRVTTGEN */ 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0128000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ 0x00000000 /* EMC_CTT */ 0x00000003 /* EMC_CTT_DURATION */ - 0x000040a0 /* EMC_CFG_PIPE */ - 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000e /* EMC_QPOP */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; - timing-792000000 { - clock-frequency = <792000000>; + timing-204000000 { + clock-frequency = <204000000>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200418>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f8000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; nvidia,emc-zcal-cnt-long = <0x00000042>; nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000cc /* EMC_RFC */ + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ 0x00000000 /* EMC_RFC_SLR */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000008 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000004 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x0000000b /* EMC_QUSE */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ 0x00000002 /* EMC_QUSE_WIDTH */ 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x0000000d /* EMC_EINPUT_DURATION */ - 0x00080000 /* EMC_PUTERM_EXTRA */ - 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000004 /* EMC_EINPUT */ + 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ 0x00000000 /* EMC_PUTERM_ADJ */ 0x00000000 /* EMC_CDB_CNTL_1 */ 0x00000000 /* EMC_CDB_CNTL_2 */ 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000014 /* EMC_QSAFE */ - 0x00000018 /* EMC_RDV */ - 0x0000001a /* EMC_RDV_MASK */ - 0x000017e2 /* EMC_REFRESH */ + 0x00000003 /* EMC_QRST */ + 0x0000000d /* EMC_QSAFE */ + 0x0000000f /* EMC_RDV */ + 0x00000011 /* EMC_RDV_MASK */ + 0x00000607 /* EMC_REFRESH */ 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000011 /* EMC_PDEX2RD */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ 0x00000001 /* EMC_PCHG2PDEN */ 0x00000000 /* EMC_ACT2PDEN */ - 0x000000c6 /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d6 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000006 /* EMC_TCKESR */ - 0x00000005 /* EMC_TPD */ - 0x0000001d /* EMC_TFAW */ + 0x00000032 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000007 /* EMC_TFAW */ 0x00000000 /* EMC_TRPAB */ - 0x00000008 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001822 /* EMC_TREFBW */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ 0x00000000 /* EMC_FBIO_CFG6 */ - 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_WRITE */ 0x00000000 /* EMC_ODT_READ */ - 0x104ab198 /* EMC_FBIO_CFG5 */ - 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000009 /* EMC_DLL_XFORM_DQS0 */ - 0x00000009 /* EMC_DLL_XFORM_DQS1 */ - 0x00000009 /* EMC_DLL_XFORM_DQS2 */ - 0x00000007 /* EMC_DLL_XFORM_DQS3 */ - 0x00000006 /* EMC_DLL_XFORM_DQS4 */ - 0x00000006 /* EMC_DLL_XFORM_DQS5 */ - 0x007fc009 /* EMC_DLL_XFORM_DQS6 */ - 0x00000006 /* EMC_DLL_XFORM_DQS7 */ - 0x00000009 /* EMC_DLL_XFORM_DQS8 */ - 0x00000009 /* EMC_DLL_XFORM_DQS9 */ - 0x00000009 /* EMC_DLL_XFORM_DQS10 */ - 0x00000007 /* EMC_DLL_XFORM_DQS11 */ - 0x00000006 /* EMC_DLL_XFORM_DQS12 */ - 0x00000007 /* EMC_DLL_XFORM_DQS13 */ - 0x00000009 /* EMC_DLL_XFORM_DQS14 */ - 0x00000007 /* EMC_DLL_XFORM_DQS15 */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ @@ -5709,12 +2067,12 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR0 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR3 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ @@ -5723,347 +2081,895 @@ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00090000 /* EMC_DLL_XFORM_DQ0 */ + 0x00090000 /* EMC_DLL_XFORM_DQ1 */ + 0x00094000 /* EMC_DLL_XFORM_DQ2 */ + 0x00094000 /* EMC_DLL_XFORM_DQ3 */ + 0x00009400 /* EMC_DLL_XFORM_DQ4 */ + 0x00009000 /* EMC_DLL_XFORM_DQ5 */ + 0x00009000 /* EMC_DLL_XFORM_DQ6 */ + 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 0x00111111 /* EMC_XM2CMDPADCTRL5 */ 0x00000000 /* EMC_XM2DQPADCTRL2 */ 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ 0x81f1f108 /* EMC_XM2COMPPADCTRL */ 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x61861820 /* EMC_XM2DQSPADCTRL3 */ - 0x004d34d3 /* EMC_XM2DQSPADCTRL4 */ - 0x004d34d3 /* EMC_XM2DQSPADCTRL5 */ - 0x61861800 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000066 /* EMC_TXDSRVTTGEN */ 0x00000000 /* EMC_FBIO_SPARE */ 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000007 /* EMC_CTT */ - 0x00000004 /* EMC_CTT_DURATION */ - 0x00004080 /* EMC_CFG_PIPE */ - 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000f /* EMC_QPOP */ - >; - }; - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000d2b3 /* EMC_CFG_PIPE */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-300000000 { clock-frequency = <300000000>; - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0174000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d /* EMC_RC */ + 0x0000004c /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000009 /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000007 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x0000000e /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x000008e4 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000004a /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000051 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000924 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00060000 /* EMC_DLL_XFORM_DQ0 */ + 0x00060000 /* EMC_DLL_XFORM_DQ1 */ + 0x00060000 /* EMC_DLL_XFORM_DQ2 */ + 0x00060000 /* EMC_DLL_XFORM_DQ3 */ + 0x00006000 /* EMC_DLL_XFORM_DQ4 */ + 0x00006000 /* EMC_DLL_XFORM_DQ5 */ + 0x00006000 /* EMC_DLL_XFORM_DQ6 */ + 0x00006000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0174000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; timing-396000000 { clock-frequency = <396000000>; - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000065 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000001 /* EMC_EINPUT */ + 0x00000008 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000000 /* EMC_QRST */ + 0x0000000f /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x00000bd1 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000063 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006b /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c11 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x00004800 /* EMC_DLL_XFORM_DQ4 */ + 0x00004800 /* EMC_DLL_XFORM_DQ5 */ + 0x00004800 /* EMC_DLL_XFORM_DQ6 */ + 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x015b000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; timing-528000000 { clock-frequency = <528000000>; - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ - 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180e /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x013a000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 /* EMC_RC */ + 0x00000088 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000011 /* EMC_RAS */ + 0x00000006 /* EMC_RP */ + 0x00000006 /* EMC_R2W */ + 0x00000009 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000d /* EMC_W2P */ + 0x00000006 /* EMC_RD_RCD */ + 0x00000006 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000007 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000009 /* EMC_EINPUT_DURATION */ + 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000010 /* EMC_QSAFE */ + 0x00000013 /* EMC_RDV */ + 0x00000015 /* EMC_RDV_MASK */ + 0x00000fd6 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000b /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000084 /* EMC_AR2PDEN */ + 0x00000012 /* EMC_RW2PDEN */ + 0x0000008f /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000013 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001017 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x013a000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000042a0 /* EMC_CFG_PIPE */ + 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b /* EMC_QPOP */ >; }; timing-600000000 { clock-frequency = <600000000>; - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0128000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001c /* EMC_RC */ + 0x0000009a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000013 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000007 /* EMC_R2W */ + 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000010 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x0000000a /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000003 /* EMC_EINPUT */ + 0x0000000b /* EMC_EINPUT_DURATION */ + 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000002 /* EMC_QRST */ + 0x00000012 /* EMC_QSAFE */ + 0x00000016 /* EMC_RDV */ + 0x00000018 /* EMC_RDV_MASK */ + 0x00001208 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000d /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000096 /* EMC_AR2PDEN */ + 0x00000015 /* EMC_RW2PDEN */ + 0x000000a2 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001249 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0128000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000040a0 /* EMC_CFG_PIPE */ + 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e /* EMC_QPOP */ >; }; timing-792000000 { clock-frequency = <792000000>; - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000cc /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000008 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x0000000b /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x0000000d /* EMC_EINPUT_DURATION */ + 0x00080000 /* EMC_PUTERM_EXTRA */ + 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000014 /* EMC_QSAFE */ + 0x00000018 /* EMC_RDV */ + 0x0000001a /* EMC_RDV_MASK */ + 0x000017e2 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000011 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000c6 /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d6 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000006 /* EMC_TCKESR */ + 0x00000005 /* EMC_TPD */ + 0x0000001d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000008 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001822 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab198 /* EMC_FBIO_CFG5 */ + 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000005 /* EMC_DLL_XFORM_DQS0 */ + 0x00000005 /* EMC_DLL_XFORM_DQS1 */ + 0x00000005 /* EMC_DLL_XFORM_DQS2 */ + 0x00000005 /* EMC_DLL_XFORM_DQS3 */ + 0x00000005 /* EMC_DLL_XFORM_DQS4 */ + 0x00000005 /* EMC_DLL_XFORM_DQS5 */ + 0x00000005 /* EMC_DLL_XFORM_DQS6 */ + 0x00000005 /* EMC_DLL_XFORM_DQS7 */ + 0x00000005 /* EMC_DLL_XFORM_DQS8 */ + 0x00000005 /* EMC_DLL_XFORM_DQS9 */ + 0x00000005 /* EMC_DLL_XFORM_DQS10 */ + 0x00000005 /* EMC_DLL_XFORM_DQS11 */ + 0x00000005 /* EMC_DLL_XFORM_DQS12 */ + 0x00000005 /* EMC_DLL_XFORM_DQS13 */ + 0x00000005 /* EMC_DLL_XFORM_DQS14 */ + 0x00000005 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x0000000a /* EMC_DLL_XFORM_DQ4 */ + 0x0000000a /* EMC_DLL_XFORM_DQ5 */ + 0x0000000a /* EMC_DLL_XFORM_DQ6 */ + 0x0000000a /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x61861820 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x61861800 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000007 /* EMC_CTT */ + 0x00000004 /* EMC_CTT_DURATION */ + 0x00004080 /* EMC_CFG_PIPE */ + 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f /* EMC_QPOP */ >; }; }; @@ -6074,286 +2980,1848 @@ timing-12750000 { clock-frequency = <12750000>; - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000004 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-20400000 { clock-frequency = <20400000>; - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x77430303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000007 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x0000009a /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000008 /* EMC_TXSR */ + 0x00000008 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000a0 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x0000000b /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-40800000 { clock-frequency = <40800000>; - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x0000000e /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000134 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000f /* EMC_TXSR */ + 0x0000000f /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000013f /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000015 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-68000000 { clock-frequency = <68000000>; - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75430403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 /* EMC_RC */ + 0x00000017 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000002 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000202 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000015 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000019 /* EMC_TXSR */ + 0x00000019 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000213 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000022 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-102000000 { clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x74e30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x00000023 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000304 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000021 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000025 /* EMC_TXSR */ + 0x00000025 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000033 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-204000000 { clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0504 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a40a05 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000047 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000006 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000004 /* EMC_EINPUT */ + 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000003 /* EMC_QRST */ + 0x0000000d /* EMC_QSAFE */ + 0x0000000f /* EMC_RDV */ + 0x00000011 /* EMC_RDV_MASK */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000044 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000004a /* EMC_TXSR */ + 0x0000004a /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00090000 /* EMC_DLL_XFORM_DQ0 */ + 0x00090000 /* EMC_DLL_XFORM_DQ1 */ + 0x00094000 /* EMC_DLL_XFORM_DQ2 */ + 0x00094000 /* EMC_DLL_XFORM_DQ3 */ + 0x00009400 /* EMC_DLL_XFORM_DQ4 */ + 0x00009000 /* EMC_DLL_XFORM_DQ5 */ + 0x00009000 /* EMC_DLL_XFORM_DQ6 */ + 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000066 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000d2b3 /* EMC_CFG_PIPE */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-300000000 { clock-frequency = <300000000>; - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000321>; + nvidia,emc-mrs-wait-cnt = <0x0117000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d /* EMC_RC */ + 0x00000067 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000009 /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000007 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x0000000e /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x000008e4 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000065 /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000924 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00060000 /* EMC_DLL_XFORM_DQ0 */ + 0x00060000 /* EMC_DLL_XFORM_DQ1 */ + 0x00060000 /* EMC_DLL_XFORM_DQ2 */ + 0x00060000 /* EMC_DLL_XFORM_DQ3 */ + 0x00006000 /* EMC_DLL_XFORM_DQ4 */ + 0x00006000 /* EMC_DLL_XFORM_DQ5 */ + 0x00006000 /* EMC_DLL_XFORM_DQ6 */ + 0x00006000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0117000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; timing-396000000 { clock-frequency = <396000000>; - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000521>; + nvidia,emc-mrs-wait-cnt = <0x00f5000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000011 /* EMC_RC */ + 0x00000089 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000001 /* EMC_EINPUT */ + 0x00000008 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000000 /* EMC_QRST */ + 0x0000000f /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x00000bd1 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000087 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000008f /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c11 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x00004800 /* EMC_DLL_XFORM_DQ4 */ + 0x00004800 /* EMC_DLL_XFORM_DQ5 */ + 0x00004800 /* EMC_DLL_XFORM_DQ6 */ + 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f5000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; timing-528000000 { clock-frequency = <528000000>; - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090c /* MC_EMEM_ARB_DA_COVERS */ - 0x7488180d /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000941>; + nvidia,emc-mrs-wait-cnt = <0x00c8000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 /* EMC_RC */ + 0x000000b7 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000010 /* EMC_RAS */ + 0x00000006 /* EMC_RP */ + 0x00000006 /* EMC_R2W */ + 0x00000009 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000d /* EMC_W2P */ + 0x00000006 /* EMC_RD_RCD */ + 0x00000006 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000007 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000009 /* EMC_EINPUT_DURATION */ + 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000010 /* EMC_QSAFE */ + 0x00000013 /* EMC_RDV */ + 0x00000015 /* EMC_RDV_MASK */ + 0x00000fd6 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000b /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000b4 /* EMC_AR2PDEN */ + 0x00000012 /* EMC_RW2PDEN */ + 0x000000bf /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000013 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001017 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00c8000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000042a0 /* EMC_CFG_PIPE */ + 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b /* EMC_QPOP */ >; }; timing-600000000 { clock-frequency = <600000000>; - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x74691b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000b61>; + nvidia,emc-mrs-wait-cnt = <0x00b0000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001b /* EMC_RC */ + 0x000000d0 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000013 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000007 /* EMC_R2W */ + 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000010 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x0000000a /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000003 /* EMC_EINPUT */ + 0x0000000b /* EMC_EINPUT_DURATION */ + 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000002 /* EMC_QRST */ + 0x00000012 /* EMC_QSAFE */ + 0x00000016 /* EMC_RDV */ + 0x00000018 /* EMC_RDV_MASK */ + 0x00001208 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000d /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000cc /* EMC_AR2PDEN */ + 0x00000015 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001249 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00b0000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000040a0 /* EMC_CFG_PIPE */ + 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e /* EMC_QPOP */ >; }; timing-792000000 { clock-frequency = <792000000>; - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00170e13 /* MC_EMEM_ARB_DA_COVERS */ - 0x746c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000d71>; + nvidia,emc-mrs-wait-cnt = <0x006f000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000024 /* EMC_RC */ + 0x00000114 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000019 /* EMC_RAS */ + 0x0000000a /* EMC_RP */ + 0x00000008 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x0000000a /* EMC_RD_RCD */ + 0x0000000a /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x0000000b /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x0000000d /* EMC_EINPUT_DURATION */ + 0x00080000 /* EMC_PUTERM_EXTRA */ + 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000014 /* EMC_QSAFE */ + 0x00000018 /* EMC_RDV */ + 0x0000001a /* EMC_RDV_MASK */ + 0x000017e2 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000011 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000010d /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x0000011e /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000006 /* EMC_TCKESR */ + 0x00000005 /* EMC_TPD */ + 0x0000001d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000008 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001822 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab198 /* EMC_FBIO_CFG5 */ + 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x007fc007 /* EMC_DLL_XFORM_DQS0 */ + 0x007fc008 /* EMC_DLL_XFORM_DQS1 */ + 0x007f400c /* EMC_DLL_XFORM_DQS2 */ + 0x007fc007 /* EMC_DLL_XFORM_DQS3 */ + 0x007f4006 /* EMC_DLL_XFORM_DQS4 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS5 */ + 0x007f8005 /* EMC_DLL_XFORM_DQS6 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS7 */ + 0x007fc007 /* EMC_DLL_XFORM_DQS8 */ + 0x007fc008 /* EMC_DLL_XFORM_DQS9 */ + 0x007f400c /* EMC_DLL_XFORM_DQS10 */ + 0x007fc007 /* EMC_DLL_XFORM_DQS11 */ + 0x007f4006 /* EMC_DLL_XFORM_DQS12 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS13 */ + 0x007f8005 /* EMC_DLL_XFORM_DQS14 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x61861820 /* EMC_XM2DQSPADCTRL3 */ + 0x00492492 /* EMC_XM2DQSPADCTRL4 */ + 0x00492492 /* EMC_XM2DQSPADCTRL5 */ + 0x61861800 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x006f000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000007 /* EMC_CTT */ + 0x00000004 /* EMC_CTT_DURATION */ + 0x00004080 /* EMC_CFG_PIPE */ + 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f /* EMC_QPOP */ >; }; }; @@ -6364,286 +4832,1848 @@ timing-12750000 { clock-frequency = <12750000>; - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-20400000 { clock-frequency = <20400000>; - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000005 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x0000009a /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000006 /* EMC_TXSR */ + 0x00000006 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000a0 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x0000000b /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-40800000 { clock-frequency = <40800000>; - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x0000000a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000134 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000c /* EMC_TXSR */ + 0x0000000c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000013f /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000015 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-68000000 { clock-frequency = <68000000>; - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 /* EMC_RC */ + 0x00000011 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000002 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000202 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000013 /* EMC_TXSR */ + 0x00000013 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000213 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000022 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-102000000 { clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000304 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000018 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000033 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-204000000 { clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000004 /* EMC_EINPUT */ + 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000003 /* EMC_QRST */ + 0x0000000d /* EMC_QSAFE */ + 0x0000000f /* EMC_RDV */ + 0x00000011 /* EMC_RDV_MASK */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000032 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00090000 /* EMC_DLL_XFORM_DQ0 */ + 0x00090000 /* EMC_DLL_XFORM_DQ1 */ + 0x00094000 /* EMC_DLL_XFORM_DQ2 */ + 0x00094000 /* EMC_DLL_XFORM_DQ3 */ + 0x00009400 /* EMC_DLL_XFORM_DQ4 */ + 0x00009000 /* EMC_DLL_XFORM_DQ5 */ + 0x00009000 /* EMC_DLL_XFORM_DQ6 */ + 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000066 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000d2b3 /* EMC_CFG_PIPE */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; timing-300000000 { clock-frequency = <300000000>; - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0174000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d /* EMC_RC */ + 0x0000004c /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000009 /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000007 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x0000000e /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x000008e4 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000004a /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000051 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000924 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00060000 /* EMC_DLL_XFORM_DQ0 */ + 0x00060000 /* EMC_DLL_XFORM_DQ1 */ + 0x00060000 /* EMC_DLL_XFORM_DQ2 */ + 0x00060000 /* EMC_DLL_XFORM_DQ3 */ + 0x00006000 /* EMC_DLL_XFORM_DQ4 */ + 0x00006000 /* EMC_DLL_XFORM_DQ5 */ + 0x00006000 /* EMC_DLL_XFORM_DQ6 */ + 0x00006000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0174000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; timing-396000000 { clock-frequency = <396000000>; - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000065 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000001 /* EMC_EINPUT */ + 0x00000008 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000000 /* EMC_QRST */ + 0x0000000f /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x00000bd1 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000063 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006b /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c11 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x00004800 /* EMC_DLL_XFORM_DQ4 */ + 0x00004800 /* EMC_DLL_XFORM_DQ5 */ + 0x00004800 /* EMC_DLL_XFORM_DQ6 */ + 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x015b000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; timing-528000000 { clock-frequency = <528000000>; - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ - 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180e /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x013a000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 /* EMC_RC */ + 0x00000088 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000011 /* EMC_RAS */ + 0x00000006 /* EMC_RP */ + 0x00000006 /* EMC_R2W */ + 0x00000009 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000d /* EMC_W2P */ + 0x00000006 /* EMC_RD_RCD */ + 0x00000006 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000007 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000009 /* EMC_EINPUT_DURATION */ + 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000010 /* EMC_QSAFE */ + 0x00000013 /* EMC_RDV */ + 0x00000015 /* EMC_RDV_MASK */ + 0x00000fd6 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000b /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000084 /* EMC_AR2PDEN */ + 0x00000012 /* EMC_RW2PDEN */ + 0x0000008f /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000013 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001017 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x013a000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000042a0 /* EMC_CFG_PIPE */ + 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b /* EMC_QPOP */ >; }; timing-600000000 { clock-frequency = <600000000>; - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0128000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001c /* EMC_RC */ + 0x0000009a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000013 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000007 /* EMC_R2W */ + 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000010 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x0000000a /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000003 /* EMC_EINPUT */ + 0x0000000b /* EMC_EINPUT_DURATION */ + 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000002 /* EMC_QRST */ + 0x00000012 /* EMC_QSAFE */ + 0x00000016 /* EMC_RDV */ + 0x00000018 /* EMC_RDV_MASK */ + 0x00001208 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000d /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000096 /* EMC_AR2PDEN */ + 0x00000015 /* EMC_RW2PDEN */ + 0x000000a2 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001249 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0128000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000040a0 /* EMC_CFG_PIPE */ + 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e /* EMC_QPOP */ >; }; timing-792000000 { clock-frequency = <792000000>; - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000cc /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000008 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x0000000b /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x0000000d /* EMC_EINPUT_DURATION */ + 0x00080000 /* EMC_PUTERM_EXTRA */ + 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000014 /* EMC_QSAFE */ + 0x00000018 /* EMC_RDV */ + 0x0000001a /* EMC_RDV_MASK */ + 0x000017e2 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000011 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000c6 /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d6 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000006 /* EMC_TCKESR */ + 0x00000005 /* EMC_TPD */ + 0x0000001d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000008 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001822 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab198 /* EMC_FBIO_CFG5 */ + 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000009 /* EMC_DLL_XFORM_DQS0 */ + 0x00000009 /* EMC_DLL_XFORM_DQS1 */ + 0x00000009 /* EMC_DLL_XFORM_DQS2 */ + 0x00000007 /* EMC_DLL_XFORM_DQS3 */ + 0x00000006 /* EMC_DLL_XFORM_DQS4 */ + 0x00000006 /* EMC_DLL_XFORM_DQS5 */ + 0x007fc009 /* EMC_DLL_XFORM_DQS6 */ + 0x00000006 /* EMC_DLL_XFORM_DQS7 */ + 0x00000009 /* EMC_DLL_XFORM_DQS8 */ + 0x00000009 /* EMC_DLL_XFORM_DQS9 */ + 0x00000009 /* EMC_DLL_XFORM_DQS10 */ + 0x00000007 /* EMC_DLL_XFORM_DQS11 */ + 0x00000006 /* EMC_DLL_XFORM_DQS12 */ + 0x00000007 /* EMC_DLL_XFORM_DQS13 */ + 0x00000009 /* EMC_DLL_XFORM_DQS14 */ + 0x00000007 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR0 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR3 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x61861820 /* EMC_XM2DQSPADCTRL3 */ + 0x004d34d3 /* EMC_XM2DQSPADCTRL4 */ + 0x004d34d3 /* EMC_XM2DQSPADCTRL5 */ + 0x61861800 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000007 /* EMC_CTT */ + 0x00000004 /* EMC_CTT_DURATION */ + 0x00004080 /* EMC_CFG_PIPE */ + 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f /* EMC_QPOP */ >; }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index 35c98734d35f..7360a1f35389 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -10,55 +10,65 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-20400000 { clock-frequency = <20400000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-40800000 { clock-frequency = <40800000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-68000000 { clock-frequency = <68000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-102000000 { clock-frequency = <102000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-204000000 { clock-frequency = <204000000>; nvidia,parent-clock-frequency = <408000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "emc-parent"; }; + timing-300000000 { clock-frequency = <300000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C>; clock-names = "emc-parent"; }; + timing-396000000 { clock-frequency = <396000000>; nvidia,parent-clock-frequency = <792000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; + /* TODO: Add 528MHz frequency */ + timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; clock-names = "emc-parent"; }; + timing-792000000 { clock-frequency = <792000000>; nvidia,parent-clock-frequency = <792000000>; @@ -68,110 +78,402 @@ }; }; - external-memory-controller@7001b000 { + memory-controller@70019000 { emc-timings-1 { nvidia,ram-code = <1>; timing-12750000 { clock-frequency = <12750000>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < + nvidia,emem-configuration = < + 0x40040001 + 0x8000000a + 0x00000001 + 0x00000001 + 0x00000002 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a + 0x00000002 0x00000003 - 0x0000000b - 0x00000000 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x77e30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 + 0x80000012 + 0x00000001 + 0x00000001 + 0x00000002 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 0x00000003 + 0x00000002 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 0x00000006 + 0x06030203 + 0x000a0402 + 0x76230303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 + 0x80000017 + 0x00000001 + 0x00000001 0x00000002 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74a30303 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 + 0x8000001e + 0x00000001 + 0x00000001 + 0x00000002 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0402 + 0x74230403 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 + 0x80000026 + 0x00000001 + 0x00000001 + 0x00000003 0x00000000 - 0x00000000 - 0x00000000 + 0x00000002 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000003 + 0x00000002 + 0x00000003 + 0x00000006 + 0x06030203 + 0x000a0403 + 0x73c30504 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 + 0x80000040 + 0x00000001 + 0x00000001 + 0x00000005 + 0x00000002 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000060 - 0x00000000 - 0x00000018 + 0x00000001 0x00000002 + 0x00000008 + 0x00000003 0x00000002 + 0x00000004 + 0x00000006 + 0x06040203 + 0x000a0405 + 0x73840a06 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 + 0x80000040 0x00000001 - 0x00000000 + 0x00000002 0x00000007 - 0x0000000f - 0x00000005 - 0x00000005 0x00000004 0x00000005 + 0x00000001 + 0x00000002 + 0x00000007 + 0x00000002 + 0x00000002 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 + 0x00000006 + 0x06040202 + 0x000b0607 + 0x77450e08 + 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 + 0x80000040 + 0x00000001 + 0x00000002 + 0x00000009 0x00000005 - 0x00000064 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 + 0x00000007 + 0x00000001 + 0x00000002 + 0x00000008 + 0x00000002 + 0x00000002 + 0x00000004 + 0x00000006 + 0x06040202 + 0x000d0709 + 0x7586120a + 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 + 0x80000040 + 0x00000002 + 0x00000003 + 0x0000000d + 0x00000008 + 0x0000000a + 0x00000001 + 0x00000002 + 0x00000009 + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000006 + 0x06050202 + 0x0010090d + 0x7428180e + 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 + 0x80000040 + 0x00000003 + 0x00000004 + 0x0000000e + 0x00000009 + 0x0000000b + 0x00000001 + 0x00000003 + 0x0000000b + 0x00000002 + 0x00000002 + 0x00000005 + 0x00000007 + 0x07050202 + 0x00130b0e + 0x73a91b0f + 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b + 0x80000040 + 0x00000004 + 0x00000005 + 0x00000013 + 0x0000000c + 0x0000000f + 0x00000002 + 0x00000003 + 0x0000000c + 0x00000002 + 0x00000002 + 0x00000006 + 0x00000008 + 0x08060202 + 0x00160d13 + 0x734c2414 + 0x70000f02 + 0x001f0000 + >; + }; + }; + }; + + external-memory-controller@7001b000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000a + 0x00000003 + 0x0000000b + 0x00000000 + 0x00000000 + 0x00000003 + 0x00000003 + 0x00000000 + 0x00000006 + 0x00000006 + 0x00000006 + 0x00000002 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00010000 + 0x00000003 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000004 + 0x0000000c + 0x0000000d + 0x0000000f + 0x00000060 + 0x00000000 + 0x00000018 + 0x00000002 + 0x00000002 + 0x00000001 + 0x00000000 + 0x00000007 + 0x0000000f + 0x00000005 + 0x00000005 + 0x00000004 + 0x00000005 + 0x00000004 + 0x00000000 + 0x00000000 + 0x00000005 + 0x00000005 + 0x00000064 + 0x00000000 + 0x00000000 + 0x00000000 + 0x106aa298 + 0x002c00a0 + 0x00008000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00064000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 @@ -1751,300 +2053,6 @@ 0x0000000f >; }; - - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0403 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000005 - 0x00000002 - 0x00000004 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040203 - 0x000a0405 - 0x73840a06 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000004 - 0x00000005 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 - 0x00000007 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 - 0x80000040 - 0x00000002 - 0x00000003 - 0x0000000d - 0x00000008 - 0x0000000a - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000006 - 0x06050202 - 0x0010090d - 0x7428180e - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000b - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000f - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000008 - 0x08060202 - 0x00160d13 - 0x734c2414 - 0x70000f02 - 0x001f0000 - >; - }; }; }; }; -- cgit v1.2.3 From 0a6a64f904c6fda33f4b7d50abcae3b8302e89f1 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 17:08:42 +0100 Subject: ARM: tegra: Specify correct PMIC compatible on Tegra114 boards The PMIC found on Dalmore, TN7 and Roth is a TPS65913, so add the specific compatible string in addition to the generic Palmas series compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 2 +- arch/arm/boot/dts/tegra114-roth.dts | 2 +- arch/arm/boot/dts/tegra114-tn7.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 7fd901f8d39a..82caefe5928c 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -894,7 +894,7 @@ }; palmas: tps65913@58 { - compatible = "ti,palmas"; + compatible = "ti,tps65913", "ti,palmas"; reg = <0x58>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 07960171fabe..71a2806c0f59 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -801,7 +801,7 @@ }; palmas: pmic@58 { - compatible = "ti,palmas"; + compatible = "ti,tps65913", "ti,palmas"; reg = <0x58>; interrupts = ; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 745d234b105b..753130b1e37b 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -62,7 +62,7 @@ clock-frequency = <400000>; palmas: pmic@58 { - compatible = "ti,palmas"; + compatible = "ti,tps65913", "ti,palmas"; reg = <0x58>; interrupts = ; -- cgit v1.2.3 From 0b9f3940d6305dd0fc059f7ffaa8334d2e2dd8b6 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 17:19:28 +0100 Subject: ARM: tegra: Rename SPI flash chip nodes SPI flash chip nodes should be named "flash" instead of "spi-flash". Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 3 ++- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 3 ++- arch/arm/boot/dts/tegra124-venice2.dts | 3 ++- arch/arm/boot/dts/tegra20-trimslice.dts | 3 ++- arch/arm/boot/dts/tegra30-beaver.dts | 3 ++- arch/arm/boot/dts/tegra30-cardhu.dtsi | 3 ++- 6 files changed, 12 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 82caefe5928c..e64199ba82cb 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1084,7 +1084,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@0 { + + flash@0 { compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 35ab296408e1..b2b3eea81232 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1655,7 +1655,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@0 { + + flash@0 { compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index e6b54ac1ebd1..02cf986c7567 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -881,7 +881,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@0 { + + flash@0 { compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 4bc87bc0c2a4..beae368f827a 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -287,7 +287,8 @@ spi@7000c380 { status = "okay"; spi-max-frequency = <48000000>; - spi-flash@0 { + + flash@0 { compatible = "winbond,w25q80bl", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <48000000>; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index e159feeedef7..f724abcdb1a5 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1898,7 +1898,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@1 { + + flash@1 { compatible = "winbond,w25q32", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 448f1397e64a..e7bfe0e5ee06 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -374,7 +374,8 @@ spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; - spi-flash@1 { + + flash@1 { compatible = "winbond,w25q32", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <20000000>; -- cgit v1.2.3 From 4f74ed817ef8d8aa2ef5049537f329fde2f9fca7 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 12 Dec 2021 00:14:03 +0300 Subject: ARM: tegra: Rename top-level clocks Clocks defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the clock to the node name. [treding@nvidia.com: factored out patch and wrote commit message] Signed-off-by: David Heidelberg Co-developed-by: Thierry Reding Signed-off-by: Thierry Reding Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 2 +- arch/arm/boot/dts/tegra114-roth.dts | 2 +- arch/arm/boot/dts/tegra114-tn7.dts | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +- arch/arm/boot/dts/tegra124-venice2.dts | 2 +- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++-- arch/arm/boot/dts/tegra20-harmony.dts | 2 +- arch/arm/boot/dts/tegra20-paz00.dts | 2 +- arch/arm/boot/dts/tegra20-seaboard.dts | 2 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +- arch/arm/boot/dts/tegra20-trimslice.dts | 2 +- arch/arm/boot/dts/tegra20-ventana.dts | 2 +- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 2 +- arch/arm/boot/dts/tegra30-beaver.dts | 2 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- 16 files changed, 17 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index e64199ba82cb..ad8116780dc9 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1152,7 +1152,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 71a2806c0f59..ed6ebbf008e1 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1016,7 +1016,7 @@ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 753130b1e37b..36717331101e 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -273,7 +273,7 @@ power-supply = <&lcd_bl_en>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index b2b3eea81232..f59135b93cb0 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1869,7 +1869,7 @@ vbus-supply = <&vdd_usb3_vbus>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 63a81270300a..f15623f83893 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -582,7 +582,7 @@ 256>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 02cf986c7567..14eeb1242b15 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1062,7 +1062,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 23d3f8daab23..1aaee6f09fd8 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -827,7 +827,7 @@ }; /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock@0 { + clk32k_in: clock-32k-in { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -839,7 +839,7 @@ * oscillator is used as a reference clock-source by the * Azurewave WiFi/BT module. */ - rtc_32k_wifi: clock@1 { + rtc_32k_wifi: clock-32k-wifi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index ae4312eedcbd..4d137461f3c4 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -640,7 +640,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 5b38b0606f99..d3d24523553e 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -575,7 +575,7 @@ default-brightness-level = <10>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 92d494b8c3d2..ffeae5da22e7 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -792,7 +792,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index dd4d506683de..d5f1a46da0bc 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -502,7 +502,7 @@ status = "okay"; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index beae368f827a..49c3b3bfac51 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -380,7 +380,7 @@ bus-width = <4>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 5a2578b3707f..ef97457f1334 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -606,7 +606,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 07d4ea130964..72159eb55a3d 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1069,7 +1069,7 @@ }; /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index f724abcdb1a5..91ecca0be5a2 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1967,7 +1967,7 @@ status = "okay"; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index e7bfe0e5ee06..6074885280fc 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -434,7 +434,7 @@ default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; -- cgit v1.2.3 From c629196d04c8cdb0624a0763cec78fa18ba8ab1f Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:04 +0300 Subject: ARM: tegra: Rename top-level regulators Regulators defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the regulator to the node name. [treding@nvidia.com: factored out patch and wrote commit message] Signed-off-by: David Heidelberg Co-developed-by: Thierry Reding Signed-off-by: Thierry Reding Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 14 ++++++------ arch/arm/boot/dts/tegra114-roth.dts | 12 +++++----- arch/arm/boot/dts/tegra114-tn7.dts | 6 ++--- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 24 ++++++++++---------- arch/arm/boot/dts/tegra124-nyan.dtsi | 26 +++++++++++----------- arch/arm/boot/dts/tegra124-venice2.dts | 26 +++++++++++----------- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 8 +++---- arch/arm/boot/dts/tegra20-harmony.dts | 14 ++++++------ arch/arm/boot/dts/tegra20-medcom-wide.dts | 8 +++---- arch/arm/boot/dts/tegra20-paz00.dts | 4 ++-- arch/arm/boot/dts/tegra20-plutux.dts | 8 +++---- arch/arm/boot/dts/tegra20-seaboard.dts | 14 ++++++------ arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +- arch/arm/boot/dts/tegra20-tec.dts | 8 +++---- arch/arm/boot/dts/tegra20-trimslice.dts | 10 ++++----- arch/arm/boot/dts/tegra20-ventana.dts | 10 ++++----- .../dts/tegra30-asus-nexus7-grouper-common.dtsi | 8 +++---- .../tegra30-asus-nexus7-grouper-maxim-pmic.dtsi | 4 ++-- .../dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi | 2 +- arch/arm/boot/dts/tegra30-beaver.dts | 18 +++++++-------- arch/arm/boot/dts/tegra30-cardhu-a02.dts | 12 +++++----- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 14 ++++++------ arch/arm/boot/dts/tegra30-cardhu.dtsi | 26 +++++++++++----------- 23 files changed, 139 insertions(+), 139 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index ad8116780dc9..658edfb8d7fa 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1187,7 +1187,7 @@ }; }; - vdd_ac_bat_reg: regulator@0 { + vdd_ac_bat_reg: regulator-acbat { compatible = "regulator-fixed"; regulator-name = "vdd_ac_bat"; regulator-min-microvolt = <5000000>; @@ -1195,7 +1195,7 @@ regulator-always-on; }; - dvdd_ts_reg: regulator@1 { + dvdd_ts_reg: regulator-ts { compatible = "regulator-fixed"; regulator-name = "dvdd_ts"; regulator-min-microvolt = <1800000>; @@ -1204,7 +1204,7 @@ gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; }; - usb1_vbus_reg: regulator@3 { + usb1_vbus_reg: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -1215,7 +1215,7 @@ vin-supply = <&tps65090_dcdc1_reg>; }; - usb3_vbus_reg: regulator@4 { + usb3_vbus_reg: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "usb2_vbus"; regulator-min-microvolt = <5000000>; @@ -1226,7 +1226,7 @@ vin-supply = <&tps65090_dcdc1_reg>; }; - vdd_hdmi_reg: regulator@5 { + vdd_hdmi_reg: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "vdd_hdmi_5v0"; regulator-min-microvolt = <5000000>; @@ -1234,7 +1234,7 @@ vin-supply = <&tps65090_dcdc1_reg>; }; - vdd_cam_1v8_reg: regulator@6 { + vdd_cam_1v8_reg: regulator-cam { compatible = "regulator-fixed"; regulator-name = "vdd_cam_1v8_reg"; regulator-min-microvolt = <1800000>; @@ -1243,7 +1243,7 @@ gpio = <&palmas_gpio 6 0>; }; - vdd_5v0_hdmi: regulator@7 { + vdd_5v0_hdmi: regulator-hdmicon { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index ed6ebbf008e1..2498cf18fd39 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1045,7 +1045,7 @@ }; }; - lcd_bl_en: regulator@0 { + lcd_bl_en: regulator-lcden { compatible = "regulator-fixed"; regulator-name = "lcd_bl_en"; regulator-min-microvolt = <5000000>; @@ -1053,7 +1053,7 @@ regulator-boot-on; }; - vdd_lcd: regulator@1 { + vdd_lcd: regulator-lcd { compatible = "regulator-fixed"; regulator-name = "vdd_lcd_1v8"; regulator-min-microvolt = <1800000>; @@ -1064,7 +1064,7 @@ regulator-boot-on; }; - regulator@2 { + regulator-1v8ts { compatible = "regulator-fixed"; regulator-name = "vdd_1v8_ts"; regulator-min-microvolt = <1800000>; @@ -1073,7 +1073,7 @@ regulator-boot-on; }; - regulator@3 { + regulator-3v3ts { compatible = "regulator-fixed"; regulator-name = "vdd_3v3_ts"; regulator-min-microvolt = <3300000>; @@ -1083,7 +1083,7 @@ regulator-boot-on; }; - regulator@4 { + regulator-1v8com { compatible = "regulator-fixed"; regulator-name = "vdd_1v8_com"; regulator-min-microvolt = <1800000>; @@ -1094,7 +1094,7 @@ regulator-boot-on; }; - regulator@5 { + regulator-3v3com { compatible = "regulator-fixed"; regulator-name = "vdd_3v3_com"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 36717331101e..ef8f722dd9cb 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -303,7 +303,7 @@ }; /* FIXME: output of BQ24192 */ - vs_sys: regulator@0 { + vs_sys: regulator-vs { compatible = "regulator-fixed"; regulator-name = "VS_SYS"; regulator-min-microvolt = <4200000>; @@ -312,7 +312,7 @@ regulator-boot-on; }; - lcd_bl_en: regulator@1 { + lcd_bl_en: regulator-lcden { compatible = "regulator-fixed"; regulator-name = "VDD_LCD_BL"; regulator-min-microvolt = <16500000>; @@ -323,7 +323,7 @@ regulator-boot-on; }; - vdd_lcd: regulator@2 { + vdd_lcd: regulator-lcd { compatible = "regulator-fixed"; regulator-name = "VD_LCD_1V8"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index f59135b93cb0..c3edb332187a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1893,7 +1893,7 @@ }; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <12000000>; @@ -1902,7 +1902,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-5v0sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -1912,7 +1912,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-3v3sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -1922,7 +1922,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-3v3run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -1934,7 +1934,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-3v3hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -1942,7 +1942,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_usb1_vbus: regulator@5 { + vdd_usb1_vbus: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "+USB0_VBUS_SW"; regulator-min-microvolt = <5000000>; @@ -1953,7 +1953,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@6 { + vdd_usb3_vbus: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -1964,7 +1964,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_lp0: regulator@7 { + vdd_3v3_lp0: regulator-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; @@ -1976,7 +1976,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@8 { + vdd_hdmi_pll: regulator-hdmipll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; regulator-min-microvolt = <1050000>; @@ -1985,7 +1985,7 @@ vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@9 { + vdd_5v0_hdmi: regulator-hdmicon { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; @@ -1996,7 +1996,7 @@ }; /* Molex power connector */ - vdd_5v0_sata: regulator@10 { + vdd_5v0_sata: regulator-5v0sata { compatible = "regulator-fixed"; regulator-name = "+5V_SATA"; regulator-min-microvolt = <5000000>; @@ -2006,7 +2006,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_12v0_sata: regulator@11 { + vdd_12v0_sata: regulator-12v0sata { compatible = "regulator-fixed"; regulator-name = "+12V_SATA"; regulator-min-microvolt = <12000000>; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index f15623f83893..2d045d1a9bcf 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -615,7 +615,7 @@ }; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <12000000>; @@ -624,7 +624,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-5v0sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -634,7 +634,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-3v3sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -644,7 +644,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-3v3run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -656,7 +656,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-3v3hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -664,7 +664,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_led: regulator@5 { + vdd_led: regulator-led { compatible = "regulator-fixed"; regulator-name = "+VDD_LED"; gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; @@ -672,7 +672,7 @@ vin-supply = <&vdd_mux>; }; - vdd_5v0_ts: regulator@6 { + vdd_5v0_ts: regulator-ts { compatible = "regulator-fixed"; regulator-name = "+5V_VDD_TS_SW"; regulator-min-microvolt = <5000000>; @@ -683,7 +683,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb1_vbus: regulator@7 { + vdd_usb1_vbus: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -694,7 +694,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@8 { + vdd_usb3_vbus: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_SS"; regulator-min-microvolt = <5000000>; @@ -705,7 +705,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_panel: regulator@9 { + vdd_3v3_panel: regulator-panel { compatible = "regulator-fixed"; regulator-name = "+3.3V_PANEL"; regulator-min-microvolt = <3300000>; @@ -715,7 +715,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_3v3_lp0: regulator@10 { + vdd_3v3_lp0: regulator-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; @@ -730,7 +730,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@11 { + vdd_hdmi_pll: regulator-hdmipll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; regulator-min-microvolt = <1050000>; @@ -739,7 +739,7 @@ vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@12 { + vdd_5v0_hdmi: regulator-hdmicon { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 14eeb1242b15..5f17a2f7d270 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1087,7 +1087,7 @@ ddc-i2c-bus = <&dpaux>; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <12000000>; @@ -1096,7 +1096,7 @@ regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-5v0sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -1106,7 +1106,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-3v3sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -1116,7 +1116,7 @@ vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-3v3run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -1128,7 +1128,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -1136,7 +1136,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_led: regulator@5 { + vdd_led: regulator-led { compatible = "regulator-fixed"; regulator-name = "+VDD_LED"; regulator-min-microvolt = <3300000>; @@ -1146,7 +1146,7 @@ vin-supply = <&vdd_mux>; }; - vdd_5v0_ts: regulator@6 { + vdd_5v0_ts: regulator-ts { compatible = "regulator-fixed"; regulator-name = "+5V_VDD_TS_SW"; regulator-min-microvolt = <5000000>; @@ -1157,7 +1157,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb1_vbus: regulator@7 { + vdd_usb1_vbus: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -1168,7 +1168,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@8 { + vdd_usb3_vbus: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "+5V_USB_SS"; regulator-min-microvolt = <5000000>; @@ -1179,7 +1179,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_panel: regulator@9 { + vdd_3v3_panel: regulator-panel { compatible = "regulator-fixed"; regulator-name = "+3.3V_PANEL"; regulator-min-microvolt = <3300000>; @@ -1189,7 +1189,7 @@ vin-supply = <&vdd_3v3_run>; }; - vdd_3v3_lp0: regulator@10 { + vdd_3v3_lp0: regulator-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; @@ -1204,7 +1204,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@11 { + vdd_hdmi_pll: regulator-hdmipll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; regulator-min-microvolt = <1050000>; @@ -1213,7 +1213,7 @@ vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@12 { + vdd_5v0_hdmi: regulator-hdmicon { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 1aaee6f09fd8..2e6340e92fe1 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -964,7 +964,7 @@ }; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -972,7 +972,7 @@ regulator-always-on; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3_vs"; regulator-min-microvolt = <3300000>; @@ -981,7 +981,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_1v8_sys: regulator@2 { + vdd_1v8_sys: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd_1v8_vs"; regulator-min-microvolt = <1800000>; @@ -990,7 +990,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_pnl: regulator@3 { + vdd_pnl: regulator-panel { compatible = "regulator-fixed"; regulator-name = "vdd_panel"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 4d137461f3c4..a8494378c382 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -666,7 +666,7 @@ backlight = <&backlight>; }; - vdd_5v0_reg: regulator@0 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -674,7 +674,7 @@ regulator-always-on; }; - regulator@1 { + regulator-1v5 { compatible = "regulator-fixed"; regulator-name = "vdd_1v5"; regulator-min-microvolt = <1500000>; @@ -682,7 +682,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - regulator@2 { + regulator-1v2 { compatible = "regulator-fixed"; regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; @@ -691,7 +691,7 @@ enable-active-high; }; - pci_vdd_reg: regulator@3 { + pci_vdd_reg: regulator-1v05 { compatible = "regulator-fixed"; regulator-name = "vdd_1v05"; regulator-min-microvolt = <1050000>; @@ -700,7 +700,7 @@ enable-active-high; }; - vdd_pnl_reg: regulator@4 { + vdd_pnl_reg: regulator-pn1 { compatible = "regulator-fixed"; regulator-name = "vdd_pnl"; regulator-min-microvolt = <2800000>; @@ -709,7 +709,7 @@ enable-active-high; }; - vdd_bl_reg: regulator@5 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <2800000>; @@ -718,7 +718,7 @@ enable-active-high; }; - vdd_5v0_hdmi: regulator@6 { + vdd_5v0_hdmi: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "VDDIO_HDMI"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index b31c9bca16e6..cb6199d7d224 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -92,7 +92,7 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - vcc_24v_reg: regulator@100 { + vcc_24v_reg: regulator-24v0 { compatible = "regulator-fixed"; regulator-name = "vcc_24v"; regulator-min-microvolt = <24000000>; @@ -100,7 +100,7 @@ regulator-always-on; }; - vdd_5v0_reg: regulator@101 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; vin-supply = <&vcc_24v_reg>; @@ -109,7 +109,7 @@ regulator-always-on; }; - vdd_3v3_reg: regulator@102 { + vdd_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; vin-supply = <&vcc_24v_reg>; @@ -118,7 +118,7 @@ regulator-always-on; }; - vdd_1v8_reg: regulator@103 { + vdd_1v8_reg: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd_1v8"; vin-supply = <&vdd_3v3_reg>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index d3d24523553e..46d81d703548 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -612,7 +612,7 @@ backlight = <&backlight>; }; - p5valw_reg: regulator@0 { + p5valw_reg: regulator-5v0alw { compatible = "regulator-fixed"; regulator-name = "+5valw"; regulator-min-microvolt = <5000000>; @@ -620,7 +620,7 @@ regulator-always-on; }; - vdd_pnl_reg: regulator@1 { + vdd_pnl_reg: regulator-3v0 { compatible = "regulator-fixed"; regulator-name = "+3VS,vdd_pnl"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index 5811b7006a9b..71a8236491df 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -60,7 +60,7 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - vcc_24v_reg: regulator@100 { + vcc_24v_reg: regulator-24v0 { compatible = "regulator-fixed"; regulator-name = "vcc_24v"; regulator-min-microvolt = <24000000>; @@ -68,7 +68,7 @@ regulator-always-on; }; - vdd_5v0_reg: regulator@101 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; vin-supply = <&vcc_24v_reg>; @@ -77,7 +77,7 @@ regulator-always-on; }; - vdd_3v3_reg: regulator@102 { + vdd_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; vin-supply = <&vcc_24v_reg>; @@ -86,7 +86,7 @@ regulator-always-on; }; - vdd_1v8_reg: regulator@103 { + vdd_1v8_reg: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd_1v8"; vin-supply = <&vdd_3v3_reg>; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index ffeae5da22e7..ca7adeb1fdd9 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -828,7 +828,7 @@ ddc-i2c-bus = <&lvds_ddc>; }; - vdd_5v0_reg: regulator@0 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -836,7 +836,7 @@ regulator-always-on; }; - regulator@1 { + regulator-1v5 { compatible = "regulator-fixed"; regulator-name = "vdd_1v5"; regulator-min-microvolt = <1500000>; @@ -844,7 +844,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - regulator@2 { + regulator-1v2 { compatible = "regulator-fixed"; regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; @@ -853,7 +853,7 @@ enable-active-high; }; - vbus_reg: regulator@3 { + vbus_reg: regulator-vbus { compatible = "regulator-fixed"; regulator-name = "vdd_vbus_wup1"; regulator-min-microvolt = <5000000>; @@ -864,7 +864,7 @@ regulator-boot-on; }; - vdd_pnl_reg: regulator@4 { + vdd_pnl_reg: regulator-pnl { compatible = "regulator-fixed"; regulator-name = "vdd_pnl"; regulator-min-microvolt = <2800000>; @@ -873,7 +873,7 @@ enable-active-high; }; - vdd_bl_reg: regulator@5 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <2800000>; @@ -882,7 +882,7 @@ enable-active-high; }; - vdd_hdmi: regulator@6 { + vdd_hdmi: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "VDDIO_HDMI"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index d5f1a46da0bc..2ad56f84bb62 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -508,7 +508,7 @@ #clock-cells = <0>; }; - pci_vdd_reg: regulator@1 { + pci_vdd_reg: regulator-1v05 { compatible = "regulator-fixed"; regulator-name = "vdd_1v05"; regulator-min-microvolt = <1050000>; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 10ff09d86efa..4f41c74384b2 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -69,7 +69,7 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - vcc_24v_reg: regulator@100 { + vcc_24v_reg: regulator-24v { compatible = "regulator-fixed"; regulator-name = "vcc_24v"; regulator-min-microvolt = <24000000>; @@ -77,7 +77,7 @@ regulator-always-on; }; - vdd_5v0_reg: regulator@101 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; vin-supply = <&vcc_24v_reg>; @@ -86,7 +86,7 @@ regulator-always-on; }; - vdd_3v3_reg: regulator@102 { + vdd_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; vin-supply = <&vcc_24v_reg>; @@ -95,7 +95,7 @@ regulator-always-on; }; - vdd_1v8_reg: regulator@103 { + vdd_1v8_reg: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd_1v8"; vin-supply = <&vdd_3v3_reg>; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 49c3b3bfac51..dd05e2c87c29 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -402,7 +402,7 @@ gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; - hdmi_vdd_reg: regulator@0 { + hdmi_vdd_reg: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "avdd_hdmi"; regulator-min-microvolt = <3300000>; @@ -410,7 +410,7 @@ regulator-always-on; }; - hdmi_pll_reg: regulator@1 { + hdmi_pll_reg: regulator-hdmipll { compatible = "regulator-fixed"; regulator-name = "avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; @@ -418,7 +418,7 @@ regulator-always-on; }; - vbus_reg: regulator@2 { + vbus_reg: regulator-vbus { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -429,7 +429,7 @@ regulator-boot-on; }; - pci_clk_reg: regulator@3 { + pci_clk_reg: regulator-pciclk { compatible = "regulator-fixed"; regulator-name = "pci_clk"; regulator-min-microvolt = <3300000>; @@ -437,7 +437,7 @@ regulator-always-on; }; - pci_vdd_reg: regulator@4 { + pci_vdd_reg: regulator-pcivdd { compatible = "regulator-fixed"; regulator-name = "pci_vdd"; regulator-min-microvolt = <1050000>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index ef97457f1334..4284054ebd2c 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -647,7 +647,7 @@ ddc-i2c-bus = <&lvds_ddc>; }; - vdd_5v0_reg: regulator@0 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -655,7 +655,7 @@ regulator-always-on; }; - regulator@1 { + regulator-1v5 { compatible = "regulator-fixed"; regulator-name = "vdd_1v5"; regulator-min-microvolt = <1500000>; @@ -663,7 +663,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - regulator@2 { + regulator-1v2 { compatible = "regulator-fixed"; regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; @@ -672,7 +672,7 @@ enable-active-high; }; - vdd_pnl_reg: regulator@3 { + vdd_pnl_reg: regulator-pnl { compatible = "regulator-fixed"; regulator-name = "vdd_pnl"; regulator-min-microvolt = <2800000>; @@ -681,7 +681,7 @@ enable-active-high; }; - vdd_bl_reg: regulator@4 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <2800000>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 72159eb55a3d..e6aed19a5f3b 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1207,7 +1207,7 @@ }; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -1216,7 +1216,7 @@ regulator-boot-on; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; regulator-min-microvolt = <3300000>; @@ -1226,7 +1226,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_pnl: regulator@2 { + vdd_pnl: regulator-panel { compatible = "regulator-fixed"; regulator-name = "vdd_panel"; regulator-min-microvolt = <3300000>; @@ -1237,7 +1237,7 @@ vin-supply = <&vdd_3v3_sys>; }; - vcc_3v3_ts: regulator@3 { + vcc_3v3_ts: regulator-ts { compatible = "regulator-fixed"; regulator-name = "ldo_s-1167_3v3"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi index 53966fa4eef2..cd28e8782f7d 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -166,12 +166,12 @@ }; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-3v3 { gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; enable-active-high; }; - regulator@4 { + regulator-usb { compatible = "regulator-fixed"; regulator-name = "avdd_usb"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi index 9365ae607239..ee4a3f482769 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi @@ -143,7 +143,7 @@ }; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-3v3 { gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; enable-active-high; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 91ecca0be5a2..7c2b70b13cc4 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1986,7 +1986,7 @@ }; }; - vdd_5v_in_reg: regulator@0 { + vdd_5v_in_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v_in"; regulator-min-microvolt = <5000000>; @@ -1994,7 +1994,7 @@ regulator-always-on; }; - chargepump_5v_reg: regulator@1 { + chargepump_5v_reg: regulator-chargepump { compatible = "regulator-fixed"; regulator-name = "chargepump_5v"; regulator-min-microvolt = <5000000>; @@ -2005,7 +2005,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - ddr_reg: regulator@2 { + ddr_reg: regulator-ddr { compatible = "regulator-fixed"; regulator-name = "vdd_ddr"; regulator-min-microvolt = <1500000>; @@ -2017,7 +2017,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - vdd_5v_sata_reg: regulator@3 { + vdd_5v_sata_reg: regulator-sata { compatible = "regulator-fixed"; regulator-name = "vdd_5v_sata"; regulator-min-microvolt = <5000000>; @@ -2029,7 +2029,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - usb1_vbus_reg: regulator@4 { + usb1_vbus_reg: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -2040,7 +2040,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - usb3_vbus_reg: regulator@5 { + usb3_vbus_reg: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "usb3_vbus"; regulator-min-microvolt = <5000000>; @@ -2051,7 +2051,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - sys_3v3_reg: regulator@6 { + sys_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "sys_3v3,vdd_3v3_alw"; regulator-min-microvolt = <3300000>; @@ -2063,7 +2063,7 @@ vin-supply = <&vdd_5v_in_reg>; }; - sys_3v3_pexs_reg: regulator@7 { + sys_3v3_pexs_reg: regulator-pexs { compatible = "regulator-fixed"; regulator-name = "sys_3v3_pexs"; regulator-min-microvolt = <3300000>; @@ -2075,7 +2075,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_5v0_hdmi: regulator@8 { + vdd_5v0_hdmi: regulator-hdmi { compatible = "regulator-fixed"; regulator-name = "+VDD_5V_HDMI"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts index 4899e05a0d9c..247185314f46 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -16,7 +16,7 @@ keep-power-in-suspend; }; - ddr_reg: regulator@100 { + ddr_reg: regulator-ddr { compatible = "regulator-fixed"; regulator-name = "vdd_ddr"; regulator-min-microvolt = <1500000>; @@ -27,7 +27,7 @@ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; }; - sys_3v3_reg: regulator@101 { + sys_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "sys_3v3"; regulator-min-microvolt = <3300000>; @@ -38,7 +38,7 @@ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; }; - usb1_vbus_reg: regulator@102 { + usb1_vbus_reg: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -49,7 +49,7 @@ vin-supply = <&vdd_5v0_reg>; }; - usb3_vbus_reg: regulator@103 { + usb3_vbus_reg: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "usb3_vbus"; regulator-min-microvolt = <5000000>; @@ -60,7 +60,7 @@ vin-supply = <&vdd_5v0_reg>; }; - vdd_5v0_reg: regulator@104 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "5v0"; regulator-min-microvolt = <5000000>; @@ -69,7 +69,7 @@ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; }; - vdd_bl_reg: regulator@105 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index a11028b8b67b..2911f08863a0 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -16,7 +16,7 @@ keep-power-in-suspend; }; - ddr_reg: regulator@100 { + ddr_reg: regulator-ddr { compatible = "regulator-fixed"; regulator-name = "ddr"; regulator-min-microvolt = <1500000>; @@ -27,7 +27,7 @@ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; }; - sys_3v3_reg: regulator@101 { + sys_3v3_reg: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "sys_3v3"; regulator-min-microvolt = <3300000>; @@ -38,7 +38,7 @@ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; }; - usb1_vbus_reg: regulator@102 { + usb1_vbus_reg: regulator-usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -49,7 +49,7 @@ vin-supply = <&vdd_5v0_reg>; }; - usb3_vbus_reg: regulator@103 { + usb3_vbus_reg: regulator-usb3 { compatible = "regulator-fixed"; regulator-name = "usb3_vbus"; regulator-min-microvolt = <5000000>; @@ -60,7 +60,7 @@ vin-supply = <&vdd_5v0_reg>; }; - vdd_5v0_reg: regulator@104 { + vdd_5v0_reg: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "5v0"; regulator-min-microvolt = <5000000>; @@ -69,7 +69,7 @@ gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; }; - vdd_bl_reg: regulator@105 { + vdd_bl_reg: regulator-bl { compatible = "regulator-fixed"; regulator-name = "vdd_bl"; regulator-min-microvolt = <5000000>; @@ -80,7 +80,7 @@ gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; }; - vdd_bl2_reg: regulator@106 { + vdd_bl2_reg: regulator-bl2 { compatible = "regulator-fixed"; regulator-name = "vdd_bl2"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 6074885280fc..886d4bb2d82c 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -476,7 +476,7 @@ backlight = <&backlight>; }; - vdd_ac_bat_reg: regulator@0 { + vdd_ac_bat_reg: regulator-acbat { compatible = "regulator-fixed"; regulator-name = "vdd_ac_bat"; regulator-min-microvolt = <5000000>; @@ -484,7 +484,7 @@ regulator-always-on; }; - cam_1v8_reg: regulator@1 { + cam_1v8_reg: regulator-cam { compatible = "regulator-fixed"; regulator-name = "cam_1v8"; regulator-min-microvolt = <1800000>; @@ -494,7 +494,7 @@ vin-supply = <&vio_reg>; }; - cp_5v_reg: regulator@2 { + cp_5v_reg: regulator-5v0cp { compatible = "regulator-fixed"; regulator-name = "cp_5v"; regulator-min-microvolt = <5000000>; @@ -505,7 +505,7 @@ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - emmc_3v3_reg: regulator@3 { + emmc_3v3_reg: regulator-emmc { compatible = "regulator-fixed"; regulator-name = "emmc_3v3"; regulator-min-microvolt = <3300000>; @@ -517,7 +517,7 @@ vin-supply = <&sys_3v3_reg>; }; - modem_3v3_reg: regulator@4 { + modem_3v3_reg: regulator-modem { compatible = "regulator-fixed"; regulator-name = "modem_3v3"; regulator-min-microvolt = <3300000>; @@ -526,7 +526,7 @@ gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; }; - pex_hvdd_3v3_reg: regulator@5 { + pex_hvdd_3v3_reg: regulator-pex { compatible = "regulator-fixed"; regulator-name = "pex_hvdd_3v3"; regulator-min-microvolt = <3300000>; @@ -536,7 +536,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_cam1_ldo_reg: regulator@6 { + vdd_cam1_ldo_reg: regulator-cam1 { compatible = "regulator-fixed"; regulator-name = "vdd_cam1_ldo"; regulator-min-microvolt = <2800000>; @@ -546,7 +546,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_cam2_ldo_reg: regulator@7 { + vdd_cam2_ldo_reg: regulator-cam2 { compatible = "regulator-fixed"; regulator-name = "vdd_cam2_ldo"; regulator-min-microvolt = <2800000>; @@ -556,7 +556,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_cam3_ldo_reg: regulator@8 { + vdd_cam3_ldo_reg: regulator-cam3 { compatible = "regulator-fixed"; regulator-name = "vdd_cam3_ldo"; regulator-min-microvolt = <3300000>; @@ -566,7 +566,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_com_reg: regulator@9 { + vdd_com_reg: regulator-com { compatible = "regulator-fixed"; regulator-name = "vdd_com"; regulator-min-microvolt = <3300000>; @@ -578,7 +578,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_fuse_3v3_reg: regulator@10 { + vdd_fuse_3v3_reg: regulator-fuse { compatible = "regulator-fixed"; regulator-name = "vdd_fuse_3v3"; regulator-min-microvolt = <3300000>; @@ -588,7 +588,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_pnl1_reg: regulator@11 { + vdd_pnl1_reg: regulator-pnl1 { compatible = "regulator-fixed"; regulator-name = "vdd_pnl1"; regulator-min-microvolt = <3300000>; @@ -600,7 +600,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_vid_reg: regulator@12 { + vdd_vid_reg: regulator-vid { compatible = "regulator-fixed"; regulator-name = "vddio_vid"; regulator-min-microvolt = <5000000>; -- cgit v1.2.3 From f8d5db7e27b389825b7c61255f14f81d6104061b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 10:55:06 +0100 Subject: ARM: tegra: Fix compatible string for Tegra114+ timer The TKE (time-keeping engine) found on Tegra114 and later is no longer backwards compatible with the version found on Tegra20, so update the compatible string list accordingly. Note that while the hardware block is strictly backwards-compatible, an architectural timer exists on those newer SoCs that is more reliable, so that should always be preferred. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 2 +- arch/arm/boot/dts/tegra124.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 546272e396b4..328425dba023 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -164,7 +164,7 @@ }; timer@60005000 { - compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; reg = <0x60005000 0x400>; interrupts = , , diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 63a64171b422..f4ac0c327c2e 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -259,7 +259,7 @@ }; timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; reg = <0x0 0x60005000 0x0 0x400>; interrupts = , , -- cgit v1.2.3 From 82d03bec4e97f01d982b1663d438c55b100de7e3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 10:56:21 +0100 Subject: ARM: tegra: Add #reset-cells for Tegra114 MC The Tegra memory controller provides reset controls for hotflush reset, so the #reset-cells property must be specified. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 328425dba023..ce7410ee08b8 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -542,6 +542,7 @@ interrupts = ; + #reset-cells = <1>; #iommu-cells = <1>; }; -- cgit v1.2.3 From 63658cbc66a27b5fcb683623d299e59cc2771964 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 10:59:24 +0100 Subject: ARM: tegra: Rename GPIO hog nodes to match schema GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to the DT schema. Rename all such nodes to allow validation to pass. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 4 ++-- arch/arm/boot/dts/tegra124-apalis.dtsi | 4 ++-- arch/arm/boot/dts/tegra20-colibri.dtsi | 6 +++--- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 2 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 +- 8 files changed, 12 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index 28c29b6813a7..3209554ec7e6 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -246,7 +246,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + pex-perst-n-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index f3afde410615..814257c79bf1 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -248,7 +248,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + pex-perst-n-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index cde9ae8fa04b..4ba4d5229fcf 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -2055,7 +2055,7 @@ &gpio { /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n { + lan-reset-n-hog { gpio-hog; gpios = ; output-high; @@ -2063,7 +2063,7 @@ }; /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl { + reset-moci-ctrl-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index a46d9ba9bb7a..3760744cc1b0 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -2047,7 +2047,7 @@ &gpio { /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n { + lan-reset-n-hog { gpio-hog; gpios = ; output-high; @@ -2055,7 +2055,7 @@ }; /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl { + reset-moci-ctrl-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 585a5b441cf6..80e439003a6d 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -747,7 +747,7 @@ }; &gpio { - lan-reset-n { + lan-reset-n-hog { gpio-hog; gpios = ; output-high; @@ -755,7 +755,7 @@ }; /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ - npwe { + npwe-hog { gpio-hog; gpios = ; output-high; @@ -763,7 +763,7 @@ }; /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ - rdnwr { + rdnwr-hog { gpio-hog; gpios = ; output-low; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 9f653ef41da4..93b83b3c5655 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -239,7 +239,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + pex-perst-n-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index 86e138e8c7f0..fbfa75e53f32 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -257,7 +257,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + pex-perst-n-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 413e35215804..fcd3d26bef2d 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -1044,7 +1044,7 @@ }; &gpio { - lan-reset-n { + lan-reset-n-hog { gpio-hog; gpios = ; output-high; -- cgit v1.2.3 From 1b5bad01abdcefd1bbf58590d5a78e15741f6a34 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:03:12 +0100 Subject: ARM: tegra: Rename GPU node on Tegra124 In order to be able to pass DT schema validation, change the GPU nodes' unit-address to the standard notation. Previously this was using a "0," prefix that originated from a time when the top-level device tree node contained #address-cells = <2>. Note that this technically breaks backwards-compatibility with certain older versions of the U-Boot bootloader because early versions used a hard-coded DT path lookup to find the GPU node and perform some fixups on it. However, this was changed to a compatible string based lookup in April 2016, so it's reasonable to expect people to update U-Boot on the systems that they want to use this updated kernel DTB with. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +- arch/arm/boot/dts/tegra124-venice2.dts | 2 +- arch/arm/boot/dts/tegra124.dtsi | 7 +------ 6 files changed, 6 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 4ba4d5229fcf..f00ef4d08fd4 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -57,7 +57,7 @@ }; }; - gpu@0,57000000 { + gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 3760744cc1b0..e6d25813b416 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -56,7 +56,7 @@ }; }; - gpu@0,57000000 { + gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index c3edb332187a..f42191f22c19 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -72,7 +72,7 @@ status = "okay"; }; - gpu@0,57000000 { + gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 2d045d1a9bcf..998b129321f8 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -61,7 +61,7 @@ }; }; - gpu@0,57000000 { + gpu@57000000 { status = "okay"; vdd-supply = <&vdd_gpu>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 5f17a2f7d270..7985d1cbc1c0 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -51,7 +51,7 @@ }; }; - gpu@0,57000000 { + gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index f4ac0c327c2e..d0ec1a30ff54 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -223,12 +223,7 @@ interrupt-parent = <&gic>; }; - /* - * Please keep the following 0, notation in place as a former mainline - * U-Boot version was looking for that particular notation in order to - * perform required fix-ups on that GPU node. - */ - gpu@0,57000000 { + gpu@57000000 { compatible = "nvidia,gk20a"; reg = <0x0 0x57000000 0x0 0x01000000>, <0x0 0x58000000 0x0 0x01000000>; -- cgit v1.2.3 From 9ab9ecd83a3ecf269e8cda08233652203347f5f1 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:11:33 +0100 Subject: ARM: tegra: Drop reg-shift for Tegra HS UART When the Tegra High-Speed UART is used instead of the regular UART, the reg-shift property is implied from the compatible string and should not be explicitly listed. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 3 +++ arch/arm/boot/dts/tegra124-apalis.dtsi | 3 +++ arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 ++ arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 2 ++ arch/arm/boot/dts/tegra20-colibri.dtsi | 2 ++ arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 3 +++ arch/arm/boot/dts/tegra30-apalis.dtsi | 3 +++ arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 2 ++ arch/arm/boot/dts/tegra30-cardhu.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 2 ++ arch/arm/boot/dts/tegra30-ouya.dts | 3 ++- 11 files changed, 25 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index f00ef4d08fd4..b952b272afc0 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1539,14 +1539,17 @@ serial@70006040 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c700 { diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index e6d25813b416..2b1bb4382b42 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1532,14 +1532,17 @@ serial@70006040 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c400 { diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index f42191f22c19..e805cb2e20f4 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1389,6 +1389,7 @@ */ serial@70006000 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; }; @@ -1401,6 +1402,7 @@ */ serial@70006040 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 2e6340e92fe1..f973df0158c9 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -382,11 +382,13 @@ uartb: serial@70006040 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; /* GPS BCM4751 */ }; uartc: serial@70006200 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; status = "okay"; /* Azurewave AW-NH665 BCM4329B1 */ diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 80e439003a6d..6fed5706da79 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -428,10 +428,12 @@ serial@70006040 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; }; nand-controller@70008000 { diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 6a3a72f81c44..6fe775b2b38d 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -829,14 +829,17 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c700 { diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index b2ac51fb15b1..7df2841690d7 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -820,14 +820,17 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c700 { diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index e6aed19a5f3b..ab33ceb63fff 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -804,11 +804,13 @@ uartb: serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; /* GPS BCM4751 */ }; uartc: serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; nvidia,adjust-baud-rates = <0 9600 100>, diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 886d4bb2d82c..12e185846dcb 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -175,6 +175,7 @@ serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index fcd3d26bef2d..b585831e3212 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -701,10 +701,12 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; }; hdmi_ddc: i2c@7000c700 { diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 4259871b76c9..2a6dc423b9fc 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -82,8 +82,9 @@ }; uartc: serial@70006200 { - status = "okay"; compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; nvidia,adjust-baud-rates = <0 9600 100>, <9600 115200 200>, -- cgit v1.2.3 From 272c5c3a3792366dfd441182f1bd94aa4b6e346f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:14:33 +0100 Subject: ARM: tegra: Rename thermal zone nodes The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 6 +++--- arch/arm/boot/dts/tegra124-apalis.dtsi | 6 +++--- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 +++--- arch/arm/boot/dts/tegra124.dtsi | 8 ++++---- 4 files changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index b952b272afc0..f5440ae14cb4 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -2024,7 +2024,7 @@ }; thermal-zones { - cpu { + cpu-thermal { trips { cpu-shutdown-trip { temperature = <101000>; @@ -2034,7 +2034,7 @@ }; }; - mem { + mem-thermal { trips { mem-shutdown-trip { temperature = <101000>; @@ -2044,7 +2044,7 @@ }; }; - gpu { + gpu-thermal { trips { gpu-shutdown-trip { temperature = <101000>; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 2b1bb4382b42..1d83f2e254c5 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -2016,7 +2016,7 @@ }; thermal-zones { - cpu { + cpu-thermal { trips { cpu-shutdown-trip { temperature = <101000>; @@ -2026,7 +2026,7 @@ }; }; - mem { + mem-thermal { trips { mem-shutdown-trip { temperature = <101000>; @@ -2036,7 +2036,7 @@ }; }; - gpu { + gpu-thermal { trips { gpu-shutdown-trip { temperature = <101000>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index e805cb2e20f4..28b889e4e33b 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -2047,7 +2047,7 @@ }; thermal-zones { - cpu { + cpu-thermal { trips { cpu-shutdown-trip { temperature = <101000>; @@ -2057,7 +2057,7 @@ }; }; - mem { + mem-thermal { trips { mem-shutdown-trip { temperature = <101000>; @@ -2067,7 +2067,7 @@ }; }; - gpu { + gpu-thermal { trips { gpu-shutdown-trip { temperature = <101000>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index d0ec1a30ff54..752a28268024 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1242,7 +1242,7 @@ }; thermal-zones { - cpu { + cpu-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -1270,7 +1270,7 @@ }; }; - mem { + mem-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -1298,7 +1298,7 @@ }; }; - gpu { + gpu-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -1326,7 +1326,7 @@ }; }; - pllx { + pllx-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; -- cgit v1.2.3 From c6d4a8977598c022355521fcf29d706dd95c7a83 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:41 +0300 Subject: ARM: tegra: Rename CPU and EMC OPP table device-tree nodes OPP table name now should start with "opp-table" and OPP entries shouldn't contain commas and @ signs in accordance to the new schema requirement. Reorganize CPU and EMC OPP table device-tree nodes. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 4 +- arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 4 +- arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 8 +- arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 8 +- arch/arm/boot/dts/tegra124-peripherals-opp.dtsi | 140 ++++++++++---------- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 +- arch/arm/boot/dts/tegra20-colibri.dtsi | 2 +- arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi | 82 ++++++------ arch/arm/boot/dts/tegra20-cpu-opp.dtsi | 82 ++++++------ arch/arm/boot/dts/tegra20-paz00.dts | 2 +- arch/arm/boot/dts/tegra20-peripherals-opp.dtsi | 36 +++--- ...tegra30-asus-nexus7-grouper-memory-timings.dtsi | 12 +- arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi | 144 ++++++++++----------- arch/arm/boot/dts/tegra30-cpu-opp.dtsi | 144 ++++++++++----------- arch/arm/boot/dts/tegra30-ouya.dts | 4 +- arch/arm/boot/dts/tegra30-peripherals-opp.dtsi | 128 +++++++++--------- 16 files changed, 402 insertions(+), 402 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index 25c1006a2c5a..7143c6b2ec3e 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -1477,9 +1477,9 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@1200000000,1100; + /delete-node/ opp-1200000000-1100; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@1200000000; + /delete-node/ opp-1200000000; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index 3ad2e02c7d3a..79e776db5f37 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -2432,9 +2432,9 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@1200000000,1100; + /delete-node/ opp-1200000000-1100; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@1200000000; + /delete-node/ opp-1200000000; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index 49a6d6afc633..31b2e26c69d4 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -6681,11 +6681,11 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@924000000,1100; - /delete-node/ opp@1200000000,1100; + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@924000000; - /delete-node/ opp@1200000000; + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index 7360a1f35389..2ce1b12be44d 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -2058,11 +2058,11 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@924000000,1100; - /delete-node/ opp@1200000000,1100; + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@924000000; - /delete-node/ opp@1200000000; + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; }; diff --git a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi index 781ac8601030..b262c1289da5 100644 --- a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi @@ -1,421 +1,421 @@ // SPDX-License-Identifier: GPL-2.0 / { - emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; - opp@12750000,800 { + opp-12750000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0003>; }; - opp@12750000,950 { + opp-12750000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0008>; }; - opp@12750000,1050 { + opp-12750000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0010>; }; - opp@12750000,1110 { + opp-12750000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0004>; }; - opp@20400000,800 { + opp-20400000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x0003>; }; - opp@20400000,950 { + opp-20400000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x0008>; }; - opp@20400000,1050 { + opp-20400000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x0010>; }; - opp@20400000,1110 { + opp-20400000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x0004>; }; - opp@40800000,800 { + opp-40800000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x0003>; }; - opp@40800000,950 { + opp-40800000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x0008>; }; - opp@40800000,1050 { + opp-40800000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x0010>; }; - opp@40800000,1110 { + opp-40800000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x0004>; }; - opp@68000000,800 { + opp-68000000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x0003>; }; - opp@68000000,950 { + opp-68000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x0008>; }; - opp@68000000,1050 { + opp-68000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x0010>; }; - opp@68000000,1110 { + opp-68000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x0004>; }; - opp@102000000,800 { + opp-102000000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0003>; }; - opp@102000000,950 { + opp-102000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0008>; }; - opp@102000000,1050 { + opp-102000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0010>; }; - opp@102000000,1110 { + opp-102000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0004>; }; - opp@204000000,800 { + opp-204000000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0003>; opp-suspend; }; - opp@204000000,950 { + opp-204000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0008>; opp-suspend; }; - opp@204000000,1050 { + opp-204000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0010>; opp-suspend; }; - opp@204000000,1110 { + opp-204000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0004>; opp-suspend; }; - opp@264000000,800 { + opp-264000000-800 { opp-microvolt = <800000 800000 1150000>; opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x0003>; }; - opp@264000000,950 { + opp-264000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x0008>; }; - opp@264000000,1050 { + opp-264000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x0010>; }; - opp@264000000,1110 { + opp-264000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x0004>; }; - opp@300000000,850 { + opp-300000000-850 { opp-microvolt = <850000 850000 1150000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x0003>; }; - opp@300000000,950 { + opp-300000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x0008>; }; - opp@300000000,1050 { + opp-300000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x0010>; }; - opp@300000000,1110 { + opp-300000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x0004>; }; - opp@348000000,850 { + opp-348000000-850 { opp-microvolt = <850000 850000 1150000>; opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x0003>; }; - opp@348000000,950 { + opp-348000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x0008>; }; - opp@348000000,1050 { + opp-348000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x0010>; }; - opp@348000000,1110 { + opp-348000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x0004>; }; - opp@396000000,950 { + opp-396000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x0008>; }; - opp@396000000,1000 { + opp-396000000-1000 { opp-microvolt = <1000000 1000000 1150000>; opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x0003>; }; - opp@396000000,1050 { + opp-396000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x0010>; }; - opp@396000000,1110 { + opp-396000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x0004>; }; - opp@528000000,950 { + opp-528000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x0008>; }; - opp@528000000,1000 { + opp-528000000-1000 { opp-microvolt = <1000000 1000000 1150000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x0003>; }; - opp@528000000,1050 { + opp-528000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x0010>; }; - opp@528000000,1110 { + opp-528000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x0004>; }; - opp@600000000,950 { + opp-600000000-950 { opp-microvolt = <950000 950000 1150000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x0008>; }; - opp@600000000,1000 { + opp-600000000-1000 { opp-microvolt = <1000000 1000000 1150000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x0003>; }; - opp@600000000,1050 { + opp-600000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x0010>; }; - opp@600000000,1110 { + opp-600000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x0004>; }; - opp@792000000,1000 { + opp-792000000-1000 { opp-microvolt = <1000000 1000000 1150000>; opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x000B>; }; - opp@792000000,1050 { + opp-792000000-1050 { opp-microvolt = <1050000 1050000 1150000>; opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x0010>; }; - opp@792000000,1110 { + opp-792000000-1110 { opp-microvolt = <1110000 1110000 1150000>; opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x0004>; }; - opp@924000000,1100 { + opp-924000000-1100 { opp-microvolt = <1100000 1100000 1150000>; opp-hz = /bits/ 64 <924000000>; opp-supported-hw = <0x0013>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { opp-microvolt = <1100000 1100000 1150000>; opp-hz = /bits/ 64 <1200000000>; opp-supported-hw = <0x0003>; }; }; - emc_bw_dfs_opp_table: emc-bandwidth-opp-table { + emc_bw_dfs_opp_table: opp-table-actmon { compatible = "operating-points-v2"; - opp@12750000 { + opp-12750000 { opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <204000>; }; - opp@20400000 { + opp-20400000 { opp-hz = /bits/ 64 <20400000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <326400>; }; - opp@40800000 { + opp-40800000 { opp-hz = /bits/ 64 <40800000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <652800>; }; - opp@68000000 { + opp-68000000 { opp-hz = /bits/ 64 <68000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <1088000>; }; - opp@102000000 { + opp-102000000 { opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <1632000>; }; - opp@204000000 { + opp-204000000 { opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <3264000>; opp-suspend; }; - opp@264000000 { + opp-264000000 { opp-hz = /bits/ 64 <264000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <4224000>; }; - opp@300000000 { + opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <4800000>; }; - opp@348000000 { + opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <5568000>; }; - opp@396000000 { + opp-396000000 { opp-hz = /bits/ 64 <396000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <6336000>; }; - opp@528000000 { + opp-528000000 { opp-hz = /bits/ 64 <528000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <8448000>; }; - opp@600000000 { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <9600000>; }; - opp@792000000 { + opp-792000000 { opp-hz = /bits/ 64 <792000000>; opp-supported-hw = <0x001F>; opp-peak-kBps = <12672000>; }; - opp@924000000 { + opp-924000000 { opp-hz = /bits/ 64 <924000000>; opp-supported-hw = <0x0013>; opp-peak-kBps = <14784000>; }; - opp@1200000000 { + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-supported-hw = <0x0003>; opp-peak-kBps = <19200000>; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index f973df0158c9..2d5fead9de6b 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -1508,6 +1508,6 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@666000000; - /delete-node/ opp@760000000; + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 6fed5706da79..e36b258c82df 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -745,7 +745,7 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@760000000; + /delete-node/ opp-760000000; }; &gpio { diff --git a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi index 6f3e8c5fc5f0..7330c1b13d93 100644 --- a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi +++ b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi @@ -1,164 +1,164 @@ // SPDX-License-Identifier: GPL-2.0 / { - cpu0_opp_table: cpu_opp_table0 { - opp@216000000,750 { + cpu0_opp_table: opp-table-cpu0 { + opp-216000000-750 { opp-microvolt = <750000 750000 1125000>; }; - opp@216000000,800 { + opp-216000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@312000000,750 { + opp-312000000-750 { opp-microvolt = <750000 750000 1125000>; }; - opp@312000000,800 { + opp-312000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000,750 { + opp-456000000-750 { opp-microvolt = <750000 750000 1125000>; }; - opp@456000000,800 { + opp-456000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000,825 { + opp-456000000-825 { opp-microvolt = <825000 825000 1125000>; }; - opp@608000000,750 { + opp-608000000-750 { opp-microvolt = <750000 750000 1125000>; }; - opp@608000000,800 { + opp-608000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@608000000,825 { + opp-608000000-825 { opp-microvolt = <825000 825000 1125000>; }; - opp@608000000,850 { + opp-608000000-850 { opp-microvolt = <850000 850000 1125000>; }; - opp@608000000,900 { + opp-608000000-900 { opp-microvolt = <900000 900000 1125000>; }; - opp@760000000,775 { + opp-760000000-775 { opp-microvolt = <775000 775000 1125000>; }; - opp@760000000,800 { + opp-760000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@760000000,850 { + opp-760000000-850 { opp-microvolt = <850000 850000 1125000>; }; - opp@760000000,875 { + opp-760000000-875 { opp-microvolt = <875000 875000 1125000>; }; - opp@760000000,900 { + opp-760000000-900 { opp-microvolt = <900000 900000 1125000>; }; - opp@760000000,975 { + opp-760000000-975 { opp-microvolt = <975000 975000 1125000>; }; - opp@816000000,800 { + opp-816000000-800 { opp-microvolt = <800000 800000 1125000>; }; - opp@816000000,850 { + opp-816000000-850 { opp-microvolt = <850000 850000 1125000>; }; - opp@816000000,875 { + opp-816000000-875 { opp-microvolt = <875000 875000 1125000>; }; - opp@816000000,950 { + opp-816000000-950 { opp-microvolt = <950000 950000 1125000>; }; - opp@816000000,1000 { + opp-816000000-1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@912000000,850 { + opp-912000000-850 { opp-microvolt = <850000 850000 1125000>; }; - opp@912000000,900 { + opp-912000000-900 { opp-microvolt = <900000 900000 1125000>; }; - opp@912000000,925 { + opp-912000000-925 { opp-microvolt = <925000 925000 1125000>; }; - opp@912000000,950 { + opp-912000000-950 { opp-microvolt = <950000 950000 1125000>; }; - opp@912000000,1000 { + opp-912000000-1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@912000000,1050 { + opp-912000000-1050 { opp-microvolt = <1050000 1050000 1125000>; }; - opp@1000000000,875 { + opp-1000000000-875 { opp-microvolt = <875000 875000 1125000>; }; - opp@1000000000,900 { + opp-1000000000-900 { opp-microvolt = <900000 900000 1125000>; }; - opp@1000000000,950 { + opp-1000000000-950 { opp-microvolt = <950000 950000 1125000>; }; - opp@1000000000,975 { + opp-1000000000-975 { opp-microvolt = <975000 975000 1125000>; }; - opp@1000000000,1000 { + opp-1000000000-1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@1000000000,1025 { + opp-1000000000-1025 { opp-microvolt = <1025000 1025000 1125000>; }; - opp@1000000000,1100 { + opp-1000000000-1100 { opp-microvolt = <1100000 1100000 1125000>; }; - opp@1200000000,1000 { + opp-1200000000-1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@1200000000,1050 { + opp-1200000000-1050 { opp-microvolt = <1050000 1050000 1125000>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { opp-microvolt = <1100000 1100000 1125000>; }; - opp@1200000000,1125 { + opp-1200000000-1125 { opp-microvolt = <1125000 1125000 1125000>; }; }; diff --git a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi index 135de316383b..47c8e78ca958 100644 --- a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi @@ -1,250 +1,250 @@ // SPDX-License-Identifier: GPL-2.0 / { - cpu0_opp_table: cpu_opp_table0 { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; - opp@216000000,750 { + opp-216000000-750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0003>; opp-hz = /bits/ 64 <216000000>; opp-suspend; }; - opp@216000000,800 { + opp-216000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0004>; opp-hz = /bits/ 64 <216000000>; opp-suspend; }; - opp@312000000,750 { + opp-312000000-750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0003>; opp-hz = /bits/ 64 <312000000>; }; - opp@312000000,800 { + opp-312000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0004>; opp-hz = /bits/ 64 <312000000>; }; - opp@456000000,750 { + opp-456000000-750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0C 0x0003>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000,800 { + opp-456000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>, <0x04 0x0004>, <0x08 0x0004>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000,825 { + opp-456000000-825 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <456000000>; }; - opp@608000000,750 { + opp-608000000-750 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0003>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,800 { + opp-608000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0006>, <0x08 0x0004>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,825 { + opp-608000000-825 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,850 { + opp-608000000-850 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,900 { + opp-608000000-900 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <608000000>; }; - opp@760000000,775 { + opp-760000000-775 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0003>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,800 { + opp-760000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,850 { + opp-760000000-850 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0006>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,875 { + opp-760000000-875 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>, <0x02 0x0002>, <0x01 0x0004>, <0x02 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,900 { + opp-760000000-900 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,975 { + opp-760000000-975 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <760000000>; }; - opp@816000000,800 { + opp-816000000-800 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,850 { + opp-816000000-850 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,875 { + opp-816000000-875 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0005>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,950 { + opp-816000000-950 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,1000 { + opp-816000000-1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <816000000>; }; - opp@912000000,850 { + opp-912000000-850 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,900 { + opp-912000000-900 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,925 { + opp-912000000-925 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,950 { + opp-912000000-950 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>, <0x04 0x0004>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,1000 { + opp-912000000-1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000,1050 { + opp-912000000-1050 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <912000000>; }; - opp@1000000000,875 { + opp-1000000000-875 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,900 { + opp-1000000000-900 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,950 { + opp-1000000000-950 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,975 { + opp-1000000000-975 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1000 { + opp-1000000000-1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1025 { + opp-1000000000-1025 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1100 { + opp-1000000000-1100 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1200000000,1000 { + opp-1200000000-1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1050 { + opp-1200000000-1050 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1125 { + opp-1200000000-1125 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0004>; opp-hz = /bits/ 64 <1200000000>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 46d81d703548..1fd5a7458c7a 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -705,5 +705,5 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@760000000; + /delete-node/ opp-760000000; }; diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi index ef3ad2e5f270..d4d0a5fa7015 100644 --- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi @@ -1,107 +1,107 @@ // SPDX-License-Identifier: GPL-2.0 / { - emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; - opp@36000000 { + opp-36000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <36000000>; opp-supported-hw = <0x000F>; }; - opp@47500000 { + opp-47500000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <47500000>; opp-supported-hw = <0x000F>; }; - opp@50000000 { + opp-50000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <50000000>; opp-supported-hw = <0x000F>; }; - opp@54000000 { + opp-54000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x000F>; }; - opp@57000000 { + opp-57000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <57000000>; opp-supported-hw = <0x000F>; }; - opp@100000000 { + opp-100000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <100000000>; opp-supported-hw = <0x000F>; }; - opp@108000000 { + opp-108000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x000F>; }; - opp@126666000 { + opp-126666000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <126666000>; opp-supported-hw = <0x000F>; }; - opp@150000000 { + opp-150000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <150000000>; opp-supported-hw = <0x000F>; }; - opp@190000000 { + opp-190000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <190000000>; opp-supported-hw = <0x000F>; }; - opp@216000000 { + opp-216000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <216000000>; opp-supported-hw = <0x000F>; opp-suspend; }; - opp@300000000 { + opp-300000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x000F>; }; - opp@333000000 { + opp-333000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <333000000>; opp-supported-hw = <0x000F>; }; - opp@380000000 { + opp-380000000 { opp-microvolt = <1100000 1100000 1300000>; opp-hz = /bits/ 64 <380000000>; opp-supported-hw = <0x000F>; }; - opp@600000000 { + opp-600000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x000F>; }; - opp@666000000 { + opp-666000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <666000000>; opp-supported-hw = <0x000F>; }; - opp@760000000 { + opp-760000000 { opp-microvolt = <1300000 1300000 1300000>; opp-hz = /bits/ 64 <760000000>; opp-supported-hw = <0x000F>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi index bcff0997ee51..6c229e1d67e7 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi @@ -1565,13 +1565,13 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@750000000,1300; - /delete-node/ opp@800000000,1300; - /delete-node/ opp@900000000,1350; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@750000000; - /delete-node/ opp@800000000; - /delete-node/ opp@900000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; }; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi index 1be715d2a442..b8e0e9117021 100644 --- a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi +++ b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi @@ -1,288 +1,288 @@ // SPDX-License-Identifier: GPL-2.0 / { - cpu0_opp_table: cpu_opp_table0 { - opp@51000000,800 { + cpu0_opp_table: opp-table-cpu0 { + opp-51000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@51000000,850 { + opp-51000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@51000000,912 { + opp-51000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@102000000,800 { + opp-102000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@102000000,850 { + opp-102000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@102000000,912 { + opp-102000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@204000000,800 { + opp-204000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@204000000,850 { + opp-204000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@204000000,912 { + opp-204000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@312000000,850 { + opp-312000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@312000000,912 { + opp-312000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@340000000,800 { + opp-340000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@340000000,850 { + opp-340000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@370000000,800 { + opp-370000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@456000000,850 { + opp-456000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@456000000,912 { + opp-456000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@475000000,800 { + opp-475000000-800 { opp-microvolt = <800000 800000 1250000>; }; - opp@475000000,850 { + opp-475000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@608000000,850 { + opp-608000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@608000000,912 { + opp-608000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@620000000,850 { + opp-620000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000,850 { + opp-640000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000,900 { + opp-640000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000,850 { + opp-760000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000,900 { + opp-760000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000,912 { + opp-760000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@760000000,975 { + opp-760000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@816000000,850 { + opp-816000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@816000000,912 { + opp-816000000-912 { opp-microvolt = <912000 912000 1250000>; }; - opp@860000000,850 { + opp-860000000-850 { opp-microvolt = <850000 850000 1250000>; }; - opp@860000000,900 { + opp-860000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000,975 { + opp-860000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000,1000 { + opp-860000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@910000000,900 { + opp-910000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1000000000,900 { + opp-1000000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1000000000,975 { + opp-1000000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000,1000 { + opp-1000000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1000000000,1025 { + opp-1000000000-1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1100000000,900 { + opp-1100000000-900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1100000000,975 { + opp-1100000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000,1000 { + opp-1100000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000,1025 { + opp-1100000000-1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1100000000,1075 { + opp-1100000000-1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1150000000,975 { + opp-1150000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1200000000,975 { + opp-1200000000-975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1200000000,1000 { + opp-1200000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000,1025 { + opp-1200000000-1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000,1050 { + opp-1200000000-1050 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1200000000,1075 { + opp-1200000000-1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1300000000,1000 { + opp-1300000000-1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1300000000,1025 { + opp-1300000000-1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1300000000,1050 { + opp-1300000000-1050 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000,1075 { + opp-1300000000-1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1300000000,1100 { + opp-1300000000-1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1300000000,1125 { + opp-1300000000-1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1300000000,1150 { + opp-1300000000-1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1300000000,1175 { + opp-1300000000-1175 { opp-microvolt = <1175000 1175000 1250000>; }; - opp@1400000000,1100 { + opp-1400000000-1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1400000000,1125 { + opp-1400000000-1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1400000000,1150 { + opp-1400000000-1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1400000000,1175 { + opp-1400000000-1175 { opp-microvolt = <1175000 1175000 1250000>; }; - opp@1400000000,1237 { + opp-1400000000-1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1500000000,1125 { + opp-1500000000-1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000,1150 { + opp-1500000000-1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000,1200 { + opp-1500000000-1200 { opp-microvolt = <1200000 1200000 1250000>; }; - opp@1500000000,1237 { + opp-1500000000-1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1600000000,1212 { + opp-1600000000-1212 { opp-microvolt = <1212000 1212000 1250000>; }; - opp@1600000000,1237 { + opp-1600000000-1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1700000000,1212 { + opp-1700000000-1212 { opp-microvolt = <1212000 1212000 1250000>; }; - opp@1700000000,1237 { + opp-1700000000-1237 { opp-microvolt = <1237000 1237000 1250000>; }; }; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi index 72f2fe26cc0e..5b9ebb75a09f 100644 --- a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi @@ -1,116 +1,116 @@ // SPDX-License-Identifier: GPL-2.0 / { - cpu0_opp_table: cpu_opp_table0 { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; - opp@51000000,800 { + opp-51000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <51000000>; }; - opp@51000000,850 { + opp-51000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <51000000>; }; - opp@51000000,912 { + opp-51000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <51000000>; }; - opp@102000000,800 { + opp-102000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <102000000>; }; - opp@102000000,850 { + opp-102000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <102000000>; }; - opp@102000000,912 { + opp-102000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <102000000>; }; - opp@204000000,800 { + opp-204000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <204000000>; opp-suspend; }; - opp@204000000,850 { + opp-204000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <204000000>; opp-suspend; }; - opp@204000000,912 { + opp-204000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <204000000>; opp-suspend; }; - opp@312000000,850 { + opp-312000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C00>; opp-hz = /bits/ 64 <312000000>; }; - opp@312000000,912 { + opp-312000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <312000000>; }; - opp@340000000,800 { + opp-340000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0192>; opp-hz = /bits/ 64 <340000000>; }; - opp@340000000,850 { + opp-340000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>; opp-hz = /bits/ 64 <340000000>; }; - opp@370000000,800 { + opp-370000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x306C>; opp-hz = /bits/ 64 <370000000>; }; - opp@456000000,850 { + opp-456000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C00>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000,912 { + opp-456000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <456000000>; }; - opp@475000000,800 { + opp-475000000-800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x31FE>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000,850 { + opp-475000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>, <0x01 0x0002>, <0x01 0x0010>, <0x01 0x0080>, @@ -118,25 +118,25 @@ opp-hz = /bits/ 64 <475000000>; }; - opp@608000000,850 { + opp-608000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0400>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000,912 { + opp-608000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <608000000>; }; - opp@620000000,850 { + opp-620000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x306C>; opp-hz = /bits/ 64 <620000000>; }; - opp@640000000,850 { + opp-640000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>, <0x02 0x0002>, <0x04 0x0002>, <0x08 0x0002>, @@ -149,13 +149,13 @@ opp-hz = /bits/ 64 <640000000>; }; - opp@640000000,900 { + opp-640000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <640000000>; }; - opp@760000000,850 { + opp-760000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x3461>, <0x08 0x0002>, <0x08 0x0004>, <0x08 0x0008>, @@ -165,7 +165,7 @@ opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,900 { + opp-760000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>, <0x04 0x0002>, <0x02 0x0004>, @@ -177,37 +177,37 @@ opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,912 { + opp-760000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000,975 { + opp-760000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <760000000>; }; - opp@816000000,850 { + opp-816000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0400>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000,912 { + opp-816000000-912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <816000000>; }; - opp@860000000,850 { + opp-860000000-850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0C 0x0001>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000,900 { + opp-860000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>, <0x08 0x0002>, <0x04 0x0004>, @@ -220,7 +220,7 @@ opp-hz = /bits/ 64 <860000000>; }; - opp@860000000,975 { + opp-860000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>, <0x02 0x0004>, <0x02 0x0008>, @@ -229,25 +229,25 @@ opp-hz = /bits/ 64 <860000000>; }; - opp@860000000,1000 { + opp-860000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <860000000>; }; - opp@910000000,900 { + opp-910000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x3060>; opp-hz = /bits/ 64 <910000000>; }; - opp@1000000000,900 { + opp-1000000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x0C 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,975 { + opp-1000000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x03 0x0001>, <0x04 0x0002>, <0x08 0x0002>, <0x04 0x0004>, @@ -260,25 +260,25 @@ opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1000 { + opp-1000000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000,1025 { + opp-1000000000-1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1100000000,900 { + opp-1100000000-900 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000,975 { + opp-1100000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x06 0x0001>, <0x08 0x0002>, <0x08 0x0004>, <0x08 0x0008>, @@ -288,7 +288,7 @@ opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000,1000 { + opp-1100000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>, <0x04 0x0002>, <0x04 0x0004>, <0x04 0x0008>, @@ -297,31 +297,31 @@ opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000,1025 { + opp-1100000000-1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000,1075 { + opp-1100000000-1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1150000000,975 { + opp-1150000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x3060>; opp-hz = /bits/ 64 <1150000000>; }; - opp@1200000000,975 { + opp-1200000000-975 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1000 { + opp-1200000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>, <0x08 0x0004>, <0x08 0x0008>, @@ -331,7 +331,7 @@ opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1025 { + opp-1200000000-1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>, <0x04 0x0004>, <0x04 0x0008>, @@ -340,39 +340,39 @@ opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1050 { + opp-1200000000-1050 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1075 { + opp-1200000000-1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000,1100 { + opp-1200000000-1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1300000000,1000 { + opp-1300000000-1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>, <0x10 0x0080>, <0x10 0x0100>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1025 { + opp-1300000000-1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>, <0x08 0x0080>, <0x08 0x0100>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1050 { + opp-1300000000-1050 { clock-latency-ns = <100000>; opp-supported-hw = <0x12 0x3061>, <0x04 0x0002>, <0x08 0x0004>, <0x08 0x0008>, @@ -383,68 +383,68 @@ opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1075 { + opp-1300000000-1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0182>, <0x04 0x0004>, <0x04 0x0008>, <0x04 0x0010>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1100 { + opp-1300000000-1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x001C>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1125 { + opp-1300000000-1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1150 { + opp-1300000000-1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0182>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000,1175 { + opp-1300000000-1175 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1400000000,1100 { + opp-1400000000-1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x307C>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000,1125 { + opp-1400000000-1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x000C>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000,1150 { + opp-1400000000-1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x000C>, <0x04 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000,1175 { + opp-1400000000-1175 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000,1237 { + opp-1400000000-1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1500000000,1125 { + opp-1500000000-1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>, <0x10 0x0020>, <0x10 0x0040>, <0x10 0x1000>, @@ -452,7 +452,7 @@ opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000,1150 { + opp-1500000000-1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>, <0x08 0x0020>, <0x08 0x0040>, <0x08 0x1000>, @@ -460,37 +460,37 @@ opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000,1200 { + opp-1500000000-1200 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000,1237 { + opp-1500000000-1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1600000000,1212 { + opp-1600000000-1212 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x3060>; opp-hz = /bits/ 64 <1600000000>; }; - opp@1600000000,1237 { + opp-1600000000-1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x3060>; opp-hz = /bits/ 64 <1600000000>; }; - opp@1700000000,1212 { + opp-1700000000-1212 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x3060>; opp-hz = /bits/ 64 <1700000000>; }; - opp@1700000000,1237 { + opp-1700000000-1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x3060>; opp-hz = /bits/ 64 <1700000000>; diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 2a6dc423b9fc..9e59d9bd6b35 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -4524,9 +4524,9 @@ }; &emc_icc_dvfs_opp_table { - /delete-node/ opp@900000000,1350; + /delete-node/ opp-900000000-1350; }; &emc_bw_dfs_opp_table { - /delete-node/ opp@900000000; + /delete-node/ opp-900000000; }; diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi index 2c9780319725..ff25350869b3 100644 --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -1,383 +1,383 @@ // SPDX-License-Identifier: GPL-2.0 / { - emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; - opp@12750000,950 { + opp-12750000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0006>; }; - opp@12750000,1000 { + opp-12750000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0001>; }; - opp@12750000,1250 { + opp-12750000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0008>; }; - opp@25500000,950 { + opp-25500000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0006>; }; - opp@25500000,1000 { + opp-25500000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0001>; }; - opp@25500000,1250 { + opp-25500000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0008>; }; - opp@27000000,950 { + opp-27000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0006>; }; - opp@27000000,1000 { + opp-27000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0001>; }; - opp@27000000,1250 { + opp-27000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0008>; }; - opp@51000000,950 { + opp-51000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0006>; }; - opp@51000000,1000 { + opp-51000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0001>; }; - opp@51000000,1250 { + opp-51000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0008>; }; - opp@54000000,950 { + opp-54000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0006>; }; - opp@54000000,1000 { + opp-54000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0001>; }; - opp@54000000,1250 { + opp-54000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0008>; }; - opp@102000000,950 { + opp-102000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0006>; }; - opp@102000000,1000 { + opp-102000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0001>; }; - opp@102000000,1250 { + opp-102000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0008>; }; - opp@108000000,1000 { + opp-108000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x0007>; }; - opp@108000000,1250 { + opp-108000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x0008>; }; - opp@204000000,1000 { + opp-204000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0007>; opp-suspend; }; - opp@204000000,1250 { + opp-204000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0008>; opp-suspend; }; - opp@333500000,1000 { + opp-333500000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0006>; }; - opp@333500000,1200 { + opp-333500000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0001>; }; - opp@333500000,1250 { + opp-333500000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0008>; }; - opp@375000000,1000 { + opp-375000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0006>; }; - opp@375000000,1200 { + opp-375000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0001>; }; - opp@375000000,1250 { + opp-375000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0008>; }; - opp@400000000,1000 { + opp-400000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0006>; }; - opp@400000000,1200 { + opp-400000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0001>; }; - opp@400000000,1250 { + opp-400000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0008>; }; - opp@416000000,1200 { + opp-416000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x0007>; }; - opp@416000000,1250 { + opp-416000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x0008>; }; - opp@450000000,1200 { + opp-450000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x0007>; }; - opp@450000000,1250 { + opp-450000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x0008>; }; - opp@533000000,1200 { + opp-533000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x0007>; }; - opp@533000000,1250 { + opp-533000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x0008>; }; - opp@625000000,1200 { + opp-625000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x0006>; }; - opp@625000000,1250 { + opp-625000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x0008>; }; - opp@667000000,1200 { + opp-667000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <667000000>; opp-supported-hw = <0x0006>; }; - opp@750000000,1300 { + opp-750000000-1300 { opp-microvolt = <1300000 1300000 1350000>; opp-hz = /bits/ 64 <750000000>; opp-supported-hw = <0x0004>; }; - opp@800000000,1300 { + opp-800000000-1300 { opp-microvolt = <1300000 1300000 1350000>; opp-hz = /bits/ 64 <800000000>; opp-supported-hw = <0x0004>; }; - opp@900000000,1350 { + opp-900000000-1350 { opp-microvolt = <1350000 1350000 1350000>; opp-hz = /bits/ 64 <900000000>; opp-supported-hw = <0x0004>; }; }; - emc_bw_dfs_opp_table: emc-bandwidth-opp-table { + emc_bw_dfs_opp_table: opp-table-actmon { compatible = "operating-points-v2"; - opp@12750000 { + opp-12750000 { opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <102000>; }; - opp@25500000 { + opp-25500000 { opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <204000>; }; - opp@27000000 { + opp-27000000 { opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <216000>; }; - opp@51000000 { + opp-51000000 { opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <408000>; }; - opp@54000000 { + opp-54000000 { opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <432000>; }; - opp@102000000 { + opp-102000000 { opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <816000>; }; - opp@108000000 { + opp-108000000 { opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <864000>; }; - opp@204000000 { + opp-204000000 { opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <1632000>; opp-suspend; }; - opp@333500000 { + opp-333500000 { opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <2668000>; }; - opp@375000000 { + opp-375000000 { opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <3000000>; }; - opp@400000000 { + opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <3200000>; }; - opp@416000000 { + opp-416000000 { opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <3328000>; }; - opp@450000000 { + opp-450000000 { opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <3600000>; }; - opp@533000000 { + opp-533000000 { opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x000F>; opp-peak-kBps = <4264000>; }; - opp@625000000 { + opp-625000000 { opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x000E>; opp-peak-kBps = <5000000>; }; - opp@667000000 { + opp-667000000 { opp-hz = /bits/ 64 <667000000>; opp-supported-hw = <0x0006>; opp-peak-kBps = <5336000>; }; - opp@750000000 { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; opp-supported-hw = <0x0004>; opp-peak-kBps = <6000000>; }; - opp@800000000 { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-supported-hw = <0x0004>; opp-peak-kBps = <6400000>; }; - opp@900000000 { + opp-900000000 { opp-hz = /bits/ 64 <900000000>; opp-supported-hw = <0x0004>; opp-peak-kBps = <7200000>; -- cgit v1.2.3 From 9b07cfe27647639e52a411d07413608cb5cda7dc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:22:26 +0100 Subject: ARM: tegra: Fix Tegra124 I2C compatible string list The I2C controller found on Tegra124 is not fully compatible with the Tegra114 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 752a28268024..0e0a769fb30f 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -438,7 +438,7 @@ }; i2c@7000c000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -453,7 +453,7 @@ }; i2c@7000c400 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c400 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -468,7 +468,7 @@ }; i2c@7000c500 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c500 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -483,7 +483,7 @@ }; i2c@7000c700 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c700 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -498,7 +498,7 @@ }; i2c@7000d000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -513,7 +513,7 @@ }; i2c@7000d100 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d100 0x0 0x100>; interrupts = ; #address-cells = <1>; -- cgit v1.2.3 From e51c87b7cb1a41d99e059ca3a9c8edf41656ce1f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:23:43 +0100 Subject: ARM: tegra: Drop unused AHCI clocks on Tegra124 The CML1 and PLL_E clocks are never explicitly used by the AHCI controller found on Tegra124, so drop them from the corresponding device tree node. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 0e0a769fb30f..36566a777e49 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -672,10 +672,8 @@ <0x0 0x70020000 0x0 0x7000>; /* SATA */ interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SATA>, - <&tegra_car TEGRA124_CLK_SATA_OOB>, - <&tegra_car TEGRA124_CLK_CML1>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "sata", "sata-oob", "cml1", "pll_e"; + <&tegra_car TEGRA124_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; resets = <&tegra_car 124>, <&tegra_car 129>, <&tegra_car 123>; -- cgit v1.2.3 From 4b7f222d832364e17363e4232d5110c7e7660932 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:25:49 +0100 Subject: ARM: tegra: Sort Tegra124 XUSB clocks correctly Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 36566a777e49..e87da6c24f7c 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -710,8 +710,8 @@ <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA124_CLK_PLL_U_480M>, @@ -719,7 +719,7 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, -- cgit v1.2.3 From 959fddf537c8d3f305df135881976318d7e13b93 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 11:27:46 +0100 Subject: ARM: tegra: Avoid pwm- prefix in pinmux nodes The "pwm-" prefix currently matches the DT schema for PWM controllers and throws an error in that case. This is something that should be fixed in the PWM DT schema, but in this case we can also preempt any such conflict by naming the nodes after the pins like we do for many others of these nodes. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-eval-v3.dts | 4 ++-- arch/arm/boot/dts/tegra20-colibri-iris.dts | 4 ++-- arch/arm/boot/dts/tegra20-colibri.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts index a05fb3853da8..d2a3bf9d28bd 100644 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -70,11 +70,11 @@ nvidia,tristate = ; }; - pwm-a-b { + sdc { nvidia,tristate = ; }; - pwm-c-d { + sdb_sdd { nvidia,tristate = ; }; diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 425494b9ed54..00ecbbd5e9e1 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -70,11 +70,11 @@ nvidia,tristate = ; }; - pwm-a-b { + sdc { nvidia,tristate = ; }; - pwm-c-d { + sdb_sdd { nvidia,tristate = ; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index e36b258c82df..28e22097578d 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -113,7 +113,7 @@ }; /* Colibri Backlight PWM, PWM */ - pwm-a-b { + sdc { nvidia,pins = "sdc"; nvidia,function = "pwm"; nvidia,tristate = ; @@ -242,7 +242,7 @@ }; /* Colibri PWM, PWM */ - pwm-c-d { + sdb_sdd { nvidia,pins = "sdb", "sdd"; nvidia,function = "pwm"; nvidia,tristate = ; -- cgit v1.2.3 From 8c4e1b1617bba39658c46449ad480b2bf4b9ff6f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 6 Dec 2021 02:11:58 +0100 Subject: ARM: configs: gemini: Activate crypto driver This enables the SL3516 crypto driver on the Gemini platforms where it is available, by default in the defconfig. Clean up some noise around the crypto options while we're at it. Signed-off-by: Linus Walleij Cc: Corentin Labbe Link: https://lore.kernel.org/r/20211206011158.4180141-1-linus.walleij@linaro.org' Signed-off-by: Arnd Bergmann --- arch/arm/configs/gemini_defconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/gemini_defconfig b/arch/arm/configs/gemini_defconfig index e6ff844821cf..a7acfee11ffc 100644 --- a/arch/arm/configs/gemini_defconfig +++ b/arch/arm/configs/gemini_defconfig @@ -63,7 +63,6 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=1 CONFIG_SERIAL_8250_RUNTIME_UARTS=1 CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_HW_RANDOM is not set CONFIG_I2C_GPIO=y CONFIG_SPI=y CONFIG_SPI_GPIO=y @@ -99,5 +98,5 @@ CONFIG_TMPFS_POSIX_ACL=y CONFIG_ROMFS_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y -# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_CRYPTO_DEV_SL3516=y CONFIG_DEBUG_FS=y -- cgit v1.2.3 From bae2f5979c6e537334c9099013b5407019e88c44 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Fri, 29 Oct 2021 17:02:04 -0700 Subject: ARM: dts: qcom: Add SDX65 platform and MTP board support Add basic devicetree support for SDX65 platform and MTP board from Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. This commit adds basic devicetree support that includes GCC, RPMh clock, INTC and Debug UART. Signed-off-by: Vamsi Krishna Lanka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 25 +++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 210 +++++++++++++++++++++++++++++++++++ 3 files changed, 237 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/qcom-sdx65-mtp.dts create mode 100644 arch/arm/boot/dts/qcom-sdx65.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bba17ee51e29..3497c08c1afc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -987,7 +987,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-mdm9615-wp8548-mangoh-green.dtb \ qcom-sdx55-mtp.dtb \ qcom-sdx55-t55.dtb \ - qcom-sdx55-telit-fn980-tlb.dtb + qcom-sdx55-telit-fn980-tlb.dtb \ + qcom-sdx65-mtp.dtb dtb-$(CONFIG_ARCH_RDA) += \ rda8810pl-orangepi-2g-iot.dtb \ rda8810pl-orangepi-i96.dtb diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts new file mode 100644 index 000000000000..59457da8e5f1 --- /dev/null +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; + +#include "qcom-sdx65.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX65 MTP"; + compatible = "qcom,sdx65-mtp", "qcom,sdx65"; + qcom,board-id = <0x2010008 0x302>; + + aliases { + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart3 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi new file mode 100644 index 000000000000..5aecb004e953 --- /dev/null +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SDX65 SoC device tree source + * + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; + interrupt-parent = <&intc>; + + memory { + device_type = "memory"; + reg = <0 0>; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cmd_db: reserved-memory@8fee0000 { + compatible = "qcom,cmd-db"; + reg = <0x8fee0000 0x20000>; + no-map; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdx65"; + reg = <0x00100000 0x001f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + blsp1_uart3: serial@831000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x00831000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + pdc: interrupt-controller@b210000 { + compatible = "qcom,sdx65-pdc", "qcom,pdc"; + reg = <0xb210000 0x10000>; + qcom,pdc-ranges = <0 147 52>, <52 266 32>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17800000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x17800000 0x1000>, + <0x17802000 0x1000>; + }; + + timer@17820000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17820000 0x1000>; + clock-frequency = <19200000>; + + frame@17821000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17821000 0x1000>, + <0x17822000 0x1000>; + }; + + frame@17823000 { + frame-number = <1>; + interrupts = ; + reg = <0x17823000 0x1000>; + status = "disabled"; + }; + + frame@17824000 { + frame-number = <2>; + interrupts = ; + reg = <0x17824000 0x1000>; + status = "disabled"; + }; + + frame@17825000 { + frame-number = <3>; + interrupts = ; + reg = <0x17825000 0x1000>; + status = "disabled"; + }; + + frame@17826000 { + frame-number = <4>; + interrupts = ; + reg = <0x17826000 0x1000>; + status = "disabled"; + }; + + frame@17827000 { + frame-number = <5>; + interrupts = ; + reg = <0x17827000 0x1000>; + status = "disabled"; + }; + + frame@17828000 { + frame-number = <6>; + interrupts = ; + reg = <0x17828000 0x1000>; + status = "disabled"; + }; + + frame@17829000 { + frame-number = <7>; + interrupts = ; + reg = <0x17829000 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17830000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x17830000 0x10000>, + <0x17840000 0x10000>; + reg-names = "drv-0", "drv-1"; + interrupts = , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <1>; + qcom,tcs-config = , + , + , + ; + + rpmhcc: clock-controller@1 { + compatible = "qcom,sdx65-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 12 0xf08>, + <1 10 0xf08>, + <1 11 0xf08>; + clock-frequency = <19200000>; + }; +}; -- cgit v1.2.3 From ff8b573a6ccf4deba10285abef072c577099e038 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Fri, 29 Oct 2021 17:02:05 -0700 Subject: ARM: dts: qcom: sdx65: Add pincontrol node This commit adds pincontrol node to SDX65 dts. Signed-off-by: Vamsi Krishna Lanka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1635552125-16407-4-git-send-email-quic_vamslank@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 5aecb004e953..796641d30e06 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -91,6 +91,18 @@ status = "disabled"; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sdx65-tlmm"; + reg = <0xf100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 109>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx65-pdc", "qcom,pdc"; reg = <0xb210000 0x10000>; -- cgit v1.2.3 From cbb469f7518f12b06b9f66eb39e84e097278b682 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:11 +0300 Subject: ARM: tegra_defconfig: Enable drivers wanted by Acer Chromebooks and ASUS tablets Enable charger, touchpad and EC drivers found on Acer Tegra124 (Nyan) Chromebooks, display bridge found on ASUS TF700T and audio codecs found on ASUS tablets. Suggested-by: Thomas Graichen # Nyan options Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/configs/tegra_defconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 8a8f12b3e6dd..a8093b222551 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -104,6 +104,8 @@ CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y CONFIG_BRCMFMAC=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m CONFIG_RT2X00=y CONFIG_RT2800USB=m CONFIG_INPUT_JOYDEV=y @@ -112,6 +114,8 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_TEGRA=y CONFIG_KEYBOARD_CROS_EC=y CONFIG_KEYBOARD_CAP11XX=y +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_SMBUS=y CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y @@ -131,6 +135,7 @@ CONFIG_SERIAL_DEV_BUS=y # CONFIG_HW_RANDOM is not set # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX_GPIO=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_TEGRA=y @@ -151,7 +156,9 @@ CONFIG_GPIO_TPS65910=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_AS3722=y CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_BATTERY_SBS=y +CONFIG_CHARGER_BQ24735=y CONFIG_BATTERY_BQ27XXX=y CONFIG_CHARGER_GPIO=y CONFIG_CHARGER_SMB347=y @@ -200,7 +207,9 @@ CONFIG_DRM_TEGRA_STAGING=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=y CONFIG_DRM_LVDS_CODEC=y +CONFIG_DRM_TOSHIBA_TC358768=y CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y @@ -279,6 +288,9 @@ CONFIG_STAGING_MEDIA=y CONFIG_TEGRA_VDE=y CONFIG_CHROME_PLATFORMS=y CONFIG_CROS_EC=y +CONFIG_CROS_EC_I2C=m +CONFIG_CROS_EC_SPI=m +CONFIG_I2C_CROS_EC_TUNNEL=m CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_ARCH_TEGRA_2x_SOC=y -- cgit v1.2.3 From ca1f7d245f530fd8ad57e7f596826da4d56bec80 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:12 +0300 Subject: ARM: config: multi v7: Enable display drivers used by Tegra devices Enable display-related drivers used by various Tegra-based tablets. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/configs/multi_v7_defconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index c951aeed2138..3d509bc13444 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -382,6 +382,7 @@ CONFIG_TCG_TPM=m CONFIG_TCG_TIS_I2C_INFINEON=m CONFIG_I2C_CHARDEV=y CONFIG_I2C_ARB_GPIO_CHALLENGE=m +CONFIG_I2C_MUX_GPIO=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_DEMUX_PINCTRL=y @@ -680,19 +681,23 @@ CONFIG_DRM_FSL_DCU=m CONFIG_DRM_TEGRA=y CONFIG_DRM_STM=m CONFIG_DRM_STM_DSI=m +CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y CONFIG_DRM_PANEL_SAMSUNG_LD9040=m +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m CONFIG_DRM_PANEL_RAYDIUM_RM68200=m CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m +CONFIG_DRM_LVDS_CODEC=m CONFIG_DRM_NXP_PTN3460=m CONFIG_DRM_PARADE_PS8622=m CONFIG_DRM_SII902X=m CONFIG_DRM_SII9234=m CONFIG_DRM_SIMPLE_BRIDGE=m CONFIG_DRM_TOSHIBA_TC358764=m +CONFIG_DRM_TOSHIBA_TC358768=m CONFIG_DRM_I2C_ADV7511=m CONFIG_DRM_I2C_ADV7511_AUDIO=y CONFIG_DRM_STI=m -- cgit v1.2.3 From 86a3a7f8a42bcdda6281b949d7e78e6e20ddc8ff Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 13:51:33 +0100 Subject: ARM: tegra: Add compatible string for built-in ASIX on Colibri boards The device tree node for the built-in ASIX Ethernet device on Colibri boards needs a compatible string in order to pass DT schema validation. Add the USB VID,PID compatible string as required by the DT schema for USB devices. Reviewed-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 28e22097578d..b1f2f7f82928 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -691,6 +691,7 @@ #size-cells = <0>; asix@1 { + compatible = "usbb95,772b"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index b585831e3212..febcb403412c 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -953,6 +953,7 @@ #size-cells = <0>; asix@1 { + compatible = "usbb95,772b"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; }; -- cgit v1.2.3 From e1808b09df868135240b6b489b692e105d0b17a7 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 13:57:40 +0100 Subject: ARM: tegra: Remove PHY reset GPIO references from USB controller node The PHY reset GPIO references belong in the USB PHY nodes, where they already exist. There is no need to keep them in the USB controller's device tree node as well. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-harmony.dts | 2 -- arch/arm/boot/dts/tegra20-paz00.dts | 2 -- arch/arm/boot/dts/tegra20-seaboard.dts | 2 -- arch/arm/boot/dts/tegra20-trimslice.dts | 2 -- arch/arm/boot/dts/tegra20-ventana.dts | 2 -- 5 files changed, 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index a8494378c382..f560bf743a19 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -595,8 +595,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 1fd5a7458c7a..12c245869a74 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -533,8 +533,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index ca7adeb1fdd9..98e61068b981 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -742,8 +742,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index dd05e2c87c29..8bb0eaa610f2 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -349,8 +349,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 4284054ebd2c..b1c92ba789be 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -556,8 +556,6 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { -- cgit v1.2.3 From c98167bbe865591351df10fd88f759f41006d060 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 13:59:59 +0100 Subject: ARM: tegra: Add dummy backlight power supplies The Medcom Wide and PAZ00 boards don't specify the power supply for the backlight, which means that the Linux driver will provide a dummy one. Wire up an explicit dummy to also make the DT schema validation succeed. Unfortunately I don't have access to the schematics for the Medcom Wide, so I don't know if a more accurate description is possible. The AC100 (PAZ00) schematics from here: https://www.s-manuals.com/pdf/motherboard/compal/compal_la-6352p_r1.0a_schematics.pdf aren't entirely clear which one of the supplies powers backlight, but the panel supply is probably close enough. Based on work by David Heidelberg . Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-medcom-wide.dts | 3 +++ arch/arm/boot/dts/tegra20-paz00.dts | 3 +++ 2 files changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index cb6199d7d224..f144487c5da3 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -54,6 +54,9 @@ brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; + + /* close enough */ + power-supply = <&vdd_3v3_reg>; }; panel: panel { diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 12c245869a74..5ce6a1ff93de 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -571,6 +571,9 @@ brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; default-brightness-level = <10>; + + /* close enough */ + power-supply = <&vdd_pnl_reg>; }; clk32k_in: clock-32k { -- cgit v1.2.3 From 9b34a2a1bc6e29562d0a2a2f77934d8829daedb4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:01:53 +0100 Subject: ARM: tegra: Use correct vendor prefix for Invensense The correct vendor prefix for Invensense is "invensense," rather than "invn,". Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-seaboard.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 98e61068b981..f9309c07a9f2 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -358,7 +358,7 @@ }; gyrometer@68 { - compatible = "invn,mpu3050"; + compatible = "invensense,mpu3050"; reg = <0x68>; interrupt-parent = <&gpio>; interrupts = ; -- cgit v1.2.3 From fe3c94e8e7e458dca28024e39fdaad537b2ea28c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:03:00 +0100 Subject: ARM: tegra: Remove unsupported properties on Apalis The +V1.2_VDD_CORE regulator on Apalis and Colibri boards uses the unsupported ti,vsel{0,1}-state-low properties. It turns out that these are in fact the default and can be overridden by ti,vsel{0,1}-state-high properties if needed. Drop them since they are not needed. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 3 --- arch/arm/boot/dts/tegra30-apalis.dtsi | 3 --- arch/arm/boot/dts/tegra30-colibri.dtsi | 3 --- 3 files changed, 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 6fe775b2b38d..380f22a35821 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -1050,9 +1050,6 @@ regulator-max-microvolt = <1400000>; regulator-boot-on; regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; }; }; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 7df2841690d7..9bdc4cb71449 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1033,9 +1033,6 @@ regulator-max-microvolt = <1400000>; regulator-boot-on; regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; }; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index febcb403412c..9bf8170fee79 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -901,9 +901,6 @@ regulator-max-microvolt = <1400000>; regulator-boot-on; regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; }; }; -- cgit v1.2.3 From e6cc64655480de215993cabec45d1f32bb1f5857 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Wed, 8 Dec 2021 20:36:05 +0300 Subject: ARM: tegra: nexus7: Drop clock-frequency from NFC node The clock-frequency property was never used and is deprecated now. Remove it from Nexus 7 device-tree. Signed-off-by: David Heidelberg Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi | 1 - arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi | 2 -- 2 files changed, 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi index a044dbd200a9..564cfcde21a9 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi @@ -137,7 +137,6 @@ nfc@28 { compatible = "nxp,pn544-i2c"; reg = <0x28>; - clock-frequency = <100000>; interrupt-parent = <&gpio>; interrupts = ; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi index a681ad51fddd..cd63e0ef7445 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi @@ -223,8 +223,6 @@ compatible = "nxp,pn544-i2c"; reg = <0x2a>; - clock-frequency = <100000>; - interrupt-parent = <&gpio>; interrupts = ; -- cgit v1.2.3 From e3cc9c1c51f872629e860ef3b780ddf07f515123 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:06:16 +0100 Subject: ARM: tegra: Remove stray #reset-cells property The Ouya board specifies the #reset-cells property for the GPIO controller. Since the GPIO controller doesn't provide reset controls this is not needed, so they can be dropped. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-ouya.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 9e59d9bd6b35..9a774500cb88 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -70,7 +70,6 @@ gpio: gpio@6000d000 { gpio-ranges = <&pinmux 0 0 248>; - #reset-cells = <1>; }; pinmux@70000868 { -- cgit v1.2.3 From 695494bb969a6070663c20425608c7b72f22887f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:07:30 +0100 Subject: ARM: tegra: Fix SLINK compatible string on Tegra30 The SLINK controller found on Tegra30 is not compatible with its predecessor found on Tegra20. Drop the fallback compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index ae3df73c20a7..46befba0bc72 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -666,7 +666,7 @@ }; spi@7000d400 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000d400 0x200>; interrupts = ; #address-cells = <1>; @@ -680,7 +680,7 @@ }; spi@7000d600 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000d600 0x200>; interrupts = ; #address-cells = <1>; @@ -694,7 +694,7 @@ }; spi@7000d800 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000d800 0x200>; interrupts = ; #address-cells = <1>; @@ -708,7 +708,7 @@ }; spi@7000da00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000da00 0x200>; interrupts = ; #address-cells = <1>; @@ -722,7 +722,7 @@ }; spi@7000dc00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000dc00 0x200>; interrupts = ; #address-cells = <1>; @@ -736,7 +736,7 @@ }; spi@7000de00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; + compatible = "nvidia,tegra30-slink"; reg = <0x7000de00 0x200>; interrupts = ; #address-cells = <1>; -- cgit v1.2.3 From b716d046041e19af9ba188bd2865e141f749a76a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 14:08:32 +0100 Subject: ARM: tegra: Fix I2C mux reset GPIO reference on Cardhu Use the correct "reset-gpios" property for the I2C mux reset GPIO reference instead of the deprecated "reset-gpio" property. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 12e185846dcb..c2a56eb0b9fa 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -210,7 +210,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; - reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; }; }; -- cgit v1.2.3 From c6e331a2bb0696075d28810e1afd5c35658c240e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Dec 2021 13:49:02 +0100 Subject: ARM: tegra: Avoid phandle indirection on Ouya Move the default state pinmux definition into the pinmux node. There's no need for the indirection via the phandle. Note that the phandle indirection is kept for the EMC operating performance point tables because they reference nodes that are defined in an external file. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-ouya.dts | 8912 +++++++++++++++++++----------------- 1 file changed, 4590 insertions(+), 4322 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 9a774500cb88..b28c5504e1b1 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -75,4450 +75,4718 @@ pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; + state_default: pinmux { - /* located at $state_default below */ - }; - }; + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - uartc: serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - /delete-property/ reg-shift; - status = "okay"; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - nvidia,adjust-baud-rates = <0 9600 100>, - <9600 115200 200>, - <1000000 4000000 136>; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - /* Azurewave AW-NH660 BCM4330B1 */ - bluetooth { - compatible = "brcm,bcm4330-bt"; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wakeup"; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - max-speed = <4000000>; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "txco"; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vbat-supply = <&sys_3v3_reg>; - vddio-supply = <&vdd_1v8>; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - }; - }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - uartd: serial@70006300 { - status = "okay"; - }; + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - cpu_temp: nct1008@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&sys_3v3_reg>; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - interrupt-parent = <&gpio>; - interrupts = ; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - #thermal-sensor-cells = <1>; - }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - pmic: pmic@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - wakeup-source; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>; - ti,system-power-controller; - ti,sleep-keep-ck32k; - ti,sleep-enable; + lcd_pwr1_pc1 { + nvidia,pins = "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - #gpio-cells = <2>; - gpio-controller; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vcc1-supply = <&vdd_5v0_reg>; - vcc2-supply = <&vdd_5v0_reg>; - vcc3-supply = <&vdd_1v8>; - vcc4-supply = <&vdd_5v0_reg>; - vcc5-supply = <&vdd_5v0_reg>; - vcc6-supply = <&vdd2_reg>; - vcc7-supply = <&vdd_5v0_reg>; - vccio-supply = <&vdd_5v0_reg>; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - regulators { - vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; - vdd2_reg: vdd2 { - regulator-name = "vdd_1v5_gen"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; - vdd_cpu: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1270000>; - regulator-coupled-with = <&vdd_core>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-always-on; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - nvidia,tegra-cpu-regulator; - }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vdd_1v8: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo1_reg: ldo1 { - regulator-name = "vdd_pexa,vdd_pexb"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; + sdmmc3_dat4_pd1 { + nvidia,pins = "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo2_reg: ldo2 { - regulator-name = "vdd_sata,avdd_plle"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - /* LDO3 is not connected to anything */ + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; + sdmmc3_dat7_pd4 { + nvidia,pins = "sdmmc3_dat7_pd4"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo5_reg: ldo5 { - regulator-name = "vddio_sdmmc,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo6_reg: ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo7_reg: ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; + vi_hsync_pd7 { + nvidia,pins = "vi_hsync_pd7"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; + lcd_d0_pe0 { + nvidia,pins = "lcd_d0_pe0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; - }; - vdd_core: tps62361@60 { - compatible = "ti,tps62361"; - reg = <0x60>; + lcd_d1_pe1 { + nvidia,pins = "lcd_d1_pe1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - regulator-name = "vdd_core"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-coupled-with = <&vdd_cpu>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - ti,enable-vout-discharge; + lcd_d2_pe2 { + nvidia,pins = "lcd_d2_pe2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - nvidia,tegra-core-regulator; - }; - }; + lcd_d3_pe3 { + nvidia,pins = "lcd_d3_pe3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; + lcd_d4_pe4 { + nvidia,pins = "lcd_d4_pe4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - mc_timings: memory-controller@7000f000 { - /* timings located at &mc_timings below */ - }; + lcd_d5_pe5 { + nvidia,pins = "lcd_d5_pe5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - emc_timings: memory-controller@7000f400 { - /* timings located at &emc_timings below */ - }; + lcd_d6_pe6 { + nvidia,pins = "lcd_d6_pe6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - hda@70030000 { - status = "okay"; - }; + lcd_d7_pe7 { + nvidia,pins = "lcd_d7_pe7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; + lcd_d8_pf0 { + nvidia,pins = "lcd_d8_pf0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; + lcd_d9_pf1 { + nvidia,pins = "lcd_d9_pf1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; + lcd_d10_pf2 { + nvidia,pins = "lcd_d10_pf2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - sdmmc3: mmc@78000400 { - status = "okay"; + lcd_d11_pf3 { + nvidia,pins = "lcd_d11_pf3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - #address-cells = <1>; - #size-cells = <0>; + lcd_d12_pf4 { + nvidia,pins = "lcd_d12_pf4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; - assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; - assigned-clock-rates = <50000000>; + lcd_d13_pf5 { + nvidia,pins = "lcd_d13_pf5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - max-frequency = <50000000>; - keep-power-in-suspend; + lcd_d14_pf6 { + nvidia,pins = "lcd_d14_pf6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - bus-width = <4>; - non-removable; + lcd_d15_pf7 { + nvidia,pins = "lcd_d15_pf7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - mmc-pwrseq = <&wifi_pwrseq>; - vmmc-supply = <&sdmmc_3v3_reg>; - vqmmc-supply = <&vdd_1v8>; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - /* Azurewave AW-NH660 BCM4330 */ - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wake"; - }; - }; + gmi_ad1_pg1 { + nvidia,pins = "gmi_ad1_pg1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - sdmmc4: mmc@78000600 { - status = "okay"; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - keep-power-in-suspend; - bus-width = <8>; - non-removable; - vmmc-supply = <&sys_3v3_reg>; - vqmmc-supply = <&vdd_1v8>; - nvidia,default-tap = <0x0F>; - max-frequency = <25500000>; - }; + gmi_ad3_pg3 { + nvidia,pins = "gmi_ad3_pg3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb@7d000000 { - compatible = "nvidia,tegra30-udc"; - status = "okay"; - }; + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb-phy@7d000000 { - status = "okay"; - dr_mode = "peripheral"; - }; + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb@7d004000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - smsc@2 { /* SMSC 10/100T Ethernet Controller */ - compatible = "usb424,9e00"; - reg = <2>; - local-mac-address = [00 11 22 33 44 55]; - }; - }; + gmi_ad7_pg7 { + nvidia,pins = "gmi_ad7_pg7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb-phy@7d004000 { - vbus-supply = <&vdd_smsc>; - status = "okay"; - }; + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb@7d008000 { - status = "okay"; - }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb-phy@7d008000 { - vbus-supply = <&usb3_vbus_reg>; - status = "okay"; - }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic-oscillator"; - }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - cpus { - cpu0: cpu@0 { - operating-points-v2 = <&cpu0_opp_table>; - cpu-supply = <&vdd_cpu>; - #cooling-cells = <2>; - }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - cpu1: cpu@1 { - operating-points-v2 = <&cpu0_opp_table>; - cpu-supply = <&vdd_cpu>; - #cooling-cells = <2>; - }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - cpu2: cpu@2 { - operating-points-v2 = <&cpu0_opp_table>; - cpu-supply = <&vdd_cpu>; - #cooling-cells = <2>; - }; + gmi_ad14_ph6 { + nvidia,pins = "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - cpu3: cpu@3 { - operating-points-v2 = <&cpu0_opp_table>; - cpu-supply = <&vdd_cpu>; - #cooling-cells = <2>; - }; - }; + gmi_wr_n_pi0 { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <0x0>; - tlm,version-minor = <0x0>; - }; - }; + gmi_oe_n_pi1 { + nvidia,pins = "gmi_oe_n_pi1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - fan: gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 4500 1>; - #cooling-cells = <2>; - }; + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <5000>; - polling-delay-passive = <5000>; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - thermal-sensors = <&cpu_temp 1>; + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - trips { - cpu_alert0: cpu-alert0 { - temperature = <50000>; - hysteresis = <10000>; - type = "active"; - }; - cpu_alert1: cpu-alert1 { - temperature = <70000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; + lcd_de_pj1 { + nvidia,pins = "lcd_de_pj1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; - }; - }; - vdd_12v_in: vdd_12v_in { - compatible = "regulator-fixed"; - regulator-name = "vdd_12v_in"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; + gmi_cs1_n_pj2 { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - sdmmc_3v3_reg: sdmmc_3v3_reg { - compatible = "regulator-fixed"; - regulator-name = "sdmmc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + lcd_hsync_pj3 { + nvidia,pins = "lcd_hsync_pj3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vdd_fuse_3v3_reg: vdd_fuse_3v3_reg { - compatible = "regulator-fixed"; - regulator-name = "vdd_fuse_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - regulator-always-on; - }; + lcd_vsync_pj4 { + nvidia,pins = "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vdd_vid_reg: vdd_vid_reg { - compatible = "regulator-fixed"; - regulator-name = "vddio_vid"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v0_reg>; - regulator-boot-on; - }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - ddr_reg: ddr_reg { - compatible = "regulator-fixed"; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - vin-supply = <&vdd_12v_in>; - }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - sys_3v3_reg: sys_3v3_reg { - compatible = "regulator-fixed"; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_12v_in>; - }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vdd_5v0_reg: vdd_5v0_reg { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_12v_in>; - }; + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - vdd_smsc: vdd_smsc { - compatible = "regulator-fixed"; - regulator-name = "vdd_smsc"; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; - }; + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - usb3_vbus_reg: usb3_vbus_reg { - compatible = "regulator-fixed"; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v0_reg>; - }; + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - gpio-keys { - compatible = "gpio-keys"; + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - power { - gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - debounce-interval = <10>; - linux,code = ; - wakeup-event-action = ; - wakeup-source; - }; - }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - leds { - compatible = "gpio-leds"; + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; - led-power { - label = "power-led"; - gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - retain-state-suspended; - }; - }; -}; -&mc_timings { - emc-timings-0 { - nvidia,ram-code = <0>; /* Samsung RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emem-configuration = < - 0x00030003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75830303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emem-configuration = < - 0x00010003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74630303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x00000006 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emem-configuration = < - 0x0000000c /* MC_EMEM_ARB_CFG */ - 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7086120a /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emem-configuration = < - 0x00000018 /* MC_EMEM_ARB_CFG */ - 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x712c2414 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - emc-timings-1 { - nvidia,ram-code = <1>; /* Hynix M RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emem-configuration = < - 0x00030003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75830303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emem-configuration = < - 0x00010003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74630303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x00000006 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emem-configuration = < - 0x0000000c /* MC_EMEM_ARB_CFG */ - 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7086120a /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emem-configuration = < - 0x00000018 /* MC_EMEM_ARB_CFG */ - 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x712c2414 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - emc-timings-2 { - nvidia,ram-code = <2>; /* Hynix A RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emem-configuration = < - 0x00030003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75e30303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emem-configuration = < - 0x00010003 /* MC_EMEM_ARB_CFG */ - 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x74e30303 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emem-configuration = < - 0x00000003 /* MC_EMEM_ARB_CFG */ - 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x74430504 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emem-configuration = < - 0x00000006 /* MC_EMEM_ARB_CFG */ - 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ - 0x74040a06 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emem-configuration = < - 0x0000000c /* MC_EMEM_ARB_CFG */ - 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7086120a /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emem-configuration = < - 0x00000018 /* MC_EMEM_ARB_CFG */ - 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x712c2414 /* MC_EMEM_ARB_MISC0 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; -}; -&emc_timings { - emc-timings-0 { - nvidia,ram-code = <0>; /* Samsung RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000006 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000007 /* EMC_TXSR */ - 0x00000007 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x0000000d /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000e /* EMC_TXSR */ - 0x0000000e /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000066 /* EMC_RFC */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x00000bf0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000010 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c30 /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x001d0084 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000ce /* EMC_RFC */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000004 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001820 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000012 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000020 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000007 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001860 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf0070191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000800a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f0000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; - }; - }; - emc-timings-1 { - nvidia,ram-code = <1>; /* Hynix M RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000006 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000007 /* EMC_TXSR */ - 0x00000007 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x0000000d /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000e /* EMC_TXSR */ - 0x0000000e /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000066 /* EMC_RFC */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x00000bf0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000010 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c30 /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x001d0084 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ - 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000ce /* EMC_RFC */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000004 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001820 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000012 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000020 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000007 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001860 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf0070191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000800a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f0000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; + vi_d2_pl0 { + nvidia,pins = "vi_d2_pl0"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d3_pl1 { + nvidia,pins = "vi_d3_pl1"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d5_pl3 { + nvidia,pins = "vi_d5_pl3"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d7_pl5 { + nvidia,pins = "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d9_pl7 { + nvidia,pins = "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d16_pm0 { + nvidia,pins = "lcd_d16_pm0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d17_pm1 { + nvidia,pins = "lcd_d17_pm1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d18_pm2 { + nvidia,pins = "lcd_d18_pm2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d19_pm3 { + nvidia,pins = "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d20_pm4 { + nvidia,pins = "lcd_d20_pm4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d21_pm5 { + nvidia,pins = "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d22_pm6 { + nvidia,pins = "lcd_d22_pm6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d23_pm7 { + nvidia,pins = "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sdout_pn5 { + nvidia,pins = "lcd_sdout_pn5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_dc0_pn6 { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d0_pt4 { + nvidia,pins = "vi_d0_pt4"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "clk_12m_out"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs1_n_pw0 { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_m1_pw1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_cs0_n_px6 { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sdin_pz2 { + nvidia,pins = "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sck_pz4 { + nvidia,pins = "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_prsnt_n_pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_prsnt_n_pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_groups { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; }; }; - emc-timings-2 { - nvidia,ram-code = <2>; /* Hynix A RAM */ - timing-25500000 { - clock-frequency = <25500000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x00000007 /* EMC_RFC */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x000000c0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000008 /* EMC_TXSR */ - 0x00000008 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000002 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000c7 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-51000000 { - clock-frequency = <51000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000002 /* EMC_RC */ - 0x0000000f /* EMC_RFC */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000181 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000010 /* EMC_TXSR */ - 0x00000010 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000018e /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001e /* EMC_RFC */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000303 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000020 /* EMC_TXSR */ - 0x00000020 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x007800a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00000000 /* EMC_ZCAL_INTERVAL */ - 0x00000040 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-cfg-dyn-self-ref; - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x0000003d /* EMC_RFC */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000002 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000b /* EMC_RDV */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000040 /* EMC_TXSR */ - 0x00000040 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000006 /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00004288 /* EMC_FBIO_CFG5 */ - 0x004400a4 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00080000 /* EMC_DLL_XFORM_DQS0 */ - 0x00080000 /* EMC_DLL_XFORM_DQS1 */ - 0x00080000 /* EMC_DLL_XFORM_DQS2 */ - 0x00080000 /* EMC_DLL_XFORM_DQS3 */ - 0x00080000 /* EMC_DLL_XFORM_DQS4 */ - 0x00080000 /* EMC_DLL_XFORM_DQS5 */ - 0x00080000 /* EMC_DLL_XFORM_DQS6 */ - 0x00080000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800211c /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f108 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168 /* EMC_XM2QUSEPADCTRL */ - 0x08000000 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff00 /* EMC_CFG_RSV */ - >; - }; - timing-400000000 { - clock-frequency = <400000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000076 /* EMC_RFC */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000003 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000004 /* EMC_WDV */ - 0x00000006 /* EMC_QUSE */ - 0x00000004 /* EMC_QRST */ - 0x0000000a /* EMC_QSAFE */ - 0x0000000c /* EMC_RDV */ - 0x00000bf0 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000007c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000010 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000004 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c30 /* EMC_TREFBW */ - 0x00000000 /* EMC_QUSE_EXTRA */ - 0x00000004 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00007088 /* EMC_FBIO_CFG5 */ - 0x001d0084 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00044000 /* EMC_DLL_XFORM_DQS0 */ - 0x00044000 /* EMC_DLL_XFORM_DQS1 */ - 0x00044000 /* EMC_DLL_XFORM_DQS2 */ - 0x00044000 /* EMC_DLL_XFORM_DQS3 */ - 0x00044000 /* EMC_DLL_XFORM_DQS4 */ - 0x00044000 /* EMC_DLL_XFORM_DQS5 */ - 0x00044000 /* EMC_DLL_XFORM_DQS6 */ - 0x00044000 /* EMC_DLL_XFORM_DQS7 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00058000 /* EMC_DLL_XFORM_DQ0 */ - 0x00058000 /* EMC_DLL_XFORM_DQ1 */ - 0x00058000 /* EMC_DLL_XFORM_DQ2 */ - 0x00058000 /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0800013d /* EMC_XM2DQSPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f508 /* EMC_XM2COMPPADCTRL */ - 0x05057404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x08000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0148000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff89 /* EMC_CFG_RSV */ - >; - }; - timing-800000000 { - clock-frequency = <800000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-zcal-cnt-long = <0x00000040>; - nvidia,emc-cfg-periodic-qrst; - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000ee /* EMC_RFC */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000001 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000007 /* EMC_WDV */ - 0x0000000a /* EMC_QUSE */ - 0x00000009 /* EMC_QRST */ - 0x0000000b /* EMC_QSAFE */ - 0x00000011 /* EMC_RDV */ - 0x00001820 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000012 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000f8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000020 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000007 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001860 /* EMC_TREFBW */ - 0x0000000b /* EMC_QUSE_EXTRA */ - 0x00000006 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x00005088 /* EMC_FBIO_CFG5 */ - 0xf0070191 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000c /* EMC_DLL_XFORM_DQS0 */ - 0x007fc00a /* EMC_DLL_XFORM_DQS1 */ - 0x00000008 /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000c /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0 /* EMC_XM2CMDPADCTRL */ - 0x0600013d /* EMC_XM2DQSPADCTRL2 */ - 0x22220000 /* EMC_XM2DQPADCTRL2 */ - 0x77fff884 /* EMC_XM2CLKPADCTRL */ - 0x01f1f501 /* EMC_XM2COMPPADCTRL */ - 0x07077404 /* EMC_XM2VTTGENPADCTRL */ - 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x080001e8 /* EMC_XM2QUSEPADCTRL */ - 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ - 0x00000802 /* EMC_CTT_TERM_CTRL */ - 0x00020000 /* EMC_ZCAL_INTERVAL */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00d0000c /* EMC_MRS_WAIT_CNT */ - 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ - 0x00000000 /* EMC_CTT */ - 0x00000000 /* EMC_CTT_DURATION */ - 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ - 0xe8000000 /* EMC_FBIO_SPARE */ - 0xff00ff49 /* EMC_CFG_RSV */ - >; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* Azurewave AW-NH660 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + vbat-supply = <&sys_3v3_reg>; + vddio-supply = <&vdd_1v8>; + + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; }; }; -}; -&state_default { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr0_pb2 { - nvidia,pins = "lcd_pwr0_pb2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pclk_pb3 { - nvidia,pins = "lcd_pclk_pb3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr1_pc1 { - nvidia,pins = "lcd_pwr1_pc1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat5_pd0 { - nvidia,pins = "sdmmc3_dat5_pd0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat4_pd1 { - nvidia,pins = "sdmmc3_dat4_pd1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_dc1_pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat6_pd3 { - nvidia,pins = "sdmmc3_dat6_pd3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat7_pd4 { - nvidia,pins = "sdmmc3_dat7_pd4"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d1_pd5 { - nvidia,pins = "vi_d1_pd5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_vsync_pd6 { - nvidia,pins = "vi_vsync_pd6"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_hsync_pd7 { - nvidia,pins = "vi_hsync_pd7"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d0_pe0 { - nvidia,pins = "lcd_d0_pe0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d1_pe1 { - nvidia,pins = "lcd_d1_pe1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d2_pe2 { - nvidia,pins = "lcd_d2_pe2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d3_pe3 { - nvidia,pins = "lcd_d3_pe3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d4_pe4 { - nvidia,pins = "lcd_d4_pe4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d5_pe5 { - nvidia,pins = "lcd_d5_pe5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d6_pe6 { - nvidia,pins = "lcd_d6_pe6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d7_pe7 { - nvidia,pins = "lcd_d7_pe7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d8_pf0 { - nvidia,pins = "lcd_d8_pf0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d9_pf1 { - nvidia,pins = "lcd_d9_pf1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d10_pf2 { - nvidia,pins = "lcd_d10_pf2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d11_pf3 { - nvidia,pins = "lcd_d11_pf3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d12_pf4 { - nvidia,pins = "lcd_d12_pf4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d13_pf5 { - nvidia,pins = "lcd_d13_pf5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d14_pf6 { - nvidia,pins = "lcd_d14_pf6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d15_pf7 { - nvidia,pins = "lcd_d15_pf7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad1_pg1 { - nvidia,pins = "gmi_ad1_pg1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad3_pg3 { - nvidia,pins = "gmi_ad3_pg3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad4_pg4 { - nvidia,pins = "gmi_ad4_pg4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_dqs_pi2 { - nvidia,pins = "gmi_dqs_pi2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wait_pi7 { - nvidia,pins = "gmi_wait_pi7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_de_pj1 { - nvidia,pins = "lcd_de_pj1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_hsync_pj3 { - nvidia,pins = "lcd_hsync_pj3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_vsync_pj4 { - nvidia,pins = "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d2_pl0 { - nvidia,pins = "vi_d2_pl0"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d3_pl1 { - nvidia,pins = "vi_d3_pl1"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d4_pl2 { - nvidia,pins = "vi_d4_pl2"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d5_pl3 { - nvidia,pins = "vi_d5_pl3"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d6_pl4 { - nvidia,pins = "vi_d6_pl4"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d7_pl5 { - nvidia,pins = "vi_d7_pl5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d8_pl6 { - nvidia,pins = "vi_d8_pl6"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d9_pl7 { - nvidia,pins = "vi_d9_pl7"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d16_pm0 { - nvidia,pins = "lcd_d16_pm0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d17_pm1 { - nvidia,pins = "lcd_d17_pm1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d18_pm2 { - nvidia,pins = "lcd_d18_pm2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d19_pm3 { - nvidia,pins = "lcd_d19_pm3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d20_pm4 { - nvidia,pins = "lcd_d20_pm4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d21_pm5 { - nvidia,pins = "lcd_d21_pm5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d22_pm6 { - nvidia,pins = "lcd_d22_pm6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d23_pm7 { - nvidia,pins = "lcd_d23_pm7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_cs0_n_pn4 { - nvidia,pins = "lcd_cs0_n_pn4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sdout_pn5 { - nvidia,pins = "lcd_sdout_pn5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_dc0_pn6 { - nvidia,pins = "lcd_dc0_pn6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_pclk_pt0 { - nvidia,pins = "vi_pclk_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_mclk_pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d10_pt2 { - nvidia,pins = "vi_d10_pt2"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d11_pt3 { - nvidia,pins = "vi_d11_pt3"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d0_pt4 { - nvidia,pins = "vi_d0_pt4"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck_pu7 { - nvidia,pins = "jtag_rtck_pu7"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "clk_12m_out"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_hsync_pv6 { - nvidia,pins = "crt_hsync_pv6"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_vsync_pv7 { - nvidia,pins = "crt_vsync_pv7"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_cs1_n_pw0 { - nvidia,pins = "lcd_cs1_n_pw0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_m1_pw1 { - nvidia,pins = "lcd_m1_pw1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_cs1_n_pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_sck_px2 { - nvidia,pins = "spi2_sck_px2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_mosi_px4 { - nvidia,pins = "spi1_mosi_px4"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_sck_px5 { - nvidia,pins = "spi1_sck_px5"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_cs0_n_px6 { - nvidia,pins = "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_miso_px7 { - nvidia,pins = "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sdin_pz2 { - nvidia,pins = "lcd_sdin_pz2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_wr_n_pz3 { - nvidia,pins = "lcd_wr_n_pz3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sck_pz4 { - nvidia,pins = "lcd_sck_pz4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; + + uartd: serial@70006300 { + status = "okay"; }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + cpu_temp: nct1008@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&sys_3v3_reg>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_reg>; + vcc2-supply = <&vdd_5v0_reg>; + vcc3-supply = <&vdd_1v8>; + vcc4-supply = <&vdd_5v0_reg>; + vcc5-supply = <&vdd_5v0_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_5v0_reg>; + vccio-supply = <&vdd_5v0_reg>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1270000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + vdd_core: tps62361@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + ti,enable-vout-discharge; + + nvidia,tegra-core-regulator; + }; }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; + + memory-controller@7000f000 { + emc-timings-0 { + nvidia,ram-code = <0>; /* Samsung RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix M RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-2 { + nvidia,ram-code = <2>; /* Hynix A RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75e30303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74e30303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x74430504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x74040a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + memory-controller@7000f400 { + emc-timings-0 { + nvidia,ram-code = <0>; /* Samsung RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000006 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000007 /* EMC_TXSR */ + 0x00000007 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000d /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000e /* EMC_TXSR */ + 0x0000000e /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000066 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ce /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix M RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000006 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000007 /* EMC_TXSR */ + 0x00000007 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000d /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000e /* EMC_TXSR */ + 0x0000000e /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000066 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ce /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + + emc-timings-2 { + nvidia,ram-code = <2>; /* Hynix A RAM */ + + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000007 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000008 /* EMC_TXSR */ + 0x00000008 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000f /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000010 /* EMC_TXSR */ + 0x00000010 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001e /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000020 /* EMC_TXSR */ + 0x00000020 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x0000003d /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000040 /* EMC_TXSR */ + 0x00000040 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000076 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000007c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00044000 /* EMC_DLL_XFORM_DQS0 */ + 0x00044000 /* EMC_DLL_XFORM_DQS1 */ + 0x00044000 /* EMC_DLL_XFORM_DQS2 */ + 0x00044000 /* EMC_DLL_XFORM_DQS3 */ + 0x00044000 /* EMC_DLL_XFORM_DQS4 */ + 0x00044000 /* EMC_DLL_XFORM_DQS5 */ + 0x00044000 /* EMC_DLL_XFORM_DQS6 */ + 0x00044000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00058000 /* EMC_DLL_XFORM_DQ0 */ + 0x00058000 /* EMC_DLL_XFORM_DQ1 */ + 0x00058000 /* EMC_DLL_XFORM_DQ2 */ + 0x00058000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0148000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ee /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000f8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000c /* EMC_DLL_XFORM_DQS0 */ + 0x007fc00a /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00d0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + hda@70030000 { + status = "okay"; }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + sdmmc3: mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&wifi_pwrseq>; + vmmc-supply = <&sdmmc_3v3_reg>; + vqmmc-supply = <&vdd_1v8>; + + /* Azurewave AW-NH660 BCM4330 */ + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + sdmmc4: mmc@78000600 { + status = "okay"; + + keep-power-in-suspend; + bus-width = <8>; + non-removable; + vmmc-supply = <&sys_3v3_reg>; + vqmmc-supply = <&vdd_1v8>; + nvidia,default-tap = <0x0F>; + max-frequency = <25500000>; }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + usb@7d004000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + smsc@2 { /* SMSC 10/100T Ethernet Controller */ + compatible = "usb424,9e00"; + reg = <2>; + local-mac-address = [00 11 22 33 44 55]; + }; }; - sdmmc4_rst_n_pcc3 { - nvidia,pins = "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; + + usb-phy@7d004000 { + vbus-supply = <&vdd_smsc>; + status = "okay"; }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,io-reset = ; + + usb@7d008000 { + status = "okay"; }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + usb-phy@7d008000 { + vbus-supply = <&usb3_vbus_reg>; + status = "okay"; }; - pex_l2_rst_n_pcc6 { - nvidia,pins = "pex_l2_rst_n_pcc6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; }; - pex_l2_clkreq_n_pcc7 { - nvidia,pins = "pex_l2_clkreq_n_pcc7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; }; - pex_l0_prsnt_n_pdd0 { - nvidia,pins = "pex_l0_prsnt_n_pdd0"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + fan: gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 4500 1>; + #cooling-cells = <2>; }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay = <5000>; + polling-delay-passive = <5000>; + + thermal-sensors = <&cpu_temp 1>; + + trips { + cpu_alert0: cpu-alert0 { + temperature = <50000>; + hysteresis = <10000>; + type = "active"; + }; + cpu_alert1: cpu-alert1 { + temperature = <70000>; + hysteresis = <5000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + vdd_12v_in: vdd_12v_in { + compatible = "regulator-fixed"; + regulator-name = "vdd_12v_in"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; }; - pex_l1_prsnt_n_pdd4 { - nvidia,pins = "pex_l1_prsnt_n_pdd4"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + sdmmc_3v3_reg: sdmmc_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "sdmmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + vdd_fuse_3v3_reg: vdd_fuse_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + regulator-always-on; }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + vdd_vid_reg: vdd_vid_reg { + compatible = "regulator-fixed"; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v0_reg>; + regulator-boot-on; }; - pex_l2_prsnt_n_pdd7 { - nvidia,pins = "pex_l2_prsnt_n_pdd7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + ddr_reg: ddr_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + sys_3v3_reg: sys_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "dev3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + vdd_5v0_reg: vdd_5v0_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; }; - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + vdd_smsc: vdd_smsc { + compatible = "regulator-fixed"; + regulator-name = "vdd_smsc"; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; + + usb3_vbus_reg: usb3_vbus_reg { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v0_reg>; }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + + gpio-keys { + compatible = "gpio-keys"; + + power { + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; }; - drive_groups { - nvidia,pins = "drive_gma", - "drive_gmb", - "drive_gmc", - "drive_gmd"; - nvidia,pull-down-strength = <9>; - nvidia,pull-up-strength = <9>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; + + + leds { + compatible = "gpio-leds"; + + led-power { + label = "power-led"; + gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + retain-state-suspended; + }; }; }; -- cgit v1.2.3 From b405066bd3e04e9d0c34a25db85adf19c08274ef Mon Sep 17 00:00:00 2001 From: Nikola Milosavljevic Date: Sun, 12 Dec 2021 00:13:49 +0300 Subject: ARM: tegra: Add device-tree for ASUS Transformer EeePad TF101 Add device-tree for Tegra20-based ASUS Transformer EeePad TF101. Link: https://wiki.postmarketos.org/wiki/ASUS_Eee_Pad_Transformer_(asus-tf101) Co-developed-by: David Heidelberg Signed-off-by: David Heidelberg Co-developed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel Co-developed-by: Antoni Aloy Torrens Signed-off-by: Antoni Aloy Torrens Signed-off-by: Nikola Milosavljevic Co-developed-by: Dmitry Osipenko Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra20-asus-tf101.dts | 1280 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/tegra20.dtsi | 2 +- 3 files changed, 1282 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/tegra20-asus-tf101.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0de64f237cd8..f51edce19a60 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1304,6 +1304,7 @@ dtb-$(CONFIG_MACH_SUNIV) += \ suniv-f1c100s-licheepi-nano.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-acer-a500-picasso.dtb \ + tegra20-asus-tf101.dtb \ tegra20-harmony.dtb \ tegra20-colibri-eval-v3.dtb \ tegra20-colibri-iris.dtb \ diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts new file mode 100644 index 000000000000..020172ee7340 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts @@ -0,0 +1,1280 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include +#include + +#include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" +#include "tegra20-cpu-opp-microvolt.dtsi" + +/ { + model = "ASUS EeePad Transformer TF101"; + compatible = "asus,tf101", "nvidia,tegra20"; + chassis-type = "convertible"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* MicroSD */ + mmc2 = &sdmmc1; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@0 { + reg = <0x00000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@2ffe0000 { + compatible = "ramoops"; + reg = <0x2ffe0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + linux,cma@30000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x30000000 0x10000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port@0 { + lcd_output: endpoint { + remote-endpoint = <&lvds_encoder_input>; + bus-width = <18>; + }; + }; + }; + }; + + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + hdmi-supply = <&vdd_hdmi_en>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + gpio@6000d000 { + charging-enable-hog { + gpio-hog; + gpios = ; + output-low; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + + lm1 { + nvidia,pins = "lm1"; + nvidia,function = "rsvd3"; + }; + + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + + gpv { + nvidia,pins = "gpv", "slxa"; + nvidia,function = "pcie"; + }; + + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lpw0", + "lpw2", "lsc0", "lsc1", "lsck", "lsda", + "lspi", "lvp1", "lvs"; + nvidia,function = "displaya"; + }; + + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; + nvidia,function = "sdio3"; + }; + + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + + slxd { + nvidia,pins = "slxd"; + nvidia,function = "spdif"; + }; + + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "dap1", "dap4", + "dte", "ddc", "dtf", "gma", "gmc", + "gme", "gpu", "gpu7", "gpv", "i2cp", + "irrx", "irtx", "pta", "rm", "sdc", + "sdd", "slxc", "slxd", "slxk", "spdi", + "spdo", "uac", "uad", + "uda", "csus"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_ate { + nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd", + "owc", "spia", "spib", "spic", + "spid", "spie", "spig", "slxa"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + + conf_crtp { + nvidia,pins = "crtp", "spih"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_spif { + nvidia,pins = "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsck", "lsda", "lsdi", "lvp0"; + nvidia,tristate = ; + }; + + conf_kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "uaa", "uab", + "uca", "ucb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lsc1", "lspi", + "lvp1", "lvs", "pmc", "sdb"; + nvidia,tristate = ; + }; + + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_csus { + nvidia,pins = "drive_csus"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006040 { + compatible = "nvidia,tegra20-hsuart"; + /* GPS BCM4751 */ + }; + + serial@70006200 { + compatible = "nvidia,tegra20-hsuart"; + status = "okay"; + + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + /* PLLP 216MHz / 16 / 4 */ + max-speed = <3375000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_sys>; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + }; + }; + + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* Aichi AMI306 digital compass */ + magnetometer@e { + compatible = "asahi-kasei,ak8974"; + reg = <0xe>; + + avdd-supply = <&vdd_3v3_sys>; + dvdd-supply = <&vdd_1v8_sys>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0x83>; + micdet-delay = <100>; + + gpio-cfg = < + 0xffffffff /* don't touch */ + 0xffffffff /* don't touch */ + 0x00000000 /* Speaker-enable GPIO, output, low */ + 0x00000400 /* Mic bias current detect */ + 0xffffffff /* don't touch */ + >; + + AVDD-supply = <&vdd_1v8_sys>; + CPVDD-supply = <&vdd_1v8_sys>; + DBVDD-supply = <&vdd_1v8_sys>; + DCVDD-supply = <&vdd_1v8_sys>; + }; + + /* Atmel MXT1386 Touchscreen */ + touchscreen@5b { + compatible = "atmel,maxtouch"; + reg = <0x5b>; + + interrupt-parent = <&gpio>; + interrupts = ; + + reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + + atmel,wakeup-method = ; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + vlogic-supply = <&vdd_1v8_sys>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0xf>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_sys>; + vddio-supply = <&vdd_1v8_sys>; + + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c2: i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_sys>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + vdd_core: sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + }; + + vdd_cpu: sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; + regulator-coupled-with = <&vdd_core &rtc_vdd>; + regulator-coupled-max-spread = <550000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + rtc_vdd: ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&vdd_core &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-rtc-regulator; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + nct1008: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&vdd_3v3_sys>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <100>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + memory-controller@7000f400 { + nvidia,use-ram-code; + + emc-tables@3 { + reg = <0x3>; + + #address-cells = <1>; + #size-cells = <0>; + + lpddr2 { + compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; + revision-id1 = <1>; + density = <2048>; + io-width = <16>; + }; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dc010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e0 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; + + /* Peripheral USB via ASUS connector */ + usb@c5000000 { + compatible = "nvidia,tegra20-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@c5000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + /* Dock's USB port */ + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + vbus-supply = <&vdd_5v0_sys>; + }; + + sdmmc1: mmc@c8000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <40000000>; + + max-frequency = <40000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + + /* Azurewave AW-NH615 BCM4329B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc3: mmc@c8000400 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + sdmmc4: mmc@c8000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_3v3_sys>; + non-removable; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_3v3_sys>; + pwms = <&pwm 2 4000000>; + + brightness-levels = <7 255>; + num-interpolated-steps = <248>; + default-brightness-level = <20>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + dock-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; + wakeup-source; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + display-panel { + compatible = "panel-lvds"; + + /* AUO B101EW05 using custom timings */ + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; + power-supply = <&vdd_pnl_reg>; + + width-mm = <218>; + height-mm = <135>; + + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <71200000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <8>; + hback-porch = <18>; + hsync-len = <184>; + vsync-len = <3>; + vfront-porch = <4>; + vback-porch = <8>; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&lvds_encoder_output>; + }; + }; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&i2c2>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + smart-battery@b { + compatible = "ti,bq20z75", "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&mains>; + }; + }; + }; + + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + remote-endpoint = <&lcd_output>; + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + vdd_5v0_sys: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "pcie_vdd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + vdd_pnl_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_1v8_sys: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_vs"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_hdmi_en: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_hdmi_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "asus,tegra-audio-wm8903-tf101", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Asus EeePad Transformer WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,headset; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + thermal-zones { + /* + * NCT1008 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone is a simpler solution which prevents TF101 from + * getting too hot from a user's tactile perspective. + * The CPU zone is intended to protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 0>; + + trips { + trip0: skin-alert { + /* start throttling at 60C */ + temperature = <60000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 70C */ + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 1>; + + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + power-off-delay-us = <200>; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; +}; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9508248fd166..6f493a8a8a9f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -523,7 +523,7 @@ status = "disabled"; }; - i2c@7000c400 { + i2c2: i2c@7000c400 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c400 0x100>; interrupts = ; -- cgit v1.2.3 From 91ead34f47c907d931a1f6d396d7dfbbc068263a Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:50 +0300 Subject: ARM: tegra: Add common device-tree base for Tegra30 ASUS Transformers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add common DTSI for Tegra30 ASUS Transformers. It will be used by multiple device-trees of ASUS devices. The common part initially was born out of the ASUS TF300T tablet's device-tree that was created by Michał Mirosław. It was heavily reworked and improved by Svyatoslav Ryhel, Maxim Schwalm, Ion Agorria et al. [digetx@gmail.com: factored out common part into separate patch and wrote commit message] Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Co-developed-by: Michał Mirosław Signed-off-by: Michał Mirosław Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- .../boot/dts/tegra30-asus-transformer-common.dtsi | 1787 ++++++++++++++++++++ 1 file changed, 1787 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi new file mode 100644 index 000000000000..85b43a86a26d --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi @@ -0,0 +1,1787 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + chassis-type = "convertible"; + + aliases { + mmc0 = "/mmc@78000600"; /* eMMC */ + mmc1 = "/mmc@78000000"; /* uSD slot */ + mmc2 = "/mmc@78000400"; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + display0 = &lcd; + display1 = &hdmi; + + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@beb00000 { + compatible = "ramoops"; + reg = <0xbeb00000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; /* 2MB */ + no-map; + }; + }; + + host1x@50000000 { + hdmi: hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&hdmi_5v0_sys>; + pll-supply = <&vdd_1v8_vio>; + vdd-supply = <&vdd_3v3_sys>; + + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + }; + }; + + gpio@6000d000 { + init-lpm-in-hog { + gpio-hog; + gpios = , + ; + input; + }; + + init-lpm-out-hog { + gpio-hog; + gpios = , + ; + output-low; + }; + + usb-charge-limit-hog { + gpio-hog; + gpios = ; + output-high; + }; + }; + + vde@6001a000 { + assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; + assigned-clock-rates = <408000000>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cmd { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cd { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_wp { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_rst_n { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + /* I2C pinmux */ + gen1_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + gen2_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + ddc_i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + }; + + pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + hotplug_i2c { + nvidia,pins = "pu4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI pinmux */ + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + hdmi_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-B */ + uartb_txd_rts { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartb_rxd_cts { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-C */ + uartc_rxd_cts { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartc_txd_rts { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-D */ + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2S pinmux */ + dap_i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap_i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_dout { + nvidia,pins = "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap_i2s3 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Sensors pinmux */ + nct_irq { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Asus EC pinmux */ + ec_irqs { + nvidia,pins = "kb_row10_ps2", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ec_reqs { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Memory type bootstrap */ + mem_boostraps { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_wake_n_pdd3", + "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_dc0_pn6", + "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + blink { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC keys */ + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col1_pq1 { + nvidia,pins = "kb_row1_pr1", + "kb_row3_pr3", + "kb_row8_ps0", + "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row12_ps4", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs0_n_pj0 { + nvidia,pins = "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* GPIO keys pinmux */ + power_key { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vol_keys { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Bluetooth */ + bt_shutdown { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + bt_dev_wake { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + bt_host_wake { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_rst_n_pi4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Vibrator control */ + vibrator { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PWM pimnmux */ + pwm_0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pwm_2 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Spdif pinmux */ + spdif_out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5", + "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + /* Broadcom GPS BCM47511 */ + }; + + serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + bluetooth { + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_com>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + pwm@7000a000 { + status = "okay"; + }; + + lcd_ddc: i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000c500 { + status = "okay"; + + /* Aichi AMI306 digital compass */ + magnetometer@e { + compatible = "asahi-kasei,ak8974"; + reg = <0x0e>; + + avdd-supply = <&vdd_3v3_sys>; + dvdd-supply = <&vdd_1v8_vio>; + }; + + /* Dynaimage ambient light sensor */ + light-sensor@1c { + compatible = "dynaimage,al3010"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + vlogic-supply = <&vdd_1v8_vio>; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_vio>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <93750>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + + /* Texas Instruments TPS659110 PMIC */ + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_bat>; + vcc2-supply = <&vdd_5v0_bat>; + vcc3-supply = <&vdd_1v8_vio>; + vcc4-supply = <&vdd_5v0_sys>; + vcc5-supply = <&vdd_5v0_bat>; + vcc6-supply = <&vdd_3v3_sys>; + vcc7-supply = <&vdd_5v0_bat>; + vccio-supply = <&vdd_5v0_bat>; + + pmic-sleep-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + }; + + regulators { + /* VDD1 is not used by Transformers */ + + vddio_ddr: vdd2 { + regulator-name = "vddio_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <1>; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8_vio: vio { + regulator-name = "vdd_1v8_gen"; + /* FIXME: eMMC won't work, if set to 1.8 V */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + /* FIXME: Without this, voltage switching fails */ + regulator-always-on; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3100000>; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* LDO5 is not used by Transformers */ + + ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + ti,regulator-ext-sleep-control = <8>; + }; + }; + }; + + vdd_core: core-regulator@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,enable-vout-discharge; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + /* FIXME: LP1 doesn't work at the moment */ + nvidia,suspend-mode = <2>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x81>; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + i2s@70080400 { /* i2s1 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70080600 { /* i2s3 */ + status = "okay"; + }; + }; + + mmc@78000000 { + status = "okay"; + + /* FIXME: Full 208Mhz clock rate doesn't work reliably */ + max-frequency = <104000000>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + bus-width = <4>; + + vmmc-supply = <&vdd_usd>; /* ldo2 */ + vqmmc-supply = <&vddio_usd>; /* ldo3 */ + }; + + mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_com>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* Azurewave AW-NH615 BCM4329B1 or AW-NH665 BCM4330B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + mmc@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + mmc-ddr-3_3v; + non-removable; + }; + + /* USB via ASUS connector */ + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + /* Dock's USB port */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_5v0_bat>; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 4000000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <40>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu2: cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu3: cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + extcon-keys { + compatible = "gpio-keys"; + interrupt-parent = <&gpio>; + + dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; + wakeup-source; + }; + + lineout-detect { + label = "Audio dock line-out detect"; + gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + interrupt-parent = <&gpio>; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + vdd_5v0_bat: regulator-bat { + compatible = "regulator-fixed"; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_cp: regulator-sby { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_sby"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_5v0_sys: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_1v5_ddr: regulator-ddr { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_3v3_sys: regulator-3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_com: regulator-com { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_bat>; + }; + + hdmi_5v0_sys: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + sound { + nvidia,i2s-controller = <&tegra_i2s1>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,hp-mute-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * Transformers from getting too hot from a user's + * tactile perspective. The CPU zone is intended to + * protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 57C until temperature drops to 56.8C */ + temperature = <57000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 65C */ + temperature = <65000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 75C until temperature drops to 74.8C */ + temperature = <75000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; +}; -- cgit v1.2.3 From a0d7dba8c3c125692405ac3e2db0e9414952c14f Mon Sep 17 00:00:00 2001 From: Maxim Schwalm Date: Sun, 12 Dec 2021 00:13:51 +0300 Subject: ARM: tegra: Add common device-tree for LVDS display panels of Tegra30 ASUS tablets All Tegra30 ASUS tablets have a similar design pattern in terms of hardware integration of LVDS display panels, like exactly the same GPIOs are used for power and reset, etc. Add a common device-tree for LVDS display panels of Tegra30 ASUS tablets to avoid replicating the boilerplate panel description. [digetx@gmail.com: factored out common part into separate patch and wrote commit message] Co-developed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel Signed-off-by: Maxim Schwalm Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi | 61 ++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi new file mode 100644 index 000000000000..a047abfa6369 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */ + +/ { + host1x@50000000 { + lcd: dc@54200000 { + rgb { + status = "okay"; + + port@0 { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + display-panel { + power-supply = <&vdd_pnl>; + ddc-i2c-bus = <&lcd_ddc>; + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + + /* Texas Instruments SN75LVDS83B LVDS Transmitter */ + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; +}; -- cgit v1.2.3 From 9b66bd835dfd85efaf5f590f34230d1d75b446f9 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:52 +0300 Subject: ARM: tegra: Add device-tree for ASUS Transformer Prime TF201 Add device-tree for ASUS Transformer Prime TF201, which is a NVIDIA Tegra30-based 2-in-1 detachable, orignally running Android. Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Prime_(asus-tf201) Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-asus-tf201.dts | 627 +++++++++++++++++++++++++++++++ 2 files changed, 628 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-tf201.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f51edce19a60..fcc48f8aa3b4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1321,6 +1321,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-nexus7-grouper-PM269.dtb \ tegra30-asus-nexus7-grouper-E1565.dtb \ tegra30-asus-nexus7-tilapia-E1565.dtb \ + tegra30-asus-tf201.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-asus-tf201.dts b/arch/arm/boot/dts/tegra30-asus-tf201.dts new file mode 100644 index 000000000000..315c6dc068c5 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-tf201.dts @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Prime TF201"; + compatible = "asus,tf201", "nvidia,tegra30"; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Atmel MXT768E touchscreen */ + touchscreen@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + }; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + + magnetometer@e { + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0x80000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0x80000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0x80000048 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000006 + 0x00000001 0x00000000 0x00000004 0x00000004 + 0x04040001 0x000d090c 0x71c6120d 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* TF201 Unknown 1GB LPDDR2 500MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0x80000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0x80000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0x80000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-500000000 { + clock-frequency = <500000000>; + + nvidia,emem-configuration = < 0x00000007 0x8000005a + 0x00000003 0x00000004 0x0000000e 0x00000009 + 0x0000000c 0x00000002 0x00000002 0x00000008 + 0x00000001 0x00000000 0x00000004 0x00000005 + 0x05040001 0x00100a0e 0x71c8170f 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x00098000 0x00098000 0x00098000 + 0x00098000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x00098000 0x00098000 0x00098000 + 0x00098000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000018 0x00000018 0x00000018 + 0x00000018 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000a0000 0x000a0000 0x000a0000 + 0x000a0000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00120220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x00440084 + 0x00008000 0x00074000 0x00074000 0x00074000 + 0x00074000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000018 0x00000018 0x00000018 + 0x00000018 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00078000 0x00078000 0x00078000 + 0x00078000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010082>; + nvidia,emc-mode-2 = <0x00020004>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000024>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000017 + 0x00000033 0x00000010 0x00000007 0x00000007 + 0x00000007 0x00000002 0x0000000a 0x00000007 + 0x00000007 0x00000003 0x00000002 0x00000000 + 0x00000003 0x00000007 0x00000004 0x0000000d + 0x0000000e 0x000005e9 0x00000000 0x0000017a + 0x00000002 0x00000002 0x00000007 0x00000000 + 0x00000001 0x0000000c 0x00000038 0x00000038 + 0x00000006 0x00000014 0x00000009 0x00000004 + 0x00000002 0x00000680 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0x001d0084 + 0x00008000 0x0002c000 0x0002c000 0x0002c000 + 0x0002c000 0x00000010 0x00000010 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000c0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00000000 + 0x00000024 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; + }; + }; + + emc-timings-1 { + /* TF201 Unknown 1GB LPDDR2 500MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x00780084 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x00440084 + 0x00008000 0x00060000 0x00060000 0x00060000 + 0x00060000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000d0000 0x000d0000 0x000d0000 + 0x000d0000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-500000000 { + clock-frequency = <500000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020005>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000002d>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001d + 0x00000040 0x00000014 0x00000008 0x00000007 + 0x00000009 0x00000003 0x0000000d 0x00000008 + 0x00000008 0x00000004 0x00000002 0x00000000 + 0x00000004 0x00000008 0x00000005 0x0000000d + 0x0000000f 0x00000763 0x00000000 0x000001d8 + 0x00000003 0x00000003 0x00000008 0x00000000 + 0x00000001 0x0000000e 0x00000046 0x00000046 + 0x00000008 0x00000019 0x0000000b 0x00000004 + 0x00000002 0x00000820 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0xf0140091 + 0x00008000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x00080220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000b4 0x000d000d 0xa0f10404 0x00000000 + 0x00000000 0x80000fde 0xe0000000 0xff00ff88 >; + }; + }; + }; + + usb-phy@7d000000 { + /delete-property/ nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ + }; + + usb-phy@7d008000 { + /delete-property/ nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ + }; + + display-panel { + compatible = "hannstar,hsd101pww2"; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-533000000-1200; + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-533000000; + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; -- cgit v1.2.3 From 65fce832a97cb7ed3e4896475baabeb7f506de3b Mon Sep 17 00:00:00 2001 From: Michał Mirosław Date: Sun, 12 Dec 2021 00:13:53 +0300 Subject: ARM: tegra: Add device-tree for ASUS Transformer Pad TF300T MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device-tree for ASUS Transformer Pad TF300T, which is a NVIDIA Tegra30-based 2-in-1 detachable, originally running Android. Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(asus-tf300t) Tested-by: Ihor Didenko Tested-by: Andreas Westman Dorcsak Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Co-developed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel Signed-off-by: Michał Mirosław Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-asus-tf300t.dts | 1034 +++++++++++++++++++++++++++++ 2 files changed, 1035 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-tf300t.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index fcc48f8aa3b4..71ec43e72380 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1322,6 +1322,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-nexus7-grouper-E1565.dtb \ tegra30-asus-nexus7-tilapia-E1565.dtb \ tegra30-asus-tf201.dtb \ + tegra30-asus-tf300t.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/tegra30-asus-tf300t.dts new file mode 100644 index 000000000000..f47434871a5c --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-tf300t.dts @@ -0,0 +1,1034 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Pad TF300T"; + compatible = "asus,tf300t", "nvidia,tegra30"; + + gpio@6000d000 { + tf300t-init-hog { + gpio-hog; + gpios = ; + output-low; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech EKTH1036 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2240>; + touchscreen-size-y = <1408>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + + magnetometer@e { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Wolfson Microelectronics WM8903 audio codec */ + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + + gpio-cfg = < + 0xffffffff /* don't touch */ + 0xffffffff /* don't touch */ + 0x00000000 /* Speaker-enable GPIO, output, low */ + 0xffffffff /* don't touch */ + 0xffffffff /* don't touch */ + >; + + AVDD-supply = <&vdd_1v8_vio>; + CPVDD-supply = <&vdd_1v8_vio>; + DBVDD-supply = <&vdd_1v8_vio>; + DCVDD-supply = <&vdd_1v8_vio>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00030003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x0000000a 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x00000014 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00030003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010003 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0605 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x0000000a 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000005 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x00000014 0xc0000079 + 0x00000003 0x00000004 0x00000011 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00140b11 0x70ea1f12 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00140b10 0x70ea1f11 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x0f000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000003 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000b 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000020 + 0x0000006a 0x00000018 0x00000008 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x00000008 0x00000008 0x00000008 + 0x00000008 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0155000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x00000009 + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xd8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xd8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000016 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000008 + 0x00000008 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xf8000000 0xff00ff49 >; + }; + }; + }; + + display-panel { + compatible = "innolux,g101ice-l01"; + }; + + sound { + compatible = "asus,tegra-audio-wm8903-tf300t", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Asus Transformer Pad TF300T WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "IN1L", "Mic Jack", + "IN2L", "Mic Jack", + "DMICDAT", "Int Mic"; + + nvidia,audio-codec = <&wm8903>; + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,headset; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; -- cgit v1.2.3 From 2602de4800e6058f811b467b40e1cd16a21d0a30 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:54 +0300 Subject: ARM: tegra: Add device-tree for ASUS Transformer Pad TF300TG Add device-tree for ASUS Transformer Pad TF300TG, which is a NVIDIA Tegra30-based 2-in-1 detachable, originally running Android. It's a variant of the TF300T that has a 3G modem. Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(asus-tf300t) Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-asus-tf300tg.dts | 1087 ++++++++++++++++++++++++++++ 2 files changed, 1088 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-tf300tg.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 71ec43e72380..c957986f023c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1323,6 +1323,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-nexus7-tilapia-E1565.dtb \ tegra30-asus-tf201.dtb \ tegra30-asus-tf300t.dtb \ + tegra30-asus-tf300tg.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts new file mode 100644 index 000000000000..96345f821c3d --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts @@ -0,0 +1,1087 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Pad 3G TF300TG"; + compatible = "asus,tf300tg", "nvidia,tegra30"; + + gpio@6000d000 { + tf300tg-init-hog { + gpio-hog; + gpios = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + output-low; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,tristate = ; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech EKTH1036 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2240>; + touchscreen-size-y = <1408>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + + magnetometer@e { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0x8000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0x80000079 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00050000 0x00050000 0x00050000 + 0x00050000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0a00013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x0a000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000020 + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-2 { + /* Micron 1GB 667MHZ */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00040000 0x00040000 0x00040000 + 0x00040000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000016 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0600013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + }; + + display-panel { + compatible = "innolux,g101ice-l01"; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; -- cgit v1.2.3 From e6d391a0b29bd083dabc620534892f0d05707501 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:55 +0300 Subject: ARM: tegra: Add device-tree for ASUS Transformer Infinity TF700T Add device-tree for ASUS Transformer Infinity TF700T, which is a NVIDIA Tegra30-based 2-in-1 detachable, originally running Android. Link: https://wiki.postmarketos.org/wiki/Asus_Transformer_Pad_Infinity_TF700T_(asus-tf700t) Tested-by: Andreas Westman Dorcsak Tested-by: Jasper Korten Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Co-developed-by: Dmitry Osipenko Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-asus-tf700t.dts | 823 ++++++++++++++++++++++++++++++ 2 files changed, 824 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-asus-tf700t.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c957986f023c..47cd157496f9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1324,6 +1324,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-tf201.dtb \ tegra30-asus-tf300t.dtb \ tegra30-asus-tf300tg.dtb \ + tegra30-asus-tf700t.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/tegra30-asus-tf700t.dts new file mode 100644 index 000000000000..18a9bfa5e97b --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-tf700t.dts @@ -0,0 +1,823 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" + +/ { + model = "Asus Transformer Infinity TF700T"; + compatible = "asus,tf700t", "nvidia,tegra30"; + + host1x@50000000 { + lcd: dc@54200000 { + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + + rgb { + status = "okay"; + + port@0 { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH665 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech ELAN-3024-7053 or 5184N FPC-1 REV: 2/3 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2944>; + touchscreen-size-y = <1856>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + + magnetometer@e { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Micron 1GB 800MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x75830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74630303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000002 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x73c30504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000004 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x73840a06 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000007 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000d0709 0x7086120a 0x001f0000 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emem-configuration = < 0x0000000c 0xc0000090 + 0x00000004 0x00000005 0x00000013 0x0000000c + 0x0000000f 0x00000002 0x00000003 0x0000000c + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00160d13 0x712c2414 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Elpida 1GB 800MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x75830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74630303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000002 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x73c30504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000004 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x73840a06 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000007 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000d0709 0x7086120a 0x001f0000 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emem-configuration = < 0x0000000c 0xc0000090 + 0x00000004 0x00000005 0x00000013 0x0000000c + 0x0000000f 0x00000002 0x00000003 0x0000000c + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00160d13 0x712c2414 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Micron 1GB 800MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000006 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000007 0x00000007 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x0000000d 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000000e 0x0000000e + 0x00000004 0x00000003 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x0000001a 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000001c 0x0000001c + 0x00000004 0x00000005 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000035 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000038 0x00000038 + 0x00000004 0x00000009 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x00000012 + 0x00000066 0x0000000c 0x00000004 0x00000003 + 0x00000008 0x00000002 0x0000000a 0x00000004 + 0x00000004 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x00000bf0 0x00000000 0x000002fc + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000008 0x0000000f 0x0000006c 0x00000200 + 0x00000004 0x00000010 0x00000000 0x00000004 + 0x00000005 0x00000c30 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x001d0084 + 0x00008000 0x00044000 0x00044000 0x00044000 + 0x00044000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0600013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0158000c 0xa0f10000 0x00000000 + 0x00000000 0x800018c8 0xe8000000 0xff00ff89 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000025 + 0x000000ce 0x0000001a 0x00000009 0x00000005 + 0x0000000d 0x00000004 0x00000013 0x00000009 + 0x00000009 0x00000004 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001820 0x00000000 0x00000608 + 0x00000003 0x00000012 0x00000001 0x00000000 + 0x0000000f 0x00000018 0x000000d8 0x00000200 + 0x00000005 0x00000020 0x00000000 0x00000007 + 0x00000008 0x00001860 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf0070191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x00f0000c 0xa0f10000 0x00000000 + 0x00000000 0x8000308c 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Elpida 1GB 800MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000006 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000007 0x00000007 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x0000000d 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000000e 0x0000000e + 0x00000004 0x00000003 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000004 + 0x0000001a 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x0000001c 0x0000001c + 0x00000004 0x00000005 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000009 + 0x00000035 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000038 0x00000038 + 0x00000004 0x00000009 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x00000012 + 0x00000066 0x0000000c 0x00000004 0x00000003 + 0x00000008 0x00000002 0x0000000a 0x00000004 + 0x00000004 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x00000bf0 0x00000000 0x000002fc + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000008 0x0000000f 0x0000006c 0x00000200 + 0x00000004 0x00000010 0x00000000 0x00000004 + 0x00000005 0x00000c30 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x001d0084 + 0x00008000 0x00044000 0x00044000 0x00044000 + 0x00044000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0600013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0158000c 0xa0f10000 0x00000000 + 0x00000000 0x800018c8 0xe8000000 0xff00ff89 >; + }; + + timing-800000000 { + clock-frequency = <800000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000025 + 0x000000ce 0x0000001a 0x00000009 0x00000005 + 0x0000000d 0x00000004 0x00000013 0x00000009 + 0x00000009 0x00000004 0x00000001 0x00000000 + 0x00000007 0x0000000a 0x00000009 0x0000000a + 0x00000011 0x00001820 0x00000000 0x00000608 + 0x00000003 0x00000012 0x00000001 0x00000000 + 0x0000000f 0x00000018 0x000000d8 0x00000200 + 0x00000005 0x00000020 0x00000000 0x00000007 + 0x00000008 0x00001860 0x0000000b 0x00000006 + 0x00000000 0x00000000 0x00005088 0xf0070191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x000002a0 0x0a00013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x00f0000c 0xa0f10000 0x00000000 + 0x00000000 0x8000308c 0xe8000000 0xff00ff49 >; + }; + }; + }; + + tc358768_refclk: clock-tc358768 { + compatible = "fixed-clock"; + clock-frequency = <23100000>; + clock-accuracy = <100>; + #clock-cells = <0>; + }; + + tc358768_osc: clock-tc358768-osc-gate { + compatible = "gpio-gate-clock"; + enable-gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>; + clocks = <&tc358768_refclk>; + #clock-cells = <0>; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; + + i2c-mux { + compatible = "i2c-mux-gpio"; + + mux-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; + i2c-parent = <&lcd_ddc>; + idle-state = <0x0>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dsi-bridge@7 { + compatible = "toshiba,tc358768"; + reg = <0x7>; + + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&tc358768_osc>; + clock-names = "refclk"; + + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + + vddc-supply = <&vdd_1v2_mipi>; + vddio-supply = <&vdd_1v8_vio>; + vddmipi-supply = <&vdd_1v2_mipi>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + data-lines = <24>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + + /* + * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1 + * LCD SuperIPS+ Full HD panel. + */ + panel@1 { + compatible = "panasonic,vvx10f004b00"; + reg = <1>; + + power-supply = <&vdd_pnl>; + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + }; + }; + }; + + vdd_1v2_mipi: regulator-mipi { + compatible = "regulator-fixed"; + regulator-name = "tc358768_1v2_vdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <10000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-900000000; +}; -- cgit v1.2.3 From 2b69c7b5fd350754b524c3410563a8d0fc452f99 Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sun, 12 Dec 2021 00:13:56 +0300 Subject: ARM: tegra: Add device-tree for ASUS Transformer Pad TF701T Add device-tree for Tegra114-based ASUS Transformer Pad TF701T (K00C) tablet. Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(TF701T)_(asus-tf701t) Signed-off-by: Anton Bambura Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra114-asus-tf701t.dts | 807 +++++++++++++++++++++++++++++ arch/arm/boot/dts/tegra114.dtsi | 4 +- 3 files changed, 810 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/tegra114-asus-tf701t.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 47cd157496f9..faaeae1f2a58 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1331,6 +1331,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-colibri-eval-v3.dtb \ tegra30-ouya.dtb dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ + tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ tegra114-roth.dtb \ tegra114-tn7.dtb diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/tegra114-asus-tf701t.dts new file mode 100644 index 000000000000..b791ce97424b --- /dev/null +++ b/arch/arm/boot/dts/tegra114-asus-tf701t.dts @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include +#include + +#include "tegra114.dtsi" + +/ { + model = "Asus Transformer Pad TF701T"; + compatible = "asus,tf701t", "nvidia,tegra114"; + chassis-type = "convertible"; + + aliases { + mmc0 = "/mmc@78000600"; /* eMMC */ + mmc1 = "/mmc@78000400"; /* uSD slot */ + mmc2 = "/mmc@78000000"; /* WiFi */ + + rtc0 = &palmas; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; /* Console */ + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + memory@80000000 { + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; + linux,cma-default; + reusable; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; + no-map; + }; + }; + + host1x@50000000 { + dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&tps65913_ldo2>; + + nvidia,ganged-mode = <&dsib>; + + panel_primary: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + + link2 = <&panel_secondary>; + + power-supply = <&vdd_lcd>; + backlight = <&backlight>; + }; + }; + + dsi@54400000 { + status = "okay"; + + avdd-dsi-csi-supply = <&tps65913_ldo2>; + + panel_secondary: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + }; + }; + }; + + pinmux@70000868 { + asus_pad_ec_default: asus-pad-ec-default { + ec-interrupt { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ec-request { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + backlight_default: backlight-default { + backlight-enable { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + codec_default: codec-default { + ldo1-en { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + interrupt { + nvidia,pins = "gpio_w2_aud_pw2", + "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + gpio_keys_default: gpio-keys-default { + power { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + volume { + nvidia,pins = "kb_row1_pr1", + "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + gpio_hall_sensor_default: gpio-hall-sensor-default { + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + hp_det_default: hp-det-default { + gmi_iordy_pi5 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + imu_default: imu-default { + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + pwm_default: pwm-default { + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + /* XXX make this something more sensible */ + pwm_sleep: pwm-sleep { + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + sdmmc3_default: sdmmc3-default { + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "kb_col4_pq4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5", + "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + + sdmmc3_vdd_default: sdmmc3-vdd-default { + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + vdd_lcd_default: vdd-lcd-default { + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006040 { + /* GPS */ + }; + + serial@70006200 { + /* Bluetooth */ + }; + + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm_default>; + pinctrl-1 = <&pwm_sleep>; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + magnetometer@c { + compatible = "asahi-kasei,ak09911"; + reg = <0xc>; + + vdd-supply = <&vdd_3v3_sys>; + }; + + rt5639: audio-codec@1c { + compatible = "realtek,rt5639"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&codec_default>; + }; + + motion-tracker@68 { + compatible = "invensense,mpu6500"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + + pinctrl-names = "default"; + pinctrl-0 = <&imu_default>; + }; + + temp_sensor: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + }; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + light-sensor@1c { + compatible = "dynaimage,al3320a"; + reg = <0x1c>; + + vdd-supply = <&vdd_3v3_sys>; + }; + }; + + i2c@7000c700 { + /* HDMI DDC */ + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + palmas: pmic@58 { + compatible = "ti,tps65913", "ti,palmas"; + reg = <0x58>; + interrupts = ; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + + ldo1-in-supply = <&tps65913_smps7>; + ldo2-in-supply = <&tps65913_smps7>; + ldo4-in-supply = <&tps65913_smps8>; + ldo5-in-supply = <&tps65913_smps9>; + ldo6-in-supply = <&tps65913_smps9>; + ldo7-in-supply = <&tps65913_smps9>; + ldo9-in-supply = <&tps65913_smps9>; + + regulators { + tps65913_smps123: smps123 { + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <1>; + ti,mode-sleep = <3>; + }; + + tps65913_smps45: smps45 { + regulator-name = "vdd-core"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <3>; + }; + + smps6 { + regulator-name = "va-lcd-hv"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps7: smps7 { + regulator-name = "vdd-ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps8: smps8 { + regulator-name = "vdd-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps9: smps9 { + regulator-name = "vdd-sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + + tps65913_smps10_out1: smps10_out1 { + regulator-name = "vd-smps10-out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_smps10_out2: smps10_out2 { + regulator-name = "vd-smps10-out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + tps65913_ldo1: ldo1 { + regulator-name = "vdd-hdmi-pll"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + ti,roof-floor = <3>; + }; + + tps65913_ldo2: ldo2 { + regulator-name = "vdd-2v8-dsi-csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + ldo3 { + regulator-name = "vpp-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo4 { + regulator-name = "vdd-1v2-cam"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo5 { + regulator-name = "vdd-cam"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo6 { + regulator-name = "vdd-dev"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-boot-on; + }; + + ldo7 { + regulator-name = "vdd-2v8-cam"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + tps65913_ldo8: ldo8 { + regulator-name = "vdd-rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + ti,enable-ldo8-tracking; + }; + + tps65913_ldo9: ldo9 { + regulator-name = "vdd-sdmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + }; + + tps65913_ldoln: ldoln { + regulator-name = "vdd-hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldousb { + regulator-name = "vdd-usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 0>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_powergood { + pins = "powergood"; + function = "powergood"; + }; + + pin_vac { + pins = "vac"; + function = "vac"; + }; + + pin_gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "gpio"; + }; + + pin_gpio2 { + pins = "gpio2"; + function = "gpio"; + }; + + pin_gpio3 { + pins = "gpio3"; + function = "gpio"; + }; + + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + + pin_gpio5 { + pins = "gpio5"; + function = "gpio"; + }; + + pin_gpio6 { + pins = "gpio6"; + function = "gpio"; + }; + + pin_gpio7 { + pins = "gpio7"; + function = "gpio"; + }; + }; + }; + }; + }; + + ahub@70080000 { + i2s@70080300 { + status = "okay"; + }; + }; + + mmc@78000000 { + /* WiFi */ + }; + + /* MicroSD card */ + mmc@78000400 { + status = "okay"; + + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&tps65913_ldo9>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc3_default>; + }; + + mmc@78000600 { + /* eMMC */ + }; + + usb@7d000000 { + compatible = "nvidia,tegra114-udc"; + status = "okay"; + dr_mode = "peripheral"; + + /* Peripheral USB via ASUS connector */ + }; + + usb-phy@7d000000 { + status = "okay"; + }; + + usb@7d008000 { + status = "okay"; + + /* Host USB via dock */ + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_5v0_sys>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_sys>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <224>; + + pinctrl-names = "default"; + pinctrl-0 = <&backlight_default>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + label = "GPIO Buttons"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + label = "GPIO Hall Effect Sensor"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_hall_sensor_default>; + + hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + }; + + sound { + compatible = "asus,tegra-audio-rt5639-tf701t", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "Asus Transformer Pad TF701T RT5639"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL", + "Speakers", "SPORP", + "Speakers", "SPORN", + "Speakers", "SPOLP", + "Speakers", "SPOLN", + "Mic Jack", "MICBIAS1", + "IN2P", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s0>; + nvidia,audio-codec = <&rt5639>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA114_CLK_PLL_A>, + <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA114_CLK_EXTERN1>; + + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_default>; + }; + + vdd_5v0_sys: regulator-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: regulator-3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_lcd: regulator-vdd-lcd { + compatible = "regulator-fixed"; + regulator-name = "vdd_lcd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&tps65913_smps8>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + + pinctrl-names = "default"; + pinctrl-0 = <&vdd_lcd_default>; + }; + + vdd_usd: regulator-vdd-usd { + compatible = "regulator-fixed"; + regulator-name = "vdd_sd_slot"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + vin-supply = <&tps65913_smps9>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc3_vdd_default>; + }; +}; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index ce7410ee08b8..8b45f4617b2f 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -105,7 +105,7 @@ status = "disabled"; }; - dsi@54300000 { + dsia: dsi@54300000 { compatible = "nvidia,tegra114-dsi"; reg = <0x54300000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_DSIA>, @@ -121,7 +121,7 @@ #size-cells = <0>; }; - dsi@54400000 { + dsib: dsi@54400000 { compatible = "nvidia,tegra114-dsi"; reg = <0x54400000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_DSIB>, -- cgit v1.2.3 From 87d9cf2e846968c7ca8e2a3299e4fb93899bd7fc Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:57 +0300 Subject: ARM: tegra: Add device-tree for Pegatron Chagall Add device-tree for Pegatron Chagall, which is a NVIDIA Tegra30-based Android tablet. Link: https://wiki.postmarketos.org/wiki/Pegatron_Chagall_(pegatron-chagall) Co-developed-by: Raffaele Tranquillini Signed-off-by: Raffaele Tranquillini Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Co-developed-by: Maxim Schwalm Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko [treding@nvidia.com: cosmetic fixups] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/tegra30-pegatron-chagall.dts | 2859 ++++++++++++++++++++++++ 2 files changed, 2861 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/tegra30-pegatron-chagall.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faaeae1f2a58..8f93e9e65a7c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1329,7 +1329,8 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ tegra30-colibri-eval-v3.dtb \ - tegra30-ouya.dtb + tegra30-ouya.dtb \ + tegra30-pegatron-chagall.dtb dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts new file mode 100644 index 000000000000..f4b2d4218849 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts @@ -0,0 +1,2859 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Pegatron Chagall"; + compatible = "pegatron,chagall", "nvidia,tegra30"; + chassis-type = "tablet"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* uSD slot */ + mmc2 = &sdmmc3; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + display0 = &lcd; + display1 = &hdmi; + + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@beb00000 { + compatible = "ramoops"; + reg = <0xbeb00000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; /* 2MB */ + no-map; + }; + }; + + host1x@50000000 { + hdmi: hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&hdmi_5v0_sys>; + pll-supply = <&vdd_1v8_vio>; + vdd-supply = <&vdd_3v3_sys>; + + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + }; + }; + + vde@6001a000 { + assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; + assigned-clock-rates = <408000000>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_dat5_pd0", + "sdmmc3_dat4_pd1", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2C pinmux */ + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + }; + + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + /* HDMI-CEC pinmux */ + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = <0>; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-B */ + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-C */ + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-D */ + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2S pinmux */ + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2", + "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_pwr2_pc6", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_dc0_pn6", + "lcd_sdin_pz2", + "lcd_wr_n_pz3", + "lcd_sck_pz4", + "lcd_cs1_n_pw0", + "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC keys */ + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row3_pr3", + "kb_row8_ps0", + "kb_col0_pq0", + "kb_col1_pq1", + "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4", + "kb_row7_pr7", + "kb_row10_ps2", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs4_n_pk2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5", + "gmi_ad12_ph4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "sata"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI hot-plug-detect */ + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2", + "kb_row5_pr5"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,pull-down-strength = <5>; + nvidia,pull-up-strength = <5>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_gma { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_lcd2 { + nvidia,pins = "drive_lcd2"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + /* Broadcom GPS BCM47511 */ + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* Azurewave AW-AH663 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + lcd_ddc: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* Wolfson Microelectronics WM8903 audio codec */ + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + + AVDD-supply = <&vdd_1v8_vio>; + CPVDD-supply = <&vdd_1v8_vio>; + DBVDD-supply = <&vdd_1v8_vio>; + DCVDD-supply = <&vdd_1v8_vio>; + }; + }; + + i2c2: i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + + /* Atmel touchscreen */ + touchscreen@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + + interrupt-parent = <&gpio>; + interrupts = ; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + }; + }; + + i2c3: i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sen>; + }; + + /* AsahiKASEI AK8975 magnetometer sensor */ + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + + vdd-supply = <&vdd_3v3_sen>; + vid-supply = <&vdd_1v8_vio>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sen>; + vlogic-supply = <&vdd_1v8_vio>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_vio>; + vddio-supply = <&vdd_1v8_vio>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "1"; + }; + }; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <93750>; + }; + + i2c5: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + + /* Texas Instruments TPS659110 PMIC */ + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_sys>; + vcc2-supply = <&vdd_5v0_sys>; + vcc3-supply = <&vdd_1v8_vio>; + vcc4-supply = <&vdd_1v8_vio>; + vcc5-supply = <&vdd_5v0_sys>; + vcc6-supply = <&vddio_1v2_ddr>; + vcc7-supply = <&vdd_5v0_sys>; + vccio-supply = <&vdd_5v0_sys>; + + pmic-sleep-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>, + <2 GPIO_ACTIVE_HIGH>, + <6 GPIO_ACTIVE_HIGH>, + <8 GPIO_ACTIVE_HIGH>; + output-high; + }; + + regulators { + /* VDD1 is not used by Chagall */ + + vddio_1v2_ddr: vdd2 { + regulator-name = "vddio_1v2_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <1>; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8_vio: vio { + regulator-name = "vdd_1v8_gen"; + /* FIXME: eMMC won't work, if set to 1.8 V */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <3200000>; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_1v3_cam_isp"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + ti,regulator-ext-sleep-control = <8>; + }; + }; + }; + + vdd_core: core-regulator@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,enable-vout-discharge; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + vdd_5v0_sys: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: regulator-3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <300000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_sen: regulator-sensors { + compatible = "regulator-fixed"; + regulator-name = "sen_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + hdmi_5v0_sys: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_vbus_usb1: regulator-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus_micro_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_vbus_usb3: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus_typea_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <2>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x81>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* SAMSUNG K4P8G304EB FGC1 */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000006 + 0x00000001 0x00000000 0x00000004 0x00000004 + 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* ELPIDA EDB8132B2MA 8D_F */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000048 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000006 + 0x00000001 0x00000000 0x00000004 0x00000004 + 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; + }; + }; + + emc-timings-2 { + /* SAMSUNG K4P8G304EB FGC2 */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x00000008 0xc0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + + emc-timings-3 { + /* HYNIX H9TCNNN8JDMMPR NGM */ + nvidia,ram-code = <3>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x00000008 0xc0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* SAMSUNG K4P8G304EB FGC1 */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010082>; + nvidia,emc-mode-2 = <0x00020004>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000024>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000017 + 0x00000033 0x00000010 0x00000007 0x00000007 + 0x00000007 0x00000002 0x0000000a 0x00000007 + 0x00000007 0x00000003 0x00000002 0x00000000 + 0x00000003 0x00000007 0x00000004 0x0000000d + 0x0000000e 0x000005e9 0x00000000 0x0000017a + 0x00000002 0x00000002 0x00000007 0x00000000 + 0x00000001 0x0000000c 0x00000038 0x00000038 + 0x00000006 0x00000014 0x00000009 0x00000004 + 0x00000002 0x00000680 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0x001d0084 + 0x00008000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00038000 0x00038000 0x00038000 + 0x00038000 0x00080220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000090 0x000c000c 0xa0f10404 0x00000000 + 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; + }; + }; + + emc-timings-1 { + /* ELPIDA EDB8132B2MA 8D_F */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-400000000 { + clock-frequency = <400000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010082>; + nvidia,emc-mode-2 = <0x00020004>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000024>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000017 + 0x00000033 0x00000010 0x00000007 0x00000007 + 0x00000007 0x00000002 0x0000000a 0x00000007 + 0x00000007 0x00000003 0x00000002 0x00000000 + 0x00000003 0x00000007 0x00000004 0x0000000d + 0x0000000e 0x000005e9 0x00000000 0x0000017a + 0x00000002 0x00000002 0x00000007 0x00000000 + 0x00000001 0x0000000c 0x00000038 0x00000038 + 0x00000006 0x00000014 0x00000009 0x00000004 + 0x00000002 0x00000680 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0x001d0084 + 0x00008000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00034000 0x00034000 0x00034000 + 0x00034000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x00060220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000090 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; + }; + }; + + emc-timings-2 { + /* SAMSUNG K4P8G304EB FGC2 */ + nvidia,ram-code = <2>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000004 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000005 0x00000004 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x0000000a 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000004 + 0x00000002 0x000008aa 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x007f8008 0x007f8008 0x007f8008 + 0x007f8008 0x007f8008 0x007f8008 0x007f8008 + 0x007f8008 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x00080220 0x0200003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xf0000000 0xff00ff88 >; + }; + }; + + emc-timings-3 { + /* HYNIX H9TCNNN8JDMMPR NGM */ + nvidia,ram-code = <3>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x0000000a 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xd0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x00000009 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000004 + 0x00000002 0x000008aa 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000a0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; + }; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + i2s@70080400 { /* i2s1 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70080600 { /* i2s3 */ + status = "okay"; + }; + }; + + sdmmc1: mmc@78000000 { + status = "okay"; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + bus-width = <4>; + + vmmc-supply = <&vdd_usd>; /* ldo2 */ + vqmmc-supply = <&vddio_usd>; /* ldo3 */ + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + sdmmc3: mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* Azurewave AW-AH663 BCM4330B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc4: mmc@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + non-removable; + }; + + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "otg"; + vbus-supply = <&vdd_vbus_usb1>; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_vbus_usb3>; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <15>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu2: cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu3: cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + display-panel { + compatible = "panel-lvds"; + + width-mm = <217>; + height-mm = <136>; + + data-mapping = "jeida-24"; + + panel-timing { + /* 1280x800@60Hz */ + clock-frequency = <68000000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <48>; + hback-porch = <18>; + hsync-len = <30>; + vsync-len = <5>; + vfront-porch = <3>; + vback-porch = <12>; + }; + }; + + extcon-keys { + compatible = "gpio-keys"; + interrupt-parent = <&gpio>; + + dock-insert { + label = "Chagall Dock"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + lineout-detect { + label = "Audio dock line-out detect"; + gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + interrupt-parent = <&gpio>; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; + + sound { + compatible = "pegatron,tegra-audio-wm8903-chagall", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Pegatron Chagall WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "IN1R", "Mic Jack", + "DMICDAT", "Int Mic"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,headset; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * Chagall from getting too hot from a user's tactile + * perspective. The CPU zone is intended to protect + * silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 57C until temperature drops to 56.8C */ + temperature = <57000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 65C */ + temperature = <65000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; -- cgit v1.2.3 From ef6fb9875ce0f495115ebb22a635a1aaafc0f467 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:13:58 +0300 Subject: ARM: tegra: Add device-tree for 1080p version of Nyan Big Add dedicated device-tree for 1080p version of Nyan Big in order to describe display panel properly. FHD panel doesn't support modes other than 1080p, hence it's wrong to use incompatible lower resolution panel in device-tree. Tested-by: Thomas Graichen Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra124-nyan-big-fhd.dts | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 arch/arm/boot/dts/tegra124-nyan-big-fhd.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8f93e9e65a7c..a8763a75b3b2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1341,6 +1341,7 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ tegra124-apalis-v1.2-eval.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ + tegra124-nyan-big-fhd.dtb \ tegra124-nyan-blaze.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ARCH_U8500) += \ diff --git a/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts b/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts new file mode 100644 index 000000000000..d35fb79d2f51 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra124-nyan-big.dts" + +/ { + /* Version of Nyan Big with 1080p panel */ + panel { + compatible = "auo,b133htn01"; + }; +}; -- cgit v1.2.3 From e6fd5c1e9fc5b35ad855cf748cc18b86776b6389 Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Sun, 12 Dec 2021 00:13:59 +0300 Subject: ARM: tegra: Add usb-role-switch property to USB OTG ports If an USB port is an OTG port, then we should add the usb-role-switch property. Otherwise XUSB setup fails and therefore padctl is unable to set up the ports. This leads to broken USB and PCIe ports. Add the usb-role-switch properties to Tegra124 device-trees to fix the problem. The error message shown without this patch is e.g: usb2-0: usb-role-switch not found for otg mode [digetx@gmail.com: improved commit message] Tested-by: Thomas Graichen # T124 Nyan Big Signed-off-by: Stefan Eichenberger Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 + arch/arm/boot/dts/tegra124-apalis.dtsi | 1 + arch/arm/boot/dts/tegra124-nyan.dtsi | 1 + arch/arm/boot/dts/tegra124-venice2.dts | 2 +- 4 files changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index f5440ae14cb4..dbb0da08cb95 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1888,6 +1888,7 @@ usb2-0 { status = "okay"; mode = "otg"; + usb-role-switch; vbus-supply = <®_usbo1_vbus>; }; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 1d83f2e254c5..d3f16c117b0c 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1880,6 +1880,7 @@ usb2-0 { status = "okay"; mode = "otg"; + usb-role-switch; vbus-supply = <®_usbo1_vbus>; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 998b129321f8..cab0a6e95b7e 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -466,6 +466,7 @@ vbus-supply = <&vdd_usb1_vbus>; status = "okay"; mode = "otg"; + usb-role-switch; }; usb2-1 { diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 7985d1cbc1c0..232c90604df9 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -973,7 +973,7 @@ usb2-0 { status = "okay"; mode = "otg"; - + usb-role-switch; vbus-supply = <&vdd_usb1_vbus>; }; -- cgit v1.2.3 From 770586291f9a99c0abb6edee7d709a189355ac7e Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:00 +0300 Subject: ARM: tegra: Enable HDMI CEC on Nyan Enable HDMI CEC on Nyan Chromebooks. It allows to control TV over HDMI. Suggested-by: Thomas Graichen Tested-by: Thomas Graichen # T124 Nyan Big Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-nyan.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index cab0a6e95b7e..e702f91e0707 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -390,6 +390,10 @@ nvidia,sys-clock-req-active-high; }; + cec@70015000 { + status = "okay"; + }; + hda@70030000 { status = "okay"; }; -- cgit v1.2.3 From 894ea1121b29713c5da17e1032d1049f31e11d19 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:01 +0300 Subject: ARM: tegra: Enable CPU DFLL on Nyan Enable CPU DFLL node on Nyan Chromebooks. DFLL was previously disabled due to Linux kernel CPUFreq driver which didn't support suspend-resume. That problem was fixed years ago, but DFLL was never re-enabled. Tested-by: Thomas Graichen # T124 Nyan Big Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index e702f91e0707..f693daad68d8 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -532,7 +532,7 @@ /* CPU DFLL clock */ clock@70110000 { - status = "disabled"; + status = "okay"; vdd-cpu-supply = <&vdd_cpu>; nvidia,i2c-fs-rate = <400000>; }; -- cgit v1.2.3 From 7525c2a354e083a33f8775f810edd544f11ec108 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Dec 2021 00:14:02 +0300 Subject: ARM: tegra: Add CPU thermal zones to Nyan device-tree CPU of Nyan Chromebooks is overheating badly because apparently hardware soctherm controller doesn't work well. Add CPU thermal zones to enable software thermal control over CPU and fix the overheat trouble. Tested-by: Thomas Graichen # T124 Nyan Big Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-nyan.dtsi | 49 +++++++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index f693daad68d8..a93cfb492ba1 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include "tegra124.dtsi" / { @@ -87,7 +88,7 @@ interrupts = ; }; - temperature-sensor@4c { + tmp451: temperature-sensor@4c { compatible = "ti,tmp451"; reg = <0x4c>; interrupt-parent = <&gpio>; @@ -789,6 +790,52 @@ gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; priority = <200>; }; + + cpus { + cpu0: cpu@0 { + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + #cooling-cells = <2>; + }; + }; + + thermal-zones { + cpu-skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tmp451 0>; + + trips { + cpu_passive_trip: cpu-alert0 { + /* throttle at 70C until temperature drops to 69.8C */ + temperature = <70000>; + hysteresis = <200>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_passive_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; }; #include "cros-ec-keyboard.dtsi" -- cgit v1.2.3 From a28c1b4f11fc201103faf51902bb207edba76c73 Mon Sep 17 00:00:00 2001 From: Maxim Schwalm Date: Sun, 12 Dec 2021 00:14:06 +0300 Subject: ARM: tegra: nexus7: Use common LVDS display device-tree Make Nexus 7 device-tree to use common LVDS bridge description. This makes device-trees more consistent. [digetx@gmail.com: factored Nexus7 change into separate patch and wrote commit message] Signed-off-by: Maxim Schwalm Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../dts/tegra30-asus-nexus7-grouper-common.dtsi | 54 ++-------------------- 1 file changed, 3 insertions(+), 51 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index ab33ceb63fff..d79a99470ac2 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -8,6 +8,7 @@ #include "tegra30.dtsi" #include "tegra30-cpu-opp.dtsi" #include "tegra30-cpu-opp-microvolt.dtsi" +#include "tegra30-asus-lvds-display.dtsi" / { aliases { @@ -59,21 +60,6 @@ }; }; - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - port@0 { - lcd_output: endpoint { - remote-endpoint = <&lvds_encoder_input>; - bus-width = <24>; - }; - }; - }; - }; - }; - gpio@6000d000 { init-mode-hog { gpio-hog; @@ -1116,20 +1102,14 @@ */ compatible = "panel-lvds"; - power-supply = <&vdd_pnl>; - backlight = <&backlight>; - width-mm = <94>; height-mm = <150>; rotation = <180>; data-mapping = "jeida-24"; - port { - panel_input: endpoint { - remote-endpoint = <&lvds_encoder_output>; - }; - }; + /* DDC unconnected on Nexus 7 */ + /delete-property/ ddc-i2c-bus; }; firmware { @@ -1181,34 +1161,6 @@ }; }; - lvds-encoder { - compatible = "ti,sn75lvds83", "lvds-encoder"; - - powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; - power-supply = <&vdd_3v3_sys>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_encoder_input: endpoint { - remote-endpoint = <&lcd_output>; - }; - }; - - port@1 { - reg = <1>; - - lvds_encoder_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; -- cgit v1.2.3 From e6e395578a6e92307c54232bc695bb08b32b0f86 Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sun, 12 Dec 2021 00:14:08 +0300 Subject: ARM: tegra: Enable video decoder on Tegra114 Add Video Decoder Engine node to Tegra114 device-tree. Signed-off-by: Anton Bambura Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 8b45f4617b2f..ae1be90a9385 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -17,6 +17,19 @@ reg = <0x80000000 0x0>; }; + sram@40000000 { + compatible = "mmio-sram"; + reg = <0x40000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x40000>; + + vde_pool: sram@400 { + reg = <0x400 0x3fc00>; + pool; + }; + }; + host1x@50000000 { compatible = "nvidia,tegra114-host1x"; reg = <0x50000000 0x00028000>; @@ -253,6 +266,30 @@ */ }; + vde@6001a000 { + compatible = "nvidia,tegra114-vde"; + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x400>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&vde_pool>; /* IRAM region */ + interrupts = , /* Sync token interrupt */ + , /* BSE-V interrupt */ + ; /* SXE interrupt */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&tegra_car TEGRA114_CLK_VDE>; + reset-names = "vde", "mc"; + resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; + iommus = <&mc TEGRA_SWGROUP_VDE>; + }; + apbmisc@70000800 { compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; reg = <0x70000800 0x64>, /* Chip revision */ -- cgit v1.2.3 From ef5ad2608511596b8bd28f1e2b4fa8fadfd2f536 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Tue, 23 Nov 2021 23:19:22 +0700 Subject: ARM: dts: qcom: Drop input-name property This property doesn't seem to exist in the documentation nor in source code, but for some reason it is defined in a bunch of device trees. Signed-off-by: Dang Huynh Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211123161919.1506755-1-danct12@riseup.net --- arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts | 1 - arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts | 1 - arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 1 - arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 1 - arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts | 1 - arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts | 1 - arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts | 1 - 7 files changed, 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts index f8c97efc61fc..0cee62c7b8b0 100644 --- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts +++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts @@ -19,7 +19,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts index ea15b645b229..6d77e0f8ca4d 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -20,7 +20,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 30ee913faae6..069136170198 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -450,7 +450,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 003f0fa9c857..96e1c978b878 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -349,7 +349,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts index 398a3eaf306b..79e2cfbbb1ba 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts @@ -20,7 +20,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts index b4dd85bd4faf..e66937e3f7dd 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts @@ -20,7 +20,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts index 9743beebd84d..a62e5c25b23c 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -20,7 +20,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; -- cgit v1.2.3 From eb197dfe389a35566c8e27c537355aaed04fed67 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Fri, 10 Dec 2021 10:23:19 -0300 Subject: ARM: dts: imx6ulz-bsh-smm-m2: Add BSH SMM-M2 IMX6ULZ SystemMaster Add DTS of BSH SMM-M2 SystemMaster. This version comes with: - 128 MiB DDR3 RAM - 256 MiB Nand - wifi - bluetooth Signed-off-by: Ariel D'Alessandro Signed-off-by: Michael Trimarchi Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts | 146 +++++++++++++++++++++++++++++++ 2 files changed, 148 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 51a6dd687191..ab965ad2d6a9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -701,7 +701,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ - imx6ulz-14x14-evk.dtb + imx6ulz-14x14-evk.dtb \ + imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-aster.dtb \ diff --git a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts new file mode 100644 index 000000000000..59bcfc9a6b10 --- /dev/null +++ b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include +#include "imx6ulz.dtsi" + +/ { + model = "BSH SMM M2"; + compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz"; + + chosen { + stdout-path = &uart4; + }; + + usdhc2_pwrseq: usdhc2-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + bus-width = <4>; + no-1-8-v; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + cap-sdio-irq; + mmc-pwrseq = <&usdhc2_pwrseq>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&wdog1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b099 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b099 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 /* BT_REG_ON */ + MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x100b1 /* BT_DEV_WAKE out */ + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BT_HOST_WAKE in */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x79 /* WL_REG_ON */ + MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x100b1 /* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 /* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */ + MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */ + >; + }; +}; -- cgit v1.2.3 From 538e5f7106f61e6b8404b0509f71f518123968cd Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Wed, 8 Dec 2021 22:40:45 +1000 Subject: ARM: dts: imx7d-remarkable2: add wacom digitizer device Add Wacom I2C support for the reMarkable 2 eInk tablet using the generic I2C HID framework. Signed-off-by: Alistair Francis Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-remarkable2.dts | 59 +++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-remarkable2.dts b/arch/arm/boot/dts/imx7d-remarkable2.dts index 89cbf13097a4..a2a91bfdd98e 100644 --- a/arch/arm/boot/dts/imx7d-remarkable2.dts +++ b/arch/arm/boot/dts/imx7d-remarkable2.dts @@ -34,6 +34,19 @@ startup-delay-us = <150>; }; + reg_digitizer: regulator-digitizer { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_DIGITIZER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_digitizer_reg>; + pinctrl-1 = <&pinctrl_digitizer_reg>; + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; /* 100 ms */ + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -51,6 +64,26 @@ assigned-clock-rates = <0>, <32768>; }; +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + wacom_digitizer: digitizer@9 { + compatible = "hid-over-i2c"; + reg = <0x09>; + hid-descr-addr = <0x01>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wacom>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + touchscreen-inverted-x; + touchscreen-inverted-y; + vdd-supply = <®_digitizer>; + }; +}; + &snvs_pwrkey { status = "okay"; }; @@ -117,6 +150,25 @@ fsl,ext-reset-output; }; +&iomuxc_lpsr { + pinctrl_digitizer_reg: digitizerreggrp { + fsl,pins = < + /* DIGITIZER_PWR_EN */ + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 + >; + }; + + pinctrl_wacom: wacomgrp { + fsl,pins = < + /*MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x00000014 FWE */ + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x00000074 /* PDCTB */ + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x00000034 /* WACOM INT */ + /*MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x00000014 WACOM PWR ENABLE */ + /*MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x00000074 WACOM RESET */ + >; + }; +}; + &iomuxc { pinctrl_brcm_reg: brcmreggrp { fsl,pins = < @@ -125,6 +177,13 @@ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 -- cgit v1.2.3 From c720e38f4c2dd1e0b5cf4f7dcf8bb6951cd3856d Mon Sep 17 00:00:00 2001 From: Johann Neuhauser Date: Mon, 13 Dec 2021 12:18:08 +0100 Subject: ARM: imx_v6_v7_defconfig: Enable for DHCOM devices required RTC_DRV_RV3029C2 All imx6 DHCOM devices uses a on module gold cap/battery powered i2c rtc "microcrystal,rv3029", which isn't enabled in the imx_v6_v7_defconfig. The rtc for all imx6 DHCOM devices is defined in: imx6qdl-dhcom-som.dtsi To have a working clock on all imx6qdl DHCOM based devices, enable the driver. Signed-off-by: Johann Neuhauser Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 1fbb8e45e604..f7498df08dfe 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -378,6 +378,7 @@ CONFIG_RTC_DRV_PCF8523=y CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_M41T80=y CONFIG_RTC_DRV_RC5T619=y +CONFIG_RTC_DRV_RV3029C2=y CONFIG_RTC_DRV_DA9063=y CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y -- cgit v1.2.3 From 20c7b41d03d3c1d75cd652a45554b3594e513e3d Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Tue, 14 Dec 2021 10:03:53 +0100 Subject: ARM: dts: imx6qdl-dhcom: Add USB overcurrent pin on SoM layer Add USB overcurrent pin muxing on SoM layer. On DRC02 and PDK2 the USB overcurrent pin isn't connected, but a USB hub on the board takes care of the USB overcurrent instead. Therefore disable it there with the property disable-over-current. Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Marek Vasut Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi | 4 ++++ arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi | 4 ++++ arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi | 1 + 3 files changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi index 3d0a50a9ab21..702cd4a1b2e6 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi @@ -95,6 +95,10 @@ rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */ }; +&usbh1 { + disable-over-current; +}; + &usdhc2 { /* SD card */ status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi index dc21853706a5..dc89b554e694 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi @@ -260,6 +260,10 @@ status = "okay"; }; +&usbh1 { + disable-over-current; +}; + &usdhc2 { /* SD card */ status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi index b2b7daf43ede..5befbe13d1a3 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi @@ -729,6 +729,7 @@ pinctrl_usbh1: usbh1-grp { fsl,pins = < MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b1 >; }; -- cgit v1.2.3 From 841b71c57bcf63137983bad340ffc7b6bfbc6b0a Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 16 Dec 2021 09:41:05 +0100 Subject: ARM: dts: imx6qdl: phytec: Add support for optional PEB-EVAL-01 board The PHYTEC PEV-EVAL-01 expansion board adds support for additional gpio-triggered user-leds and gpio-key support. Signed-off-by: Yunus Bas Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 + arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 + arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 + .../boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi | 71 ++++++++++++++++++++++ arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 + 5 files changed, 75 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts index 9f7f9f98139d..b057fa664a6b 100644 --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts @@ -8,6 +8,7 @@ #include "imx6dl.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" / { model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts index 2e70ea5623c6..db6e2cc36759 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts @@ -8,6 +8,7 @@ #include "imx6q.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts index 65d2e483c136..51ff601b1aec 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts @@ -8,6 +8,7 @@ #include "imx6q.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi new file mode 100644 index 000000000000..037b60197598 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik + * Author: Christian Hemp + */ + +#include + +/ { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + power { + label = "Power Button"; + gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + sleep { + label = "Sleep Button"; + gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>; + status = "disabled"; + + user-led1 { + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + + user-led2 { + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + + user-led3 { + gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0 + >; + }; + + pinctrl_user_leds: userledsgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts index f27d7ab42626..06fe0c5315fc 100644 --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts @@ -8,6 +8,7 @@ #include "imx6qp.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" +#include "imx6qdl-phytec-mira-peb-eval-01.dtsi" / { model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; -- cgit v1.2.3 From d3af422c0587f55f9d9d3375bf6bb61bea53f014 Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 16 Dec 2021 09:41:06 +0100 Subject: ARM: dts: imx6qdl: phytec: Add support for optional PEB-AV-02 LCD adapter The PEB-AV-02 expansion adapter extends the phyBOARD-Mira boards to connect parallel LCD displays, either with capacitive or resistive touch. Signed-off-by: Yunus Bas Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 + arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 + arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 + .../boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi | 119 +++++++++++++++++++++ arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 + 5 files changed, 123 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts index b057fa664a6b..8165fae2b1d1 100644 --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts index db6e2cc36759..bbf5097ca974 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts @@ -9,6 +9,7 @@ #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts index 51ff601b1aec..95051e18324f 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi new file mode 100644 index 000000000000..393475cb0f4d --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik + * Author: Christian Hemp + */ + +/ { + display: display0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0>; + interface-pix-fmt = "rgb24"; + status = "disabled"; + + port@0 { + reg = <0>; + + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display0_out: endpoint { + remote-endpoint = <&peb_panel_lcd_in>; + }; + }; + }; + + panel-lcd { + compatible = "edt,etm0700g0edh6"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_pwr>; + power-supply = <®_display>; + enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + status = "disabled"; + + port { + peb_panel_lcd_in: endpoint { + remote-endpoint = <&display0_out>; + }; + }; + }; + + reg_display: regulator-peb-display { + compatible = "regulator-fixed"; + regulator-name = "peb-display"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&i2c1 { + edt_ft5x06: touchscreen@38 { + compatible = "edt,edt-ft5406"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + reg = <0x38>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_NONE>; + status = "disabled"; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_disp0: disp0grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_disp0_pwr: disp0pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_edt_ft5x06: edtft5x06grp { + fsl,pins = < + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0xb0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts index 06fe0c5315fc..343639cb035c 100644 --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6qdl-phytec-phycore-som.dtsi" #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" +#include "imx6qdl-phytec-mira-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; -- cgit v1.2.3 From 3478494dcae155f0580e8f841458905f4fc739c2 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:42 +0300 Subject: ARM: tegra: Add 500 MHz entry to Tegra30 memory OPP table Extend memory OPPs with 500 MHz entry. This clock rate is used by ASUS Transformer tablets. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-peripherals-opp.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi index ff25350869b3..af9640401402 100644 --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -216,6 +216,18 @@ opp-supported-hw = <0x0008>; }; + opp-500000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x0007>; + }; + + opp-500000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x0008>; + }; + opp-533000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <533000000>; @@ -347,6 +359,12 @@ opp-peak-kBps = <3600000>; }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <4000000>; + }; + opp-533000000 { opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x000F>; -- cgit v1.2.3 From 83b7f0b8aeab4fc8271392fd32164efb7b3f55e9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:43 +0300 Subject: ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees Add OPP tables and power domains to all peripheral devices which support power management on Tegra20 SoC. Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 1 + arch/arm/boot/dts/tegra20-colibri.dtsi | 3 +- arch/arm/boot/dts/tegra20-harmony.dts | 3 +- arch/arm/boot/dts/tegra20-paz00.dts | 1 + arch/arm/boot/dts/tegra20-peripherals-opp.dtsi | 912 ++++++++++++++++++++++++ arch/arm/boot/dts/tegra20-seaboard.dts | 3 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 3 +- arch/arm/boot/dts/tegra20-trimslice.dts | 9 + arch/arm/boot/dts/tegra20-ventana.dts | 1 + arch/arm/boot/dts/tegra20.dtsi | 102 ++- 10 files changed, 1033 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 2d5fead9de6b..4aa0eb0c50fe 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -718,6 +718,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <458>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; usb@c5000000 { diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index b1f2f7f82928..1eefb9ee4ac8 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -497,7 +497,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "VDD_CORE_1.2V"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -603,6 +603,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */ i2c-thermtrip { diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index f560bf743a19..79b6b79fab65 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -339,7 +339,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "vdd_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -565,6 +565,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; pcie@80003000 { diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 5ce6a1ff93de..fe1bffedc266 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -519,6 +519,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <0>; nvidia,sys-clock-req-active-high; + core-supply = <&core_vdd_reg>; }; usb@c5000000 { diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi index d4d0a5fa7015..1b808233a933 100644 --- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi @@ -1,6 +1,46 @@ // SPDX-License-Identifier: GPL-2.0 / { + core_opp_table: opp-table-core { + compatible = "operating-points-v2"; + opp-shared; + + core_opp_950: opp-950000 { + opp-microvolt = <950000 950000 1300000>; + opp-level = <950000>; + }; + + core_opp_1000: opp-1000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-level = <1000000>; + }; + + core_opp_1100: opp-1100000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-level = <1100000>; + }; + + core_opp_1200: opp-1200000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-level = <1200000>; + }; + + core_opp_1225: opp-1225000 { + opp-microvolt = <1225000 1225000 1300000>; + opp-level = <1225000>; + }; + + core_opp_1275: opp-1275000 { + opp-microvolt = <1275000 1275000 1300000>; + opp-level = <1275000>; + }; + + core_opp_1300: opp-1300000 { + opp-microvolt = <1300000 1300000 1300000>; + opp-level = <1300000>; + }; + }; + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; @@ -8,66 +48,77 @@ opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <36000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-47500000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <47500000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-50000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <50000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-54000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-57000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <57000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; }; opp-100000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <100000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-108000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-126666000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <126666000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-150000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <150000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-190000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <190000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-216000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <216000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; opp-suspend; }; @@ -75,36 +126,897 @@ opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-333000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <333000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; }; opp-380000000 { opp-microvolt = <1100000 1100000 1300000>; opp-hz = /bits/ 64 <380000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; }; opp-600000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; }; opp-666000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <666000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; }; opp-760000000 { opp-microvolt = <1300000 1300000 1300000>; opp-hz = /bits/ 64 <760000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1300>; + }; + }; + + host1x_dvfs_opp_table: opp-table-host1x { + compatible = "operating-points-v2"; + + opp-104500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <104500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-133000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-166000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <166000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + mpe_dvfs_opp_table: opp-table-mpe { + compatible = "operating-points-v2"; + + opp-104500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <104500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-142500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <142500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-152000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-228000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-228000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-237500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <237500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-266000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <266000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-275500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <275500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1100>; + }; + }; + + vi_dvfs_opp_table: opp-table-vi { + compatible = "operating-points-v2"; + + opp-85000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <85000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-100000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-150000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + epp_dvfs_opp_table: opp-table-epp { + compatible = "operating-points-v2"; + + opp-133000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-171000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + gr2d_dvfs_opp_table: opp-table-gr2d { + compatible = "operating-points-v2"; + + opp-133000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-171000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + gr3d_dvfs_opp_table: opp-table-gr3d { + compatible = "operating-points-v2"; + + opp-114000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <114000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-161500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-161500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-209000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-218500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-247000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-247000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-256500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <256500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-285000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-304000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-323000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <323000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-333500000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp-333500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1200>; + }; + + opp-351500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <351500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1275>; + }; + + opp-380000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-400000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1275>; + }; + + opp-400000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1200>; + }; + }; + + disp1_dvfs_opp_table: opp-table-disp1 { + compatible = "operating-points-v2"; + + opp-158000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-190000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + disp2_dvfs_opp_table: opp-table-disp2 { + compatible = "operating-points-v2"; + + opp-158000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-190000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + dsi_dvfs_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-100000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-500000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + hdmi_dvfs_opp_table: opp-table-hdmi { + compatible = "operating-points-v2"; + + opp-148500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <148500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + tvo_dvfs_opp_table: opp-table-tvo { + compatible = "operating-points-v2"; + + opp-250000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sclk_dvfs_opp_table: opp-table-sclk { + compatible = "operating-points-v2"; + + opp-95000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <95000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-123500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-133000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-152000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-159500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <159500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-171000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-180500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <180500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-207000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <207000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-218500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-222500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <222500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-229500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <229500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-240000000-1225 { + opp-microvolt = <1225000 1225000 1300000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1225>; + }; + + opp-240000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1200>; + }; + + opp-247000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp-256500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <256500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + + opp-260000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <260000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-262000000-1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <262000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1300>; + }; + + opp-264000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1275>; + }; + + opp-277500000-1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <277500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1300>; + }; + + opp-285000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1275>; + }; + + opp-292500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <292500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-300000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1275>; + }; + }; + + vde_dvfs_opp_table: opp-table-vde { + compatible = "operating-points-v2"; + + opp-95000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <95000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp-123500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-123500000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp-152000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp-152000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp-171000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp-209000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-209000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-218500000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp-237500000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <237500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp-275500000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <275500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp-285000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-300000000-1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp-300000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + }; + + ndflash_dvfs_opp_table: opp-table-ndflash { + compatible = "operating-points-v2"; + + opp-130000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <130000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-150000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-158000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-164000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <164000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + nor_dvfs_opp_table: opp-table-nor { + compatible = "operating-points-v2"; + + opp-92000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <92000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc2_dvfs_opp_table: opp-table-sdmmc2 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc4_dvfs_opp_table: opp-table-sdmmc4 { + compatible = "operating-points-v2"; + + opp-44000000-950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + pcie_dvfs_opp_table: opp-table-pcie { + compatible = "operating-points-v2"; + + opp-250000000-1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + usbd_dvfs_opp_table: opp-table-usbd { + compatible = "operating-points-v2"; + + opp-480000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + usb2_dvfs_opp_table: opp-table-usb2 { + compatible = "operating-points-v2"; + + opp-480000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + usb3_dvfs_opp_table: opp-table-usb3 { + compatible = "operating-points-v2"; + + opp-480000000-1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; }; }; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index f9309c07a9f2..c4a6a6a94559 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -444,7 +444,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "vdd_sm0,vdd_core"; regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1300000>; @@ -689,6 +689,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; memory-controller@7000f400 { diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 2ad56f84bb62..de39c5465c0a 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -357,7 +357,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "vdd_sys_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -477,6 +477,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; pcie@80003000 { diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 8bb0eaa610f2..9d0c86711de2 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -322,6 +322,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; pcie@80003000 { @@ -443,6 +444,14 @@ regulator-always-on; }; + vdd_core: regulator-core { + compatible = "regulator-fixed"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + sound { compatible = "nvidia,tegra-audio-trimslice"; nvidia,i2s-controller = <&tegra_i2s1>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index b1c92ba789be..b0a00970b61c 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -544,6 +544,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <458>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; usb@c5000000 { diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 6f493a8a8a9f..45fe111705af 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -42,6 +42,8 @@ clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; + power-domains = <&pd_core>; + operating-points-v2 = <&host1x_dvfs_opp_table>; #address-cells = <1>; #size-cells = <1>; @@ -55,6 +57,8 @@ clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + power-domains = <&pd_mpe>; + operating-points-v2 = <&mpe_dvfs_opp_table>; }; vi@54080000 { @@ -64,6 +68,8 @@ clocks = <&tegra_car TEGRA20_CLK_VI>; resets = <&tegra_car 20>; reset-names = "vi"; + power-domains = <&pd_venc>; + operating-points-v2 = <&vi_dvfs_opp_table>; }; epp@540c0000 { @@ -73,6 +79,8 @@ clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + power-domains = <&pd_core>; + operating-points-v2 = <&epp_dvfs_opp_table>; }; isp@54100000 { @@ -82,6 +90,7 @@ clocks = <&tegra_car TEGRA20_CLK_ISP>; resets = <&tegra_car 23>; reset-names = "isp"; + power-domains = <&pd_venc>; }; gr2d@54140000 { @@ -91,6 +100,8 @@ clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + power-domains = <&pd_core>; + operating-points-v2 = <&gr2d_dvfs_opp_table>; }; gr3d@54180000 { @@ -99,6 +110,8 @@ clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + power-domains = <&pd_3d>; + operating-points-v2 = <&gr3d_dvfs_opp_table>; }; dc@54200000 { @@ -110,6 +123,8 @@ clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp1_dvfs_opp_table>; nvidia,head = <0>; @@ -138,6 +153,8 @@ clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp2_dvfs_opp_table>; nvidia,head = <1>; @@ -166,6 +183,8 @@ clock-names = "hdmi", "parent"; resets = <&tegra_car 51>; reset-names = "hdmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&hdmi_dvfs_opp_table>; status = "disabled"; }; @@ -174,6 +193,8 @@ reg = <0x542c0000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_TVO>; + power-domains = <&pd_core>; + operating-points-v2 = <&tvo_dvfs_opp_table>; status = "disabled"; }; @@ -185,6 +206,8 @@ clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; + power-domains = <&pd_core>; + operating-points-v2 = <&dsi_dvfs_opp_table>; status = "disabled"; }; }; @@ -242,6 +265,13 @@ reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + sclk { + compatible = "nvidia,tegra20-sclk"; + clocks = <&tegra_car TEGRA20_CLK_SCLK>; + power-domains = <&pd_core>; + operating-points-v2 = <&sclk_dvfs_opp_table>; + }; }; flow-controller@60007000 { @@ -319,6 +349,8 @@ clocks = <&tegra_car TEGRA20_CLK_VDE>; reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; + power-domains = <&pd_vde>; + operating-points-v2 = <&vde_dvfs_opp_table>; }; apbmisc@70000800 { @@ -460,6 +492,8 @@ reset-names = "nand"; assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; assigned-clock-rates = <150000000>; + power-domains = <&pd_core>; + operating-points-v2 = <&ndflash_dvfs_opp_table>; status = "disabled"; }; @@ -473,6 +507,8 @@ clock-names = "gmi"; resets = <&tegra_car 42>; reset-names = "gmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&nor_dvfs_opp_table>; status = "disabled"; }; @@ -643,6 +679,52 @@ clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; + + pd_core: core-domain { + #power-domain-cells = <0>; + operating-points-v2 = <&core_opp_table>; + }; + + powergates { + pd_3d: td { + clocks = <&tegra_car TEGRA20_CLK_GR3D>; + resets = <&mc TEGRA20_MC_RESET_3D>, + <&tegra_car TEGRA20_CLK_GR3D>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA20_CLK_ISP>, + <&tegra_car TEGRA20_CLK_VI>, + <&tegra_car TEGRA20_CLK_CSI>; + resets = <&mc TEGRA20_MC_RESET_ISP>, + <&mc TEGRA20_MC_RESET_VI>, + <&tegra_car TEGRA20_CLK_ISP>, + <&tegra_car 20 /* VI */>, + <&tegra_car TEGRA20_CLK_CSI>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_vde: vdec { + clocks = <&tegra_car TEGRA20_CLK_VDE>; + resets = <&mc TEGRA20_MC_RESET_VDE>, + <&tegra_car TEGRA20_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_mpe: mpe { + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&mc TEGRA20_MC_RESET_MPEA>, + <&mc TEGRA20_MC_RESET_MPEB>, + <&mc TEGRA20_MC_RESET_MPEC>, + <&tegra_car TEGRA20_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; }; mc: memory-controller@7000f000 { @@ -662,12 +744,13 @@ reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; + power-domains = <&pd_core>; #address-cells = <1>; #size-cells = <0>; #interconnect-cells = <0>; - operating-points-v2 = <&emc_icc_dvfs_opp_table>; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; }; fuse@7000f800 { @@ -712,6 +795,9 @@ <&tegra_car 72>, <&tegra_car 74>; reset-names = "pex", "afi", "pcie_x"; + power-domains = <&pd_core>; + operating-points-v2 = <&pcie_dvfs_opp_table>; + status = "disabled"; pci@1,0 { @@ -753,6 +839,8 @@ reset-names = "usb"; nvidia,needs-double-reset; nvidia,phy = <&phy1>; + power-domains = <&pd_core>; + operating-points-v2 = <&usbd_dvfs_opp_table>; status = "disabled"; }; @@ -792,6 +880,8 @@ resets = <&tegra_car 58>; reset-names = "usb"; nvidia,phy = <&phy2>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb2_dvfs_opp_table>; status = "disabled"; }; @@ -820,6 +910,8 @@ resets = <&tegra_car 59>; reset-names = "usb"; nvidia,phy = <&phy3>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb3_dvfs_opp_table>; status = "disabled"; }; @@ -856,6 +948,8 @@ clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; status = "disabled"; }; @@ -867,6 +961,8 @@ clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc2_dvfs_opp_table>; status = "disabled"; }; @@ -878,6 +974,8 @@ clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; status = "disabled"; }; @@ -889,6 +987,8 @@ clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc4_dvfs_opp_table>; status = "disabled"; }; -- cgit v1.2.3 From d71329b69bb6dd853ee2ab0b39c9c013e706b49a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:19 +0300 Subject: ARM: tegra_defconfig: Enable S/PDIF driver Enable Tegra20 S/PDIF driver. It's a part of HDMI audio subsystem on Tegra. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/configs/tegra_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index a8093b222551..289d022acc4b 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -231,6 +231,7 @@ CONFIG_SND_HDA_CODEC_HDMI=y CONFIG_SND_SOC=y CONFIG_SND_SOC_TEGRA=y CONFIG_SND_SOC_TEGRA20_I2S=y +CONFIG_SND_SOC_TEGRA20_SPDIF=y CONFIG_SND_SOC_TEGRA30_I2S=y CONFIG_SND_SOC_TEGRA_RT5640=y CONFIG_SND_SOC_TEGRA_WM8753=y -- cgit v1.2.3 From 02e7cb574c21580eab3cffbcc863d3ac81787475 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:20 +0300 Subject: ARM: config: multi v7: Enable NVIDIA Tegra20 S/PDIF driver Enable Tegra20 S/PDIF driver that is a part of HDMI audio subsystem. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 3d509bc13444..172838566ecd 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -762,6 +762,7 @@ CONFIG_SND_SOC_STM32_DFSDM=m CONFIG_SND_SUN4I_CODEC=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA20_I2S=m +CONFIG_SND_SOC_TEGRA20_SPDIF=m CONFIG_SND_SOC_TEGRA30_I2S=m CONFIG_SND_SOC_TEGRA_RT5640=m CONFIG_SND_SOC_TEGRA_WM8753=m -- cgit v1.2.3 From 8ed567fbea94ad05298d060974d5fa59946cf689 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:21 +0300 Subject: ARM: config: multi v7: Enable NVIDIA Tegra20 APB DMA driver All Tegra20/30/114 serial and audio drivers depend on the Tegra20 APB DMA driver, enable this DMA driver. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 172838566ecd..8863fa969ede 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -958,6 +958,7 @@ CONFIG_ST_FDMA=m CONFIG_STM32_DMA=y CONFIG_STM32_DMAMUX=y CONFIG_STM32_MDMA=y +CONFIG_TEGRA20_APB_DMA=y CONFIG_UNIPHIER_MDMAC=y CONFIG_XILINX_DMA=y CONFIG_QCOM_BAM_DMA=y -- cgit v1.2.3 From 73e2b72a3518fb60b6a1c11286715f933bafdec2 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:44 +0300 Subject: ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees Add OPP tables and power domains to all peripheral devices which support power management on Tegra30 SoC. Tested-by: Peter Geis # Ouya T30 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../dts/tegra30-asus-nexus7-grouper-common.dtsi | 1 + arch/arm/boot/dts/tegra30-beaver.dts | 1 + arch/arm/boot/dts/tegra30-cardhu.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 17 +- arch/arm/boot/dts/tegra30-ouya.dts | 1 + arch/arm/boot/dts/tegra30-peripherals-opp.dtsi | 1224 ++++++++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 153 +++ 7 files changed, 1395 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index d79a99470ac2..2c2ad2a38f04 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -968,6 +968,7 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; ahub@70080000 { diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 7c2b70b13cc4..5ad62b567d32 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1916,6 +1916,7 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&core_vdd_reg>; }; ahub@70080000 { diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index c2a56eb0b9fa..ba257ed36d9c 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -393,6 +393,7 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; ahub@70080000 { diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 9bf8170fee79..be691a1c33a1 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -767,9 +767,14 @@ vddctrl_reg: vddctrl { regulator-name = "+V1.0_VDD_CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; reg_1v8_vio: vio { @@ -892,15 +897,20 @@ }; /* SW: +V1.2_VDD_CORE */ - regulator@60 { + vdd_core: regulator@60 { compatible = "ti,tps62362"; reg = <0x60>; regulator-name = "tps62362-vout"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; + + nvidia,tegra-core-regulator; }; }; @@ -913,6 +923,7 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ i2c-thermtrip { diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index b28c5504e1b1..e604ad08a2c2 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -2195,6 +2195,7 @@ nvidia,core-pwr-off-time = <458>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; memory-controller@7000f000 { diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi index af9640401402..d100a1a8b705 100644 --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -1,6 +1,56 @@ // SPDX-License-Identifier: GPL-2.0 / { + core_opp_table: opp-table-core { + compatible = "operating-points-v2"; + opp-shared; + + core_opp_950: opp-950000 { + opp-microvolt = <950000 950000 1350000>; + opp-level = <950000>; + }; + + core_opp_1000: opp-1000000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-level = <1000000>; + }; + + core_opp_1050: opp-1050000 { + opp-microvolt = <1050000 1050000 1350000>; + opp-level = <1050000>; + }; + + core_opp_1100: opp-1100000 { + opp-microvolt = <1100000 1100000 1350000>; + opp-level = <1100000>; + }; + + core_opp_1150: opp-1150000 { + opp-microvolt = <1150000 1150000 1350000>; + opp-level = <1150000>; + }; + + core_opp_1200: opp-1200000 { + opp-microvolt = <1200000 1200000 1350000>; + opp-level = <1200000>; + }; + + core_opp_1250: opp-1250000 { + opp-microvolt = <1250000 1250000 1350000>; + opp-level = <1250000>; + }; + + core_opp_1300: opp-1300000 { + opp-microvolt = <1300000 1300000 1350000>; + opp-level = <1300000>; + }; + + core_opp_1350: opp-1350000 { + opp-microvolt = <1350000 1350000 1350000>; + opp-level = <1350000>; + }; + }; + emc_icc_dvfs_opp_table: opp-table-emc { compatible = "operating-points-v2"; @@ -8,126 +58,147 @@ opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-12750000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-12750000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <12750000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-25500000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-25500000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-25500000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <25500000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-27000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-27000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-27000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <27000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-51000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-51000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-51000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <51000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-54000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-54000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-54000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-102000000-950 { opp-microvolt = <950000 950000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; }; opp-102000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; }; opp-102000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <102000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-108000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; }; opp-108000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-204000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; opp-suspend; }; @@ -135,6 +206,7 @@ opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <204000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; opp-suspend; }; @@ -142,138 +214,161 @@ opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; }; opp-333500000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; }; opp-333500000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-375000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; }; opp-375000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; }; opp-375000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <375000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-400000000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; }; opp-400000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; }; opp-400000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <400000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-416000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; }; opp-416000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <416000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-450000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; }; opp-450000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <450000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-500000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <500000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; }; opp-500000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <500000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-533000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; }; opp-533000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <533000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-625000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; }; opp-625000000-1250 { opp-microvolt = <1250000 1250000 1350000>; opp-hz = /bits/ 64 <625000000>; opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; }; opp-667000000-1200 { opp-microvolt = <1200000 1200000 1350000>; opp-hz = /bits/ 64 <667000000>; opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; }; opp-750000000-1300 { opp-microvolt = <1300000 1300000 1350000>; opp-hz = /bits/ 64 <750000000>; opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; }; opp-800000000-1300 { opp-microvolt = <1300000 1300000 1350000>; opp-hz = /bits/ 64 <800000000>; opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; }; opp-900000000-1350 { opp-microvolt = <1350000 1350000 1350000>; opp-hz = /bits/ 64 <900000000>; opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; }; }; @@ -401,4 +496,1133 @@ opp-peak-kBps = <7200000>; }; }; + + pcie_dvfs_opp_table: opp-table-pcie { + compatible = "operating-points-v2"; + + opp-250000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + host1x_dvfs_opp_table: opp-table-host1x { + compatible = "operating-points-v2"; + + opp-152000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-188000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <188000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1050>; + }; + + opp-222000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <222000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1100>; + }; + + opp-242000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <242000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-254000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <254000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1150>; + }; + + opp-267000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1200>; + }; + + opp-300000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + mpe_dvfs_opp_table: opp-table-mpe { + compatible = "operating-points-v2"; + + opp-234000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <234000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + vi_dvfs_opp_table: opp-table-vi { + compatible = "operating-points-v2"; + + opp-216000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>; + }; + + opp-219000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <219000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-267000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1050>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-300000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1100>; + }; + + opp-371000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <371000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1150>; + }; + + opp-409000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <409000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-425000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <425000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1250>; + }; + + opp-470000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <470000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + }; + + epp_dvfs_opp_table: opp-table-epp { + compatible = "operating-points-v2"; + + opp-267000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + gr2d_dvfs_opp_table: opp-table-gr2d { + compatible = "operating-points-v2"; + + opp-267000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + gr3d_dvfs_opp_table: opp-table-gr3d { + compatible = "operating-points-v2"; + + opp-234000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <234000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>, <&core_opp_1000>; + }; + + opp-247000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>, <&core_opp_1000>; + }; + + opp-285000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>, <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>, <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>, <&core_opp_1100>; + }; + + opp-361000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>, <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>, <&core_opp_1150>; + }; + + opp-408000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>, <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>, <&core_opp_1200>; + }; + + opp-446000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>, <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>, <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>, <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>, <&core_opp_1350>; + }; + }; + + disp1_dvfs_opp_table: opp-table-disp1 { + compatible = "operating-points-v2"; + + opp-120000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <120000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1000>; + }; + + opp-155000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <155000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1200>; + }; + + opp-268000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <268000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1050>; + }; + }; + + disp2_dvfs_opp_table: opp-table-disp2 { + compatible = "operating-points-v2"; + + opp-120000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <120000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1000>; + }; + + opp-155000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <155000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-190000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0009>; + required-opps = <&core_opp_1200>; + }; + + opp-268000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <268000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1050>; + }; + }; + + hdmi_dvfs_opp_table: opp-table-hdmi { + compatible = "operating-points-v2"; + + opp-148500000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <148500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + tvo_dvfs_opp_table: opp-table-tvo { + compatible = "operating-points-v2"; + + opp-297000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <297000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + }; + + dsia_dvfs_opp_table: opp-table-dsia { + compatible = "operating-points-v2"; + + opp-275000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + dsib_dvfs_opp_table: opp-table-dsib { + compatible = "operating-points-v2"; + + opp-275000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sclk_dvfs_opp_table: opp-table-sclk { + compatible = "operating-points-v2"; + + opp-51000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_950>; + }; + + opp-136000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <136000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp-164000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <164000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1050>; + }; + + opp-191000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <191000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp-205000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <205000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1000>; + }; + + opp-216000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1150>; + }; + + opp-227000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <227000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1100>; + }; + + opp-267000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp-334000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <334000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1250>; + }; + + opp-378000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <378000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + }; + + pll_c_dvfs_opp_table: opp-table-pllc { + compatible = "operating-points-v2"; + + opp-533000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-667000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-800000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-1066000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <1066000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + + opp-1200000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1350>; + }; + }; + + pll_e_dvfs_opp_table: opp-table-plle { + compatible = "operating-points-v2"; + + opp-100000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + pll_m_dvfs_opp_table: opp-table-pllm { + compatible = "operating-points-v2"; + + opp-533000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-667000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-800000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp-1066000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <1066000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + vde_dvfs_opp_table: opp-table-vde { + compatible = "operating-points-v2"; + + opp-228000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1000>; + }; + + opp-247000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp-275000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1050>; + }; + + opp-304000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1050>; + }; + + opp-332000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1100>; + }; + + opp-352000000-1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <352000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp-380000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1150>; + }; + + opp-400000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1150>; + }; + + opp-416000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp-437000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <437000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp-484000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1250>; + }; + + opp-520000000-1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp-600000000-1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1350>; + }; + }; + + fuse_burn_dvfs_opp_table: opp-table-fuseburn { + compatible = "operating-points-v2"; + + opp-26000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <26000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1150>; + }; + }; + + nor_dvfs_opp_table: opp-table-nor { + compatible = "operating-points-v2"; + + opp-108000000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + + opp-115000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <115000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-130000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <130000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1050>; + }; + + opp-133000000-1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1150>; + }; + }; + + pwm_dvfs_opp_table: opp-table-pwm { + compatible = "operating-points-v2"; + + opp-408000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sbc1_dvfs_opp_table: opp-table-sbc1 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc2_dvfs_opp_table: opp-table-sbc2 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc3_dvfs_opp_table: opp-table-sbc3 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc4_dvfs_opp_table: opp-table-sbc4 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc5_dvfs_opp_table: opp-table-sbc5 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sbc6_dvfs_opp_table: opp-table-sbc6 { + compatible = "operating-points-v2"; + + opp-52000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp-60000000-1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1050>; + }; + + opp-100000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { + compatible = "operating-points-v2"; + + opp-104000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <104000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-208000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <208000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { + compatible = "operating-points-v2"; + + opp-104000000-950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <104000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp-208000000-1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <208000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + usbd_dvfs_opp_table: opp-table-usbd { + compatible = "operating-points-v2"; + + opp-480000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + usb2_dvfs_opp_table: opp-table-usb2 { + compatible = "operating-points-v2"; + + opp-480000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + usb3_dvfs_opp_table: opp-table-usb3 { + compatible = "operating-points-v2"; + + opp-480000000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 46befba0bc72..83095a467b35 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -55,6 +55,8 @@ <&tegra_car 72>, <&tegra_car 74>; reset-names = "pex", "afi", "pcie_x"; + power-domains = <&pd_core>; + operating-points-v2 = <&pcie_dvfs_opp_table>; status = "disabled"; pci@1,0 { @@ -124,6 +126,8 @@ resets = <&tegra_car 28>; reset-names = "host1x"; iommus = <&mc TEGRA_SWGROUP_HC>; + power-domains = <&pd_heg>; + operating-points-v2 = <&host1x_dvfs_opp_table>; #address-cells = <1>; #size-cells = <1>; @@ -137,6 +141,8 @@ clocks = <&tegra_car TEGRA30_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + power-domains = <&pd_mpe>; + operating-points-v2 = <&mpe_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_MPE>; }; @@ -148,6 +154,8 @@ clocks = <&tegra_car TEGRA30_CLK_VI>; resets = <&tegra_car 20>; reset-names = "vi"; + power-domains = <&pd_venc>; + operating-points-v2 = <&vi_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_VI>; }; @@ -159,6 +167,8 @@ clocks = <&tegra_car TEGRA30_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + power-domains = <&pd_heg>; + operating-points-v2 = <&epp_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_EPP>; }; @@ -170,6 +180,7 @@ clocks = <&tegra_car TEGRA30_CLK_ISP>; resets = <&tegra_car 23>; reset-names = "isp"; + power-domains = <&pd_venc>; iommus = <&mc TEGRA_SWGROUP_ISP>; }; @@ -181,6 +192,8 @@ clocks = <&tegra_car TEGRA30_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + power-domains = <&pd_heg>; + operating-points-v2 = <&gr2d_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_G2>; }; @@ -194,6 +207,9 @@ resets = <&tegra_car 24>, <&tegra_car 98>; reset-names = "3d", "3d2"; + power-domains = <&pd_3d0>, <&pd_3d1>; + power-domain-names = "3d0", "3d1"; + operating-points-v2 = <&gr3d_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_NV>, <&mc TEGRA_SWGROUP_NV2>; @@ -208,6 +224,8 @@ clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp1_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_DC>; @@ -238,6 +256,8 @@ clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + power-domains = <&pd_core>; + operating-points-v2 = <&disp2_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_DCB>; @@ -268,6 +288,8 @@ clock-names = "hdmi", "parent"; resets = <&tegra_car 51>; reset-names = "hdmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&hdmi_dvfs_opp_table>; status = "disabled"; }; @@ -276,6 +298,8 @@ reg = <0x542c0000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_TVO>; + power-domains = <&pd_core>; + operating-points-v2 = <&tvo_dvfs_opp_table>; status = "disabled"; }; @@ -287,6 +311,8 @@ clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; + power-domains = <&pd_core>; + operating-points-v2 = <&dsia_dvfs_opp_table>; status = "disabled"; }; @@ -298,6 +324,8 @@ clock-names = "dsi", "parent"; resets = <&tegra_car 84>; reset-names = "dsi"; + power-domains = <&pd_core>; + operating-points-v2 = <&dsib_dvfs_opp_table>; status = "disabled"; }; }; @@ -358,6 +386,34 @@ reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + sclk { + compatible = "nvidia,tegra30-sclk"; + clocks = <&tegra_car TEGRA30_CLK_SCLK>; + power-domains = <&pd_core>; + operating-points-v2 = <&sclk_dvfs_opp_table>; + }; + + pll-c { + compatible = "nvidia,tegra30-pllc"; + clocks = <&tegra_car TEGRA30_CLK_PLL_C>; + power-domains = <&pd_core>; + operating-points-v2 = <&pll_c_dvfs_opp_table>; + }; + + pll-e { + compatible = "nvidia,tegra30-plle"; + clocks = <&tegra_car TEGRA30_CLK_PLL_E>; + power-domains = <&pd_core>; + operating-points-v2 = <&pll_e_dvfs_opp_table>; + }; + + pll-m { + compatible = "nvidia,tegra30-pllm"; + clocks = <&tegra_car TEGRA30_CLK_PLL_M>; + power-domains = <&pd_core>; + operating-points-v2 = <&pll_m_dvfs_opp_table>; + }; }; flow-controller@60007000 { @@ -468,6 +524,8 @@ reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; iommus = <&mc TEGRA_SWGROUP_VDE>; + power-domains = <&pd_vde>; + operating-points-v2 = <&vde_dvfs_opp_table>; }; apbmisc@70000800 { @@ -565,6 +623,8 @@ clock-names = "gmi"; resets = <&tegra_car 42>; reset-names = "gmi"; + power-domains = <&pd_core>; + operating-points-v2 = <&nor_dvfs_opp_table>; status = "disabled"; }; @@ -575,6 +635,8 @@ clocks = <&tegra_car TEGRA30_CLK_PWM>; resets = <&tegra_car 17>; reset-names = "pwm"; + power-domains = <&pd_core>; + operating-points-v2 = <&pwm_dvfs_opp_table>; status = "disabled"; }; @@ -676,6 +738,8 @@ reset-names = "spi"; dmas = <&apbdma 15>, <&apbdma 15>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc1_dvfs_opp_table>; status = "disabled"; }; @@ -690,6 +754,8 @@ reset-names = "spi"; dmas = <&apbdma 16>, <&apbdma 16>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc2_dvfs_opp_table>; status = "disabled"; }; @@ -704,6 +770,8 @@ reset-names = "spi"; dmas = <&apbdma 17>, <&apbdma 17>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc3_dvfs_opp_table>; status = "disabled"; }; @@ -718,6 +786,8 @@ reset-names = "spi"; dmas = <&apbdma 18>, <&apbdma 18>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc4_dvfs_opp_table>; status = "disabled"; }; @@ -732,6 +802,8 @@ reset-names = "spi"; dmas = <&apbdma 27>, <&apbdma 27>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc5_dvfs_opp_table>; status = "disabled"; }; @@ -746,6 +818,8 @@ reset-names = "spi"; dmas = <&apbdma 28>, <&apbdma 28>; dma-names = "rx", "tx"; + power-domains = <&pd_core>; + operating-points-v2 = <&sbc6_dvfs_opp_table>; status = "disabled"; }; @@ -765,6 +839,72 @@ clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; + + pd_core: core-domain { + #power-domain-cells = <0>; + operating-points-v2 = <&core_opp_table>; + }; + + powergates { + pd_3d0: td { + clocks = <&tegra_car TEGRA30_CLK_GR3D>; + resets = <&mc TEGRA30_MC_RESET_3D>, + <&tegra_car TEGRA30_CLK_GR3D>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_3d1: td2 { + clocks = <&tegra_car TEGRA30_CLK_GR3D2>; + resets = <&mc TEGRA30_MC_RESET_3D2>, + <&tegra_car TEGRA30_CLK_GR3D2>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA30_CLK_ISP>, + <&tegra_car TEGRA30_CLK_VI>, + <&tegra_car TEGRA30_CLK_CSI>; + resets = <&mc TEGRA30_MC_RESET_ISP>, + <&mc TEGRA30_MC_RESET_VI>, + <&tegra_car TEGRA30_CLK_ISP>, + <&tegra_car 20 /* VI */>, + <&tegra_car TEGRA30_CLK_CSI>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_vde: vdec { + clocks = <&tegra_car TEGRA30_CLK_VDE>; + resets = <&mc TEGRA30_MC_RESET_VDE>, + <&tegra_car TEGRA30_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_mpe: mpe { + clocks = <&tegra_car TEGRA30_CLK_MPE>; + resets = <&mc TEGRA30_MC_RESET_MPE>, + <&tegra_car TEGRA30_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_heg: heg { + clocks = <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + resets = <&mc TEGRA30_MC_RESET_2D>, + <&mc TEGRA30_MC_RESET_EPP>, + <&mc TEGRA30_MC_RESET_HC>, + <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; }; mc: memory-controller@7000f000 { @@ -785,6 +925,7 @@ reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_EMC>; + power-domains = <&pd_core>; nvidia,memory-controller = <&mc>; operating-points-v2 = <&emc_icc_dvfs_opp_table>; @@ -799,6 +940,8 @@ clock-names = "fuse"; resets = <&tegra_car 39>; reset-names = "fuse"; + power-domains = <&pd_core>; + operating-points-v2 = <&fuse_burn_dvfs_opp_table>; }; tsensor: tsensor@70014000 { @@ -921,6 +1064,8 @@ clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; status = "disabled"; }; @@ -943,6 +1088,8 @@ clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; + power-domains = <&pd_core>; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; status = "disabled"; }; @@ -967,6 +1114,8 @@ reset-names = "usb"; nvidia,needs-double-reset; nvidia,phy = <&phy1>; + power-domains = <&pd_core>; + operating-points-v2 = <&usbd_dvfs_opp_table>; status = "disabled"; }; @@ -1008,6 +1157,8 @@ resets = <&tegra_car 58>; reset-names = "usb"; nvidia,phy = <&phy2>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb2_dvfs_opp_table>; status = "disabled"; }; @@ -1048,6 +1199,8 @@ resets = <&tegra_car 59>; reset-names = "usb"; nvidia,phy = <&phy3>; + power-domains = <&pd_core>; + operating-points-v2 = <&usb3_dvfs_opp_table>; status = "disabled"; }; -- cgit v1.2.3 From 1caf3ef4c0febbfe3180da3a57e53ebfa4a0fa3b Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:45 +0300 Subject: ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x Memory access must be blocked before hardware reset is asserted and before power is gated, otherwise a serious hardware fault is inevitable. Add reset for memory clients to the GR2D, GR3D and Host1x nodes. Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 45fe111705af..4068952cc6c0 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -40,8 +40,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA20_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; + reset-names = "host1x", "mc"; power-domains = <&pd_core>; operating-points-v2 = <&host1x_dvfs_opp_table>; @@ -98,8 +98,8 @@ reg = <0x54140000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; + resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; + reset-names = "2d", "mc"; power-domains = <&pd_core>; operating-points-v2 = <&gr2d_dvfs_opp_table>; }; @@ -108,8 +108,8 @@ compatible = "nvidia,tegra20-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; + resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; + reset-names = "3d", "mc"; power-domains = <&pd_3d>; operating-points-v2 = <&gr3d_dvfs_opp_table>; }; -- cgit v1.2.3 From 2c16be669291b7be4df37066acc331615f747182 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:46 +0300 Subject: ARM: tegra: Add Memory Client resets to Tegra30 GR2D, GR3D and Host1x Memory access must be blocked before hardware reset is asserted and before power is gated, otherwise a serious hardware fault is inevitable. Add reset for memory clients to the GR2D, GR3D and Host1x nodes. Tested-by: Peter Geis # Ouya T30 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 83095a467b35..b0160883336f 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -123,8 +123,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA30_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>; + reset-names = "host1x", "mc"; iommus = <&mc TEGRA_SWGROUP_HC>; power-domains = <&pd_heg>; operating-points-v2 = <&host1x_dvfs_opp_table>; @@ -190,8 +190,8 @@ reg = <0x54140000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; + resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>; + reset-names = "2d", "mc"; power-domains = <&pd_heg>; operating-points-v2 = <&gr2d_dvfs_opp_table>; @@ -205,8 +205,10 @@ <&tegra_car TEGRA30_CLK_GR3D2>; clock-names = "3d", "3d2"; resets = <&tegra_car 24>, - <&tegra_car 98>; - reset-names = "3d", "3d2"; + <&tegra_car 98>, + <&mc TEGRA30_MC_RESET_3D>, + <&mc TEGRA30_MC_RESET_3D2>; + reset-names = "3d", "3d2", "mc", "mc2"; power-domains = <&pd_3d0>, <&pd_3d1>; power-domain-names = "3d0", "3d1"; operating-points-v2 = <&gr3d_dvfs_opp_table>; -- cgit v1.2.3 From 279e7aa30424ea900d34ef3a540e2f26a930353d Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:47 +0300 Subject: ARM: tegra20/30: Disable unused host1x hardware MPE, VI, EPP and ISP were never used and we don't have drivers for them. Since these modules are enabled by default in a device-tree, a device is created for them, blocking voltage scaling because there is no driver to bind, and thus, state of PMC driver is never synced. Disable them. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 4 ++++ arch/arm/boot/dts/tegra30.dtsi | 8 ++++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 4068952cc6c0..c8f2061b927f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -59,6 +59,7 @@ reset-names = "mpe"; power-domains = <&pd_mpe>; operating-points-v2 = <&mpe_dvfs_opp_table>; + status = "disabled"; }; vi@54080000 { @@ -70,6 +71,7 @@ reset-names = "vi"; power-domains = <&pd_venc>; operating-points-v2 = <&vi_dvfs_opp_table>; + status = "disabled"; }; epp@540c0000 { @@ -81,6 +83,7 @@ reset-names = "epp"; power-domains = <&pd_core>; operating-points-v2 = <&epp_dvfs_opp_table>; + status = "disabled"; }; isp@54100000 { @@ -91,6 +94,7 @@ resets = <&tegra_car 23>; reset-names = "isp"; power-domains = <&pd_venc>; + status = "disabled"; }; gr2d@54140000 { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index b0160883336f..dc1f86309672 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -145,6 +145,8 @@ operating-points-v2 = <&mpe_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_MPE>; + + status = "disabled"; }; vi@54080000 { @@ -158,6 +160,8 @@ operating-points-v2 = <&vi_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_VI>; + + status = "disabled"; }; epp@540c0000 { @@ -171,6 +175,8 @@ operating-points-v2 = <&epp_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_EPP>; + + status = "disabled"; }; isp@54100000 { @@ -183,6 +189,8 @@ power-domains = <&pd_venc>; iommus = <&mc TEGRA_SWGROUP_ISP>; + + status = "disabled"; }; gr2d@54140000 { -- cgit v1.2.3 From dcbc40848de4f07a0c92a348a57d078e881292c9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:22 +0300 Subject: ARM: tegra: Add S/PDIF node to Tegra20 device-tree Add S/PDIF node to Tegra20 device-tree. It's needed for enabling HDMI audio support. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index c8f2061b927f..2d2f446373b2 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -189,6 +189,7 @@ reset-names = "hdmi"; power-domains = <&pd_core>; operating-points-v2 = <&hdmi_dvfs_opp_table>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -388,6 +389,23 @@ status = "disabled"; }; + tegra_spdif: spdif@70002400 { + compatible = "nvidia,tegra20-spdif"; + reg = <0x70002400 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>, + <&tegra_car TEGRA20_CLK_SPDIF_IN>; + clock-names = "out", "in"; + resets = <&tegra_car 10>; + dmas = <&apbdma 3>, <&apbdma 3>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>; + }; + tegra_i2s1: i2s@70002800 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; -- cgit v1.2.3 From dd2cac867a786cb13821f98afd6730761ebc0773 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:23 +0300 Subject: ARM: tegra: Add HDMI audio graph to Tegra20 device-tree Add HDMI audio graph to Tegra20 device-tree to enable HDMI audio on Tegra20 devices. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 2d2f446373b2..1bf5bd5efd93 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -178,7 +178,7 @@ }; }; - hdmi@54280000 { + tegra_hdmi: hdmi@54280000 { compatible = "nvidia,tegra20-hdmi"; reg = <0x54280000 0x00040000>; interrupts = ; @@ -1040,4 +1040,24 @@ interrupt-affinity = <&{/cpus/cpu@0}>, <&{/cpus/cpu@1}>; }; + + sound-hdmi { + compatible = "simple-audio-card"; + simple-audio-card,name = "NVIDIA Tegra20 HDMI"; + + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + + cpu { + sound-dai = <&tegra_spdif>; + }; + + codec { + sound-dai = <&tegra_hdmi>; + }; + }; + }; }; -- cgit v1.2.3 From 7a53acabf80fc7b3462c52da4eb04daa213c7619 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:24 +0300 Subject: ARM: tegra: acer-a500: Enable S/PDIF and HDMI audio Enable S/PDIF controller to enable HDMI audio support on Acer A500. Use nvidia,fixed-parent-rate property that prevents audio rate conflict between S/PDIF and I2S. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 4aa0eb0c50fe..a170a4ba36c1 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -376,8 +376,16 @@ }; }; + tegra_spdif: spdif@70002400 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + tegra_i2s1: i2s@70002800 { status = "okay"; + + nvidia,fixed-parent-rate; }; uartb: serial@70006040 { -- cgit v1.2.3 From 919be27fd0046ed2554f1ff9cbd49d3798446cb5 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sat, 4 Dec 2021 17:37:25 +0300 Subject: ARM: tegra: paz00: Enable S/PDIF and HDMI audio Enable S/PDIF controller to enable HDMI audio support on Toshiba AC100. Use nvidia,fixed-parent-rate property that prevents audio rate conflict between S/PDIF and I2S. Tested-by: Agneli Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-paz00.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index fe1bffedc266..d53a175dc17a 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -264,8 +264,16 @@ }; }; + spdif@70002400 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + i2s@70002800 { status = "okay"; + + nvidia,fixed-parent-rate; }; serial@70006000 { -- cgit v1.2.3 From 9ca9a608a787f0f67adea8757fad86d6632c6232 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 26 Jul 2018 17:40:25 +0200 Subject: ARM: tegra: Add back gpio-ranges properties The properties have been commented out to prevent a regression a while ago. The first regression should be resolved by commit 44af7927316e ("spi: Map SPI OF client IRQ at probe time"). The second regression is probably addressed by commit 494fd7b7ad10 ("PM / core: fix deferred probe breaking suspend resume order") and/or maybe others. Readd the gpio-ranges properties to see whether regressions still get reported. This reverts commit 4f1d841475e1 ("ARM: tegra: Comment out gpio-ranges properties"). Signed-off-by: Stefan Agner Reviewed-by: Dmitry Osipenko Tested-by: Dmitry Osipenko [treding@nvidia.com: drop redundant gpio-ranges from Ouya DTS file] Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 2 -- arch/arm/boot/dts/tegra124.dtsi | 2 -- arch/arm/boot/dts/tegra20.dtsi | 2 -- arch/arm/boot/dts/tegra30-ouya.dts | 4 ---- arch/arm/boot/dts/tegra30.dtsi | 2 -- 5 files changed, 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index ae1be90a9385..f20be4ca16a1 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -261,9 +261,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; - /* gpio-ranges = <&pinmux 0 0 246>; - */ }; vde@6001a000 { diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index e87da6c24f7c..ada152b50ade 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -308,9 +308,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; - /* gpio-ranges = <&pinmux 0 0 251>; - */ }; apbdma: dma@60020000 { diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 1bf5bd5efd93..62bf0b306472 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -328,9 +328,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; - /* gpio-ranges = <&pinmux 0 0 224>; - */ }; vde@6001a000 { diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index e604ad08a2c2..a5cfbab5f565 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -68,10 +68,6 @@ }; }; - gpio: gpio@6000d000 { - gpio-ranges = <&pinmux 0 0 248>; - }; - pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index dc1f86309672..9dab8d2c158a 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -507,9 +507,7 @@ gpio-controller; #interrupt-cells = <2>; interrupt-controller; - /* gpio-ranges = <&pinmux 0 0 248>; - */ }; vde@6001a000 { -- cgit v1.2.3 From 3951cc6bae4cd252a2efec5bad5d30265d525e0f Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 16 Dec 2021 09:41:07 +0100 Subject: ARM: dts: imx6: phytec: Add PEB-WLBT-05 support The PEB-WLBT-05 is equipped with a Sterling-LWB radio module, which is capable of Wi-Fi 802.11 b/g/n and Bluetooth 4.2. Signed-off-by: Yunus Bas Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts | 1 + arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts | 1 + arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts | 1 + .../boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi | 85 ++++++++++++++++++++ arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts | 1 + .../boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 1 + .../boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi | 90 ++++++++++++++++++++++ .../boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 1 + .../boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts | 1 + .../boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi | 19 +++++ 10 files changed, 201 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts index 8165fae2b1d1..d906a7f05aaa 100644 --- a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts index bbf5097ca974..322f071d972f 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts @@ -10,6 +10,7 @@ #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts index 95051e18324f..3f13726c8058 100644 --- a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi new file mode 100644 index 000000000000..84f884d6e55b --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +#include +#include + +/ { + reg_wl_en: regulator-wl-en { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wl>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + status = "disabled"; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_bt>; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_wl>; + vmmc-supply = <®_wl_en>; + bus-width = <4>; + non-removable; + no-1-8-v; + status = "disabled"; + + brmcf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl_uart3_bt: uart3grp-bt { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0xb0b1 /* BT ENABLE */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0xb0b1 /* DEV WAKEUP */ + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0xb0b1 /* HOST WAKEUP */ + >; + }; + + pinctrl_usdhc3_wl: usdhc3grp-wl { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_wl: wlgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0xb0b1 /* WLAN ENABLE */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts index 343639cb035c..a18266598d39 100644 --- a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6qdl-phytec-mira.dtsi" #include "imx6qdl-phytec-mira-peb-eval-01.dtsi" #include "imx6qdl-phytec-mira-peb-av-02.dtsi" +#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts index bff98e676980..607eddc5030f 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6ul-phytec-segin.dtsi" #include "imx6ul-phytec-segin-peb-eval-01.dtsi" #include "imx6ul-phytec-segin-peb-av-02.dtsi" +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi new file mode 100644 index 000000000000..04477fd4b9a9 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +#include +#include + +/ { + reg_wl_en: regulator-wl-en { + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wl>; + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3031 /* BT ENABLE */ + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3031 /* HOST WAKEUP */ + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x3031 /* DEV WAKEUP */ + >; + }; + + pinctrl_uart2_bt: uart2grp-bt { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x17059 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x17059 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x17059 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x17059 + >; + }; + + pinctrl_usdhc2_wl: usdhc2grp-wl { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x10051 + MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10061 + MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x10051 + MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x10051 + MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x10051 + MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x10051 + >; + }; + + pinctrl_wl: wlgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 /* WLAN ENABLE */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt &pinctrl_bt>; + uart-has-rtscts; + status = "disabled"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_wl>; + vmmc-supply = <®_wl_en>; + bus-width = <4>; + non-removable; + no-1-8-v; + status = "disabled"; + + brmcf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts index c8d3eff9ed4b..1d7362b5ac91 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts @@ -10,6 +10,7 @@ #include "imx6ull-phytec-segin.dtsi" #include "imx6ull-phytec-segin-peb-eval-01.dtsi" #include "imx6ull-phytec-segin-peb-av-02.dtsi" +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND"; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts index e168494e0a6d..4bcbae024d8d 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6ull-phytec-phycore-som.dtsi" #include "imx6ull-phytec-segin.dtsi" #include "imx6ull-phytec-segin-peb-eval-01.dtsi" +#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND"; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi new file mode 100644 index 000000000000..df25814a3371 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi" + +&iomuxc { + /delete-node/ wlgrp; +}; + +&iomuxc_snvs { + pinctrl_wl: wlgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 + >; + }; +}; -- cgit v1.2.3 From 251cc826be7dec61e574b291b371362c10dd84ea Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 30 Oct 2021 18:52:58 +0100 Subject: ARM: 9154/1: decompressor: do not copy source files while building As commit 7ae4a78daacf ("ARM: 8969/1: decompressor: simplify libfdt builds") stated, copying source files during the build time may not end up with as clean code as expected. Do similar for the other library files for further cleanups of the Makefile and .gitignore. Signed-off-by: Masahiro Yamada Signed-off-by: Russell King (Oracle) --- arch/arm/boot/compressed/.gitignore | 5 ----- arch/arm/boot/compressed/Makefile | 33 +++------------------------------ arch/arm/boot/compressed/ashldi3.S | 3 +++ arch/arm/boot/compressed/bswapsdi2.S | 3 +++ arch/arm/boot/compressed/font.c | 2 ++ arch/arm/boot/compressed/hyp-stub.S | 2 ++ arch/arm/boot/compressed/lib1funcs.S | 3 +++ scripts/remove-stale-files | 2 +- 8 files changed, 17 insertions(+), 36 deletions(-) create mode 100644 arch/arm/boot/compressed/ashldi3.S create mode 100644 arch/arm/boot/compressed/bswapsdi2.S create mode 100644 arch/arm/boot/compressed/font.c create mode 100644 arch/arm/boot/compressed/hyp-stub.S create mode 100644 arch/arm/boot/compressed/lib1funcs.S (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore index 60606b0f378d..d32f41778437 100644 --- a/arch/arm/boot/compressed/.gitignore +++ b/arch/arm/boot/compressed/.gitignore @@ -1,9 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -ashldi3.S -bswapsdi2.S -font.c -lib1funcs.S -hyp-stub.S piggy_data vmlinux vmlinux.lds diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 91265e7ff672..74d2f1401acb 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -13,7 +13,6 @@ ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y) OBJS += debug.o AFLAGS_head.o += -DDEBUG endif -FONTC = $(srctree)/lib/fonts/font_acorn_8x8.c # string library code (-Os is enforced to keep it much smaller) OBJS += string.o @@ -99,11 +98,8 @@ $(foreach o, $(libfdt_objs) atags_to_fdt.o fdt_check_mem_start.o, \ $(eval CFLAGS_$(o) := -I $(srctree)/scripts/dtc/libfdt -fno-stack-protector)) targets := vmlinux vmlinux.lds piggy_data piggy.o \ - lib1funcs.o ashldi3.o bswapsdi2.o \ head.o $(OBJS) -clean-files += lib1funcs.S ashldi3.S bswapsdi2.S hyp-stub.S - KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin \ @@ -134,23 +130,7 @@ endif # Next argument is a linker script LDFLAGS_vmlinux += -T -# For __aeabi_uidivmod -lib1funcs = $(obj)/lib1funcs.o - -$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S - $(call cmd,shipped) - -# For __aeabi_llsl -ashldi3 = $(obj)/ashldi3.o - -$(obj)/ashldi3.S: $(srctree)/arch/$(SRCARCH)/lib/ashldi3.S - $(call cmd,shipped) - -# For __bswapsi2, __bswapdi2 -bswapsdi2 = $(obj)/bswapsdi2.o - -$(obj)/bswapsdi2.S: $(srctree)/arch/$(SRCARCH)/lib/bswapsdi2.S - $(call cmd,shipped) +OBJS += lib1funcs.o ashldi3.o bswapsdi2.o # We need to prevent any GOTOFF relocs being used with references # to symbols in the .bss section since we cannot relocate them @@ -175,8 +155,8 @@ fi efi-obj-$(CONFIG_EFI_STUB) := $(objtree)/drivers/firmware/efi/libstub/lib.a $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.o \ - $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) $(ashldi3) \ - $(bswapsdi2) $(efi-obj-y) FORCE + $(addprefix $(obj)/, $(OBJS)) \ + $(efi-obj-y) FORCE @$(check_for_multiple_zreladdr) $(call if_changed,ld) @$(check_for_bad_syms) @@ -187,11 +167,4 @@ $(obj)/piggy_data: $(obj)/../Image FORCE $(obj)/piggy.o: $(obj)/piggy_data CFLAGS_font.o := -Dstatic= - -$(obj)/font.c: $(FONTC) - $(call cmd,shipped) - AFLAGS_hyp-stub.o := -Wa,-march=armv7-a - -$(obj)/hyp-stub.S: $(srctree)/arch/$(SRCARCH)/kernel/hyp-stub.S - $(call cmd,shipped) diff --git a/arch/arm/boot/compressed/ashldi3.S b/arch/arm/boot/compressed/ashldi3.S new file mode 100644 index 000000000000..216f82eda609 --- /dev/null +++ b/arch/arm/boot/compressed/ashldi3.S @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* For __aeabi_llsl */ +#include "../../lib/ashldi3.S" diff --git a/arch/arm/boot/compressed/bswapsdi2.S b/arch/arm/boot/compressed/bswapsdi2.S new file mode 100644 index 000000000000..b2156b378c7b --- /dev/null +++ b/arch/arm/boot/compressed/bswapsdi2.S @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* For __bswapsi2, __bswapdi2 */ +#include "../../lib/bswapsdi2.S" diff --git a/arch/arm/boot/compressed/font.c b/arch/arm/boot/compressed/font.c new file mode 100644 index 000000000000..46a677649db4 --- /dev/null +++ b/arch/arm/boot/compressed/font.c @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "../../../../lib/fonts/font_acorn_8x8.c" diff --git a/arch/arm/boot/compressed/hyp-stub.S b/arch/arm/boot/compressed/hyp-stub.S new file mode 100644 index 000000000000..a703eaa86f10 --- /dev/null +++ b/arch/arm/boot/compressed/hyp-stub.S @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include "../../kernel/hyp-stub.S" diff --git a/arch/arm/boot/compressed/lib1funcs.S b/arch/arm/boot/compressed/lib1funcs.S new file mode 100644 index 000000000000..815dec73ba4d --- /dev/null +++ b/arch/arm/boot/compressed/lib1funcs.S @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* For __aeabi_uidivmod */ +#include "../../lib/lib1funcs.S" diff --git a/scripts/remove-stale-files b/scripts/remove-stale-files index 0114c41e6938..f0d53227fe7b 100755 --- a/scripts/remove-stale-files +++ b/scripts/remove-stale-files @@ -24,7 +24,7 @@ set -e # with O=, make sure to remove the stale files in the output tree. Otherwise, # the build system wrongly compiles the stale ones. if [ -n "${building_out_of_srctree}" ]; then - for f in fdt_rw.c fdt_ro.c fdt_wip.c fdt.c + for f in fdt_rw.c fdt_ro.c fdt_wip.c fdt.c ashldi3.S bswapsdi2.S font.c lib1funcs.S hyp-stub.S do rm -f arch/arm/boot/compressed/${f} done -- cgit v1.2.3 From 4a2f57ac7dada84224d71fe895580990b9062d68 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 15 Nov 2021 08:57:12 +0100 Subject: ARM: 9158/1: leave it to core code to manage thread_info::cpu Since commit bcf9033e5449 ("sched: move CPU field back into thread_info if THREAD_INFO_IN_TASK=y"), the CPU field in thread_info went back to being managed by the core code, so we no longer have to keep it in sync in arch code. While at it, mark THREAD_INFO_IN_TASK as done for ARM in the documentation. Reviewed-by: Linus Walleij Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King (Oracle) --- .../features/core/thread-info-in-task/arch-support.txt | 2 +- arch/arm/include/asm/switch_to.h | 14 -------------- arch/arm/kernel/smp.c | 3 --- 3 files changed, 1 insertion(+), 18 deletions(-) (limited to 'arch/arm') diff --git a/Documentation/features/core/thread-info-in-task/arch-support.txt b/Documentation/features/core/thread-info-in-task/arch-support.txt index 3361e86b0958..bc74d8beea72 100644 --- a/Documentation/features/core/thread-info-in-task/arch-support.txt +++ b/Documentation/features/core/thread-info-in-task/arch-support.txt @@ -8,7 +8,7 @@ ----------------------- | alpha: | TODO | | arc: | TODO | - | arm: | TODO | + | arm: | ok | | arm64: | ok | | csky: | TODO | | h8300: | TODO | diff --git a/arch/arm/include/asm/switch_to.h b/arch/arm/include/asm/switch_to.h index b55c7b2755e4..61e4a3c4ca6e 100644 --- a/arch/arm/include/asm/switch_to.h +++ b/arch/arm/include/asm/switch_to.h @@ -23,23 +23,9 @@ */ extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *); -static inline void set_ti_cpu(struct task_struct *p) -{ -#ifdef CONFIG_THREAD_INFO_IN_TASK - /* - * The core code no longer maintains the thread_info::cpu field once - * CONFIG_THREAD_INFO_IN_TASK is in effect, but we rely on it for - * raw_smp_processor_id(), which cannot access struct task_struct* - * directly for reasons of circular #inclusion hell. - */ - task_thread_info(p)->cpu = task_cpu(p); -#endif -} - #define switch_to(prev,next,last) \ do { \ __complete_pending_tlbi(); \ - set_ti_cpu(next); \ if (IS_ENABLED(CONFIG_CURRENT_POINTER_IN_TPIDRURO)) \ __this_cpu_write(__entry_task, next); \ last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \ diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index cde5b6d8bac5..97ee6b1567e9 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -154,9 +154,6 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir); #endif secondary_data.task = idle; - if (IS_ENABLED(CONFIG_THREAD_INFO_IN_TASK)) - task_thread_info(idle)->cpu = cpu; - sync_cache_w(&secondary_data); /* -- cgit v1.2.3 From a92882a4d270fbcc021ee6848de5e48b7f0d27f3 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 22 Nov 2021 16:28:43 +0100 Subject: ARM: 9159/1: decompressor: Avoid UNPREDICTABLE NOP encoding In the decompressor's head.S we need to start with an instruction that is some kind of NOP, but also mimics as the PE/COFF header, when the kernel is linked as an UEFI application. The clever solution here is "tstne r0, #0x4d000", which in the worst case just clobbers the condition flags, and bears the magic "MZ" signature in the lowest 16 bits. However the encoding used (0x13105a4d) is actually not valid, since bits [15:12] are supposed to be 0 (written as "(0)" in the ARM ARM). Violating this is UNPREDICTABLE, and *can* trigger an UNDEFINED exception. Common Cortex cores seem to ignore those bits, but QEMU chooses to trap, so the code goes fishing because of a missing exception handler at this point. We are just saved by the fact that commonly (with -kernel or when running from U-Boot) the "Z" bit is set, so the instruction is never executed. See [0] for more details. To make things more robust and avoid UNPREDICTABLE behaviour in the kernel code, lets replace this with a "two-instruction NOP": The first instruction is an exclusive OR, the effect of which the second instruction reverts. This does not leave any trace, neither in a register nor in the condition flags. Also it's a perfectly valid encoding. Kudos to Peter Maydell for coming up with this gem. [0] https://lore.kernel.org/qemu-devel/YTPIdbUCmwagL5%2FD@os.inf.tu-dresden.de/T/ Link: https://lore.kernel.org/linux-arm-kernel/20210908162617.104962-1-andre.przywara@arm.com/T/ Fixes: 81a0bc39ea19 ("ARM: add UEFI stub support") Signed-off-by: Andre Przywara Reported-by: Adam Lackorzynski Suggested-by: Peter Maydell Reviewed-by: Ard Biesheuvel Reviewed-by: Linus Walleij Signed-off-by: Russell King (Oracle) --- arch/arm/boot/compressed/efi-header.S | 22 ++++++++++++++-------- arch/arm/boot/compressed/head.S | 3 ++- 2 files changed, 16 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/efi-header.S b/arch/arm/boot/compressed/efi-header.S index c0e7a745103e..230030c13085 100644 --- a/arch/arm/boot/compressed/efi-header.S +++ b/arch/arm/boot/compressed/efi-header.S @@ -9,16 +9,22 @@ #include .macro __nop -#ifdef CONFIG_EFI_STUB - @ This is almost but not quite a NOP, since it does clobber the - @ condition flags. But it is the best we can do for EFI, since - @ PE/COFF expects the magic string "MZ" at offset 0, while the - @ ARM/Linux boot protocol expects an executable instruction - @ there. - .inst MZ_MAGIC | (0x1310 << 16) @ tstne r0, #0x4d000 -#else AR_CLASS( mov r0, r0 ) M_CLASS( nop.w ) + .endm + + .macro __initial_nops +#ifdef CONFIG_EFI_STUB + @ This is a two-instruction NOP, which happens to bear the + @ PE/COFF signature "MZ" in the first two bytes, so the kernel + @ is accepted as an EFI binary. Booting via the UEFI stub + @ will not execute those instructions, but the ARM/Linux + @ boot protocol does, so we need some NOPs here. + .inst MZ_MAGIC | (0xe225 << 16) @ eor r5, r5, 0x4d000 + eor r5, r5, 0x4d000 @ undo previous insn +#else + __nop + __nop #endif .endm diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index b1cb1972361b..bf79f2f78d23 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -203,7 +203,8 @@ start: * were patching the initial instructions of the kernel, i.e * had started to exploit this "patch area". */ - .rept 7 + __initial_nops + .rept 5 __nop .endr #ifndef CONFIG_THUMB2_KERNEL -- cgit v1.2.3 From d0eae8287cf3dff6670e7e9910159942bda45a20 Mon Sep 17 00:00:00 2001 From: Wang Kefeng Date: Fri, 3 Dec 2021 10:21:42 +0100 Subject: ARM: 9161/1: mm: mark private VM_FAULT_X defines as vm_fault_t This fixes several sparse warnings for fault.c: arch/arm/mm/fault.c:210:24: sparse: expected restricted vm_fault_t arch/arm/mm/fault.c:210:24: sparse: got int ... arch/arm/mm/fault.c:345:24: sparse: sparse: restricted vm_fault_t degrades to integer Reported-by: kernel test robot Fixes: caed89dab0ca ("ARM: 9128/1: mm: Refactor the __do_page_fault()") Signed-off-by: Kefeng Wang Signed-off-by: Russell King (Oracle) --- arch/arm/mm/fault.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index bc8779d54a64..013921a5909b 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -191,8 +191,8 @@ void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs) } #ifdef CONFIG_MMU -#define VM_FAULT_BADMAP 0x010000 -#define VM_FAULT_BADACCESS 0x020000 +#define VM_FAULT_BADMAP ((__force vm_fault_t)0x010000) +#define VM_FAULT_BADACCESS ((__force vm_fault_t)0x020000) static inline bool is_permission_fault(unsigned int fsr) { -- cgit v1.2.3 From 0ba8695e3dfbbc78ed716805678119121d33a730 Mon Sep 17 00:00:00 2001 From: Wang Kefeng Date: Fri, 3 Dec 2021 10:26:31 +0100 Subject: ARM: 9164/1: mm: Provide set_memory_valid() This function validates and invalidates PTE entries, it will be used in the later patch. Acked-by: Marco Elver Signed-off-by: Kefeng Wang Signed-off-by: Russell King (Oracle) --- arch/arm/include/asm/set_memory.h | 1 + arch/arm/mm/pageattr.c | 42 +++++++++++++++++++++++++++++---------- 2 files changed, 33 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/set_memory.h b/arch/arm/include/asm/set_memory.h index ec17fc0fda7a..0211b9c5b14d 100644 --- a/arch/arm/include/asm/set_memory.h +++ b/arch/arm/include/asm/set_memory.h @@ -11,6 +11,7 @@ int set_memory_ro(unsigned long addr, int numpages); int set_memory_rw(unsigned long addr, int numpages); int set_memory_x(unsigned long addr, int numpages); int set_memory_nx(unsigned long addr, int numpages); +int set_memory_valid(unsigned long addr, int numpages, int enable); #else static inline int set_memory_ro(unsigned long addr, int numpages) { return 0; } static inline int set_memory_rw(unsigned long addr, int numpages) { return 0; } diff --git a/arch/arm/mm/pageattr.c b/arch/arm/mm/pageattr.c index 9790ae3a8c68..c3c34fe714b0 100644 --- a/arch/arm/mm/pageattr.c +++ b/arch/arm/mm/pageattr.c @@ -32,14 +32,31 @@ static bool in_range(unsigned long start, unsigned long size, size <= range_end - start; } +/* + * This function assumes that the range is mapped with PAGE_SIZE pages. + */ +static int __change_memory_common(unsigned long start, unsigned long size, + pgprot_t set_mask, pgprot_t clear_mask) +{ + struct page_change_data data; + int ret; + + data.set_mask = set_mask; + data.clear_mask = clear_mask; + + ret = apply_to_page_range(&init_mm, start, size, change_page_range, + &data); + + flush_tlb_kernel_range(start, start + size); + return ret; +} + static int change_memory_common(unsigned long addr, int numpages, pgprot_t set_mask, pgprot_t clear_mask) { unsigned long start = addr & PAGE_MASK; unsigned long end = PAGE_ALIGN(addr) + numpages * PAGE_SIZE; unsigned long size = end - start; - int ret; - struct page_change_data data; WARN_ON_ONCE(start != addr); @@ -50,14 +67,7 @@ static int change_memory_common(unsigned long addr, int numpages, !in_range(start, size, VMALLOC_START, VMALLOC_END)) return -EINVAL; - data.set_mask = set_mask; - data.clear_mask = clear_mask; - - ret = apply_to_page_range(&init_mm, start, size, change_page_range, - &data); - - flush_tlb_kernel_range(start, end); - return ret; + return __change_memory_common(start, size, set_mask, clear_mask); } int set_memory_ro(unsigned long addr, int numpages) @@ -87,3 +97,15 @@ int set_memory_x(unsigned long addr, int numpages) __pgprot(0), __pgprot(L_PTE_XN)); } + +int set_memory_valid(unsigned long addr, int numpages, int enable) +{ + if (enable) + return __change_memory_common(addr, PAGE_SIZE * numpages, + __pgprot(L_PTE_VALID), + __pgprot(0)); + else + return __change_memory_common(addr, PAGE_SIZE * numpages, + __pgprot(0), + __pgprot(L_PTE_VALID)); +} -- cgit v1.2.3 From 3c341b217414d1d63718438f2b2fa588cf2b73fc Mon Sep 17 00:00:00 2001 From: Wang Kefeng Date: Fri, 3 Dec 2021 10:26:32 +0100 Subject: ARM: 9165/1: mm: Provide is_write_fault() The function will check whether the fault is caused by a write access, it will be called in die_kernel_fault() too in next patch, so put it before the function of die_kernel_fault(). Acked-by: Marco Elver Signed-off-by: Kefeng Wang Signed-off-by: Russell King (Oracle) --- arch/arm/mm/fault.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 013921a5909b..1d41e8fad4f3 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -99,6 +99,11 @@ void show_pte(const char *lvl, struct mm_struct *mm, unsigned long addr) { } #endif /* CONFIG_MMU */ +static inline bool is_write_fault(unsigned int fsr) +{ + return (fsr & FSR_WRITE) && !(fsr & FSR_CM); +} + static void die_kernel_fault(const char *msg, struct mm_struct *mm, unsigned long addr, unsigned int fsr, struct pt_regs *regs) @@ -261,7 +266,7 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) if (user_mode(regs)) flags |= FAULT_FLAG_USER; - if ((fsr & FSR_WRITE) && !(fsr & FSR_CM)) { + if (is_write_fault(fsr)) { flags |= FAULT_FLAG_WRITE; vm_flags = VM_WRITE; } -- cgit v1.2.3 From 75969686ec0df23157afe24dc818d7bddb087d78 Mon Sep 17 00:00:00 2001 From: Wang Kefeng Date: Fri, 3 Dec 2021 10:26:33 +0100 Subject: ARM: 9166/1: Support KFENCE for ARM Add architecture specific implementation details for KFENCE and enable KFENCE on ARM. In particular, this implements the required interface in . KFENCE requires that attributes for pages from its memory pool can individually be set. Therefore, force the kfence pool to be mapped at page granularity. Testing this patch using the testcases in kfence_test.c and all passed with or without ARM_LPAE. Acked-by: Marco Elver Signed-off-by: Kefeng Wang Signed-off-by: Russell King (Oracle) --- arch/arm/Kconfig | 1 + arch/arm/include/asm/kfence.h | 53 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/mm/fault.c | 9 ++++++-- 3 files changed, 61 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/kfence.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0f9e8bec83a..321b0a1c2820 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -69,6 +69,7 @@ config ARM select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU + select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL select HAVE_ARCH_MMAP_RND_BITS if MMU diff --git a/arch/arm/include/asm/kfence.h b/arch/arm/include/asm/kfence.h new file mode 100644 index 000000000000..7980d0f2271f --- /dev/null +++ b/arch/arm/include/asm/kfence.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __ASM_ARM_KFENCE_H +#define __ASM_ARM_KFENCE_H + +#include + +#include +#include + +static inline int split_pmd_page(pmd_t *pmd, unsigned long addr) +{ + int i; + unsigned long pfn = PFN_DOWN(__pa(addr)); + pte_t *pte = pte_alloc_one_kernel(&init_mm); + + if (!pte) + return -ENOMEM; + + for (i = 0; i < PTRS_PER_PTE; i++) + set_pte_ext(pte + i, pfn_pte(pfn + i, PAGE_KERNEL), 0); + pmd_populate_kernel(&init_mm, pmd, pte); + + flush_tlb_kernel_range(addr, addr + PMD_SIZE); + return 0; +} + +static inline bool arch_kfence_init_pool(void) +{ + unsigned long addr; + pmd_t *pmd; + + for (addr = (unsigned long)__kfence_pool; is_kfence_address((void *)addr); + addr += PAGE_SIZE) { + pmd = pmd_off_k(addr); + + if (pmd_leaf(*pmd)) { + if (split_pmd_page(pmd, addr & PMD_MASK)) + return false; + } + } + + return true; +} + +static inline bool kfence_protect_page(unsigned long addr, bool protect) +{ + set_memory_valid(addr, 1, !protect); + + return true; +} + +#endif /* __ASM_ARM_KFENCE_H */ diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 1d41e8fad4f3..a1cebe363ed5 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -136,10 +137,14 @@ __do_kernel_fault(struct mm_struct *mm, unsigned long addr, unsigned int fsr, /* * No handler, we'll have to terminate things with extreme prejudice. */ - if (addr < PAGE_SIZE) + if (addr < PAGE_SIZE) { msg = "NULL pointer dereference"; - else + } else { + if (kfence_handle_page_fault(addr, is_write_fault(fsr), regs)) + return; + msg = "paging request"; + } die_kernel_fault(msg, mm, addr, fsr, regs); } -- cgit v1.2.3 From 2965d4290f6052a9e7b47bad6ff648b867293488 Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Fri, 10 Dec 2021 14:49:43 +0100 Subject: ARM: 9167/1: Add support for Cortex-M33 processor Cortex-M33 is the first feature rich implementation of the Armv8-M architecture (still compatible with v7M) Signed-off-by: Vladimir Murzin Signed-off-by: Russell King (Oracle) --- arch/arm/mm/proc-v7m.S | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index 84459c1d31b8..fc1263710d0f 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S @@ -193,6 +193,16 @@ ENDPROC(__v7m_setup) .long \cache_fns .endm + /* + * Match ARM Cortex-M33 processor. + */ + .type __v7m_cm33_proc_info, #object +__v7m_cm33_proc_info: + .long 0x410fd210 /* ARM Cortex-M33 0xD21 */ + .long 0xff0ffff0 /* Mask off revision, patch release */ + __v7m_proc __v7m_cm33_proc_info, __v7m_setup, hwcaps = HWCAP_EDSP + .size __v7m_cm33_proc_info, . - __v7m_cm33_proc_info + /* * Match ARM Cortex-M7 processor. */ -- cgit v1.2.3 From 3d14751f341e4778f967f2799eceef23a2dba8a0 Mon Sep 17 00:00:00 2001 From: Tigran Tadevosyan Date: Fri, 10 Dec 2021 14:50:31 +0100 Subject: ARM: 9168/1: Add support for Cortex-M55 processor Add processor info object for ARM Cortex-M55 CPU which inherits the setup procedure, the processor and cache operation function from Cortex-M7 processor info object. Signed-off-by: Tigran Tadevosyan Signed-off-by: Vladimir Murzin Signed-off-by: Russell King (Oracle) --- arch/arm/mm/proc-v7m.S | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index fc1263710d0f..335144d50134 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S @@ -193,6 +193,16 @@ ENDPROC(__v7m_setup) .long \cache_fns .endm + /* + * Match ARM Cortex-M55 processor. + */ + .type __v7m_cm55_proc_info, #object +__v7m_cm55_proc_info: + .long 0x410fd220 /* ARM Cortex-M55 0xD22 */ + .long 0xff0ffff0 /* Mask off revision, patch release */ + __v7m_proc __v7m_cm55_proc_info, __v7m_cm7_setup, hwcaps = HWCAP_EDSP, cache_fns = v7m_cache_fns, proc_fns = cm7_processor_functions + .size __v7m_cm55_proc_info, . - __v7m_cm55_proc_info + /* * Match ARM Cortex-M33 processor. */ -- cgit v1.2.3 From b0343ab330ae4d6c8d4210de5c16da704c2d4743 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 13 May 2021 10:59:23 +0100 Subject: ARM: reduce the information printed in call traces A while back, Linus complained about the numeric values printed by the ARM backtracing code. Printing these values does not make sense if one does not have access to the kernel ELF image (as is normally the case when helping a third party on a mailing list), but if one does, they can be very useful to find the code, rather than searching for the function name, and then doing hex math to work out where the backtrace entry is referring to. Provide an option to control whether this information is included, which will only be visible if EXPERT is enabled. Signed-off-by: Russell King --- arch/arm/Kconfig.debug | 11 +++++++++++ arch/arm/kernel/traps.c | 8 +++++--- 2 files changed, 16 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 98436702e0c7..07055a503022 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -81,6 +81,17 @@ endchoice config ARM_UNWIND bool +config BACKTRACE_VERBOSE + bool "Verbose backtrace" + depends on EXPERT + help + When the kernel produces a warning or oops, the kernel prints a + trace of the call chain. This option controls whether we include + the numeric addresses or only include the symbolic information. + + In most cases, say N here, unless you are intending to debug the + kernel and have access to the kernel binary image. + config FRAME_POINTER bool diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 195dff58bafc..c5e25cf7219b 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -67,12 +67,14 @@ void dump_backtrace_entry(unsigned long where, unsigned long from, { unsigned long end = frame + 4 + sizeof(struct pt_regs); -#ifdef CONFIG_KALLSYMS +#ifndef CONFIG_KALLSYMS + printk("%sFunction entered at [<%08lx>] from [<%08lx>]\n", + loglvl, where, from); +#elif defined CONFIG_BACKTRACE_VERBOSE printk("%s[<%08lx>] (%ps) from [<%08lx>] (%pS)\n", loglvl, where, (void *)where, from, (void *)from); #else - printk("%sFunction entered at [<%08lx>] from [<%08lx>]\n", - loglvl, where, from); + printk("%s %ps from %pS\n", loglvl, (void *)where, (void *)from); #endif if (in_entry_text(from) && end <= ALIGN(frame, THREAD_SIZE)) -- cgit v1.2.3 From 473dcf0ffc31ce1135cd10578e7e06698cf51f4a Mon Sep 17 00:00:00 2001 From: Alexandre Ghiti Date: Thu, 16 Dec 2021 10:44:22 +0100 Subject: Documentation, arch: Remove leftovers from raw device Raw device interface was removed so remove all references to configs related to it. Fixes: 603e4922f1c8 ("remove the raw driver") Signed-off-by: Alexandre Ghiti Acked-by: Arnd Bergmann [arch/arm/configs] Signed-off-by: Arnd Bergmann --- Documentation/admin-guide/devices.txt | 8 +------- arch/arm/configs/spear13xx_defconfig | 1 - arch/arm/configs/spear3xx_defconfig | 1 - arch/arm/configs/spear6xx_defconfig | 1 - arch/powerpc/configs/pseries_defconfig | 1 - 5 files changed, 1 insertion(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/Documentation/admin-guide/devices.txt b/Documentation/admin-guide/devices.txt index 922c23bb4372..c07dc0ee860e 100644 --- a/Documentation/admin-guide/devices.txt +++ b/Documentation/admin-guide/devices.txt @@ -2339,13 +2339,7 @@ disks (see major number 3) except that the limit on partitions is 31. - 162 char Raw block device interface - 0 = /dev/rawctl Raw I/O control device - 1 = /dev/raw/raw1 First raw I/O device - 2 = /dev/raw/raw2 Second raw I/O device - ... - max minor number of raw device is set by kernel config - MAX_RAW_DEVS or raw module parameter 'max_raw_devs' + 162 char Used for (now removed) raw block device interface 163 char diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig index 3b206a31902f..065553326b39 100644 --- a/arch/arm/configs/spear13xx_defconfig +++ b/arch/arm/configs/spear13xx_defconfig @@ -61,7 +61,6 @@ CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_RAW_DRIVER=y -CONFIG_MAX_RAW_DEVS=8192 CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig index fc5f71c765ed..afca722d6605 100644 --- a/arch/arm/configs/spear3xx_defconfig +++ b/arch/arm/configs/spear3xx_defconfig @@ -41,7 +41,6 @@ CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_RAW_DRIVER=y -CONFIG_MAX_RAW_DEVS=8192 CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig index 52a56b8ce6a7..bc32c02cb86b 100644 --- a/arch/arm/configs/spear6xx_defconfig +++ b/arch/arm/configs/spear6xx_defconfig @@ -36,7 +36,6 @@ CONFIG_INPUT_FF_MEMLESS=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_RAW_DRIVER=y -CONFIG_MAX_RAW_DEVS=8192 CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig index de7641adb899..e64f2242abe1 100644 --- a/arch/powerpc/configs/pseries_defconfig +++ b/arch/powerpc/configs/pseries_defconfig @@ -189,7 +189,6 @@ CONFIG_HVCS=m CONFIG_VIRTIO_CONSOLE=m CONFIG_IBM_BSR=m CONFIG_RAW_DRIVER=y -CONFIG_MAX_RAW_DEVS=1024 CONFIG_I2C_CHARDEV=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y -- cgit v1.2.3 From 2ac7069ad7647cd1d9ca5b08765a1e116e13cdc4 Mon Sep 17 00:00:00 2001 From: Alexandre Ghiti Date: Thu, 16 Dec 2021 10:44:23 +0100 Subject: Documentation, arch: Remove leftovers from CIFS_WEAK_PW_HASH This config was removed so remove all references to it. Fixes: 76a3c92ec9e0 ("cifs: remove support for NTLM and weaker authentication algorithms") Signed-off-by: Alexandre Ghiti Reviewed-by: Steve French Acked-by: Arnd Bergmann [arch/arm/configs] Acked-by: Thomas Bogendoerfer Signed-off-by: Arnd Bergmann --- Documentation/admin-guide/cifs/usage.rst | 7 +++---- arch/arm/configs/cm_x300_defconfig | 1 - arch/arm/configs/ezx_defconfig | 1 - arch/arm/configs/imote2_defconfig | 1 - arch/arm/configs/nhk8815_defconfig | 1 - arch/arm/configs/pxa_defconfig | 1 - arch/mips/configs/fuloong2e_defconfig | 1 - arch/mips/configs/malta_qemu_32r6_defconfig | 1 - arch/mips/configs/maltaaprp_defconfig | 1 - arch/mips/configs/maltasmvp_defconfig | 1 - arch/mips/configs/maltasmvp_eva_defconfig | 1 - arch/mips/configs/maltaup_defconfig | 1 - arch/powerpc/configs/ppc6xx_defconfig | 1 - arch/sh/configs/titan_defconfig | 1 - 14 files changed, 3 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/Documentation/admin-guide/cifs/usage.rst b/Documentation/admin-guide/cifs/usage.rst index f170d8820258..3766bf8a1c20 100644 --- a/Documentation/admin-guide/cifs/usage.rst +++ b/Documentation/admin-guide/cifs/usage.rst @@ -734,10 +734,9 @@ SecurityFlags Flags which control security negotiation and using weaker password hashes is 0x37037 (lanman, plaintext, ntlm, ntlmv2, signing allowed). Some SecurityFlags require the corresponding menuconfig - options to be enabled (lanman and plaintext require - CONFIG_CIFS_WEAK_PW_HASH for example). Enabling - plaintext authentication currently requires also - enabling lanman authentication in the security flags + options to be enabled. Enabling plaintext + authentication currently requires also enabling + lanman authentication in the security flags because the cifs module only supports sending laintext passwords using the older lanman dialect form of the session setup SMB. (e.g. for authentication diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig index 502a9d870ca4..45769d0ddd4e 100644 --- a/arch/arm/configs/cm_x300_defconfig +++ b/arch/arm/configs/cm_x300_defconfig @@ -146,7 +146,6 @@ CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_PARTITION_ADVANCED=y CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_ISO8859_1=m diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig index a49e699e52de..ec84d80096b1 100644 --- a/arch/arm/configs/ezx_defconfig +++ b/arch/arm/configs/ezx_defconfig @@ -314,7 +314,6 @@ CONFIG_NFSD_V3_ACL=y CONFIG_SMB_FS=m CONFIG_CIFS=m CONFIG_CIFS_STATS=y -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig index 118c4c927f26..6db871d4e077 100644 --- a/arch/arm/configs/imote2_defconfig +++ b/arch/arm/configs/imote2_defconfig @@ -288,7 +288,6 @@ CONFIG_NFSD_V3_ACL=y CONFIG_SMB_FS=m CONFIG_CIFS=m CONFIG_CIFS_STATS=y -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index 23595fc5a29a..907d6512821a 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig @@ -127,7 +127,6 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3_ACL=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig index 58f4834289e6..dedaaae3d0d8 100644 --- a/arch/arm/configs/pxa_defconfig +++ b/arch/arm/configs/pxa_defconfig @@ -699,7 +699,6 @@ CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_CIFS=m CONFIG_CIFS_STATS=y -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_DEFAULT="utf8" diff --git a/arch/mips/configs/fuloong2e_defconfig b/arch/mips/configs/fuloong2e_defconfig index 5c24ac7fdf56..ba47c5e929b7 100644 --- a/arch/mips/configs/fuloong2e_defconfig +++ b/arch/mips/configs/fuloong2e_defconfig @@ -206,7 +206,6 @@ CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_CIFS=m CONFIG_CIFS_STATS2=y -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_CIFS_DEBUG2=y diff --git a/arch/mips/configs/malta_qemu_32r6_defconfig b/arch/mips/configs/malta_qemu_32r6_defconfig index 614af02d83e6..6fb9bc29f4a0 100644 --- a/arch/mips/configs/malta_qemu_32r6_defconfig +++ b/arch/mips/configs/malta_qemu_32r6_defconfig @@ -165,7 +165,6 @@ CONFIG_TMPFS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/mips/configs/maltaaprp_defconfig b/arch/mips/configs/maltaaprp_defconfig index 9c051f8fd330..eb72df528243 100644 --- a/arch/mips/configs/maltaaprp_defconfig +++ b/arch/mips/configs/maltaaprp_defconfig @@ -166,7 +166,6 @@ CONFIG_TMPFS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/mips/configs/maltasmvp_defconfig b/arch/mips/configs/maltasmvp_defconfig index 2e90d97551d6..1fb40d310f49 100644 --- a/arch/mips/configs/maltasmvp_defconfig +++ b/arch/mips/configs/maltasmvp_defconfig @@ -167,7 +167,6 @@ CONFIG_TMPFS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/mips/configs/maltasmvp_eva_defconfig b/arch/mips/configs/maltasmvp_eva_defconfig index d1f7fdb27284..75cb778c6149 100644 --- a/arch/mips/configs/maltasmvp_eva_defconfig +++ b/arch/mips/configs/maltasmvp_eva_defconfig @@ -169,7 +169,6 @@ CONFIG_TMPFS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/mips/configs/maltaup_defconfig b/arch/mips/configs/maltaup_defconfig index 48e5bd492452..7b4f247dc60c 100644 --- a/arch/mips/configs/maltaup_defconfig +++ b/arch/mips/configs/maltaup_defconfig @@ -165,7 +165,6 @@ CONFIG_TMPFS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_NLS_CODEPAGE_437=m diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig index 6697c5e6682f..bb549cb1c3e3 100644 --- a/arch/powerpc/configs/ppc6xx_defconfig +++ b/arch/powerpc/configs/ppc6xx_defconfig @@ -1022,7 +1022,6 @@ CONFIG_NFSD=m CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_UPCALL=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y diff --git a/arch/sh/configs/titan_defconfig b/arch/sh/configs/titan_defconfig index ba887f1351be..cd5c58916c65 100644 --- a/arch/sh/configs/titan_defconfig +++ b/arch/sh/configs/titan_defconfig @@ -242,7 +242,6 @@ CONFIG_NFSD=y CONFIG_NFSD_V3=y CONFIG_SMB_FS=m CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_PARTITION_ADVANCED=y CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_ASCII=m -- cgit v1.2.3 From b59e11495b1a0e94d6357ce5df54e24ecbeb8319 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 17 Dec 2021 14:51:51 +0100 Subject: ARM: tegra: Add memory client hotflush resets on Tegra114 Add the host1x, gr2d and gr3d memory client hotflush resets on Tegra114. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index f20be4ca16a1..09996acad639 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -38,8 +38,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA114_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>; + reset-names = "host1x", "mc"; iommus = <&mc TEGRA_SWGROUP_HC>; #address-cells = <1>; @@ -52,8 +52,8 @@ reg = <0x54140000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; + resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; + reset-names = "2d", "mc"; iommus = <&mc TEGRA_SWGROUP_G2>; }; @@ -62,8 +62,8 @@ compatible = "nvidia,tegra114-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; + resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; + reset-names = "3d", "mc"; iommus = <&mc TEGRA_SWGROUP_NV>; }; -- cgit v1.2.3 From bd048487af68a9782ebccc3af6606e9e0d7d9f8b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 17 Dec 2021 14:52:37 +0100 Subject: ARM: tegra: Add host1x hotflush reset on Tegra124 Add the host1x memory client hotflush reset on Tegra124. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index ada152b50ade..a9ab548781e1 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -94,8 +94,8 @@ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA124_CLK_HOST1X>; clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; + resets = <&tegra_car 28>, <&mc TEGRA124_MC_RESET_HC>; + reset-names = "host1x", "mc"; iommus = <&mc TEGRA_SWGROUP_HC>; #address-cells = <2>; -- cgit v1.2.3 From 3b2e5d74e25fe6aae6e9427cdbdc2d82586ddc16 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 9 Dec 2021 17:37:44 +0200 Subject: ARM: configs: at91: sama7: Enable SPI NOR and QSPI controller sama7g5ek comes with a SPI NOR flash connected to the QSPI controller. Enable the SPI NOR subsystem and the QSPI controller. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211209153744.357465-2-tudor.ambarus@microchip.com --- arch/arm/configs/sama7_defconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig index 938aae4bd80b..0368068e04d9 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -33,7 +33,6 @@ CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y # CONFIG_EFI_PARTITION is not set # CONFIG_COREDUMP is not set @@ -83,6 +82,7 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y CONFIG_MTD_TESTS=m CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 @@ -90,6 +90,7 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_EEPROM_AT24=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y +# CONFIG_BLK_DEV_BSG is not set CONFIG_NETDEVICES=y CONFIG_MACB=y CONFIG_MICREL_PHY=y @@ -104,8 +105,8 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_AT91=y CONFIG_SPI=y -CONFIG_SPI_MEM=y CONFIG_SPI_ATMEL=y +CONFIG_SPI_ATMEL_QUADSPI=y CONFIG_SPI_GPIO=y CONFIG_PINCTRL_AT91=y CONFIG_PINCTRL_AT91PIO4=y -- cgit v1.2.3 From e1137bcefa025ec4c583e85d6c86c9ba11133224 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Wed, 15 Dec 2021 15:43:11 +0200 Subject: ARM: configs: at91: Enable crypto software implementations Enable at least the same amount of algs as the hardware IPs are supporting so that they are able to fallback to the software implementations in case they need it. Signed-off-by: Tudor Ambarus Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211215134311.304427-1-tudor.ambarus@microchip.com --- arch/arm/configs/at91_dt_defconfig | 9 ++++++++- arch/arm/configs/sama5_defconfig | 8 ++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index a6310c8abcc3..549d01be0b47 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -216,7 +216,14 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y -CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=y +CONFIG_CRYPTO_OFB=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_DEV_ATMEL_AES=y diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index fe0d7ccc8fb2..03dd80c2a19e 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -232,6 +232,14 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=y +CONFIG_CRYPTO_OFB=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_DEV_ATMEL_AES=y -- cgit v1.2.3 From 62480772263ab6b52e758f2346c70a526abd1d28 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Tue, 9 Nov 2021 17:46:04 +0100 Subject: ARM: dts: armada-38x: Add generic compatible to UART nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add generic compatible string "ns16550a" to serial port nodes of Armada 38x. This makes it possible to use earlycon. Fixes: 0d3d96ab0059 ("ARM: mvebu: add Device Tree description of the Armada 380/385 SoCs") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-38x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 9b1a24cc5e91..df3c8d1d8f64 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -168,7 +168,7 @@ }; uart0: serial@12000 { - compatible = "marvell,armada-38x-uart"; + compatible = "marvell,armada-38x-uart", "ns16550a"; reg = <0x12000 0x100>; reg-shift = <2>; interrupts = ; @@ -178,7 +178,7 @@ }; uart1: serial@12100 { - compatible = "marvell,armada-38x-uart"; + compatible = "marvell,armada-38x-uart", "ns16550a"; reg = <0x12100 0x100>; reg-shift = <2>; interrupts = ; -- cgit v1.2.3 From 13391025039fe86c68741e45a8b7bc158c69d68e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 2 Dec 2021 15:14:13 -0800 Subject: ARM: dts: Cygnus: Fixed iProc PCIe controller properties Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. We also need to re-arrange the 'ranges' property to show the two cells as being separate instead of combined since the DT checker is not able to differentiate otherwise. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 8ecb7861ce10..e73a19409d71 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -274,8 +274,8 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; phys = <&pcie0_phy>; phy-names = "pcie-phy"; @@ -283,7 +283,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -309,8 +309,8 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; phys = <&pcie1_phy>; phy-names = "pcie-phy"; @@ -318,7 +318,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; -- cgit v1.2.3 From 89b9492c113c4a22361f32639c6af041bcada2b6 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Dec 2021 16:06:22 -0800 Subject: ARM: dts: Cygnus: Update PCIe PHY node unit name(s) Update the PCIe PHY node unit name and its sub-nodes to help with upcoming changes converting the Cygnus PCIe PHY DT binding to YAML and later the iProc PCIe controller binding to YAML. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index e73a19409d71..ad65be871938 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -112,18 +112,18 @@ status = "disabled"; }; - pcie_phy: phy@301d0a0 { + pcie_phy: pcie_phy@301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; #address-cells = <1>; #size-cells = <0>; - pcie0_phy: phy@0 { + pcie0_phy: pcie-phy@0 { reg = <0>; #phy-cells = <0>; }; - pcie1_phy: phy@1 { + pcie1_phy: pcie-phy@1 { reg = <1>; #phy-cells = <0>; }; -- cgit v1.2.3 From d2b820bb16c509b313b87f616dcf6aa612d01fb9 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 2 Dec 2021 15:15:27 -0800 Subject: ARM: dts: HR2: Fixed iProc PCIe MSI sub-node Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-hr2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index 84cda16f68a2..33e6ba63a1ee 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -318,7 +318,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -354,7 +354,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; -- cgit v1.2.3 From 69c4e53bdd055ecc27761f6971a50c631ff9072e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 2 Dec 2021 15:16:27 -0800 Subject: ARM: dts: NSP: Fixed iProc PCIe MSI sub-node Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 1c08daa18858..f242763c3bde 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -587,7 +587,7 @@ status = "disabled"; msi-parent = <&msi0>; - msi0: msi-controller { + msi0: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -624,7 +624,7 @@ status = "disabled"; msi-parent = <&msi1>; - msi1: msi-controller { + msi1: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; @@ -661,7 +661,7 @@ status = "disabled"; msi-parent = <&msi2>; - msi2: msi-controller { + msi2: msi { compatible = "brcm,iproc-msi"; msi-controller; interrupt-parent = <&gic>; -- cgit v1.2.3 From 9a68c53f875e88edd3403c001ad85f4ac0ed3486 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Dec 2021 10:19:09 -0800 Subject: ARM: dts: NSP: Rename SATA unit name Rename the SATA controller unit name from ahci to sata in preparation for adding the Broadcom SATA3 controller YAML binding which will bring validation. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index f242763c3bde..5b1dc58d40ba 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -534,7 +534,7 @@ }; }; - sata: ahci@41000 { + sata: sata@41000 { compatible = "brcm,bcm-nsp-ahci"; reg-names = "ahci", "top-ctrl"; reg = <0x41000 0x1000>, <0x40020 0x1c>; -- cgit v1.2.3 From 5e33f1c4a7cb914a003a304ab8eef705b17aabb7 Mon Sep 17 00:00:00 2001 From: Arınç ÜNAL Date: Fri, 17 Dec 2021 00:03:19 +0800 Subject: ARM: dts: BCM5301X: correct RX delay and enable flow control on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current 'rx-internal-delay-ps' property value on the Realtek switch node, 2000, will be divided by 300, resulting in 6.66, which will be rounded to the closest step value, 7. Change it to 2100 to be accurate. See ef136837aaf6 ("net: dsa: rtl8365mb: set RGMII RX delay in steps of 0.3 ns") for reference. Flow control needs to be enabled on both sides of the internal and external switch. It is already enabled on the CPU port of the Realtek switch so we also enable it on the external switch port of the Broadcom switch as well. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 16dea851719f..df8199fd4eb4 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -138,7 +138,7 @@ ethernet = <&sw0_p5>; phy-mode = "rgmii"; tx-internal-delay-ps = <2000>; - rx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2100>; fixed-link { speed = <1000>; @@ -213,6 +213,7 @@ fixed-link { speed = <1000>; full-duplex; + pause; }; }; -- cgit v1.2.3 From 8a3804c030e44335890bc9ca70cfa987488d9ec6 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 17 Dec 2021 16:12:32 -0600 Subject: ARM: dts: Remove "spidev" nodes "spidev" is not a real device, but a Linux implementation detail. It has never been documented either. The kernel has WARNed on the use of it for over 6 years. Time to remove its usage from the tree. Signed-off-by: Rob Herring Acked-by: Nicolas Ferre Acked-by: Viresh Kumar Cc: Mark Brown Link: https://lore.kernel.org/r/20211217221232.3664417-1-robh@kernel.org' Reviwed-by: Mark Brown Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/at91-q5xr5.dts | 18 ----------- arch/arm/boot/dts/at91-wb50n.dts | 6 ---- arch/arm/boot/dts/imx28-tx28.dts | 36 ---------------------- arch/arm/boot/dts/imx53-tx53.dtsi | 11 ------- arch/arm/boot/dts/imx6qdl-tx6.dtsi | 12 -------- arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi | 12 -------- arch/arm/boot/dts/imx6ul-prti6g.dts | 6 ---- arch/arm/boot/dts/imx6ul-tx6ul.dtsi | 24 --------------- arch/arm/boot/dts/omap3-tao3530.dtsi | 14 --------- .../boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts | 2 +- arch/arm/boot/dts/spear1310-evb.dts | 16 ---------- arch/arm/boot/dts/spear1340-evb.dts | 16 ---------- 12 files changed, 1 insertion(+), 172 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-q5xr5.dts b/arch/arm/boot/dts/at91-q5xr5.dts index 5827383b181b..47a00062f01f 100644 --- a/arch/arm/boot/dts/at91-q5xr5.dts +++ b/arch/arm/boot/dts/at91-q5xr5.dts @@ -147,12 +147,6 @@ reg = <0x8000 0x3E000>; }; }; - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <2000000>; - reg = <1>; - }; }; &spi1 { @@ -160,18 +154,6 @@ pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>; cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>; status = "okay"; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <2000000>; - reg = <0>; - }; - - spidev@1 { - compatible = "spidev"; - spi-max-frequency = <2000000>; - reg = <1>; - }; }; &usart0 { diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts index a5e45bb95c04..89f0f717f7ed 100644 --- a/arch/arm/boot/dts/at91-wb50n.dts +++ b/arch/arm/boot/dts/at91-wb50n.dts @@ -90,12 +90,6 @@ &spi1 { status = "okay"; - - spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <8000000>; - }; }; &usb0 { diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 164254c28f8e..9e5651c7ea6b 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -239,24 +239,6 @@ >; /* enable this and disable ssp3 below, if you need full duplex SPI transfer */ status = "disabled"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <57600000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <57600000>; - }; - - spi@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <57600000>; - }; }; }; @@ -700,24 +682,6 @@ pinctrl-0 = <&spi3_pins_a>; clock-frequency = <57600000>; status = "okay"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <57600000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <57600000>; - }; - - spi@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <57600000>; - }; }; &usb0 { diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index 7c9730f3f820..81c2726a328a 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -192,17 +192,6 @@ &gpio3 19 GPIO_ACTIVE_HIGH >; - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <54000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <54000000>; - }; }; &esdhc1 { diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index 362e65ccaa78..bcc5bbcce769 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -259,18 +259,6 @@ &gpio3 19 GPIO_ACTIVE_HIGH >; status = "disabled"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <54000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <54000000>; - }; }; &fec { diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi index 935a77d717a6..18cac19aa9b0 100644 --- a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi +++ b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi @@ -114,18 +114,6 @@ pinctrl-0 = <&pinctrl_ecspi4>; cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>; status = "okay"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <5000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <5000000>; - }; }; &i2c1 { diff --git a/arch/arm/boot/dts/imx6ul-prti6g.dts b/arch/arm/boot/dts/imx6ul-prti6g.dts index d62015701d0a..c18390f238e1 100644 --- a/arch/arm/boot/dts/imx6ul-prti6g.dts +++ b/arch/arm/boot/dts/imx6ul-prti6g.dts @@ -78,12 +78,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <1000000>; - }; }; &fec1 { diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index 938a32ced88d..c485d058e079 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -227,18 +227,6 @@ &gpio1 10 GPIO_ACTIVE_HIGH >; status = "disabled"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <660000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <660000>; - }; }; sound { @@ -290,18 +278,6 @@ &gpio1 10 GPIO_ACTIVE_HIGH >; status = "disabled"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <60000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <60000000>; - }; }; &fec1 { diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index 580bfa1931c8..7f440d11f7e7 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -197,25 +197,11 @@ &mcspi1 { pinctrl-names = "default"; pinctrl-0 = <&mcspi1_pins>; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpha; - }; }; &mcspi3 { pinctrl-names = "default"; pinctrl-0 = <&mcspi3_pins>; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpha; - }; }; #include "twl4030.dtsi" diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts index 942e3a2cac35..0827de5426c1 100644 --- a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts @@ -103,7 +103,7 @@ &gsbi3_spi { spi@0 { - compatible = "swir,mangoh-iotport-spi", "spidev"; + compatible = "swir,mangoh-iotport-spi"; spi-max-frequency = <24000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts index 8fcb6be6e7c7..4cbadcb41084 100644 --- a/arch/arm/boot/dts/spear1310-evb.dts +++ b/arch/arm/boot/dts/spear1310-evb.dts @@ -395,22 +395,6 @@ pl022,wait-state = <0>; pl022,duplex = <0>; }; - - spidev@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <25000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; }; wdt@ec800620 { diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts index f70ff56d4542..fd194ebeedc9 100644 --- a/arch/arm/boot/dts/spear1340-evb.dts +++ b/arch/arm/boot/dts/spear1340-evb.dts @@ -489,22 +489,6 @@ ts,i-drive = <1>; }; }; - - spidev@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <25000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; }; timer@ec800600 { -- cgit v1.2.3 From fea289467608ffddb2f8d3a740912047974bb183 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 17 Nov 2021 11:51:05 +0800 Subject: ARM: dts: aspeed: Add secure boot controller node The ast2600 has a secure boot controller. Signed-off-by: Joel Stanley Reviewed-by: Ryan Chen Link: https://lore.kernel.org/r/20211117035106.321454-3-joel@jms.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 5106a424f1ce..16b36c13695a 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -384,6 +384,11 @@ status = "disabled"; }; + sbc: secure-boot-controller@1e6f2000 { + compatible = "aspeed,ast2600-sbc"; + reg = <0x1e6f2000 0x1000>; + }; + gpio0: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; -- cgit v1.2.3 From 0720caa3f81d6b8c1ee5d51d3d251dc43030e687 Mon Sep 17 00:00:00 2001 From: Lei YU Date: Fri, 10 Dec 2021 17:34:43 +0800 Subject: ARM: dts: Add openbmc-flash-layout-64-alt.dtsi Add openbmc-flash-layout-64-alt.dtsi to describe the partitions of the secondary flash for OpenBMC's 64M static layout. The layout is the same as openbmc-flash-layout-64.dtsi and the labels are prepended with "alt-" for the partitions. Signed-off-by: Lei YU Reviewed-by: Patrick Williams Link: https://lore.kernel.org/r/20211210093443.2140557-1-yulei.sh@bytedance.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi new file mode 100644 index 000000000000..650525867561 --- /dev/null +++ b/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Bytedance. + */ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0xe0000>; // 896KB + label = "alt-u-boot"; + }; + + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB + label = "alt-u-boot-env"; + }; + + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB + label = "alt-kernel"; + }; + + rofs@a00000 { + reg = <0xa00000 0x2000000>; // 32MB + label = "alt-rofs"; + }; + + rwfs@6000000 { + reg = <0x2a00000 0x1600000>; // 22MB + label = "alt-rwfs"; + }; +}; -- cgit v1.2.3 From b26965e99788ea163fc217bdca1c2b17a5d70c90 Mon Sep 17 00:00:00 2001 From: Lei YU Date: Fri, 10 Dec 2021 17:36:23 +0800 Subject: ARM: dts: aspeed: g220a: Enable secondary flash Enable the secondary flash of the g220a's BMC and the wdt2. Signed-off-by: Lei YU Link: https://lore.kernel.org/r/20211210093623.2140640-1-yulei.sh@bytedance.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts index 01dace8f5e5f..0d1fb5ccfd36 100644 --- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts +++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts @@ -260,6 +260,13 @@ spi-max-frequency = <50000000>; #include "openbmc-flash-layout-64.dtsi" }; + flash@1 { + status = "okay"; + label = "alt-bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; }; &spi1 { @@ -278,6 +285,11 @@ status = "okay"; }; +&wdt2 { + status = "okay"; + aspeed,alt-boot; +}; + &gpio { status = "okay"; gpio-line-names = -- cgit v1.2.3 From a8c729e966c4e9d033242d948b0e53c2a62d32e2 Mon Sep 17 00:00:00 2001 From: Howard Chiu Date: Tue, 7 Dec 2021 17:49:24 +0800 Subject: ARM: dts: aspeed: Adding Facebook Bletchley BMC Initial introduction of Facebook Bletchley equipped with Aspeed 2600 BMC SoC. Signed-off-by: Howard Chiu Link: https://lore.kernel.org/r/20211207094923.422422-1-howard.chiu@quantatw.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 756 +++++++++++++++++++++ 2 files changed, 757 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 78b71e02624c..6ff97305200d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1482,6 +1482,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ aspeed-bmc-bytedance-g220a.dtb \ + aspeed-bmc-facebook-bletchley.dtb \ aspeed-bmc-facebook-cloudripper.dtb \ aspeed-bmc-facebook-cmm.dtb \ aspeed-bmc-facebook-elbert.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts new file mode 100644 index 000000000000..f973ea883b97 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -0,0 +1,756 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2021 Facebook Inc. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model = "Facebook Bletchley BMC"; + compatible = "facebook,bletchley-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + bootargs = "console=ttyS4,57600n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + spi_gpio: spi-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + gpio-sck = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + + tpmdev@0 { + compatible = "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; + + switchphy: ethernet-phy@0 { + // Fixed link + }; + + leds { + compatible = "gpio-leds"; + + sys_log_id { + retain-state-shutdown; + default-state = "keep"; + gpios = <&front_leds 0 GPIO_ACTIVE_HIGH>; + }; + fan0_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_ioexp 8 GPIO_ACTIVE_HIGH>; + }; + fan1_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_ioexp 9 GPIO_ACTIVE_HIGH>; + }; + fan2_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_ioexp 10 GPIO_ACTIVE_HIGH>; + }; + fan3_blue { + retain-state-shutdown; + default-state = "on"; + gpios = <&fan_ioexp 11 GPIO_ACTIVE_HIGH>; + }; + fan0_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_ioexp 12 GPIO_ACTIVE_HIGH>; + }; + fan1_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_ioexp 13 GPIO_ACTIVE_HIGH>; + }; + fan2_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_ioexp 14 GPIO_ACTIVE_HIGH>; + }; + fan3_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&fan_ioexp 15 GPIO_ACTIVE_HIGH>; + }; + sled0_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled0_leds 0 GPIO_ACTIVE_LOW>; + }; + sled0_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled0_leds 1 GPIO_ACTIVE_LOW>; + }; + sled1_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled1_leds 0 GPIO_ACTIVE_LOW>; + }; + sled1_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled1_leds 1 GPIO_ACTIVE_LOW>; + }; + sled2_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled2_leds 0 GPIO_ACTIVE_LOW>; + }; + sled2_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled2_leds 1 GPIO_ACTIVE_LOW>; + }; + sled3_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled3_leds 0 GPIO_ACTIVE_LOW>; + }; + sled3_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled3_leds 1 GPIO_ACTIVE_LOW>; + }; + sled4_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled4_leds 0 GPIO_ACTIVE_LOW>; + }; + sled4_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled4_leds 1 GPIO_ACTIVE_LOW>; + }; + sled5_amber { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled5_leds 0 GPIO_ACTIVE_LOW>; + }; + sled5_blue { + retain-state-shutdown; + default-state = "off"; + gpios = <&sled5_leds 1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&switchphy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&rtc { + status = "okay"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + +&i2c0 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled0_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED0_MS_DETECT1","SLED0_VBUS_BMC_EN","SLED0_INA230_ALERT","SLED0_P12V_STBY_ALERT", + "SLED0_SSD_ALERT","SLED0_MS_DETECT0","SLED0_RST_CCG5","SLED0_FUSB302_INT", + "SLED0_MD_STBY_RESET","SLED0_MD_IOEXP_EN_FAULT","SLED0_MD_DIR","SLED0_MD_DECAY", + "SLED0_MD_MODE1","SLED0_MD_MODE2","SLED0_MD_MODE3","power-host0"; + }; + + sled0_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled0-amber","led-sled0-blue","SLED0_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled0_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c1 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled1_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED1_MS_DETECT1","SLED1_VBUS_BMC_EN","SLED1_INA230_ALERT","SLED1_P12V_STBY_ALERT", + "SLED1_SSD_ALERT","SLED1_MS_DETECT0","SLED1_RST_CCG5","SLED1_FUSB302_INT", + "SLED1_MD_STBY_RESET","SLED1_MD_IOEXP_EN_FAULT","SLED1_MD_DIR","SLED1_MD_DECAY", + "SLED1_MD_MODE1","SLED1_MD_MODE2","SLED1_MD_MODE3","power-host1"; + }; + + sled1_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled1-amber","led-sled1-blue","SLED1_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled1_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled2_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED2_MS_DETECT1","SLED2_VBUS_BMC_EN","SLED2_INA230_ALERT","SLED2_P12V_STBY_ALERT", + "SLED2_SSD_ALERT","SLED2_MS_DETECT0","SLED2_RST_CCG5","SLED2_FUSB302_INT", + "SLED2_MD_STBY_RESET","SLED2_MD_IOEXP_EN_FAULT","SLED2_MD_DIR","SLED2_MD_DECAY", + "SLED2_MD_MODE1","SLED2_MD_MODE2","SLED2_MD_MODE3","power-host2"; + }; + + sled2_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled2-amber","led-sled2-blue","SLED2_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled2_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c3 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled3_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED3_MS_DETECT1","SLED3_VBUS_BMC_EN","SLED3_INA230_ALERT","SLED3_P12V_STBY_ALERT", + "SLED3_SSD_ALERT","SLED3_MS_DETECT0","SLED3_RST_CCG5","SLED3_FUSB302_INT", + "SLED3_MD_STBY_RESET","SLED3_MD_IOEXP_EN_FAULT","SLED3_MD_DIR","SLED3_MD_DECAY", + "SLED3_MD_MODE1","SLED3_MD_MODE2","SLED3_MD_MODE3","power-host3"; + }; + + sled3_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled3-amber","led-sled3-blue","SLED3_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled3_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c4 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled4_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED4_MS_DETECT1","SLED4_VBUS_BMC_EN","SLED4_INA230_ALERT","SLED4_P12V_STBY_ALERT", + "SLED4_SSD_ALERT","SLED4_MS_DETECT0","SLED4_RST_CCG5","SLED4_FUSB302_INT", + "SLED4_MD_STBY_RESET","SLED4_MD_IOEXP_EN_FAULT","SLED4_MD_DIR","SLED4_MD_DECAY", + "SLED4_MD_MODE1","SLED4_MD_MODE2","SLED4_MD_MODE3","power-host4"; + }; + + sled4_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled4-amber","led-sled4-blue","SLED4_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled4_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c5 { + status = "okay"; + /* TODO: Add ADC INA230 */ + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled5_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED5_MS_DETECT1","SLED5_VBUS_BMC_EN","SLED5_INA230_ALERT","SLED5_P12V_STBY_ALERT", + "SLED5_SSD_ALERT","SLED5_MS_DETECT0","SLED5_RST_CCG5","SLED5_FUSB302_INT", + "SLED5_MD_STBY_RESET","SLED5_MD_IOEXP_EN_FAULT","SLED5_MD_DIR","SLED5_MD_DECAY", + "SLED5_MD_MODE1","SLED5_MD_MODE2","SLED5_MD_MODE3","power-host5"; + }; + + sled5_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled5-amber","led-sled5-blue","SLED5_RST_IOEXP","", + "","","","", + "","","","", + "","","",""; + }; + + sled5_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + +&i2c6 { + status = "okay"; + + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&i2c7 { + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c9 { + status = "okay"; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; +}; + +&i2c10 { + status = "okay"; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + hdc1080@40 { + compatible = "ti,hdc1080"; + reg = <0x40>; + }; + + front_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-fault-identify","power-p5v-stby-good", + "power-p1v0-dvdd-good","power-p1v0-avdd-good", + "","","","", + "","","","", + "","","",""; + }; +}; + +&i2c12 { + status = "okay"; + + adm1278@11 { + compatible = "adi,adm1278"; + reg = <0x11>; + }; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + tmp421@4d { + compatible = "ti,tmp421"; + reg = <0x4d>; + }; + + fan_ioexp: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-fan0","presence-fan1", + "presence-fan2","presence-fan3", + "power-fan0-good","power-fan1-good", + "power-fan2-good","power-fan3-good", + "","","","", + "","","",""; + }; +}; + +&i2c13 { + multi-master; + aspeed,hw-timeout-ms = <1000>; + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","SEL_SPI2_MUX","SPI2_MUX1", + "SPI2_MUX2","SPI2_MUX3","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","SWITCH_FRU_MUX","","","","","","", + /*H0-H7*/ "presence-riser1","presence-riser2", + "presence-sled0","presence-sled1", + "presence-sled2","presence-sled3", + "presence-sled4","presence-sled5", + /*I0-I7*/ "REV_ID0","","REV_ID1","REV_ID2", + "","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "ALERT_SLED0","ALERT_SLED1", + "ALERT_SLED2","ALERT_SLED3", + "ALERT_SLED4","ALERT_SLED5", + "P12V_AUX_ALERT1","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","", + "","BOARD_ID0","BOARD_ID1","BOARD_ID2", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","BAT_DETECT", + "BMC_BT_WP0","BMC_BT_WP1","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","RST_BMC_MVL","","", + "USB2_SEL0_A","USB2_SEL1_A", + "USB2_SEL0_B","USB2_SEL1_B", + /*W0-W7*/ "RST_FRONT_IOEXP","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","BSM_FLASH_LATCH","","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + +&adc0 { + vref = <1800>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; -- cgit v1.2.3 From 4fcbe1f5b6ba71e0c464a303e3769bf1ce1fe54c Mon Sep 17 00:00:00 2001 From: Oskar Senft Date: Tue, 30 Nov 2021 13:48:55 -0500 Subject: ARM: dts: aspeed: tyan-s7106: Add uart_routing and fix vuart config Configure the vuart in such a way that it does not inhibit the SuperIO's UART from functioning correctly. This allows the same DTS to be used for both configurations with SuperIO and VUART (depending on the BIOS build). The decision on whether to actually enable VUART can then be made at runtime. This change also enables the new uart_routing driver for the SuperIO case. Signed-off-by: Oskar Senft Link: https://lore.kernel.org/r/20211130184855.1779353-1-osk@google.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts index 60ac6d3f03b5..aff27c1d4b06 100644 --- a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts +++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts @@ -3,6 +3,7 @@ #include "aspeed-g5.dtsi" #include +#include / { model = "Tyan S7106 BMC"; @@ -127,8 +128,23 @@ status = "okay"; }; +&uart_routing { + status = "okay"; +}; + &vuart { status = "okay"; + + /* We enable the VUART here, but leave it in a state that does + * not interfere with the SuperIO. The goal is to have both the + * VUART and the SuperIO available and decide at runtime whether + * the VUART should actually be used. For that reason, configure + * an "invalid" IO address and an IRQ that is not used by the + * BMC. + */ + + aspeed,lpc-io-reg = <0xffff>; + aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; }; &lpc_ctrl { -- cgit v1.2.3 From 30daf3cd8997d0ba4bda2b4a7f7c5122c81216f1 Mon Sep 17 00:00:00 2001 From: Ali El-Haj-Mahmoud Date: Tue, 30 Nov 2021 13:01:10 -0500 Subject: ARM: dts: aspeed: Add TYAN S8036 BMC machine The TYAN S8036 is a server platform with an ASPEED AST2500 BMC. Signed-off-by: Ali El-Haj-Mahmoud Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20211130180110.2217042-1-aaelhaj@google.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts | 470 ++++++++++++++++++++++++++++ 2 files changed, 471 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6ff97305200d..25005a7b5b84 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1521,6 +1521,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-supermicro-x11spi.dtb \ aspeed-bmc-inventec-transformers.dtb \ aspeed-bmc-tyan-s7106.dtb \ + aspeed-bmc-tyan-s8036.dtb \ aspeed-bmc-vegman-n110.dtb \ aspeed-bmc-vegman-rx20.dtb \ aspeed-bmc-vegman-sx20.dtb diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts new file mode 100644 index 000000000000..708ee78e4b83 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts @@ -0,0 +1,470 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include + +/ { + model = "Tyan S8036 BMC"; + compatible = "tyan,s8036-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + p2a_memory: region@987f0000 { + no-map; + reg = <0x987f0000 0x00010000>; /* 64KB */ + }; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; /* 16M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + identify { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + label = "bmc"; + status = "okay"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + }; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + /* RS-232 connector on header */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart3 { + /* Alternative to vuart to internally connect (route) to uart1 + * when vuart cannot be used due to BIOS limitations. + */ + status = "okay"; +}; + +&uart4 { + /* Alternative to vuart to internally connect (route) to the + * external port usually used by uart1 when vuart cannot be + * used due to BIOS limitations. + */ + status = "okay"; +}; + +&uart5 { + /* BMC "debug" (console) UART; connected to RS-232 connector + * on header; selectable via jumpers as alternative to uart2 + */ + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&vuart { + status = "okay"; + + /* We enable the VUART here, but leave it in a state that does + * not interfere with the SuperIO. The goal is to have both the + * VUART and the SuperIO available and decide at runtime whether + * the VUART should actually be used. For that reason, configure + * an "invalid" IO address and an IRQ that is not used by the + * BMC. + */ + aspeed,lpc-io-reg = <0xffff>; + aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&p2a { + status = "okay"; + memory-region = <&p2a_memory>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&adc { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default>; + + /* CPU fan */ + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + /* PWM group for chassis fans #1, #2, #3 and #4 */ + fan@2 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + /* PWM group for chassis fans #5 and #6 */ + fan@6 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; +}; + +&i2c0 { + /* Directly connected to Sideband-Temperature Sensor Interface (APML) */ + status = "okay"; +}; + +&i2c1 { + /* Directly connected to IPMB HDR. */ + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + /* BMC EEPROM, incl. mainboard FRU */ + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + /* Also connected to: + * - BCM5720 + * - FPGA + * - FAN HDR + * - FPIO HDR + */ +}; + +&i2c3 { + status = "okay"; + + /* PSU1 FRU @ 0xA0 */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + /* PSU2 FRU @ 0xA2 */ + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + /* PSU1 @ 0xB0 */ + power-supply@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + /* PSU2 @ 0xB2 */ + power-supply@59 { + compatible = "pmbus"; + reg = <0x59>; + }; + +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + /* Hardware monitor with temperature sensors */ + nct7802@28 { + compatible = "nuvoton,nct7802"; + reg = <0x28>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* LTD */ + reg = <0>; + status = "okay"; + }; + + channel@1 { /* RTD1 */ + reg = <1>; + status = "okay"; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@2 { /* RTD2 */ + reg = <2>; + status = "okay"; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@3 { /* RTD3 */ + reg = <3>; + status = "okay"; + sensor-type = "temperature"; + }; + }; + + /* Also connected to: + * - PCA9544 + * - CLK BUFF + * - OCP FRU + */ +}; + +&i2c6 { + status = "okay"; + /* Connected to: + * - PCA9548 @0xE0 + * - PCA9548 @0xE2 + * - PCA9544 @0xE4 + */ +}; + +&i2c7 { + status = "okay"; + + /* Connected to: + * - PCH SMBUS #4 + */ +}; + +&i2c8 { + status = "okay"; + + /* Not connected */ +}; + +&mac0 { + status = "okay"; + use-ncsi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&ibt { + status = "okay"; +}; + +&kcs1 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */ +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +/* We're following the GPIO naming as defined at + * https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md. + * + * Notes on led-identify and id-button: + * - A physical button is connected to id-button which + * triggers the clock on a D flip-flop. The /Q output of the + * flip-flop drives its D input. + * - The flip-flop's Q output drives led-identify which is + * connected to LEDs. + * - With that, every button press toggles the LED between on and off. + * + * Notes on power-, reset- and nmi- button and control: + * - The -button signals can be used to monitor physical buttons. + * - The -control signals can be used to actuate the specific + * operation. + * - In hardware, the -button signals are connected to the -control + * signals through drivers with the -control signals being + * protected through diodes. + */ +&gpio { + status = "okay"; + gpio-line-names = + /*A0*/ "", + /*A1*/ "", + /*A2*/ "led-identify", /* in/out: BMC_CHASSIS_ID_LED_L */ + /*A3*/ "", + /*A4*/ "", + /*A5*/ "", + /*A6*/ "", + /*A7*/ "", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0*/ "", + /*D1*/ "", + /*D2*/ "power-chassis-good", /* in: PWR_GOOD_LED -- Check if this is Z3?*/ + /*D3*/ "platform-reset", /* in: RESET_LED_L */ + /*D4*/ "", + /*D5*/ "", + /*D6*/ "", + /*D7*/ "", + /*E0*/ "power-button", /* in: BMC_SYS_MON_PWR_BTN_L */ + /*E1*/ "power-chassis-control", /* out: BMC_ASSERT_PWR_BTN */ + /*E2*/ "reset-button", /* in: BMC_SYS_MOS_RST_BTN_L*/ + /*E3*/ "reset-control", /* out: BMC_ASSERT_RST_BTN */ + /*E4*/ "nmi-button", /* in: BMC_SYS_MON_NMI_BTN_L */ + /*E5*/ "nmi-control", /* out: BMC_ASSERT_NMI_BTN */ + /*E6*/ "TSI_RESERT", + /*E7*/ "led-heartbeat", /* out: BMC_GPIOE7 */ + /*F0*/ "", + /*F1*/ "clear-cmos-control", /* out: BMC_ASSERT_CLR_CMOS_L */ + /*F2*/ "", + /*F3*/ "", + /*F4*/ "led-fault", /* out: BMC_HWM_FAULT_LED_L */ + /*F5*/ "BMC_SYS_FAULT_LED_L", + /*F6*/ "BMC_ASSERT_BIOS_WP_L", + /*F7*/ "", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0*/ "", + /*Q1*/ "", + /*Q2*/ "", + /*Q3*/ "", + /*Q4*/ "", + /*Q5*/ "", + /*Q6*/ "id-button", /* in: BMC_CHASSIS_ID_BTN_L */ + /*Q7*/ "", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z2*/ "","","", + /*Z3*/ "post-complete", /* BMC_SYS_MON_PWROK */ + /*Z4-Z7*/ "","","","", + /*AA0*/ "", + /*AA1*/ "", + /*AA2*/ "", + /*AA3*/ "", + /*AA4*/ "", + /*AA5*/ "", + /*AA6*/ "", + /*AA7*/ "BMC_ASSERT_BMC_READY", + /*AB0*/ "BMC_SPD_SEL", + /*AB1-AB7*/ "","","","","","",""; +}; -- cgit v1.2.3 From 1fe5c05c7c25b5ffa66d623c790f39babd2f5e7f Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 8 Dec 2021 11:06:40 -0600 Subject: ARM: dts: aspeed: p10: Enable USB host ports Ensure both controllers are enabled on, and add GPIO hog for USB power control to set the USB power to always on. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20211208170641.13322-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 12 +++++++++++- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 6 ++++++ 2 files changed, 17 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index f42e2d776ba8..3e9edc893f55 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -280,7 +280,7 @@ /*L0-L7*/ "","","","","","","","", /*M0-M7*/ "","","","","","","","", /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", + /*O0-O7*/ "","","","usb-power","","","","", /*P0-P7*/ "","","","","led-pcieslot-power","","","", /*Q0-Q7*/ "","","regulator-standby-faulted","","","","","", /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","", @@ -292,6 +292,12 @@ /*X0-X7*/ "","","","","","","","", /*Y0-Y7*/ "","","","","","","","", /*Z0-Z7*/ "","","","","","","",""; + + usb_power { + gpio-hog; + gpios = ; + output-high; + }; }; &i2c0 { @@ -2375,6 +2381,10 @@ }; }; +&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 866f32cdccea..cb7d86a2862c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -275,6 +275,12 @@ output-high; line-name = "I2C3_MUX_OE_N"; }; + + usb_power { + gpio-hog; + gpios = ; + output-high; + }; }; &emmc_controller { -- cgit v1.2.3 From 62589e873d8e7cef7efd583ace1bb6ec90f252b7 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 8 Dec 2021 13:17:57 -0600 Subject: ARM: dts: aspeed: p10: Add TPM device Add the Nuvoton NPCT75X, a TIS I2C TPM. Modified Eddie's change to include the general compatible string, and combine the rainier and everest patches. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20211208191758.20517-8-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 5 +++++ arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 3e9edc893f55..22c06ff7a7ed 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -1887,6 +1887,11 @@ &i2c12 { status = "okay"; + + tpm@2e { + compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; }; &i2c13 { diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index cb7d86a2862c..c47974219832 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -2067,6 +2067,11 @@ &i2c12 { status = "okay"; + tpm@2e { + compatible = "nuvoton,npct75x"; + reg = <0x2e>; + }; + eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; -- cgit v1.2.3 From a350dc623e3678b9bc6c6385df72a66a1ee69c7f Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo Date: Mon, 8 Nov 2021 11:01:55 -0800 Subject: ARM: dts: aspeed: add LCLK setting into LPC IBT node If LPC BT driver is registered ahead of lpc-ctrl module, LPC BT hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property setting into LPC IBT node as one of required properties to enable the LCLK by the LPC IBT driver. Note: dtbs should be re-compiled after applying this change since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo Reviewed-by: Joel Stanley Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20211108190200.290957-2-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 1 + arch/arm/boot/dts/aspeed-g5.dtsi | 1 + arch/arm/boot/dts/aspeed-g6.dtsi | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index b313a1cf5f73..f14dace34c5a 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -381,6 +381,7 @@ compatible = "aspeed,ast2400-ibt-bmc"; reg = <0x140 0x18>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index c7049454c7cb..d0cc4be2de59 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -507,6 +507,7 @@ compatible = "aspeed,ast2500-ibt-bmc"; reg = <0x140 0x18>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 16b36c13695a..539edbd7aaee 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -586,6 +586,7 @@ compatible = "aspeed,ast2600-ibt-bmc"; reg = <0x140 0x18>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; }; -- cgit v1.2.3 From 45cd8bbaaa18ab1c4f4387529db72b33be463197 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo Date: Mon, 8 Nov 2021 11:01:58 -0800 Subject: ARM: dts: aspeed: add LCLK setting into LPC KCS nodes If LPC KCS driver is registered ahead of lpc-ctrl module, LPC KCS hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property setting into LPC KCS node as one of required properties to enable the LCLK by the LPC KCS driver. Note: dtbs should be re-compiled after applying this change since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo Reviewed-by: Joel Stanley Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20211108190200.290957-5-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 4 ++++ arch/arm/boot/dts/aspeed-g6.dtsi | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index d0cc4be2de59..7495f93c5069 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -446,6 +446,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -453,6 +454,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -460,6 +462,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -467,6 +470,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 539edbd7aaee..c32e87fad4dc 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -525,6 +525,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; kcs_chan = <1>; status = "disabled"; }; @@ -533,6 +534,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -540,6 +542,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; @@ -547,6 +550,7 @@ compatible = "aspeed,ast2500-kcs-bmc-v2"; reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; -- cgit v1.2.3 From 8b0c59c622dc4dab970ec63264fb5b152944ac80 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 23 Dec 2021 00:17:17 +0100 Subject: Revert "ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U" This reverts commit 3d2d52a0d1835b56f6bd67d268f6c39df0e41692, it caused a build regression: arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:109.4-14: Warning (reg_format): /switch/ports:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #address-cells value arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #size-cells value Reported-by: Stephen Rothwell Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ---------------------------- 1 file changed, 77 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index df8199fd4eb4..249476fdad7a 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -93,83 +93,6 @@ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; }; - - switch { - compatible = "realtek,rtl8365mb"; - /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ - mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; - reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - realtek,disable-leds; - dsa,member = <1 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - port@0 { - reg = <0>; - label = "lan5"; - phy-handle = <ðphy0>; - }; - - port@1 { - reg = <1>; - label = "lan6"; - phy-handle = <ðphy1>; - }; - - port@2 { - reg = <2>; - label = "lan7"; - phy-handle = <ðphy2>; - }; - - port@3 { - reg = <3>; - label = "lan8"; - phy-handle = <ðphy3>; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&sw0_p5>; - phy-mode = "rgmii"; - tx-internal-delay-ps = <2000>; - rx-internal-delay-ps = <2100>; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - - mdio { - compatible = "realtek,smi-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - }; - - ethphy3: ethernet-phy@3 { - reg = <3>; - }; - }; - }; }; &srab { -- cgit v1.2.3 From 5e1cdb8ee5e76bffbc11d300eebbb5193c7de530 Mon Sep 17 00:00:00 2001 From: Oleksandr Tyshchenko Date: Thu, 9 Dec 2021 22:05:32 +0200 Subject: arm/xen: Switch to use gnttab_setup_auto_xlat_frames() for DT Read the start address of the grant table space from DT (region 0). This patch mostly restores behaviour before commit 3cf4095d7446 ("arm/xen: Use xen_xlate_map_ballooned_pages to setup grant table") but trying not to break the ACPI support added after that commit. So the patch touches DT part only and leaves the ACPI part with xen_xlate_map_ballooned_pages(). Also in order to make a code more resilient use a fallback to xen_xlate_map_ballooned_pages() if grant table region wasn't found. This is a preparation for using Xen extended region feature where unused regions of guest physical address space (provided by the hypervisor) will be used to create grant/foreign/whatever mappings instead of wasting real RAM pages from the domain memory for establishing these mappings. The immediate benefit of this change: - Avoid superpage shattering in Xen P2M when establishing stage-2 mapping (GFN <-> MFN) for the grant table space - Avoid wasting real RAM pages (reducing the amount of memory usuable) for mapping grant table space - The grant table space is always mapped at the exact same place (region 0 is reserved for the grant table) Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Stefano Stabellini Link: https://lore.kernel.org/r/1639080336-26573-3-git-send-email-olekstysh@gmail.com Signed-off-by: Juergen Gross --- arch/arm/xen/enlighten.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c index 7619fbffcea2..49bb6757d031 100644 --- a/arch/arm/xen/enlighten.c +++ b/arch/arm/xen/enlighten.c @@ -59,6 +59,9 @@ unsigned long xen_released_pages; struct xen_memory_region xen_extra_mem[XEN_EXTRA_MEM_MAX_REGIONS] __initdata; static __read_mostly unsigned int xen_events_irq; +static __read_mostly phys_addr_t xen_grant_frames; + +#define GRANT_TABLE_INDEX 0 uint32_t xen_start_flags; EXPORT_SYMBOL(xen_start_flags); @@ -303,6 +306,7 @@ static void __init xen_acpi_guest_init(void) static void __init xen_dt_guest_init(void) { struct device_node *xen_node; + struct resource res; xen_node = of_find_compatible_node(NULL, NULL, "xen,xen"); if (!xen_node) { @@ -311,13 +315,19 @@ static void __init xen_dt_guest_init(void) } xen_events_irq = irq_of_parse_and_map(xen_node, 0); + + if (of_address_to_resource(xen_node, GRANT_TABLE_INDEX, &res)) { + pr_err("Xen grant table region is not found\n"); + return; + } + xen_grant_frames = res.start; } static int __init xen_guest_init(void) { struct xen_add_to_physmap xatp; struct shared_info *shared_info_page = NULL; - int cpu; + int rc, cpu; if (!xen_domain()) return 0; @@ -370,12 +380,16 @@ static int __init xen_guest_init(void) for_each_possible_cpu(cpu) per_cpu(xen_vcpu_id, cpu) = cpu; - xen_auto_xlat_grant_frames.count = gnttab_max_grant_frames(); - if (xen_xlate_map_ballooned_pages(&xen_auto_xlat_grant_frames.pfn, - &xen_auto_xlat_grant_frames.vaddr, - xen_auto_xlat_grant_frames.count)) { + if (!xen_grant_frames) { + xen_auto_xlat_grant_frames.count = gnttab_max_grant_frames(); + rc = xen_xlate_map_ballooned_pages(&xen_auto_xlat_grant_frames.pfn, + &xen_auto_xlat_grant_frames.vaddr, + xen_auto_xlat_grant_frames.count); + } else + rc = gnttab_setup_auto_xlat_frames(xen_grant_frames); + if (rc) { free_percpu(xen_vcpu_info); - return -ENOMEM; + return rc; } gnttab_init(); -- cgit v1.2.3 From b2371587fe0c02657db89b67b72efc581bd3f7a0 Mon Sep 17 00:00:00 2001 From: Oleksandr Tyshchenko Date: Thu, 9 Dec 2021 22:05:35 +0200 Subject: arm/xen: Read extended regions from DT and init Xen resource This patch implements arch_xen_unpopulated_init() on Arm where the extended regions (if any) are gathered from DT and inserted into specific Xen resource to be used as unused address space for Xen scratch pages by unpopulated-alloc code. The extended region (safe range) is a region of guest physical address space which is unused and could be safely used to create grant/foreign mappings instead of wasting real RAM pages from the domain memory for establishing these mappings. The extended regions are chosen by the hypervisor at the domain creation time and advertised to it via "reg" property under hypervisor node in the guest device-tree. As region 0 is reserved for grant table space (always present), the indexes for extended regions are 1...N. If arch_xen_unpopulated_init() fails for some reason the default behaviour will be restored (allocate xenballooned pages). This patch also removes XEN_UNPOPULATED_ALLOC dependency on x86. Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Stefano Stabellini Link: https://lore.kernel.org/r/1639080336-26573-6-git-send-email-olekstysh@gmail.com Signed-off-by: Juergen Gross --- arch/arm/xen/enlighten.c | 106 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/xen/Kconfig | 2 +- 2 files changed, 107 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c index 49bb6757d031..ec5b082f3de6 100644 --- a/arch/arm/xen/enlighten.c +++ b/arch/arm/xen/enlighten.c @@ -62,6 +62,7 @@ static __read_mostly unsigned int xen_events_irq; static __read_mostly phys_addr_t xen_grant_frames; #define GRANT_TABLE_INDEX 0 +#define EXT_REGION_INDEX 1 uint32_t xen_start_flags; EXPORT_SYMBOL(xen_start_flags); @@ -303,6 +304,111 @@ static void __init xen_acpi_guest_init(void) #endif } +#ifdef CONFIG_XEN_UNPOPULATED_ALLOC +/* + * A type-less specific Xen resource which contains extended regions + * (unused regions of guest physical address space provided by the hypervisor). + */ +static struct resource xen_resource = { + .name = "Xen unused space", +}; + +int __init arch_xen_unpopulated_init(struct resource **res) +{ + struct device_node *np; + struct resource *regs, *tmp_res; + uint64_t min_gpaddr = -1, max_gpaddr = 0; + unsigned int i, nr_reg = 0; + int rc; + + if (!xen_domain()) + return -ENODEV; + + if (!acpi_disabled) + return -ENODEV; + + np = of_find_compatible_node(NULL, NULL, "xen,xen"); + if (WARN_ON(!np)) + return -ENODEV; + + /* Skip region 0 which is reserved for grant table space */ + while (of_get_address(np, nr_reg + EXT_REGION_INDEX, NULL, NULL)) + nr_reg++; + + if (!nr_reg) { + pr_err("No extended regions are found\n"); + return -EINVAL; + } + + regs = kcalloc(nr_reg, sizeof(*regs), GFP_KERNEL); + if (!regs) + return -ENOMEM; + + /* + * Create resource from extended regions provided by the hypervisor to be + * used as unused address space for Xen scratch pages. + */ + for (i = 0; i < nr_reg; i++) { + rc = of_address_to_resource(np, i + EXT_REGION_INDEX, ®s[i]); + if (rc) + goto err; + + if (max_gpaddr < regs[i].end) + max_gpaddr = regs[i].end; + if (min_gpaddr > regs[i].start) + min_gpaddr = regs[i].start; + } + + xen_resource.start = min_gpaddr; + xen_resource.end = max_gpaddr; + + /* + * Mark holes between extended regions as unavailable. The rest of that + * address space will be available for the allocation. + */ + for (i = 1; i < nr_reg; i++) { + resource_size_t start, end; + + /* There is an overlap between regions */ + if (regs[i - 1].end + 1 > regs[i].start) { + rc = -EINVAL; + goto err; + } + + /* There is no hole between regions */ + if (regs[i - 1].end + 1 == regs[i].start) + continue; + + start = regs[i - 1].end + 1; + end = regs[i].start - 1; + + tmp_res = kzalloc(sizeof(*tmp_res), GFP_KERNEL); + if (!tmp_res) { + rc = -ENOMEM; + goto err; + } + + tmp_res->name = "Unavailable space"; + tmp_res->start = start; + tmp_res->end = end; + + rc = insert_resource(&xen_resource, tmp_res); + if (rc) { + pr_err("Cannot insert resource %pR (%d)\n", tmp_res, rc); + kfree(tmp_res); + goto err; + } + } + + *res = &xen_resource; + +err: + kfree(regs); + + return rc; +} +#endif + static void __init xen_dt_guest_init(void) { struct device_node *xen_node; diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig index 33e941e40082..120d32f164ac 100644 --- a/drivers/xen/Kconfig +++ b/drivers/xen/Kconfig @@ -327,7 +327,7 @@ config XEN_FRONT_PGDIR_SHBUF config XEN_UNPOPULATED_ALLOC bool "Use unpopulated memory ranges for guest mappings" - depends on X86 && ZONE_DEVICE + depends on ZONE_DEVICE default XEN_BACKEND || XEN_GNTDEV || XEN_DOM0 help Use unpopulated memory ranges in order to create mappings for guest -- cgit v1.2.3 From 6048fdcc5f269c7f31d774c295ce59081b36e6f9 Mon Sep 17 00:00:00 2001 From: "Jason A. Donenfeld" Date: Wed, 22 Dec 2021 14:56:58 +0100 Subject: lib/crypto: blake2s: include as built-in In preparation for using blake2s in the RNG, we change the way that it is wired-in to the build system. Instead of using ifdefs to select the right symbol, we use weak symbols. And because ARM doesn't need the generic implementation, we make the generic one default only if an arch library doesn't need it already, and then have arch libraries that do need it opt-in. So that the arch libraries can remain tristate rather than bool, we then split the shash part from the glue code. Acked-by: Herbert Xu Acked-by: Ard Biesheuvel Acked-by: Greg Kroah-Hartman Cc: Masahiro Yamada Cc: linux-kbuild@vger.kernel.org Cc: linux-crypto@vger.kernel.org Signed-off-by: Jason A. Donenfeld --- arch/arm/crypto/Makefile | 4 +- arch/arm/crypto/blake2s-core.S | 8 ++-- arch/arm/crypto/blake2s-glue.c | 73 +------------------------------------ arch/arm/crypto/blake2s-shash.c | 75 ++++++++++++++++++++++++++++++++++++++ arch/x86/crypto/Makefile | 4 +- arch/x86/crypto/blake2s-glue.c | 68 +++------------------------------- arch/x86/crypto/blake2s-shash.c | 77 +++++++++++++++++++++++++++++++++++++++ crypto/Kconfig | 3 +- drivers/net/Kconfig | 1 - include/crypto/internal/blake2s.h | 6 +-- lib/crypto/Kconfig | 23 +++--------- lib/crypto/Makefile | 9 ++--- lib/crypto/blake2s-generic.c | 6 ++- lib/crypto/blake2s.c | 6 --- 14 files changed, 189 insertions(+), 174 deletions(-) create mode 100644 arch/arm/crypto/blake2s-shash.c create mode 100644 arch/x86/crypto/blake2s-shash.c (limited to 'arch/arm') diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile index eafa898ba6a7..0274f81cc8ea 100644 --- a/arch/arm/crypto/Makefile +++ b/arch/arm/crypto/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CRYPTO_SHA1_ARM_NEON) += sha1-arm-neon.o obj-$(CONFIG_CRYPTO_SHA256_ARM) += sha256-arm.o obj-$(CONFIG_CRYPTO_SHA512_ARM) += sha512-arm.o obj-$(CONFIG_CRYPTO_BLAKE2S_ARM) += blake2s-arm.o +obj-$(if $(CONFIG_CRYPTO_BLAKE2S_ARM),y) += libblake2s-arm.o obj-$(CONFIG_CRYPTO_BLAKE2B_NEON) += blake2b-neon.o obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha-neon.o obj-$(CONFIG_CRYPTO_POLY1305_ARM) += poly1305-arm.o @@ -31,7 +32,8 @@ sha256-arm-neon-$(CONFIG_KERNEL_MODE_NEON) := sha256_neon_glue.o sha256-arm-y := sha256-core.o sha256_glue.o $(sha256-arm-neon-y) sha512-arm-neon-$(CONFIG_KERNEL_MODE_NEON) := sha512-neon-glue.o sha512-arm-y := sha512-core.o sha512-glue.o $(sha512-arm-neon-y) -blake2s-arm-y := blake2s-core.o blake2s-glue.o +blake2s-arm-y := blake2s-shash.o +libblake2s-arm-y:= blake2s-core.o blake2s-glue.o blake2b-neon-y := blake2b-neon-core.o blake2b-neon-glue.o sha1-arm-ce-y := sha1-ce-core.o sha1-ce-glue.o sha2-arm-ce-y := sha2-ce-core.o sha2-ce-glue.o diff --git a/arch/arm/crypto/blake2s-core.S b/arch/arm/crypto/blake2s-core.S index 86345751bbf3..df40e46601f1 100644 --- a/arch/arm/crypto/blake2s-core.S +++ b/arch/arm/crypto/blake2s-core.S @@ -167,8 +167,8 @@ .endm // -// void blake2s_compress_arch(struct blake2s_state *state, -// const u8 *block, size_t nblocks, u32 inc); +// void blake2s_compress(struct blake2s_state *state, +// const u8 *block, size_t nblocks, u32 inc); // // Only the first three fields of struct blake2s_state are used: // u32 h[8]; (inout) @@ -176,7 +176,7 @@ // u32 f[2]; (in) // .align 5 -ENTRY(blake2s_compress_arch) +ENTRY(blake2s_compress) push {r0-r2,r4-r11,lr} // keep this an even number .Lnext_block: @@ -303,4 +303,4 @@ ENTRY(blake2s_compress_arch) str r3, [r12], #4 bne 1b b .Lcopy_block_done -ENDPROC(blake2s_compress_arch) +ENDPROC(blake2s_compress) diff --git a/arch/arm/crypto/blake2s-glue.c b/arch/arm/crypto/blake2s-glue.c index f2cc1e5fc9ec..0238a70d9581 100644 --- a/arch/arm/crypto/blake2s-glue.c +++ b/arch/arm/crypto/blake2s-glue.c @@ -1,78 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later -/* - * BLAKE2s digest algorithm, ARM scalar implementation - * - * Copyright 2020 Google LLC - */ #include -#include - #include /* defined in blake2s-core.S */ -EXPORT_SYMBOL(blake2s_compress_arch); - -static int crypto_blake2s_update_arm(struct shash_desc *desc, - const u8 *in, unsigned int inlen) -{ - return crypto_blake2s_update(desc, in, inlen, blake2s_compress_arch); -} - -static int crypto_blake2s_final_arm(struct shash_desc *desc, u8 *out) -{ - return crypto_blake2s_final(desc, out, blake2s_compress_arch); -} - -#define BLAKE2S_ALG(name, driver_name, digest_size) \ - { \ - .base.cra_name = name, \ - .base.cra_driver_name = driver_name, \ - .base.cra_priority = 200, \ - .base.cra_flags = CRYPTO_ALG_OPTIONAL_KEY, \ - .base.cra_blocksize = BLAKE2S_BLOCK_SIZE, \ - .base.cra_ctxsize = sizeof(struct blake2s_tfm_ctx), \ - .base.cra_module = THIS_MODULE, \ - .digestsize = digest_size, \ - .setkey = crypto_blake2s_setkey, \ - .init = crypto_blake2s_init, \ - .update = crypto_blake2s_update_arm, \ - .final = crypto_blake2s_final_arm, \ - .descsize = sizeof(struct blake2s_state), \ - } - -static struct shash_alg blake2s_arm_algs[] = { - BLAKE2S_ALG("blake2s-128", "blake2s-128-arm", BLAKE2S_128_HASH_SIZE), - BLAKE2S_ALG("blake2s-160", "blake2s-160-arm", BLAKE2S_160_HASH_SIZE), - BLAKE2S_ALG("blake2s-224", "blake2s-224-arm", BLAKE2S_224_HASH_SIZE), - BLAKE2S_ALG("blake2s-256", "blake2s-256-arm", BLAKE2S_256_HASH_SIZE), -}; - -static int __init blake2s_arm_mod_init(void) -{ - return IS_REACHABLE(CONFIG_CRYPTO_HASH) ? - crypto_register_shashes(blake2s_arm_algs, - ARRAY_SIZE(blake2s_arm_algs)) : 0; -} - -static void __exit blake2s_arm_mod_exit(void) -{ - if (IS_REACHABLE(CONFIG_CRYPTO_HASH)) - crypto_unregister_shashes(blake2s_arm_algs, - ARRAY_SIZE(blake2s_arm_algs)); -} - -module_init(blake2s_arm_mod_init); -module_exit(blake2s_arm_mod_exit); - -MODULE_DESCRIPTION("BLAKE2s digest algorithm, ARM scalar implementation"); -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Eric Biggers "); -MODULE_ALIAS_CRYPTO("blake2s-128"); -MODULE_ALIAS_CRYPTO("blake2s-128-arm"); -MODULE_ALIAS_CRYPTO("blake2s-160"); -MODULE_ALIAS_CRYPTO("blake2s-160-arm"); -MODULE_ALIAS_CRYPTO("blake2s-224"); -MODULE_ALIAS_CRYPTO("blake2s-224-arm"); -MODULE_ALIAS_CRYPTO("blake2s-256"); -MODULE_ALIAS_CRYPTO("blake2s-256-arm"); +EXPORT_SYMBOL(blake2s_compress); diff --git a/arch/arm/crypto/blake2s-shash.c b/arch/arm/crypto/blake2s-shash.c new file mode 100644 index 000000000000..17c1c3bfe2f5 --- /dev/null +++ b/arch/arm/crypto/blake2s-shash.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * BLAKE2s digest algorithm, ARM scalar implementation + * + * Copyright 2020 Google LLC + */ + +#include +#include + +#include + +static int crypto_blake2s_update_arm(struct shash_desc *desc, + const u8 *in, unsigned int inlen) +{ + return crypto_blake2s_update(desc, in, inlen, blake2s_compress); +} + +static int crypto_blake2s_final_arm(struct shash_desc *desc, u8 *out) +{ + return crypto_blake2s_final(desc, out, blake2s_compress); +} + +#define BLAKE2S_ALG(name, driver_name, digest_size) \ + { \ + .base.cra_name = name, \ + .base.cra_driver_name = driver_name, \ + .base.cra_priority = 200, \ + .base.cra_flags = CRYPTO_ALG_OPTIONAL_KEY, \ + .base.cra_blocksize = BLAKE2S_BLOCK_SIZE, \ + .base.cra_ctxsize = sizeof(struct blake2s_tfm_ctx), \ + .base.cra_module = THIS_MODULE, \ + .digestsize = digest_size, \ + .setkey = crypto_blake2s_setkey, \ + .init = crypto_blake2s_init, \ + .update = crypto_blake2s_update_arm, \ + .final = crypto_blake2s_final_arm, \ + .descsize = sizeof(struct blake2s_state), \ + } + +static struct shash_alg blake2s_arm_algs[] = { + BLAKE2S_ALG("blake2s-128", "blake2s-128-arm", BLAKE2S_128_HASH_SIZE), + BLAKE2S_ALG("blake2s-160", "blake2s-160-arm", BLAKE2S_160_HASH_SIZE), + BLAKE2S_ALG("blake2s-224", "blake2s-224-arm", BLAKE2S_224_HASH_SIZE), + BLAKE2S_ALG("blake2s-256", "blake2s-256-arm", BLAKE2S_256_HASH_SIZE), +}; + +static int __init blake2s_arm_mod_init(void) +{ + return IS_REACHABLE(CONFIG_CRYPTO_HASH) ? + crypto_register_shashes(blake2s_arm_algs, + ARRAY_SIZE(blake2s_arm_algs)) : 0; +} + +static void __exit blake2s_arm_mod_exit(void) +{ + if (IS_REACHABLE(CONFIG_CRYPTO_HASH)) + crypto_unregister_shashes(blake2s_arm_algs, + ARRAY_SIZE(blake2s_arm_algs)); +} + +module_init(blake2s_arm_mod_init); +module_exit(blake2s_arm_mod_exit); + +MODULE_DESCRIPTION("BLAKE2s digest algorithm, ARM scalar implementation"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Eric Biggers "); +MODULE_ALIAS_CRYPTO("blake2s-128"); +MODULE_ALIAS_CRYPTO("blake2s-128-arm"); +MODULE_ALIAS_CRYPTO("blake2s-160"); +MODULE_ALIAS_CRYPTO("blake2s-160-arm"); +MODULE_ALIAS_CRYPTO("blake2s-224"); +MODULE_ALIAS_CRYPTO("blake2s-224-arm"); +MODULE_ALIAS_CRYPTO("blake2s-256"); +MODULE_ALIAS_CRYPTO("blake2s-256-arm"); diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile index f307c93fc90a..c3af959648e6 100644 --- a/arch/x86/crypto/Makefile +++ b/arch/x86/crypto/Makefile @@ -62,7 +62,9 @@ obj-$(CONFIG_CRYPTO_SHA512_SSSE3) += sha512-ssse3.o sha512-ssse3-y := sha512-ssse3-asm.o sha512-avx-asm.o sha512-avx2-asm.o sha512_ssse3_glue.o obj-$(CONFIG_CRYPTO_BLAKE2S_X86) += blake2s-x86_64.o -blake2s-x86_64-y := blake2s-core.o blake2s-glue.o +blake2s-x86_64-y := blake2s-shash.o +obj-$(if $(CONFIG_CRYPTO_BLAKE2S_X86),y) += libblake2s-x86_64.o +libblake2s-x86_64-y := blake2s-core.o blake2s-glue.o obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o diff --git a/arch/x86/crypto/blake2s-glue.c b/arch/x86/crypto/blake2s-glue.c index a40365ab301e..69853c13e8fb 100644 --- a/arch/x86/crypto/blake2s-glue.c +++ b/arch/x86/crypto/blake2s-glue.c @@ -5,7 +5,6 @@ #include #include -#include #include #include @@ -28,9 +27,8 @@ asmlinkage void blake2s_compress_avx512(struct blake2s_state *state, static __ro_after_init DEFINE_STATIC_KEY_FALSE(blake2s_use_ssse3); static __ro_after_init DEFINE_STATIC_KEY_FALSE(blake2s_use_avx512); -void blake2s_compress_arch(struct blake2s_state *state, - const u8 *block, size_t nblocks, - const u32 inc) +void blake2s_compress(struct blake2s_state *state, const u8 *block, + size_t nblocks, const u32 inc) { /* SIMD disables preemption, so relax after processing each page. */ BUILD_BUG_ON(SZ_4K / BLAKE2S_BLOCK_SIZE < 8); @@ -56,49 +54,12 @@ void blake2s_compress_arch(struct blake2s_state *state, block += blocks * BLAKE2S_BLOCK_SIZE; } while (nblocks); } -EXPORT_SYMBOL(blake2s_compress_arch); - -static int crypto_blake2s_update_x86(struct shash_desc *desc, - const u8 *in, unsigned int inlen) -{ - return crypto_blake2s_update(desc, in, inlen, blake2s_compress_arch); -} - -static int crypto_blake2s_final_x86(struct shash_desc *desc, u8 *out) -{ - return crypto_blake2s_final(desc, out, blake2s_compress_arch); -} - -#define BLAKE2S_ALG(name, driver_name, digest_size) \ - { \ - .base.cra_name = name, \ - .base.cra_driver_name = driver_name, \ - .base.cra_priority = 200, \ - .base.cra_flags = CRYPTO_ALG_OPTIONAL_KEY, \ - .base.cra_blocksize = BLAKE2S_BLOCK_SIZE, \ - .base.cra_ctxsize = sizeof(struct blake2s_tfm_ctx), \ - .base.cra_module = THIS_MODULE, \ - .digestsize = digest_size, \ - .setkey = crypto_blake2s_setkey, \ - .init = crypto_blake2s_init, \ - .update = crypto_blake2s_update_x86, \ - .final = crypto_blake2s_final_x86, \ - .descsize = sizeof(struct blake2s_state), \ - } - -static struct shash_alg blake2s_algs[] = { - BLAKE2S_ALG("blake2s-128", "blake2s-128-x86", BLAKE2S_128_HASH_SIZE), - BLAKE2S_ALG("blake2s-160", "blake2s-160-x86", BLAKE2S_160_HASH_SIZE), - BLAKE2S_ALG("blake2s-224", "blake2s-224-x86", BLAKE2S_224_HASH_SIZE), - BLAKE2S_ALG("blake2s-256", "blake2s-256-x86", BLAKE2S_256_HASH_SIZE), -}; +EXPORT_SYMBOL(blake2s_compress); static int __init blake2s_mod_init(void) { - if (!boot_cpu_has(X86_FEATURE_SSSE3)) - return 0; - - static_branch_enable(&blake2s_use_ssse3); + if (boot_cpu_has(X86_FEATURE_SSSE3)) + static_branch_enable(&blake2s_use_ssse3); if (IS_ENABLED(CONFIG_AS_AVX512) && boot_cpu_has(X86_FEATURE_AVX) && @@ -109,26 +70,9 @@ static int __init blake2s_mod_init(void) XFEATURE_MASK_AVX512, NULL)) static_branch_enable(&blake2s_use_avx512); - return IS_REACHABLE(CONFIG_CRYPTO_HASH) ? - crypto_register_shashes(blake2s_algs, - ARRAY_SIZE(blake2s_algs)) : 0; -} - -static void __exit blake2s_mod_exit(void) -{ - if (IS_REACHABLE(CONFIG_CRYPTO_HASH) && boot_cpu_has(X86_FEATURE_SSSE3)) - crypto_unregister_shashes(blake2s_algs, ARRAY_SIZE(blake2s_algs)); + return 0; } module_init(blake2s_mod_init); -module_exit(blake2s_mod_exit); -MODULE_ALIAS_CRYPTO("blake2s-128"); -MODULE_ALIAS_CRYPTO("blake2s-128-x86"); -MODULE_ALIAS_CRYPTO("blake2s-160"); -MODULE_ALIAS_CRYPTO("blake2s-160-x86"); -MODULE_ALIAS_CRYPTO("blake2s-224"); -MODULE_ALIAS_CRYPTO("blake2s-224-x86"); -MODULE_ALIAS_CRYPTO("blake2s-256"); -MODULE_ALIAS_CRYPTO("blake2s-256-x86"); MODULE_LICENSE("GPL v2"); diff --git a/arch/x86/crypto/blake2s-shash.c b/arch/x86/crypto/blake2s-shash.c new file mode 100644 index 000000000000..f9e2fecdb761 --- /dev/null +++ b/arch/x86/crypto/blake2s-shash.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2015-2019 Jason A. Donenfeld . All Rights Reserved. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +static int crypto_blake2s_update_x86(struct shash_desc *desc, + const u8 *in, unsigned int inlen) +{ + return crypto_blake2s_update(desc, in, inlen, blake2s_compress); +} + +static int crypto_blake2s_final_x86(struct shash_desc *desc, u8 *out) +{ + return crypto_blake2s_final(desc, out, blake2s_compress); +} + +#define BLAKE2S_ALG(name, driver_name, digest_size) \ + { \ + .base.cra_name = name, \ + .base.cra_driver_name = driver_name, \ + .base.cra_priority = 200, \ + .base.cra_flags = CRYPTO_ALG_OPTIONAL_KEY, \ + .base.cra_blocksize = BLAKE2S_BLOCK_SIZE, \ + .base.cra_ctxsize = sizeof(struct blake2s_tfm_ctx), \ + .base.cra_module = THIS_MODULE, \ + .digestsize = digest_size, \ + .setkey = crypto_blake2s_setkey, \ + .init = crypto_blake2s_init, \ + .update = crypto_blake2s_update_x86, \ + .final = crypto_blake2s_final_x86, \ + .descsize = sizeof(struct blake2s_state), \ + } + +static struct shash_alg blake2s_algs[] = { + BLAKE2S_ALG("blake2s-128", "blake2s-128-x86", BLAKE2S_128_HASH_SIZE), + BLAKE2S_ALG("blake2s-160", "blake2s-160-x86", BLAKE2S_160_HASH_SIZE), + BLAKE2S_ALG("blake2s-224", "blake2s-224-x86", BLAKE2S_224_HASH_SIZE), + BLAKE2S_ALG("blake2s-256", "blake2s-256-x86", BLAKE2S_256_HASH_SIZE), +}; + +static int __init blake2s_mod_init(void) +{ + if (IS_REACHABLE(CONFIG_CRYPTO_HASH) && boot_cpu_has(X86_FEATURE_SSSE3)) + return crypto_register_shashes(blake2s_algs, ARRAY_SIZE(blake2s_algs)); + return 0; +} + +static void __exit blake2s_mod_exit(void) +{ + if (IS_REACHABLE(CONFIG_CRYPTO_HASH) && boot_cpu_has(X86_FEATURE_SSSE3)) + crypto_unregister_shashes(blake2s_algs, ARRAY_SIZE(blake2s_algs)); +} + +module_init(blake2s_mod_init); +module_exit(blake2s_mod_exit); + +MODULE_ALIAS_CRYPTO("blake2s-128"); +MODULE_ALIAS_CRYPTO("blake2s-128-x86"); +MODULE_ALIAS_CRYPTO("blake2s-160"); +MODULE_ALIAS_CRYPTO("blake2s-160-x86"); +MODULE_ALIAS_CRYPTO("blake2s-224"); +MODULE_ALIAS_CRYPTO("blake2s-224-x86"); +MODULE_ALIAS_CRYPTO("blake2s-256"); +MODULE_ALIAS_CRYPTO("blake2s-256-x86"); +MODULE_LICENSE("GPL v2"); diff --git a/crypto/Kconfig b/crypto/Kconfig index 285f82647d2b..55718de56137 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -1919,9 +1919,10 @@ config CRYPTO_STATS config CRYPTO_HASH_INFO bool -source "lib/crypto/Kconfig" source "drivers/crypto/Kconfig" source "crypto/asymmetric_keys/Kconfig" source "certs/Kconfig" endif # if CRYPTO + +source "lib/crypto/Kconfig" diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 6cccc3dc00bc..b2a4f998c180 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -81,7 +81,6 @@ config WIREGUARD select CRYPTO select CRYPTO_LIB_CURVE25519 select CRYPTO_LIB_CHACHA20POLY1305 - select CRYPTO_LIB_BLAKE2S select CRYPTO_CHACHA20_X86_64 if X86 && 64BIT select CRYPTO_POLY1305_X86_64 if X86 && 64BIT select CRYPTO_BLAKE2S_X86 if X86 && 64BIT diff --git a/include/crypto/internal/blake2s.h b/include/crypto/internal/blake2s.h index 8e50d487500f..d39cfa0d333e 100644 --- a/include/crypto/internal/blake2s.h +++ b/include/crypto/internal/blake2s.h @@ -11,11 +11,11 @@ #include #include -void blake2s_compress_generic(struct blake2s_state *state,const u8 *block, +void blake2s_compress_generic(struct blake2s_state *state, const u8 *block, size_t nblocks, const u32 inc); -void blake2s_compress_arch(struct blake2s_state *state,const u8 *block, - size_t nblocks, const u32 inc); +void blake2s_compress(struct blake2s_state *state, const u8 *block, + size_t nblocks, const u32 inc); bool blake2s_selftest(void); diff --git a/lib/crypto/Kconfig b/lib/crypto/Kconfig index 545ccbddf6a1..8620f38e117c 100644 --- a/lib/crypto/Kconfig +++ b/lib/crypto/Kconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -comment "Crypto library routines" - config CRYPTO_LIB_AES tristate @@ -9,14 +7,14 @@ config CRYPTO_LIB_ARC4 tristate config CRYPTO_ARCH_HAVE_LIB_BLAKE2S - tristate + bool help Declares whether the architecture provides an arch-specific accelerated implementation of the Blake2s library interface, either builtin or as a module. config CRYPTO_LIB_BLAKE2S_GENERIC - tristate + def_bool !CRYPTO_ARCH_HAVE_LIB_BLAKE2S help This symbol can be depended upon by arch implementations of the Blake2s library interface that require the generic code as a @@ -24,15 +22,6 @@ config CRYPTO_LIB_BLAKE2S_GENERIC implementation is enabled, this implementation serves the users of CRYPTO_LIB_BLAKE2S. -config CRYPTO_LIB_BLAKE2S - tristate "BLAKE2s hash function library" - depends on CRYPTO_ARCH_HAVE_LIB_BLAKE2S || !CRYPTO_ARCH_HAVE_LIB_BLAKE2S - select CRYPTO_LIB_BLAKE2S_GENERIC if CRYPTO_ARCH_HAVE_LIB_BLAKE2S=n - help - Enable the Blake2s library interface. This interface may be fulfilled - by either the generic implementation or an arch-specific one, if one - is available and enabled. - config CRYPTO_ARCH_HAVE_LIB_CHACHA tristate help @@ -51,7 +40,7 @@ config CRYPTO_LIB_CHACHA_GENERIC of CRYPTO_LIB_CHACHA. config CRYPTO_LIB_CHACHA - tristate "ChaCha library interface" + tristate depends on CRYPTO_ARCH_HAVE_LIB_CHACHA || !CRYPTO_ARCH_HAVE_LIB_CHACHA select CRYPTO_LIB_CHACHA_GENERIC if CRYPTO_ARCH_HAVE_LIB_CHACHA=n help @@ -76,7 +65,7 @@ config CRYPTO_LIB_CURVE25519_GENERIC of CRYPTO_LIB_CURVE25519. config CRYPTO_LIB_CURVE25519 - tristate "Curve25519 scalar multiplication library" + tristate depends on CRYPTO_ARCH_HAVE_LIB_CURVE25519 || !CRYPTO_ARCH_HAVE_LIB_CURVE25519 select CRYPTO_LIB_CURVE25519_GENERIC if CRYPTO_ARCH_HAVE_LIB_CURVE25519=n help @@ -111,7 +100,7 @@ config CRYPTO_LIB_POLY1305_GENERIC of CRYPTO_LIB_POLY1305. config CRYPTO_LIB_POLY1305 - tristate "Poly1305 library interface" + tristate depends on CRYPTO_ARCH_HAVE_LIB_POLY1305 || !CRYPTO_ARCH_HAVE_LIB_POLY1305 select CRYPTO_LIB_POLY1305_GENERIC if CRYPTO_ARCH_HAVE_LIB_POLY1305=n help @@ -120,7 +109,7 @@ config CRYPTO_LIB_POLY1305 is available and enabled. config CRYPTO_LIB_CHACHA20POLY1305 - tristate "ChaCha20-Poly1305 AEAD support (8-byte nonce library version)" + tristate depends on CRYPTO_ARCH_HAVE_LIB_CHACHA || !CRYPTO_ARCH_HAVE_LIB_CHACHA depends on CRYPTO_ARCH_HAVE_LIB_POLY1305 || !CRYPTO_ARCH_HAVE_LIB_POLY1305 select CRYPTO_LIB_CHACHA diff --git a/lib/crypto/Makefile b/lib/crypto/Makefile index 73205ed269ba..ed43a41f2dcc 100644 --- a/lib/crypto/Makefile +++ b/lib/crypto/Makefile @@ -10,11 +10,10 @@ libaes-y := aes.o obj-$(CONFIG_CRYPTO_LIB_ARC4) += libarc4.o libarc4-y := arc4.o -obj-$(CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC) += libblake2s-generic.o -libblake2s-generic-y += blake2s-generic.o - -obj-$(CONFIG_CRYPTO_LIB_BLAKE2S) += libblake2s.o -libblake2s-y += blake2s.o +# blake2s is used by the /dev/random driver which is always builtin +obj-y += libblake2s.o +libblake2s-y := blake2s.o +libblake2s-$(CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC) += blake2s-generic.o obj-$(CONFIG_CRYPTO_LIB_CHACHA20POLY1305) += libchacha20poly1305.o libchacha20poly1305-y += chacha20poly1305.o diff --git a/lib/crypto/blake2s-generic.c b/lib/crypto/blake2s-generic.c index 04ff8df24513..75ccb3e633e6 100644 --- a/lib/crypto/blake2s-generic.c +++ b/lib/crypto/blake2s-generic.c @@ -37,7 +37,11 @@ static inline void blake2s_increment_counter(struct blake2s_state *state, state->t[1] += (state->t[0] < inc); } -void blake2s_compress_generic(struct blake2s_state *state,const u8 *block, +void blake2s_compress(struct blake2s_state *state, const u8 *block, + size_t nblocks, const u32 inc) + __weak __alias(blake2s_compress_generic); + +void blake2s_compress_generic(struct blake2s_state *state, const u8 *block, size_t nblocks, const u32 inc) { u32 m[16]; diff --git a/lib/crypto/blake2s.c b/lib/crypto/blake2s.c index 4055aa593ec4..93f2ae051370 100644 --- a/lib/crypto/blake2s.c +++ b/lib/crypto/blake2s.c @@ -16,12 +16,6 @@ #include #include -#if IS_ENABLED(CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S) -# define blake2s_compress blake2s_compress_arch -#else -# define blake2s_compress blake2s_compress_generic -#endif - void blake2s_update(struct blake2s_state *state, const u8 *in, size_t inlen) { __blake2s_update(state, in, inlen, blake2s_compress); -- cgit v1.2.3 From e9af026a3b24f59d7af4609f73e0ef60a4d6d516 Mon Sep 17 00:00:00 2001 From: "Sicelo A. Mhlongo" Date: Sun, 12 Dec 2021 23:40:06 +0100 Subject: ARM: dts: omap3-n900: Fix lp5523 for multi color Since the LED multicolor framework support was added in commit 92a81562e695 ("leds: lp55xx: Add multicolor framework support to lp55xx") LEDs on this platform stopped working. Fixes: 92a81562e695 ("leds: lp55xx: Add multicolor framework support to lp55xx") Fixes: ac219bf3c9bd ("leds: lp55xx: Convert to use GPIO descriptors") Signed-off-by: Merlijn Wajer Signed-off-by: Sicelo A. Mhlongo Signed-off-by: Pavel Machek --- arch/arm/boot/dts/omap3-n900.dts | 50 ++++++++++++++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 32335d4ce478..d40c3d2c4914 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -8,6 +8,7 @@ #include "omap34xx.dtsi" #include +#include /* * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall @@ -630,63 +631,92 @@ }; lp5523: lp5523@32 { + #address-cells = <1>; + #size-cells = <0>; compatible = "national,lp5523"; reg = <0x32>; clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ + enable-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ - chan0 { + led@0 { + reg = <0>; chan-name = "lp5523:kb1"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; }; - chan1 { + led@1 { + reg = <1>; chan-name = "lp5523:kb2"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; }; - chan2 { + led@2 { + reg = <2>; chan-name = "lp5523:kb3"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; }; - chan3 { + led@3 { + reg = <3>; chan-name = "lp5523:kb4"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; }; - chan4 { + led@4 { + reg = <4>; chan-name = "lp5523:b"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_STATUS; }; - chan5 { + led@5 { + reg = <5>; chan-name = "lp5523:g"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_STATUS; }; - chan6 { + led@6 { + reg = <6>; chan-name = "lp5523:r"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_STATUS; }; - chan7 { + led@7 { + reg = <7>; chan-name = "lp5523:kb5"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; }; - chan8 { + led@8 { + reg = <8>; chan-name = "lp5523:kb6"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; }; }; -- cgit v1.2.3 From 7ce7e984ab2b218d6e92d5165629022fe2daf9ee Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 10 Jan 2022 03:15:27 +0900 Subject: kbuild: rename cmd_{bzip2,lzma,lzo,lz4,xzkern,zstd22} GZIP-compressed files end with 4 byte data that represents the size of the original input. The decompressors (the self-extracting kernel) exploit it to know the vmlinux size beforehand. To mimic the GZIP's trailer, Kbuild provides cmd_{bzip2,lzma,lzo,lz4,xzkern,zstd22}. Unfortunately these macros are used everywhere despite the appended size data is only useful for the decompressors. There is no guarantee that such hand-crafted trailers are safely ignored. In fact, the kernel refuses compressed initramdfs with the garbage data. That is why usr/Makefile overrides size_append to make it no-op. To limit the use of such broken compressed files, this commit renames the existing macros as follows: cmd_bzip2 --> cmd_bzip2_with_size cmd_lzma --> cmd_lzma_with_size cmd_lzo --> cmd_lzo_with_size cmd_lz4 --> cmd_lz4_with_size cmd_xzkern --> cmd_xzkern_with_size cmd_zstd22 --> cmd_zstd22_with_size To keep the decompressors working, I updated the following Makefiles accordingly: arch/arm/boot/compressed/Makefile arch/h8300/boot/compressed/Makefile arch/mips/boot/compressed/Makefile arch/parisc/boot/compressed/Makefile arch/s390/boot/compressed/Makefile arch/sh/boot/compressed/Makefile arch/x86/boot/compressed/Makefile I reused the current macro names for the normal usecases; they produce the compressed data in the proper format. I did not touch the following: arch/arc/boot/Makefile arch/arm64/boot/Makefile arch/csky/boot/Makefile arch/mips/boot/Makefile arch/riscv/boot/Makefile arch/sh/boot/Makefile kernel/Makefile This means those Makefiles will stop appending the size data. I dropped the 'override size_append' hack from usr/Makefile. Signed-off-by: Masahiro Yamada Reviewed-by: Nicolas Schier --- arch/arm/boot/compressed/Makefile | 8 ++++---- arch/h8300/boot/compressed/Makefile | 4 +++- arch/mips/boot/compressed/Makefile | 12 ++++++------ arch/parisc/boot/compressed/Makefile | 10 +++++----- arch/s390/boot/compressed/Makefile | 12 ++++++------ arch/sh/boot/compressed/Makefile | 8 ++++---- arch/x86/boot/compressed/Makefile | 12 ++++++------ scripts/Makefile.lib | 30 ++++++++++++++++++++++++------ usr/Makefile | 5 ----- 9 files changed, 58 insertions(+), 43 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 91265e7ff672..adc0e318a1ea 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -77,10 +77,10 @@ CPPFLAGS_vmlinux.lds += -DTEXT_OFFSET="$(TEXT_OFFSET)" CPPFLAGS_vmlinux.lds += -DMALLOC_SIZE="$(MALLOC_SIZE)" compress-$(CONFIG_KERNEL_GZIP) = gzip -compress-$(CONFIG_KERNEL_LZO) = lzo -compress-$(CONFIG_KERNEL_LZMA) = lzma -compress-$(CONFIG_KERNEL_XZ) = xzkern -compress-$(CONFIG_KERNEL_LZ4) = lz4 +compress-$(CONFIG_KERNEL_LZO) = lzo_with_size +compress-$(CONFIG_KERNEL_LZMA) = lzma_with_size +compress-$(CONFIG_KERNEL_XZ) = xzkern_with_size +compress-$(CONFIG_KERNEL_LZ4) = lz4_with_size libfdt_objs := fdt_rw.o fdt_ro.o fdt_wip.o fdt.o diff --git a/arch/h8300/boot/compressed/Makefile b/arch/h8300/boot/compressed/Makefile index 5942793f77a0..6ab2fa5ba105 100644 --- a/arch/h8300/boot/compressed/Makefile +++ b/arch/h8300/boot/compressed/Makefile @@ -30,9 +30,11 @@ $(obj)/vmlinux.bin: vmlinux FORCE suffix-$(CONFIG_KERNEL_GZIP) := gzip suffix-$(CONFIG_KERNEL_LZO) := lzo +compress-$(CONFIG_KERNEL_GZIP) := gzip +compress-$(CONFIG_KERNEL_LZO) := lzo_with_size $(obj)/vmlinux.bin.$(suffix-y): $(obj)/vmlinux.bin FORCE - $(call if_changed,$(suffix-y)) + $(call if_changed,$(compress-y)) LDFLAGS_piggy.o := -r --format binary --oformat elf32-h8300-linux -T OBJCOPYFLAGS := -O binary diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index f27cf31b4140..832f8001d7d9 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -64,12 +64,12 @@ $(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE $(call if_changed,objcopy) tool_$(CONFIG_KERNEL_GZIP) = gzip -tool_$(CONFIG_KERNEL_BZIP2) = bzip2 -tool_$(CONFIG_KERNEL_LZ4) = lz4 -tool_$(CONFIG_KERNEL_LZMA) = lzma -tool_$(CONFIG_KERNEL_LZO) = lzo -tool_$(CONFIG_KERNEL_XZ) = xzkern -tool_$(CONFIG_KERNEL_ZSTD) = zstd22 +tool_$(CONFIG_KERNEL_BZIP2) = bzip2_with_size +tool_$(CONFIG_KERNEL_LZ4) = lz4_with_size +tool_$(CONFIG_KERNEL_LZMA) = lzma_with_size +tool_$(CONFIG_KERNEL_LZO) = lzo_with_size +tool_$(CONFIG_KERNEL_XZ) = xzkern_with_size +tool_$(CONFIG_KERNEL_ZSTD) = zstd22_with_size targets += vmlinux.bin.z diff --git a/arch/parisc/boot/compressed/Makefile b/arch/parisc/boot/compressed/Makefile index bf4f2891d0b7..2640f72d69ce 100644 --- a/arch/parisc/boot/compressed/Makefile +++ b/arch/parisc/boot/compressed/Makefile @@ -70,15 +70,15 @@ suffix-$(CONFIG_KERNEL_XZ) := xz $(obj)/vmlinux.bin.gz: $(vmlinux.bin.all-y) FORCE $(call if_changed,gzip) $(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y) FORCE - $(call if_changed,bzip2) + $(call if_changed,bzip2_with_size) $(obj)/vmlinux.bin.lz4: $(vmlinux.bin.all-y) FORCE - $(call if_changed,lz4) + $(call if_changed,lz4_with_size) $(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) FORCE - $(call if_changed,lzma) + $(call if_changed,lzma_with_size) $(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) FORCE - $(call if_changed,lzo) + $(call if_changed,lzo_with_size) $(obj)/vmlinux.bin.xz: $(vmlinux.bin.all-y) FORCE - $(call if_changed,xzkern) + $(call if_changed,xzkern_with_size) LDFLAGS_piggy.o := -r --format binary --oformat $(LD_BFD) -T $(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) FORCE diff --git a/arch/s390/boot/compressed/Makefile b/arch/s390/boot/compressed/Makefile index 3b860061e84d..8ea880b7c3ec 100644 --- a/arch/s390/boot/compressed/Makefile +++ b/arch/s390/boot/compressed/Makefile @@ -71,17 +71,17 @@ suffix-$(CONFIG_KERNEL_ZSTD) := .zst $(obj)/vmlinux.bin.gz: $(vmlinux.bin.all-y) FORCE $(call if_changed,gzip) $(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y) FORCE - $(call if_changed,bzip2) + $(call if_changed,bzip2_with_size) $(obj)/vmlinux.bin.lz4: $(vmlinux.bin.all-y) FORCE - $(call if_changed,lz4) + $(call if_changed,lz4_with_size) $(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) FORCE - $(call if_changed,lzma) + $(call if_changed,lzma_with_size) $(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) FORCE - $(call if_changed,lzo) + $(call if_changed,lzo_with_size) $(obj)/vmlinux.bin.xz: $(vmlinux.bin.all-y) FORCE - $(call if_changed,xzkern) + $(call if_changed,xzkern_with_size) $(obj)/vmlinux.bin.zst: $(vmlinux.bin.all-y) FORCE - $(call if_changed,zstd22) + $(call if_changed,zstd22_with_size) OBJCOPYFLAGS_piggy.o := -I binary -O elf64-s390 -B s390:64-bit --rename-section .data=.vmlinux.bin.compressed $(obj)/piggy.o: $(obj)/vmlinux.bin$(suffix-y) FORCE diff --git a/arch/sh/boot/compressed/Makefile b/arch/sh/boot/compressed/Makefile index c1eb9a62de55..a6808a403f4b 100644 --- a/arch/sh/boot/compressed/Makefile +++ b/arch/sh/boot/compressed/Makefile @@ -52,13 +52,13 @@ vmlinux.bin.all-y := $(obj)/vmlinux.bin $(obj)/vmlinux.bin.gz: $(vmlinux.bin.all-y) FORCE $(call if_changed,gzip) $(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y) FORCE - $(call if_changed,bzip2) + $(call if_changed,bzip2_with_size) $(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) FORCE - $(call if_changed,lzma) + $(call if_changed,lzma_with_size) $(obj)/vmlinux.bin.xz: $(vmlinux.bin.all-y) FORCE - $(call if_changed,xzkern) + $(call if_changed,xzkern_with_size) $(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) FORCE - $(call if_changed,lzo) + $(call if_changed,lzo_with_size) OBJCOPYFLAGS += -R .empty_zero_page diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile index 431bf7f846c3..2825c74bcae3 100644 --- a/arch/x86/boot/compressed/Makefile +++ b/arch/x86/boot/compressed/Makefile @@ -123,17 +123,17 @@ vmlinux.bin.all-$(CONFIG_X86_NEED_RELOCS) += $(obj)/vmlinux.relocs $(obj)/vmlinux.bin.gz: $(vmlinux.bin.all-y) FORCE $(call if_changed,gzip) $(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y) FORCE - $(call if_changed,bzip2) + $(call if_changed,bzip2_with_size) $(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) FORCE - $(call if_changed,lzma) + $(call if_changed,lzma_with_size) $(obj)/vmlinux.bin.xz: $(vmlinux.bin.all-y) FORCE - $(call if_changed,xzkern) + $(call if_changed,xzkern_with_size) $(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) FORCE - $(call if_changed,lzo) + $(call if_changed,lzo_with_size) $(obj)/vmlinux.bin.lz4: $(vmlinux.bin.all-y) FORCE - $(call if_changed,lz4) + $(call if_changed,lz4_with_size) $(obj)/vmlinux.bin.zst: $(vmlinux.bin.all-y) FORCE - $(call if_changed,zstd22) + $(call if_changed,zstd22_with_size) suffix-$(CONFIG_KERNEL_GZIP) := gz suffix-$(CONFIG_KERNEL_BZIP2) := bz2 diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 5366466ea0e4..4207a72d429f 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -395,19 +395,31 @@ printf "%08x\n" $$dec_size | \ ) quiet_cmd_bzip2 = BZIP2 $@ - cmd_bzip2 = { cat $(real-prereqs) | $(KBZIP2) -9; $(size_append); } > $@ + cmd_bzip2 = cat $(real-prereqs) | $(KBZIP2) -9 > $@ + +quiet_cmd_bzip2_with_size = BZIP2 $@ + cmd_bzip2_with_size = { cat $(real-prereqs) | $(KBZIP2) -9; $(size_append); } > $@ # Lzma # --------------------------------------------------------------------------- quiet_cmd_lzma = LZMA $@ - cmd_lzma = { cat $(real-prereqs) | $(LZMA) -9; $(size_append); } > $@ + cmd_lzma = cat $(real-prereqs) | $(LZMA) -9 > $@ + +quiet_cmd_lzma_with_size = LZMA $@ + cmd_lzma_with_size = { cat $(real-prereqs) | $(LZMA) -9; $(size_append); } > $@ quiet_cmd_lzo = LZO $@ - cmd_lzo = { cat $(real-prereqs) | $(KLZOP) -9; $(size_append); } > $@ + cmd_lzo = cat $(real-prereqs) | $(KLZOP) -9 > $@ + +quiet_cmd_lzo_with_size = LZO $@ + cmd_lzo_with_size = { cat $(real-prereqs) | $(KLZOP) -9; $(size_append); } > $@ quiet_cmd_lz4 = LZ4 $@ - cmd_lz4 = { cat $(real-prereqs) | $(LZ4) -l -c1 stdin stdout; \ + cmd_lz4 = cat $(real-prereqs) | $(LZ4) -l -c1 stdin stdout > $@ + +quiet_cmd_lz4_with_size = LZ4 $@ + cmd_lz4_with_size = { cat $(real-prereqs) | $(LZ4) -l -c1 stdin stdout; \ $(size_append); } > $@ # U-Boot mkimage @@ -450,7 +462,10 @@ quiet_cmd_uimage = UIMAGE $@ # big dictionary would increase the memory usage too much in the multi-call # decompression mode. A BCJ filter isn't used either. quiet_cmd_xzkern = XZKERN $@ - cmd_xzkern = { cat $(real-prereqs) | sh $(srctree)/scripts/xz_wrap.sh; \ + cmd_xzkern = cat $(real-prereqs) | sh $(srctree)/scripts/xz_wrap.sh > $@ + +quiet_cmd_xzkern_with_size = XZKERN $@ + cmd_xzkern_with_size = { cat $(real-prereqs) | sh $(srctree)/scripts/xz_wrap.sh; \ $(size_append); } > $@ quiet_cmd_xzmisc = XZMISC $@ @@ -476,7 +491,10 @@ quiet_cmd_zstd = ZSTD $@ cmd_zstd = cat $(real-prereqs) | $(ZSTD) -19 > $@ quiet_cmd_zstd22 = ZSTD22 $@ - cmd_zstd22 = { cat $(real-prereqs) | $(ZSTD) -22 --ultra; $(size_append); } > $@ + cmd_zstd22 = cat $(real-prereqs) | $(ZSTD) -22 --ultra > $@ + +quiet_cmd_zstd22_with_size = ZSTD22 $@ + cmd_zstd22_with_size = { cat $(real-prereqs) | $(ZSTD) -22 --ultra; $(size_append); } > $@ # ASM offsets # --------------------------------------------------------------------------- diff --git a/usr/Makefile b/usr/Makefile index 7374873a539f..cc0d2824e100 100644 --- a/usr/Makefile +++ b/usr/Makefile @@ -3,11 +3,6 @@ # kbuild file for usr/ - including initramfs image # -# cmd_bzip2, cmd_lzma, cmd_lzo, cmd_lz4 from scripts/Makefile.lib appends the -# size at the end of the compressed file, which unfortunately does not work -# with unpack_to_rootfs(). Make size_append no-op. -override size_append := : - compress-y := shipped compress-$(CONFIG_INITRAMFS_COMPRESSION_GZIP) := gzip compress-$(CONFIG_INITRAMFS_COMPRESSION_BZIP2) := bzip2 -- cgit v1.2.3 From 36ef159f4408b08eae7f2af6d62bedd3f4343758 Mon Sep 17 00:00:00 2001 From: Qi Zheng Date: Fri, 14 Jan 2022 14:05:51 -0800 Subject: mm: remove redundant check about FAULT_FLAG_ALLOW_RETRY bit Since commit 4064b9827063 ("mm: allow VM_FAULT_RETRY for multiple times") allowed VM_FAULT_RETRY for multiple times, the FAULT_FLAG_ALLOW_RETRY bit of fault_flag will not be changed in the page fault path, so the following check is no longer needed: flags & FAULT_FLAG_ALLOW_RETRY So just remove it. [akpm@linux-foundation.org: coding style fixes] Link: https://lkml.kernel.org/r/20211110123358.36511-1-zhengqi.arch@bytedance.com Signed-off-by: Qi Zheng Cc: Peter Zijlstra Cc: Ingo Molnar Cc: David Hildenbrand Cc: Kirill Shutemov Cc: Peter Xu Cc: Muchun Song Cc: Chengming Zhou Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/alpha/mm/fault.c | 16 +++++++--------- arch/arc/mm/fault.c | 3 +-- arch/arm/mm/fault.c | 2 +- arch/arm64/mm/fault.c | 6 ++---- arch/hexagon/mm/vm_fault.c | 8 +++----- arch/ia64/mm/fault.c | 16 +++++++--------- arch/m68k/mm/fault.c | 22 ++++++++++------------ arch/microblaze/mm/fault.c | 22 ++++++++++------------ arch/mips/mm/fault.c | 19 +++++++++---------- arch/nds32/mm/fault.c | 18 ++++++++---------- arch/nios2/mm/fault.c | 18 ++++++++---------- arch/openrisc/mm/fault.c | 18 ++++++++---------- arch/parisc/mm/fault.c | 18 ++++++++---------- arch/powerpc/mm/fault.c | 6 ++---- arch/riscv/mm/fault.c | 2 +- arch/s390/mm/fault.c | 28 ++++++++++++++-------------- arch/sh/mm/fault.c | 20 +++++++++----------- arch/sparc/mm/fault_32.c | 16 +++++++--------- arch/sparc/mm/fault_64.c | 16 +++++++--------- arch/um/kernel/trap.c | 8 +++----- arch/x86/mm/fault.c | 3 +-- arch/xtensa/mm/fault.c | 17 ++++++++--------- 22 files changed, 134 insertions(+), 168 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/mm/fault.c b/arch/alpha/mm/fault.c index eee5102c3d88..6c0a277388dd 100644 --- a/arch/alpha/mm/fault.c +++ b/arch/alpha/mm/fault.c @@ -165,17 +165,15 @@ retry: BUG(); } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; - /* No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ + /* No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ - goto retry; - } + goto retry; } mmap_read_unlock(mm); diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c index 5787c261c9a4..dad27e4d69ff 100644 --- a/arch/arc/mm/fault.c +++ b/arch/arc/mm/fault.c @@ -149,8 +149,7 @@ retry: /* * Fault retry nuances, mmap_lock already relinquished by core mm */ - if (unlikely((fault & VM_FAULT_RETRY) && - (flags & FAULT_FLAG_ALLOW_RETRY))) { + if (unlikely(fault & VM_FAULT_RETRY)) { flags |= FAULT_FLAG_TRIED; goto retry; } diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index bc8779d54a64..c7326a521a69 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -312,7 +312,7 @@ retry: return 0; } - if (!(fault & VM_FAULT_ERROR) && flags & FAULT_FLAG_ALLOW_RETRY) { + if (!(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_RETRY) { flags |= FAULT_FLAG_TRIED; goto retry; diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 9ae24e3b72be..a8fb54fccde0 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -606,10 +606,8 @@ retry: } if (fault & VM_FAULT_RETRY) { - if (mm_flags & FAULT_FLAG_ALLOW_RETRY) { - mm_flags |= FAULT_FLAG_TRIED; - goto retry; - } + mm_flags |= FAULT_FLAG_TRIED; + goto retry; } mmap_read_unlock(mm); diff --git a/arch/hexagon/mm/vm_fault.c b/arch/hexagon/mm/vm_fault.c index ef32c5a84ff3..4fac4b9eb316 100644 --- a/arch/hexagon/mm/vm_fault.c +++ b/arch/hexagon/mm/vm_fault.c @@ -98,11 +98,9 @@ good_area: /* The most common case -- we are done. */ if (likely(!(fault & VM_FAULT_ERROR))) { - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; - goto retry; - } + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; + goto retry; } mmap_read_unlock(mm); diff --git a/arch/ia64/mm/fault.c b/arch/ia64/mm/fault.c index 02de2e70c587..32417f49ad2f 100644 --- a/arch/ia64/mm/fault.c +++ b/arch/ia64/mm/fault.c @@ -156,17 +156,15 @@ retry: BUG(); } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; - /* No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ + /* No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ - goto retry; - } + goto retry; } mmap_read_unlock(mm); diff --git a/arch/m68k/mm/fault.c b/arch/m68k/mm/fault.c index ef46e77e97a5..53cfb9bc1066 100644 --- a/arch/m68k/mm/fault.c +++ b/arch/m68k/mm/fault.c @@ -153,18 +153,16 @@ good_area: BUG(); } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; - - /* - * No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ - - goto retry; - } + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; + + /* + * No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + + goto retry; } mmap_read_unlock(mm); diff --git a/arch/microblaze/mm/fault.c b/arch/microblaze/mm/fault.c index b3fed2cecf84..a9626e6a68af 100644 --- a/arch/microblaze/mm/fault.c +++ b/arch/microblaze/mm/fault.c @@ -232,18 +232,16 @@ good_area: BUG(); } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; - - /* - * No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ - - goto retry; - } + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; + + /* + * No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + + goto retry; } mmap_read_unlock(mm); diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index e7abda9c013f..44f98100e84e 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -171,18 +171,17 @@ good_area: goto do_sigbus; BUG(); } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; - /* - * No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; - goto retry; - } + /* + * No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + + goto retry; } mmap_read_unlock(mm); diff --git a/arch/nds32/mm/fault.c b/arch/nds32/mm/fault.c index 1d139b117168..636977a1c8b9 100644 --- a/arch/nds32/mm/fault.c +++ b/arch/nds32/mm/fault.c @@ -230,16 +230,14 @@ good_area: goto bad_area; } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; - - /* No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ - goto retry; - } + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; + + /* No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + goto retry; } mmap_read_unlock(mm); diff --git a/arch/nios2/mm/fault.c b/arch/nios2/mm/fault.c index 9476feecf512..a32f14cd72f2 100644 --- a/arch/nios2/mm/fault.c +++ b/arch/nios2/mm/fault.c @@ -149,18 +149,16 @@ good_area: BUG(); } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; - /* - * No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ + /* + * No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ - goto retry; - } + goto retry; } mmap_read_unlock(mm); diff --git a/arch/openrisc/mm/fault.c b/arch/openrisc/mm/fault.c index f0fa6394a58e..80bb66ad42f6 100644 --- a/arch/openrisc/mm/fault.c +++ b/arch/openrisc/mm/fault.c @@ -177,18 +177,16 @@ good_area: BUG(); } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - /*RGD modeled on Cris */ - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; + /*RGD modeled on Cris */ + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; - /* No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ + /* No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ - goto retry; - } + goto retry; } mmap_read_unlock(mm); diff --git a/arch/parisc/mm/fault.c b/arch/parisc/mm/fault.c index 4a6221b869fd..360b627645cc 100644 --- a/arch/parisc/mm/fault.c +++ b/arch/parisc/mm/fault.c @@ -324,16 +324,14 @@ good_area: goto bad_area; BUG(); } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - /* - * No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ - flags |= FAULT_FLAG_TRIED; - goto retry; - } + if (fault & VM_FAULT_RETRY) { + /* + * No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + flags |= FAULT_FLAG_TRIED; + goto retry; } mmap_read_unlock(mm); return; diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c index a8d0ce85d39a..ebcc61e47d62 100644 --- a/arch/powerpc/mm/fault.c +++ b/arch/powerpc/mm/fault.c @@ -516,10 +516,8 @@ retry: * case. */ if (unlikely(fault & VM_FAULT_RETRY)) { - if (flags & FAULT_FLAG_ALLOW_RETRY) { - flags |= FAULT_FLAG_TRIED; - goto retry; - } + flags |= FAULT_FLAG_TRIED; + goto retry; } mmap_read_unlock(current->mm); diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index aa08dd2f8fae..cae4b6363607 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -330,7 +330,7 @@ good_area: if (fault_signal_pending(fault, regs)) return; - if (unlikely((fault & VM_FAULT_RETRY) && (flags & FAULT_FLAG_ALLOW_RETRY))) { + if (unlikely(fault & VM_FAULT_RETRY)) { flags |= FAULT_FLAG_TRIED; /* diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c index d30f5986fa85..d7d6be283d94 100644 --- a/arch/s390/mm/fault.c +++ b/arch/s390/mm/fault.c @@ -452,21 +452,21 @@ retry: if (unlikely(fault & VM_FAULT_ERROR)) goto out_up; - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - if (IS_ENABLED(CONFIG_PGSTE) && gmap && - (flags & FAULT_FLAG_RETRY_NOWAIT)) { - /* FAULT_FLAG_RETRY_NOWAIT has been set, - * mmap_lock has not been released */ - current->thread.gmap_pfault = 1; - fault = VM_FAULT_PFAULT; - goto out_up; - } - flags &= ~FAULT_FLAG_RETRY_NOWAIT; - flags |= FAULT_FLAG_TRIED; - mmap_read_lock(mm); - goto retry; + if (fault & VM_FAULT_RETRY) { + if (IS_ENABLED(CONFIG_PGSTE) && gmap && + (flags & FAULT_FLAG_RETRY_NOWAIT)) { + /* + * FAULT_FLAG_RETRY_NOWAIT has been set, mmap_lock has + * not been released + */ + current->thread.gmap_pfault = 1; + fault = VM_FAULT_PFAULT; + goto out_up; } + flags &= ~FAULT_FLAG_RETRY_NOWAIT; + flags |= FAULT_FLAG_TRIED; + mmap_read_lock(mm); + goto retry; } if (IS_ENABLED(CONFIG_PGSTE) && gmap) { address = __gmap_link(gmap, current->thread.gmap_addr, diff --git a/arch/sh/mm/fault.c b/arch/sh/mm/fault.c index 1e1aa75df3ca..e175667b1363 100644 --- a/arch/sh/mm/fault.c +++ b/arch/sh/mm/fault.c @@ -485,17 +485,15 @@ good_area: if (mm_fault_error(regs, error_code, address, fault)) return; - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; - - /* - * No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ - goto retry; - } + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; + + /* + * No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + goto retry; } mmap_read_unlock(mm); diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c index 90dc4ae315c8..ad569d9bd124 100644 --- a/arch/sparc/mm/fault_32.c +++ b/arch/sparc/mm/fault_32.c @@ -200,17 +200,15 @@ good_area: BUG(); } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; - /* No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ + /* No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ - goto retry; - } + goto retry; } mmap_read_unlock(mm); diff --git a/arch/sparc/mm/fault_64.c b/arch/sparc/mm/fault_64.c index 9a9652a15fed..253e07043298 100644 --- a/arch/sparc/mm/fault_64.c +++ b/arch/sparc/mm/fault_64.c @@ -437,17 +437,15 @@ good_area: BUG(); } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; - /* No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ + /* No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ - goto retry; - } + goto retry; } mmap_read_unlock(mm); diff --git a/arch/um/kernel/trap.c b/arch/um/kernel/trap.c index c32efb09db21..193503484af5 100644 --- a/arch/um/kernel/trap.c +++ b/arch/um/kernel/trap.c @@ -87,12 +87,10 @@ good_area: } BUG(); } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; - goto retry; - } + goto retry; } pmd = pmd_off(mm, address); diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index 4bfed53e210e..d0074c6ed31a 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -1413,8 +1413,7 @@ good_area: * and if there is a fatal signal pending there is no guarantee * that we made any progress. Handle this case first. */ - if (unlikely((fault & VM_FAULT_RETRY) && - (flags & FAULT_FLAG_ALLOW_RETRY))) { + if (unlikely(fault & VM_FAULT_RETRY)) { flags |= FAULT_FLAG_TRIED; goto retry; } diff --git a/arch/xtensa/mm/fault.c b/arch/xtensa/mm/fault.c index fd6a70635962..06d0973a0d74 100644 --- a/arch/xtensa/mm/fault.c +++ b/arch/xtensa/mm/fault.c @@ -127,17 +127,16 @@ good_area: goto do_sigbus; BUG(); } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; - /* No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ + if (fault & VM_FAULT_RETRY) { + flags |= FAULT_FLAG_TRIED; - goto retry; - } + /* No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + + goto retry; } mmap_read_unlock(mm); -- cgit v1.2.3 From 21b084fdf2a49ca1634e8e360e9ab6f9ff0dee11 Mon Sep 17 00:00:00 2001 From: "Aneesh Kumar K.V" Date: Fri, 14 Jan 2022 14:08:21 -0800 Subject: mm/mempolicy: wire up syscall set_mempolicy_home_node Link: https://lkml.kernel.org/r/20211202123810.267175-4-aneesh.kumar@linux.ibm.com Signed-off-by: Aneesh Kumar K.V Cc: Ben Widawsky Cc: Dave Hansen Cc: Feng Tang Cc: Michal Hocko Cc: Andrea Arcangeli Cc: Mel Gorman Cc: Mike Kravetz Cc: Randy Dunlap Cc: Vlastimil Babka Cc: Andi Kleen Cc: Dan Williams Cc: Huang Ying Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/alpha/kernel/syscalls/syscall.tbl | 1 + arch/arm/tools/syscall.tbl | 1 + arch/arm64/include/asm/unistd.h | 2 +- arch/arm64/include/asm/unistd32.h | 2 ++ arch/ia64/kernel/syscalls/syscall.tbl | 1 + arch/m68k/kernel/syscalls/syscall.tbl | 1 + arch/microblaze/kernel/syscalls/syscall.tbl | 1 + arch/mips/kernel/syscalls/syscall_n32.tbl | 1 + arch/mips/kernel/syscalls/syscall_n64.tbl | 1 + arch/mips/kernel/syscalls/syscall_o32.tbl | 1 + arch/parisc/kernel/syscalls/syscall.tbl | 1 + arch/powerpc/kernel/syscalls/syscall.tbl | 1 + arch/s390/kernel/syscalls/syscall.tbl | 1 + arch/sh/kernel/syscalls/syscall.tbl | 1 + arch/sparc/kernel/syscalls/syscall.tbl | 1 + arch/x86/entry/syscalls/syscall_32.tbl | 1 + arch/x86/entry/syscalls/syscall_64.tbl | 1 + arch/xtensa/kernel/syscalls/syscall.tbl | 1 + include/linux/syscalls.h | 3 +++ include/uapi/asm-generic/unistd.h | 5 ++++- kernel/sys_ni.c | 1 + 21 files changed, 27 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/kernel/syscalls/syscall.tbl b/arch/alpha/kernel/syscalls/syscall.tbl index ca5a32228cd6..3515bc4f16a4 100644 --- a/arch/alpha/kernel/syscalls/syscall.tbl +++ b/arch/alpha/kernel/syscalls/syscall.tbl @@ -489,3 +489,4 @@ # 557 reserved for memfd_secret 558 common process_mrelease sys_process_mrelease 559 common futex_waitv sys_futex_waitv +560 common set_mempolicy_home_node sys_ni_syscall diff --git a/arch/arm/tools/syscall.tbl b/arch/arm/tools/syscall.tbl index 543100151f2b..ac964612d8b0 100644 --- a/arch/arm/tools/syscall.tbl +++ b/arch/arm/tools/syscall.tbl @@ -463,3 +463,4 @@ # 447 reserved for memfd_secret 448 common process_mrelease sys_process_mrelease 449 common futex_waitv sys_futex_waitv +450 common set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h index 6bdb5f5db438..4e65da3445c7 100644 --- a/arch/arm64/include/asm/unistd.h +++ b/arch/arm64/include/asm/unistd.h @@ -38,7 +38,7 @@ #define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE + 5) #define __ARM_NR_COMPAT_END (__ARM_NR_COMPAT_BASE + 0x800) -#define __NR_compat_syscalls 450 +#define __NR_compat_syscalls 451 #endif #define __ARCH_WANT_SYS_CLONE diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h index 41ea1195e44b..604a2053d006 100644 --- a/arch/arm64/include/asm/unistd32.h +++ b/arch/arm64/include/asm/unistd32.h @@ -905,6 +905,8 @@ __SYSCALL(__NR_landlock_restrict_self, sys_landlock_restrict_self) __SYSCALL(__NR_process_mrelease, sys_process_mrelease) #define __NR_futex_waitv 449 __SYSCALL(__NR_futex_waitv, sys_futex_waitv) +#define __NR_set_mempolicy_home_node 450 +__SYSCALL(__NR_set_mempolicy_home_node, sys_set_mempolicy_home_node) /* * Please add new compat syscalls above this comment and update diff --git a/arch/ia64/kernel/syscalls/syscall.tbl b/arch/ia64/kernel/syscalls/syscall.tbl index 707ae121f6d3..78b1d03e86e1 100644 --- a/arch/ia64/kernel/syscalls/syscall.tbl +++ b/arch/ia64/kernel/syscalls/syscall.tbl @@ -370,3 +370,4 @@ # 447 reserved for memfd_secret 448 common process_mrelease sys_process_mrelease 449 common futex_waitv sys_futex_waitv +450 common set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/m68k/kernel/syscalls/syscall.tbl b/arch/m68k/kernel/syscalls/syscall.tbl index 45bc32a41b90..b1f3940bc298 100644 --- a/arch/m68k/kernel/syscalls/syscall.tbl +++ b/arch/m68k/kernel/syscalls/syscall.tbl @@ -449,3 +449,4 @@ # 447 reserved for memfd_secret 448 common process_mrelease sys_process_mrelease 449 common futex_waitv sys_futex_waitv +450 common set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/microblaze/kernel/syscalls/syscall.tbl b/arch/microblaze/kernel/syscalls/syscall.tbl index 2204bde3ce4a..820145e47350 100644 --- a/arch/microblaze/kernel/syscalls/syscall.tbl +++ b/arch/microblaze/kernel/syscalls/syscall.tbl @@ -455,3 +455,4 @@ # 447 reserved for memfd_secret 448 common process_mrelease sys_process_mrelease 449 common futex_waitv sys_futex_waitv +450 common set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/mips/kernel/syscalls/syscall_n32.tbl b/arch/mips/kernel/syscalls/syscall_n32.tbl index 72d02d363f36..253ff994ed2e 100644 --- a/arch/mips/kernel/syscalls/syscall_n32.tbl +++ b/arch/mips/kernel/syscalls/syscall_n32.tbl @@ -388,3 +388,4 @@ # 447 reserved for memfd_secret 448 n32 process_mrelease sys_process_mrelease 449 n32 futex_waitv sys_futex_waitv +450 n32 set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/mips/kernel/syscalls/syscall_n64.tbl b/arch/mips/kernel/syscalls/syscall_n64.tbl index e2c481fcede6..3f1886ad9d80 100644 --- a/arch/mips/kernel/syscalls/syscall_n64.tbl +++ b/arch/mips/kernel/syscalls/syscall_n64.tbl @@ -364,3 +364,4 @@ # 447 reserved for memfd_secret 448 n64 process_mrelease sys_process_mrelease 449 n64 futex_waitv sys_futex_waitv +450 common set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/mips/kernel/syscalls/syscall_o32.tbl b/arch/mips/kernel/syscalls/syscall_o32.tbl index 3714c97b2643..8f243e35a7b2 100644 --- a/arch/mips/kernel/syscalls/syscall_o32.tbl +++ b/arch/mips/kernel/syscalls/syscall_o32.tbl @@ -437,3 +437,4 @@ # 447 reserved for memfd_secret 448 o32 process_mrelease sys_process_mrelease 449 o32 futex_waitv sys_futex_waitv +450 o32 set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/parisc/kernel/syscalls/syscall.tbl b/arch/parisc/kernel/syscalls/syscall.tbl index 358c00000755..68b46fe2f17c 100644 --- a/arch/parisc/kernel/syscalls/syscall.tbl +++ b/arch/parisc/kernel/syscalls/syscall.tbl @@ -447,3 +447,4 @@ # 447 reserved for memfd_secret 448 common process_mrelease sys_process_mrelease 449 common futex_waitv sys_futex_waitv +450 common set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/powerpc/kernel/syscalls/syscall.tbl b/arch/powerpc/kernel/syscalls/syscall.tbl index 15109af9d075..2600b4237292 100644 --- a/arch/powerpc/kernel/syscalls/syscall.tbl +++ b/arch/powerpc/kernel/syscalls/syscall.tbl @@ -529,3 +529,4 @@ # 447 reserved for memfd_secret 448 common process_mrelease sys_process_mrelease 449 common futex_waitv sys_futex_waitv +450 nospu set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/s390/kernel/syscalls/syscall.tbl b/arch/s390/kernel/syscalls/syscall.tbl index ed9c5c2eafad..799147658dee 100644 --- a/arch/s390/kernel/syscalls/syscall.tbl +++ b/arch/s390/kernel/syscalls/syscall.tbl @@ -452,3 +452,4 @@ # 447 reserved for memfd_secret 448 common process_mrelease sys_process_mrelease sys_process_mrelease 449 common futex_waitv sys_futex_waitv sys_futex_waitv +450 common set_mempolicy_home_node sys_set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/sh/kernel/syscalls/syscall.tbl b/arch/sh/kernel/syscalls/syscall.tbl index d9539d28bdaa..2de85c977f54 100644 --- a/arch/sh/kernel/syscalls/syscall.tbl +++ b/arch/sh/kernel/syscalls/syscall.tbl @@ -452,3 +452,4 @@ # 447 reserved for memfd_secret 448 common process_mrelease sys_process_mrelease 449 common futex_waitv sys_futex_waitv +450 common set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/sparc/kernel/syscalls/syscall.tbl b/arch/sparc/kernel/syscalls/syscall.tbl index 46adabcb1720..4398cc6fb68d 100644 --- a/arch/sparc/kernel/syscalls/syscall.tbl +++ b/arch/sparc/kernel/syscalls/syscall.tbl @@ -495,3 +495,4 @@ # 447 reserved for memfd_secret 448 common process_mrelease sys_process_mrelease 449 common futex_waitv sys_futex_waitv +450 common set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/x86/entry/syscalls/syscall_32.tbl b/arch/x86/entry/syscalls/syscall_32.tbl index 7e25543693de..320480a8db4f 100644 --- a/arch/x86/entry/syscalls/syscall_32.tbl +++ b/arch/x86/entry/syscalls/syscall_32.tbl @@ -454,3 +454,4 @@ 447 i386 memfd_secret sys_memfd_secret 448 i386 process_mrelease sys_process_mrelease 449 i386 futex_waitv sys_futex_waitv +450 i386 set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/arch/x86/entry/syscalls/syscall_64.tbl b/arch/x86/entry/syscalls/syscall_64.tbl index fe8f8dd157b4..c84d12608cd2 100644 --- a/arch/x86/entry/syscalls/syscall_64.tbl +++ b/arch/x86/entry/syscalls/syscall_64.tbl @@ -371,6 +371,7 @@ 447 common memfd_secret sys_memfd_secret 448 common process_mrelease sys_process_mrelease 449 common futex_waitv sys_futex_waitv +450 common set_mempolicy_home_node sys_set_mempolicy_home_node # # Due to a historical design error, certain syscalls are numbered differently diff --git a/arch/xtensa/kernel/syscalls/syscall.tbl b/arch/xtensa/kernel/syscalls/syscall.tbl index 3e3e1a506bed..52c94ab5c205 100644 --- a/arch/xtensa/kernel/syscalls/syscall.tbl +++ b/arch/xtensa/kernel/syscalls/syscall.tbl @@ -420,3 +420,4 @@ # 447 reserved for memfd_secret 448 common process_mrelease sys_process_mrelease 449 common futex_waitv sys_futex_waitv +450 common set_mempolicy_home_node sys_set_mempolicy_home_node diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index 528a478dbda8..819c0cb00b6d 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -1057,6 +1057,9 @@ asmlinkage long sys_landlock_add_rule(int ruleset_fd, enum landlock_rule_type ru const void __user *rule_attr, __u32 flags); asmlinkage long sys_landlock_restrict_self(int ruleset_fd, __u32 flags); asmlinkage long sys_memfd_secret(unsigned int flags); +asmlinkage long sys_set_mempolicy_home_node(unsigned long start, unsigned long len, + unsigned long home_node, + unsigned long flags); /* * Architecture-specific system calls diff --git a/include/uapi/asm-generic/unistd.h b/include/uapi/asm-generic/unistd.h index 4557a8b6086f..1c48b0ae3ba3 100644 --- a/include/uapi/asm-generic/unistd.h +++ b/include/uapi/asm-generic/unistd.h @@ -883,8 +883,11 @@ __SYSCALL(__NR_process_mrelease, sys_process_mrelease) #define __NR_futex_waitv 449 __SYSCALL(__NR_futex_waitv, sys_futex_waitv) +#define __NR_set_mempolicy_home_node 450 +__SYSCALL(__NR_set_mempolicy_home_node, sys_set_mempolicy_home_node) + #undef __NR_syscalls -#define __NR_syscalls 450 +#define __NR_syscalls 451 /* * 32 bit systems traditionally used different diff --git a/kernel/sys_ni.c b/kernel/sys_ni.c index d1944258cfc0..a492f159624f 100644 --- a/kernel/sys_ni.c +++ b/kernel/sys_ni.c @@ -297,6 +297,7 @@ COND_SYSCALL(get_mempolicy); COND_SYSCALL(set_mempolicy); COND_SYSCALL(migrate_pages); COND_SYSCALL(move_pages); +COND_SYSCALL(set_mempolicy_home_node); COND_SYSCALL(perf_event_open); COND_SYSCALL(accept4); -- cgit v1.2.3 From 47d8c15615c0a2046d2d90b04cb80b81ddf31fb1 Mon Sep 17 00:00:00 2001 From: Yury Norov Date: Sat, 14 Aug 2021 14:16:59 -0700 Subject: include: move find.h from asm_generic to linux find_bit API and bitmap API are closely related, but inclusion paths are different - include/asm-generic and include/linux, correspondingly. In the past it made a lot of troubles due to circular dependencies and/or undefined symbols. Fix this by moving find.h under include/linux. Signed-off-by: Yury Norov Tested-by: Wolfram Sang Acked-by: Geert Uytterhoeven --- MAINTAINERS | 2 +- arch/alpha/include/asm/bitops.h | 2 - arch/arc/include/asm/bitops.h | 1 - arch/arm/include/asm/bitops.h | 1 - arch/arm64/include/asm/bitops.h | 1 - arch/csky/include/asm/bitops.h | 1 - arch/h8300/include/asm/bitops.h | 1 - arch/hexagon/include/asm/bitops.h | 1 - arch/ia64/include/asm/bitops.h | 2 - arch/m68k/include/asm/bitops.h | 2 - arch/mips/include/asm/bitops.h | 1 - arch/openrisc/include/asm/bitops.h | 1 - arch/parisc/include/asm/bitops.h | 1 - arch/powerpc/include/asm/bitops.h | 2 - arch/riscv/include/asm/bitops.h | 1 - arch/s390/include/asm/bitops.h | 1 - arch/sh/include/asm/bitops.h | 1 - arch/sparc/include/asm/bitops_32.h | 1 - arch/sparc/include/asm/bitops_64.h | 2 - arch/x86/include/asm/bitops.h | 2 - arch/xtensa/include/asm/bitops.h | 1 - include/asm-generic/bitops.h | 1 - include/asm-generic/bitops/find.h | 262 ------------------------------------ include/linux/bitmap.h | 1 + include/linux/find.h | 268 +++++++++++++++++++++++++++++++++++++ 25 files changed, 270 insertions(+), 290 deletions(-) delete mode 100644 include/asm-generic/bitops/find.h create mode 100644 include/linux/find.h (limited to 'arch/arm') diff --git a/MAINTAINERS b/MAINTAINERS index dd36acc87ce6..4646786f5302 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3359,8 +3359,8 @@ M: Yury Norov R: Andy Shevchenko R: Rasmus Villemoes S: Maintained -F: include/asm-generic/bitops/find.h F: include/linux/bitmap.h +F: include/linux/find.h F: lib/bitmap.c F: lib/find_bit.c F: lib/find_bit_benchmark.c diff --git a/arch/alpha/include/asm/bitops.h b/arch/alpha/include/asm/bitops.h index 5adca78830b5..e1d8483a45f2 100644 --- a/arch/alpha/include/asm/bitops.h +++ b/arch/alpha/include/asm/bitops.h @@ -430,8 +430,6 @@ static inline unsigned int __arch_hweight8(unsigned int w) #endif /* __KERNEL__ */ -#include - #ifdef __KERNEL__ /* diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h index a7daaf64ae34..bdb7e190a294 100644 --- a/arch/arc/include/asm/bitops.h +++ b/arch/arc/include/asm/bitops.h @@ -189,7 +189,6 @@ static inline __attribute__ ((const)) unsigned long __ffs(unsigned long x) #include #include -#include #include #include diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index c92e42a5c8f7..8e94fe7ab5eb 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -264,7 +264,6 @@ static inline int find_next_bit_le(const void *p, int size, int offset) #endif -#include #include /* diff --git a/arch/arm64/include/asm/bitops.h b/arch/arm64/include/asm/bitops.h index 81a3e519b07d..9b3c787132d2 100644 --- a/arch/arm64/include/asm/bitops.h +++ b/arch/arm64/include/asm/bitops.h @@ -18,7 +18,6 @@ #include #include -#include #include #include diff --git a/arch/csky/include/asm/bitops.h b/arch/csky/include/asm/bitops.h index 02b72a000767..72e1b2aa29a0 100644 --- a/arch/csky/include/asm/bitops.h +++ b/arch/csky/include/asm/bitops.h @@ -59,7 +59,6 @@ static __always_inline unsigned long __fls(unsigned long x) #include #include -#include #ifndef _LINUX_BITOPS_H #error only can be included directly diff --git a/arch/h8300/include/asm/bitops.h b/arch/h8300/include/asm/bitops.h index c867a80cab5b..4489e3d6edd3 100644 --- a/arch/h8300/include/asm/bitops.h +++ b/arch/h8300/include/asm/bitops.h @@ -168,7 +168,6 @@ static inline unsigned long __ffs(unsigned long word) return result; } -#include #include #include #include diff --git a/arch/hexagon/include/asm/bitops.h b/arch/hexagon/include/asm/bitops.h index 71429f756af0..75d6ba3643b8 100644 --- a/arch/hexagon/include/asm/bitops.h +++ b/arch/hexagon/include/asm/bitops.h @@ -271,7 +271,6 @@ static inline unsigned long __fls(unsigned long word) } #include -#include #include #include diff --git a/arch/ia64/include/asm/bitops.h b/arch/ia64/include/asm/bitops.h index 2f24ee6459d2..577be93c0818 100644 --- a/arch/ia64/include/asm/bitops.h +++ b/arch/ia64/include/asm/bitops.h @@ -441,8 +441,6 @@ static __inline__ unsigned long __arch_hweight64(unsigned long x) #endif /* __KERNEL__ */ -#include - #ifdef __KERNEL__ #include diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index 7b93e1fd8ffa..51283db53667 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -529,6 +529,4 @@ static inline int __fls(int x) #include #endif /* __KERNEL__ */ -#include - #endif /* _M68K_BITOPS_H */ diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index dc2a6234dd3c..c09d57f907f7 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -446,7 +446,6 @@ static inline int ffs(int word) } #include -#include #ifdef __KERNEL__ diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h index 7f1ca35213d8..d773ed938acb 100644 --- a/arch/openrisc/include/asm/bitops.h +++ b/arch/openrisc/include/asm/bitops.h @@ -30,7 +30,6 @@ #include #include #include -#include #ifndef _LINUX_BITOPS_H #error only can be included directly diff --git a/arch/parisc/include/asm/bitops.h b/arch/parisc/include/asm/bitops.h index daa2afd974fb..0ec9cfc5131f 100644 --- a/arch/parisc/include/asm/bitops.h +++ b/arch/parisc/include/asm/bitops.h @@ -203,7 +203,6 @@ static __inline__ int fls(unsigned int x) #include #include #include -#include #include #include diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index 11847b6a244e..abc8f2c7c570 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -255,8 +255,6 @@ unsigned long __arch_hweight64(__u64 w); #include #endif -#include - /* wrappers that deal with KASAN instrumentation */ #include #include diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h index 396a3303c537..3540b690944b 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -20,7 +20,6 @@ #include #include #include -#include #include #include diff --git a/arch/s390/include/asm/bitops.h b/arch/s390/include/asm/bitops.h index 5a530c552c23..1d40630128a5 100644 --- a/arch/s390/include/asm/bitops.h +++ b/arch/s390/include/asm/bitops.h @@ -387,7 +387,6 @@ static inline int fls(unsigned int word) #endif /* CONFIG_HAVE_MARCH_Z9_109_FEATURES */ #include -#include #include #include #include diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h index 3b6c7b5b7ec9..10ceb0d6b5a9 100644 --- a/arch/sh/include/asm/bitops.h +++ b/arch/sh/include/asm/bitops.h @@ -68,6 +68,5 @@ static inline unsigned long __ffs(unsigned long word) #include #include -#include #endif /* __ASM_SH_BITOPS_H */ diff --git a/arch/sparc/include/asm/bitops_32.h b/arch/sparc/include/asm/bitops_32.h index 0ceff3b915a8..889afa9f990f 100644 --- a/arch/sparc/include/asm/bitops_32.h +++ b/arch/sparc/include/asm/bitops_32.h @@ -100,7 +100,6 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) #include #include #include -#include #include #include diff --git a/arch/sparc/include/asm/bitops_64.h b/arch/sparc/include/asm/bitops_64.h index ca7ea5913494..005a8ae858f1 100644 --- a/arch/sparc/include/asm/bitops_64.h +++ b/arch/sparc/include/asm/bitops_64.h @@ -52,8 +52,6 @@ unsigned int __arch_hweight8(unsigned int w); #include #endif /* __KERNEL__ */ -#include - #ifdef __KERNEL__ #include diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index 0367efdc5b7a..a288ecd230ab 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -380,8 +380,6 @@ static __always_inline int fls64(__u64 x) #include #endif -#include - #include #include diff --git a/arch/xtensa/include/asm/bitops.h b/arch/xtensa/include/asm/bitops.h index 3f71d364ba90..cd225896c40f 100644 --- a/arch/xtensa/include/asm/bitops.h +++ b/arch/xtensa/include/asm/bitops.h @@ -205,7 +205,6 @@ BIT_OPS(change, "xor", ) #undef BIT_OP #undef TEST_AND_BIT_OP -#include #include #include diff --git a/include/asm-generic/bitops.h b/include/asm-generic/bitops.h index df9b5bc3d282..a47b8a71d6fe 100644 --- a/include/asm-generic/bitops.h +++ b/include/asm-generic/bitops.h @@ -20,7 +20,6 @@ #include #include #include -#include #ifndef _LINUX_BITOPS_H #error only can be included directly diff --git a/include/asm-generic/bitops/find.h b/include/asm-generic/bitops/find.h deleted file mode 100644 index 91b1b23f2b0c..000000000000 --- a/include/asm-generic/bitops/find.h +++ /dev/null @@ -1,262 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_GENERIC_BITOPS_FIND_H_ -#define _ASM_GENERIC_BITOPS_FIND_H_ - -extern unsigned long _find_next_bit(const unsigned long *addr1, - const unsigned long *addr2, unsigned long nbits, - unsigned long start, unsigned long invert, unsigned long le); -extern unsigned long _find_first_bit(const unsigned long *addr, unsigned long size); -extern unsigned long _find_first_zero_bit(const unsigned long *addr, unsigned long size); -extern unsigned long _find_last_bit(const unsigned long *addr, unsigned long size); - -#ifndef find_next_bit -/** - * find_next_bit - find the next set bit in a memory region - * @addr: The address to base the search on - * @offset: The bitnumber to start searching at - * @size: The bitmap size in bits - * - * Returns the bit number for the next set bit - * If no bits are set, returns @size. - */ -static inline -unsigned long find_next_bit(const unsigned long *addr, unsigned long size, - unsigned long offset) -{ - if (small_const_nbits(size)) { - unsigned long val; - - if (unlikely(offset >= size)) - return size; - - val = *addr & GENMASK(size - 1, offset); - return val ? __ffs(val) : size; - } - - return _find_next_bit(addr, NULL, size, offset, 0UL, 0); -} -#endif - -#ifndef find_next_and_bit -/** - * find_next_and_bit - find the next set bit in both memory regions - * @addr1: The first address to base the search on - * @addr2: The second address to base the search on - * @offset: The bitnumber to start searching at - * @size: The bitmap size in bits - * - * Returns the bit number for the next set bit - * If no bits are set, returns @size. - */ -static inline -unsigned long find_next_and_bit(const unsigned long *addr1, - const unsigned long *addr2, unsigned long size, - unsigned long offset) -{ - if (small_const_nbits(size)) { - unsigned long val; - - if (unlikely(offset >= size)) - return size; - - val = *addr1 & *addr2 & GENMASK(size - 1, offset); - return val ? __ffs(val) : size; - } - - return _find_next_bit(addr1, addr2, size, offset, 0UL, 0); -} -#endif - -#ifndef find_next_zero_bit -/** - * find_next_zero_bit - find the next cleared bit in a memory region - * @addr: The address to base the search on - * @offset: The bitnumber to start searching at - * @size: The bitmap size in bits - * - * Returns the bit number of the next zero bit - * If no bits are zero, returns @size. - */ -static inline -unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size, - unsigned long offset) -{ - if (small_const_nbits(size)) { - unsigned long val; - - if (unlikely(offset >= size)) - return size; - - val = *addr | ~GENMASK(size - 1, offset); - return val == ~0UL ? size : ffz(val); - } - - return _find_next_bit(addr, NULL, size, offset, ~0UL, 0); -} -#endif - -#ifdef CONFIG_GENERIC_FIND_FIRST_BIT - -#ifndef find_first_bit -/** - * find_first_bit - find the first set bit in a memory region - * @addr: The address to start the search at - * @size: The maximum number of bits to search - * - * Returns the bit number of the first set bit. - * If no bits are set, returns @size. - */ -static inline -unsigned long find_first_bit(const unsigned long *addr, unsigned long size) -{ - if (small_const_nbits(size)) { - unsigned long val = *addr & GENMASK(size - 1, 0); - - return val ? __ffs(val) : size; - } - - return _find_first_bit(addr, size); -} -#endif - -#ifndef find_first_zero_bit -/** - * find_first_zero_bit - find the first cleared bit in a memory region - * @addr: The address to start the search at - * @size: The maximum number of bits to search - * - * Returns the bit number of the first cleared bit. - * If no bits are zero, returns @size. - */ -static inline -unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size) -{ - if (small_const_nbits(size)) { - unsigned long val = *addr | ~GENMASK(size - 1, 0); - - return val == ~0UL ? size : ffz(val); - } - - return _find_first_zero_bit(addr, size); -} -#endif - -#else /* CONFIG_GENERIC_FIND_FIRST_BIT */ - -#ifndef find_first_bit -#define find_first_bit(addr, size) find_next_bit((addr), (size), 0) -#endif -#ifndef find_first_zero_bit -#define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0) -#endif - -#endif /* CONFIG_GENERIC_FIND_FIRST_BIT */ - -#ifndef find_last_bit -/** - * find_last_bit - find the last set bit in a memory region - * @addr: The address to start the search at - * @size: The number of bits to search - * - * Returns the bit number of the last set bit, or size. - */ -static inline -unsigned long find_last_bit(const unsigned long *addr, unsigned long size) -{ - if (small_const_nbits(size)) { - unsigned long val = *addr & GENMASK(size - 1, 0); - - return val ? __fls(val) : size; - } - - return _find_last_bit(addr, size); -} -#endif - -/** - * find_next_clump8 - find next 8-bit clump with set bits in a memory region - * @clump: location to store copy of found clump - * @addr: address to base the search on - * @size: bitmap size in number of bits - * @offset: bit offset at which to start searching - * - * Returns the bit offset for the next set clump; the found clump value is - * copied to the location pointed by @clump. If no bits are set, returns @size. - */ -extern unsigned long find_next_clump8(unsigned long *clump, - const unsigned long *addr, - unsigned long size, unsigned long offset); - -#define find_first_clump8(clump, bits, size) \ - find_next_clump8((clump), (bits), (size), 0) - -#if defined(__LITTLE_ENDIAN) - -static inline unsigned long find_next_zero_bit_le(const void *addr, - unsigned long size, unsigned long offset) -{ - return find_next_zero_bit(addr, size, offset); -} - -static inline unsigned long find_next_bit_le(const void *addr, - unsigned long size, unsigned long offset) -{ - return find_next_bit(addr, size, offset); -} - -static inline unsigned long find_first_zero_bit_le(const void *addr, - unsigned long size) -{ - return find_first_zero_bit(addr, size); -} - -#elif defined(__BIG_ENDIAN) - -#ifndef find_next_zero_bit_le -static inline -unsigned long find_next_zero_bit_le(const void *addr, unsigned - long size, unsigned long offset) -{ - if (small_const_nbits(size)) { - unsigned long val = *(const unsigned long *)addr; - - if (unlikely(offset >= size)) - return size; - - val = swab(val) | ~GENMASK(size - 1, offset); - return val == ~0UL ? size : ffz(val); - } - - return _find_next_bit(addr, NULL, size, offset, ~0UL, 1); -} -#endif - -#ifndef find_next_bit_le -static inline -unsigned long find_next_bit_le(const void *addr, unsigned - long size, unsigned long offset) -{ - if (small_const_nbits(size)) { - unsigned long val = *(const unsigned long *)addr; - - if (unlikely(offset >= size)) - return size; - - val = swab(val) & GENMASK(size - 1, offset); - return val ? __ffs(val) : size; - } - - return _find_next_bit(addr, NULL, size, offset, 0UL, 1); -} -#endif - -#ifndef find_first_zero_bit_le -#define find_first_zero_bit_le(addr, size) \ - find_next_zero_bit_le((addr), (size), 0) -#endif - -#else -#error "Please fix " -#endif - -#endif /*_ASM_GENERIC_BITOPS_FIND_H_ */ diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h index a241dcf50f39..ead4a150bd7f 100644 --- a/include/linux/bitmap.h +++ b/include/linux/bitmap.h @@ -6,6 +6,7 @@ #include #include +#include #include #include #include diff --git a/include/linux/find.h b/include/linux/find.h new file mode 100644 index 000000000000..c5410c243e04 --- /dev/null +++ b/include/linux/find.h @@ -0,0 +1,268 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_FIND_H_ +#define __LINUX_FIND_H_ + +#ifndef __LINUX_BITMAP_H +#error only can be included directly +#endif + +#include + +extern unsigned long _find_next_bit(const unsigned long *addr1, + const unsigned long *addr2, unsigned long nbits, + unsigned long start, unsigned long invert, unsigned long le); +extern unsigned long _find_first_bit(const unsigned long *addr, unsigned long size); +extern unsigned long _find_first_zero_bit(const unsigned long *addr, unsigned long size); +extern unsigned long _find_last_bit(const unsigned long *addr, unsigned long size); + +#ifndef find_next_bit +/** + * find_next_bit - find the next set bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The bitmap size in bits + * + * Returns the bit number for the next set bit + * If no bits are set, returns @size. + */ +static inline +unsigned long find_next_bit(const unsigned long *addr, unsigned long size, + unsigned long offset) +{ + if (small_const_nbits(size)) { + unsigned long val; + + if (unlikely(offset >= size)) + return size; + + val = *addr & GENMASK(size - 1, offset); + return val ? __ffs(val) : size; + } + + return _find_next_bit(addr, NULL, size, offset, 0UL, 0); +} +#endif + +#ifndef find_next_and_bit +/** + * find_next_and_bit - find the next set bit in both memory regions + * @addr1: The first address to base the search on + * @addr2: The second address to base the search on + * @offset: The bitnumber to start searching at + * @size: The bitmap size in bits + * + * Returns the bit number for the next set bit + * If no bits are set, returns @size. + */ +static inline +unsigned long find_next_and_bit(const unsigned long *addr1, + const unsigned long *addr2, unsigned long size, + unsigned long offset) +{ + if (small_const_nbits(size)) { + unsigned long val; + + if (unlikely(offset >= size)) + return size; + + val = *addr1 & *addr2 & GENMASK(size - 1, offset); + return val ? __ffs(val) : size; + } + + return _find_next_bit(addr1, addr2, size, offset, 0UL, 0); +} +#endif + +#ifndef find_next_zero_bit +/** + * find_next_zero_bit - find the next cleared bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The bitmap size in bits + * + * Returns the bit number of the next zero bit + * If no bits are zero, returns @size. + */ +static inline +unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size, + unsigned long offset) +{ + if (small_const_nbits(size)) { + unsigned long val; + + if (unlikely(offset >= size)) + return size; + + val = *addr | ~GENMASK(size - 1, offset); + return val == ~0UL ? size : ffz(val); + } + + return _find_next_bit(addr, NULL, size, offset, ~0UL, 0); +} +#endif + +#ifdef CONFIG_GENERIC_FIND_FIRST_BIT + +#ifndef find_first_bit +/** + * find_first_bit - find the first set bit in a memory region + * @addr: The address to start the search at + * @size: The maximum number of bits to search + * + * Returns the bit number of the first set bit. + * If no bits are set, returns @size. + */ +static inline +unsigned long find_first_bit(const unsigned long *addr, unsigned long size) +{ + if (small_const_nbits(size)) { + unsigned long val = *addr & GENMASK(size - 1, 0); + + return val ? __ffs(val) : size; + } + + return _find_first_bit(addr, size); +} +#endif + +#ifndef find_first_zero_bit +/** + * find_first_zero_bit - find the first cleared bit in a memory region + * @addr: The address to start the search at + * @size: The maximum number of bits to search + * + * Returns the bit number of the first cleared bit. + * If no bits are zero, returns @size. + */ +static inline +unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size) +{ + if (small_const_nbits(size)) { + unsigned long val = *addr | ~GENMASK(size - 1, 0); + + return val == ~0UL ? size : ffz(val); + } + + return _find_first_zero_bit(addr, size); +} +#endif + +#else /* CONFIG_GENERIC_FIND_FIRST_BIT */ + +#ifndef find_first_bit +#define find_first_bit(addr, size) find_next_bit((addr), (size), 0) +#endif +#ifndef find_first_zero_bit +#define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0) +#endif + +#endif /* CONFIG_GENERIC_FIND_FIRST_BIT */ + +#ifndef find_last_bit +/** + * find_last_bit - find the last set bit in a memory region + * @addr: The address to start the search at + * @size: The number of bits to search + * + * Returns the bit number of the last set bit, or size. + */ +static inline +unsigned long find_last_bit(const unsigned long *addr, unsigned long size) +{ + if (small_const_nbits(size)) { + unsigned long val = *addr & GENMASK(size - 1, 0); + + return val ? __fls(val) : size; + } + + return _find_last_bit(addr, size); +} +#endif + +/** + * find_next_clump8 - find next 8-bit clump with set bits in a memory region + * @clump: location to store copy of found clump + * @addr: address to base the search on + * @size: bitmap size in number of bits + * @offset: bit offset at which to start searching + * + * Returns the bit offset for the next set clump; the found clump value is + * copied to the location pointed by @clump. If no bits are set, returns @size. + */ +extern unsigned long find_next_clump8(unsigned long *clump, + const unsigned long *addr, + unsigned long size, unsigned long offset); + +#define find_first_clump8(clump, bits, size) \ + find_next_clump8((clump), (bits), (size), 0) + +#if defined(__LITTLE_ENDIAN) + +static inline unsigned long find_next_zero_bit_le(const void *addr, + unsigned long size, unsigned long offset) +{ + return find_next_zero_bit(addr, size, offset); +} + +static inline unsigned long find_next_bit_le(const void *addr, + unsigned long size, unsigned long offset) +{ + return find_next_bit(addr, size, offset); +} + +static inline unsigned long find_first_zero_bit_le(const void *addr, + unsigned long size) +{ + return find_first_zero_bit(addr, size); +} + +#elif defined(__BIG_ENDIAN) + +#ifndef find_next_zero_bit_le +static inline +unsigned long find_next_zero_bit_le(const void *addr, unsigned + long size, unsigned long offset) +{ + if (small_const_nbits(size)) { + unsigned long val = *(const unsigned long *)addr; + + if (unlikely(offset >= size)) + return size; + + val = swab(val) | ~GENMASK(size - 1, offset); + return val == ~0UL ? size : ffz(val); + } + + return _find_next_bit(addr, NULL, size, offset, ~0UL, 1); +} +#endif + +#ifndef find_next_bit_le +static inline +unsigned long find_next_bit_le(const void *addr, unsigned + long size, unsigned long offset) +{ + if (small_const_nbits(size)) { + unsigned long val = *(const unsigned long *)addr; + + if (unlikely(offset >= size)) + return size; + + val = swab(val) & GENMASK(size - 1, offset); + return val ? __ffs(val) : size; + } + + return _find_next_bit(addr, NULL, size, offset, 0UL, 1); +} +#endif + +#ifndef find_first_zero_bit_le +#define find_first_zero_bit_le(addr, size) \ + find_next_zero_bit_le((addr), (size), 0) +#endif + +#else +#error "Please fix " +#endif + +#endif /*__LINUX_FIND_H_ */ -- cgit v1.2.3 From 8b59b0a53c840921b625378f137e88adfa87647e Mon Sep 17 00:00:00 2001 From: sparkhuang Date: Wed, 15 Dec 2021 10:08:23 +0100 Subject: ARM: 9170/1: fix panic when kasan and kprobe are enabled arm32 uses software to simulate the instruction replaced by kprobe. some instructions may be simulated by constructing assembly functions. therefore, before executing instruction simulation, it is necessary to construct assembly function execution environment in C language through binding registers. after kasan is enabled, the register binding relationship will be destroyed, resulting in instruction simulation errors and causing kernel panic. the kprobe emulate instruction function is distributed in three files: actions-common.c actions-arm.c actions-thumb.c, so disable KASAN when compiling these files. for example, use kprobe insert on cap_capable+20 after kasan enabled, the cap_capable assembly code is as follows: : e92d47f0 push {r4, r5, r6, r7, r8, r9, sl, lr} e1a05000 mov r5, r0 e280006c add r0, r0, #108 ; 0x6c e1a04001 mov r4, r1 e1a06002 mov r6, r2 e59fa090 ldr sl, [pc, #144] ; ebfc7bf8 bl c03aa4b4 <__asan_load4> e595706c ldr r7, [r5, #108] ; 0x6c e2859014 add r9, r5, #20 ...... The emulate_ldr assembly code after enabling kasan is as follows: c06f1384 : e92d47f0 push {r4, r5, r6, r7, r8, r9, sl, lr} e282803c add r8, r2, #60 ; 0x3c e1a05000 mov r5, r0 e7e37855 ubfx r7, r5, #16, #4 e1a00008 mov r0, r8 e1a09001 mov r9, r1 e1a04002 mov r4, r2 ebf35462 bl c03c6530 <__asan_load4> e357000f cmp r7, #15 e7e36655 ubfx r6, r5, #12, #4 e205a00f and sl, r5, #15 0a000001 beq c06f13bc e0840107 add r0, r4, r7, lsl #2 ebf3545c bl c03c6530 <__asan_load4> e084010a add r0, r4, sl, lsl #2 ebf3545a bl c03c6530 <__asan_load4> e2890010 add r0, r9, #16 ebf35458 bl c03c6530 <__asan_load4> e5990010 ldr r0, [r9, #16] e12fff30 blx r0 e356000f cm r6, #15 1a000014 bne c06f1430 e1a06000 mov r6, r0 e2840040 add r0, r4, #64 ; 0x40 ...... when running in emulate_ldr to simulate the ldr instruction, panic occurred, and the log is as follows: Unable to handle kernel NULL pointer dereference at virtual address 00000090 pgd = ecb46400 [00000090] *pgd=2e0fa003, *pmd=00000000 Internal error: Oops: 206 [#1] SMP ARM PC is at cap_capable+0x14/0xb0 LR is at emulate_ldr+0x50/0xc0 psr: 600d0293 sp : ecd63af8 ip : 00000004 fp : c0a7c30c r10: 00000000 r9 : c30897f4 r8 : ecd63cd4 r7 : 0000000f r6 : 0000000a r5 : e59fa090 r4 : ecd63c98 r3 : c06ae294 r2 : 00000000 r1 : b7611300 r0 : bf4ec008 Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user Control: 32c5387d Table: 2d546400 DAC: 55555555 Process bash (pid: 1643, stack limit = 0xecd60190) (cap_capable) from (kprobe_handler+0x218/0x340) (kprobe_handler) from (kprobe_trap_handler+0x24/0x48) (kprobe_trap_handler) from (do_undefinstr+0x13c/0x364) (do_undefinstr) from (__und_svc_finish+0x0/0x30) (__und_svc_finish) from (cap_capable+0x18/0xb0) (cap_capable) from (cap_vm_enough_memory+0x38/0x48) (cap_vm_enough_memory) from (security_vm_enough_memory_mm+0x48/0x6c) (security_vm_enough_memory_mm) from (copy_process.constprop.5+0x16b4/0x25c8) (copy_process.constprop.5) from (_do_fork+0xe8/0x55c) (_do_fork) from (SyS_clone+0x1c/0x24) (SyS_clone) from (__sys_trace_return+0x0/0x10) Code: 0050a0e1 6c0080e2 0140a0e1 0260a0e1 (f801f0e7) Fixes: 35aa1df43283 ("ARM kprobes: instruction single-stepping support") Fixes: 421015713b30 ("ARM: 9017/2: Enable KASan for ARM") Signed-off-by: huangshaobo Acked-by: Ard Biesheuvel Signed-off-by: Russell King (Oracle) --- arch/arm/probes/kprobes/Makefile | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/probes/kprobes/Makefile b/arch/arm/probes/kprobes/Makefile index 14db56f49f0a..6159010dac4a 100644 --- a/arch/arm/probes/kprobes/Makefile +++ b/arch/arm/probes/kprobes/Makefile @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 +KASAN_SANITIZE_actions-common.o := n +KASAN_SANITIZE_actions-arm.o := n +KASAN_SANITIZE_actions-thumb.o := n obj-$(CONFIG_KPROBES) += core.o actions-common.o checkers-common.o obj-$(CONFIG_ARM_KPROBES_TEST) += test-kprobes.o test-kprobes-objs := test-core.o -- cgit v1.2.3 From 15420269b02a63ed8c1841905d8b8b2403246004 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 18 Jan 2022 13:45:09 +0100 Subject: ARM: 9179/1: uaccess: avoid alignment faults in copy_[from|to]_kernel_nofault The helpers that are used to implement copy_from_kernel_nofault() and copy_to_kernel_nofault() cast a void* to a pointer to a wider type, which may result in alignment faults on ARM if the compiler decides to use double-word or multiple-word load/store instructions. Only configurations that define CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y are affected, given that commit 2423de2e6f4d ("ARM: 9115/1: mm/maccess: fix unaligned copy_{from,to}_kernel_nofault") ensures that dst and src are sufficiently aligned otherwise. So use the unaligned accessors for accessing dst and src in cases where they may be misaligned. Cc: # depends on 2423de2e6f4d Fixes: 2df4c9a741a0 ("ARM: 9112/1: uaccess: add __{get,put}_kernel_nofault") Reviewed-by: Arnd Bergmann Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King (Oracle) --- arch/arm/include/asm/uaccess.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 36fbc3329252..32dbfd81f42a 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -497,7 +498,10 @@ do { \ } \ default: __err = __get_user_bad(); break; \ } \ - *(type *)(dst) = __val; \ + if (IS_ENABLED(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)) \ + put_unaligned(__val, (type *)(dst)); \ + else \ + *(type *)(dst) = __val; /* aligned by caller */ \ if (__err) \ goto err_label; \ } while (0) @@ -507,7 +511,9 @@ do { \ const type *__pk_ptr = (dst); \ unsigned long __dst = (unsigned long)__pk_ptr; \ int __err = 0; \ - type __val = *(type *)src; \ + type __val = IS_ENABLED(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) \ + ? get_unaligned((type *)(src)) \ + : *(type *)(src); /* aligned by caller */ \ switch (sizeof(type)) { \ case 1: __put_user_asm_byte(__val, __dst, __err, ""); break; \ case 2: __put_user_asm_half(__val, __dst, __err, ""); break; \ -- cgit v1.2.3 From 9f80ccda53b9417236945bc7ece4b519037df74d Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 18 Jan 2022 19:32:17 +0100 Subject: ARM: 9180/1: Thumb2: align ALT_UP() sections in modules sufficiently When building for Thumb2, the .alt.smp.init sections that are emitted by the ALT_UP() patching code may not be 32-bit aligned, even though the fixup_smp_on_up() routine expects that. This results in alignment faults at module load time, which need to be fixed up by the fault handler. So let's align those sections explicitly, and prevent this from occurring. Cc: Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King (Oracle) --- arch/arm/include/asm/assembler.h | 2 ++ arch/arm/include/asm/processor.h | 1 + 2 files changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 7d23d4bb2168..6fe67963ba5a 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -288,6 +288,7 @@ */ #define ALT_UP(instr...) \ .pushsection ".alt.smp.init", "a" ;\ + .align 2 ;\ .long 9998b - . ;\ 9997: instr ;\ .if . - 9997b == 2 ;\ @@ -299,6 +300,7 @@ .popsection #define ALT_UP_B(label) \ .pushsection ".alt.smp.init", "a" ;\ + .align 2 ;\ .long 9998b - . ;\ W(b) . + (label - 9998b) ;\ .popsection diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 6af68edfa53a..bdc35c0e8dfb 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -96,6 +96,7 @@ unsigned long __get_wchan(struct task_struct *p); #define __ALT_SMP_ASM(smp, up) \ "9998: " smp "\n" \ " .pushsection \".alt.smp.init\", \"a\"\n" \ + " .align 2\n" \ " .long 9998b - .\n" \ " " up "\n" \ " .popsection\n" -- cgit v1.2.3 From d8c0418aac78e661b5283c9d6a1dfc61d44f26fd Mon Sep 17 00:00:00 2001 From: Luis Chamberlain Date: Fri, 21 Jan 2022 22:13:31 -0800 Subject: kernel/sysctl.c: rename sysctl_init() to sysctl_init_bases() Rename sysctl_init() to sysctl_init_bases() so to reflect exactly what this is doing. Link: https://lkml.kernel.org/r/20211129211943.640266-4-mcgrof@kernel.org Signed-off-by: Luis Chamberlain Cc: Al Viro Cc: Anil S Keshavamurthy Cc: Antti Palosaari Cc: Christian Brauner Cc: "David S. Miller" Cc: Eric Biederman Cc: Eric Biggers Cc: Iurii Zaikin Cc: Kees Cook Cc: Lukas Middendorf Cc: Masami Hiramatsu Cc: "Naveen N. Rao" Cc: Stephen Kitt Cc: Xiaoming Ni Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/mm/alignment.c | 2 +- arch/sh/mm/alignment.c | 2 +- fs/proc/proc_sysctl.c | 4 ++-- include/linux/sysctl.h | 2 +- kernel/sysctl.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index adbb3817d0be..6f499559d193 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -1005,7 +1005,7 @@ static int __init noalign_setup(char *__unused) __setup("noalign", noalign_setup); /* - * This needs to be done after sysctl_init, otherwise sys/ will be + * This needs to be done after sysctl_init_bases(), otherwise sys/ will be * overwritten. Actually, this shouldn't be in sys/ at all since * it isn't a sysctl, and it doesn't contain sysctl information. * We now locate it in /proc/cpu/alignment instead. diff --git a/arch/sh/mm/alignment.c b/arch/sh/mm/alignment.c index fb517b82a87b..d802801ceb93 100644 --- a/arch/sh/mm/alignment.c +++ b/arch/sh/mm/alignment.c @@ -161,7 +161,7 @@ static const struct proc_ops alignment_proc_ops = { }; /* - * This needs to be done after sysctl_init, otherwise sys/ will be + * This needs to be done after sysctl_init_bases(), otherwise sys/ will be * overwritten. Actually, this shouldn't be in sys/ at all since * it isn't a sysctl, and it doesn't contain sysctl information. * We now locate it in /proc/cpu/alignment instead. diff --git a/fs/proc/proc_sysctl.c b/fs/proc/proc_sysctl.c index 95dfd195e04e..7d9cfc730bd4 100644 --- a/fs/proc/proc_sysctl.c +++ b/fs/proc/proc_sysctl.c @@ -1419,7 +1419,7 @@ EXPORT_SYMBOL(register_sysctl); * Context: Can only be called after your respective sysctl base path has been * registered. So for instance, most base directories are registered early on * init before init levels are processed through proc_sys_init() and - * sysctl_init(). + * sysctl_init_bases(). */ void __init __register_sysctl_init(const char *path, struct ctl_table *table, const char *table_name) @@ -1768,7 +1768,7 @@ int __init proc_sys_init(void) proc_sys_root->proc_dir_ops = &proc_sys_dir_file_operations; proc_sys_root->nlink = 0; - return sysctl_init(); + return sysctl_init_bases(); } struct sysctl_alias { diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h index 02134a8abad7..180adf7da785 100644 --- a/include/linux/sysctl.h +++ b/include/linux/sysctl.h @@ -228,7 +228,7 @@ struct ctl_table_header *register_sysctl_paths(const struct ctl_path *path, void unregister_sysctl_table(struct ctl_table_header * table); -extern int sysctl_init(void); +extern int sysctl_init_bases(void); extern void __register_sysctl_init(const char *path, struct ctl_table *table, const char *table_name); #define register_sysctl_init(path, table) __register_sysctl_init(path, table, #table) diff --git a/kernel/sysctl.c b/kernel/sysctl.c index cdc3dc5f0005..bb07183cd305 100644 --- a/kernel/sysctl.c +++ b/kernel/sysctl.c @@ -2844,7 +2844,7 @@ DECLARE_SYSCTL_BASE(vm, vm_table); DECLARE_SYSCTL_BASE(debug, debug_table); DECLARE_SYSCTL_BASE(dev, dev_table); -int __init sysctl_init(void) +int __init sysctl_init_bases(void) { register_sysctl_base(kernel); register_sysctl_base(vm); -- cgit v1.2.3 From 359745d78351c6f5442435f81549f0207ece28aa Mon Sep 17 00:00:00 2001 From: Muchun Song Date: Fri, 21 Jan 2022 22:14:23 -0800 Subject: proc: remove PDE_DATA() completely Remove PDE_DATA() completely and replace it with pde_data(). [akpm@linux-foundation.org: fix naming clash in drivers/nubus/proc.c] [akpm@linux-foundation.org: now fix it properly] Link: https://lkml.kernel.org/r/20211124081956.87711-2-songmuchun@bytedance.com Signed-off-by: Muchun Song Acked-by: Christian Brauner Cc: Alexey Dobriyan Cc: Alexey Gladkov Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/alpha/kernel/srm_env.c | 4 +-- arch/arm/kernel/atags_proc.c | 2 +- arch/ia64/kernel/salinfo.c | 10 +++--- arch/powerpc/kernel/proc_powerpc.c | 4 +-- arch/sh/mm/alignment.c | 2 +- arch/xtensa/platforms/iss/simdisk.c | 4 +-- drivers/acpi/proc.c | 2 +- drivers/hwmon/dell-smm-hwmon.c | 4 +-- drivers/net/bonding/bond_procfs.c | 8 ++--- drivers/net/wireless/cisco/airo.c | 22 ++++++------- drivers/net/wireless/intersil/hostap/hostap_ap.c | 16 +++++----- .../net/wireless/intersil/hostap/hostap_download.c | 2 +- drivers/net/wireless/intersil/hostap/hostap_proc.c | 24 +++++++-------- drivers/net/wireless/ray_cs.c | 2 +- drivers/nubus/proc.c | 36 +++++++++++----------- drivers/parisc/led.c | 4 +-- drivers/pci/proc.c | 10 +++--- drivers/platform/x86/thinkpad_acpi.c | 4 +-- drivers/platform/x86/toshiba_acpi.c | 16 +++++----- drivers/pnp/isapnp/proc.c | 2 +- drivers/pnp/pnpbios/proc.c | 4 +-- drivers/scsi/scsi_proc.c | 4 +-- drivers/usb/gadget/function/rndis.c | 4 +-- drivers/zorro/proc.c | 2 +- fs/afs/proc.c | 6 ++-- fs/ext4/mballoc.c | 14 ++++----- fs/jbd2/journal.c | 2 +- fs/proc/proc_net.c | 8 ++--- include/linux/proc_fs.h | 4 +-- include/linux/seq_file.h | 2 +- ipc/util.c | 2 +- kernel/irq/proc.c | 8 ++--- kernel/resource.c | 4 +-- net/atm/proc.c | 4 +-- net/bluetooth/af_bluetooth.c | 8 ++--- net/can/bcm.c | 2 +- net/can/proc.c | 2 +- net/core/neighbour.c | 6 ++-- net/core/pktgen.c | 6 ++-- net/ipv4/netfilter/ipt_CLUSTERIP.c | 6 ++-- net/ipv4/raw.c | 8 ++--- net/ipv4/tcp_ipv4.c | 2 +- net/ipv4/udp.c | 6 ++-- net/netfilter/x_tables.c | 10 +++--- net/netfilter/xt_hashlimit.c | 18 +++++------ net/netfilter/xt_recent.c | 4 +-- net/sunrpc/auth_gss/svcauth_gss.c | 4 +-- net/sunrpc/cache.c | 24 +++++++-------- net/sunrpc/stats.c | 2 +- sound/core/info.c | 4 +-- 50 files changed, 178 insertions(+), 180 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/kernel/srm_env.c b/arch/alpha/kernel/srm_env.c index 528d2be58182..217b4dca51dd 100644 --- a/arch/alpha/kernel/srm_env.c +++ b/arch/alpha/kernel/srm_env.c @@ -83,14 +83,14 @@ static int srm_env_proc_show(struct seq_file *m, void *v) static int srm_env_proc_open(struct inode *inode, struct file *file) { - return single_open(file, srm_env_proc_show, PDE_DATA(inode)); + return single_open(file, srm_env_proc_show, pde_data(inode)); } static ssize_t srm_env_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) { int res; - unsigned long id = (unsigned long)PDE_DATA(file_inode(file)); + unsigned long id = (unsigned long)pde_data(file_inode(file)); char *buf = (char *) __get_free_page(GFP_USER); unsigned long ret1, ret2; diff --git a/arch/arm/kernel/atags_proc.c b/arch/arm/kernel/atags_proc.c index 3c2faf2bd124..3ec2afe78423 100644 --- a/arch/arm/kernel/atags_proc.c +++ b/arch/arm/kernel/atags_proc.c @@ -13,7 +13,7 @@ struct buffer { static ssize_t atags_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) { - struct buffer *b = PDE_DATA(file_inode(file)); + struct buffer *b = pde_data(file_inode(file)); return simple_read_from_buffer(buf, count, ppos, b->data, b->size); } diff --git a/arch/ia64/kernel/salinfo.c b/arch/ia64/kernel/salinfo.c index a25ab9b37953..bd3ba276e69c 100644 --- a/arch/ia64/kernel/salinfo.c +++ b/arch/ia64/kernel/salinfo.c @@ -282,7 +282,7 @@ salinfo_event_open(struct inode *inode, struct file *file) static ssize_t salinfo_event_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos) { - struct salinfo_data *data = PDE_DATA(file_inode(file)); + struct salinfo_data *data = pde_data(file_inode(file)); char cmd[32]; size_t size; int i, n, cpu = -1; @@ -340,7 +340,7 @@ static const struct proc_ops salinfo_event_proc_ops = { static int salinfo_log_open(struct inode *inode, struct file *file) { - struct salinfo_data *data = PDE_DATA(inode); + struct salinfo_data *data = pde_data(inode); if (!capable(CAP_SYS_ADMIN)) return -EPERM; @@ -365,7 +365,7 @@ salinfo_log_open(struct inode *inode, struct file *file) static int salinfo_log_release(struct inode *inode, struct file *file) { - struct salinfo_data *data = PDE_DATA(inode); + struct salinfo_data *data = pde_data(inode); if (data->state == STATE_NO_DATA) { vfree(data->log_buffer); @@ -433,7 +433,7 @@ retry: static ssize_t salinfo_log_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos) { - struct salinfo_data *data = PDE_DATA(file_inode(file)); + struct salinfo_data *data = pde_data(file_inode(file)); u8 *buf; u64 bufsize; @@ -494,7 +494,7 @@ salinfo_log_clear(struct salinfo_data *data, int cpu) static ssize_t salinfo_log_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos) { - struct salinfo_data *data = PDE_DATA(file_inode(file)); + struct salinfo_data *data = pde_data(file_inode(file)); char cmd[32]; size_t size; u32 offset; diff --git a/arch/powerpc/kernel/proc_powerpc.c b/arch/powerpc/kernel/proc_powerpc.c index 877817471e3c..6a029f2378e1 100644 --- a/arch/powerpc/kernel/proc_powerpc.c +++ b/arch/powerpc/kernel/proc_powerpc.c @@ -25,7 +25,7 @@ static ssize_t page_map_read( struct file *file, char __user *buf, size_t nbytes loff_t *ppos) { return simple_read_from_buffer(buf, nbytes, ppos, - PDE_DATA(file_inode(file)), PAGE_SIZE); + pde_data(file_inode(file)), PAGE_SIZE); } static int page_map_mmap( struct file *file, struct vm_area_struct *vma ) @@ -34,7 +34,7 @@ static int page_map_mmap( struct file *file, struct vm_area_struct *vma ) return -EINVAL; remap_pfn_range(vma, vma->vm_start, - __pa(PDE_DATA(file_inode(file))) >> PAGE_SHIFT, + __pa(pde_data(file_inode(file))) >> PAGE_SHIFT, PAGE_SIZE, vma->vm_page_prot); return 0; } diff --git a/arch/sh/mm/alignment.c b/arch/sh/mm/alignment.c index d802801ceb93..3a76a766f423 100644 --- a/arch/sh/mm/alignment.c +++ b/arch/sh/mm/alignment.c @@ -140,7 +140,7 @@ static int alignment_proc_open(struct inode *inode, struct file *file) static ssize_t alignment_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) { - int *data = PDE_DATA(file_inode(file)); + int *data = pde_data(file_inode(file)); char mode; if (count > 0) { diff --git a/arch/xtensa/platforms/iss/simdisk.c b/arch/xtensa/platforms/iss/simdisk.c index 07b642c1916a..8eb6ad1a3a1d 100644 --- a/arch/xtensa/platforms/iss/simdisk.c +++ b/arch/xtensa/platforms/iss/simdisk.c @@ -208,7 +208,7 @@ static int simdisk_detach(struct simdisk *dev) static ssize_t proc_read_simdisk(struct file *file, char __user *buf, size_t size, loff_t *ppos) { - struct simdisk *dev = PDE_DATA(file_inode(file)); + struct simdisk *dev = pde_data(file_inode(file)); const char *s = dev->filename; if (s) { ssize_t n = simple_read_from_buffer(buf, size, ppos, @@ -225,7 +225,7 @@ static ssize_t proc_write_simdisk(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { char *tmp = memdup_user_nul(buf, count); - struct simdisk *dev = PDE_DATA(file_inode(file)); + struct simdisk *dev = pde_data(file_inode(file)); int err; if (IS_ERR(tmp)) diff --git a/drivers/acpi/proc.c b/drivers/acpi/proc.c index 0cca7991f186..4322f2da6d10 100644 --- a/drivers/acpi/proc.c +++ b/drivers/acpi/proc.c @@ -127,7 +127,7 @@ static int acpi_system_wakeup_device_open_fs(struct inode *inode, struct file *file) { return single_open(file, acpi_system_wakeup_device_seq_show, - PDE_DATA(inode)); + pde_data(inode)); } static const struct proc_ops acpi_system_wakeup_device_proc_ops = { diff --git a/drivers/hwmon/dell-smm-hwmon.c b/drivers/hwmon/dell-smm-hwmon.c index d401f9acf450..9949eeb79378 100644 --- a/drivers/hwmon/dell-smm-hwmon.c +++ b/drivers/hwmon/dell-smm-hwmon.c @@ -451,7 +451,7 @@ static int i8k_get_power_status(void) static long i8k_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) { - struct dell_smm_data *data = PDE_DATA(file_inode(fp)); + struct dell_smm_data *data = pde_data(file_inode(fp)); int __user *argp = (int __user *)arg; int speed, err; int val = 0; @@ -585,7 +585,7 @@ static int i8k_proc_show(struct seq_file *seq, void *offset) static int i8k_open_fs(struct inode *inode, struct file *file) { - return single_open(file, i8k_proc_show, PDE_DATA(inode)); + return single_open(file, i8k_proc_show, pde_data(inode)); } static const struct proc_ops i8k_proc_ops = { diff --git a/drivers/net/bonding/bond_procfs.c b/drivers/net/bonding/bond_procfs.c index 2ec11af5f0cc..46b150e6289e 100644 --- a/drivers/net/bonding/bond_procfs.c +++ b/drivers/net/bonding/bond_procfs.c @@ -11,7 +11,7 @@ static void *bond_info_seq_start(struct seq_file *seq, loff_t *pos) __acquires(RCU) { - struct bonding *bond = PDE_DATA(file_inode(seq->file)); + struct bonding *bond = pde_data(file_inode(seq->file)); struct list_head *iter; struct slave *slave; loff_t off = 0; @@ -30,7 +30,7 @@ static void *bond_info_seq_start(struct seq_file *seq, loff_t *pos) static void *bond_info_seq_next(struct seq_file *seq, void *v, loff_t *pos) { - struct bonding *bond = PDE_DATA(file_inode(seq->file)); + struct bonding *bond = pde_data(file_inode(seq->file)); struct list_head *iter; struct slave *slave; bool found = false; @@ -57,7 +57,7 @@ static void bond_info_seq_stop(struct seq_file *seq, void *v) static void bond_info_show_master(struct seq_file *seq) { - struct bonding *bond = PDE_DATA(file_inode(seq->file)); + struct bonding *bond = pde_data(file_inode(seq->file)); const struct bond_opt_value *optval; struct slave *curr, *primary; int i; @@ -175,7 +175,7 @@ static void bond_info_show_master(struct seq_file *seq) static void bond_info_show_slave(struct seq_file *seq, const struct slave *slave) { - struct bonding *bond = PDE_DATA(file_inode(seq->file)); + struct bonding *bond = pde_data(file_inode(seq->file)); seq_printf(seq, "\nSlave Interface: %s\n", slave->dev->name); seq_printf(seq, "MII Status: %s\n", bond_slave_link_status(slave->link)); diff --git a/drivers/net/wireless/cisco/airo.c b/drivers/net/wireless/cisco/airo.c index 45594f003ef7..452d08545d31 100644 --- a/drivers/net/wireless/cisco/airo.c +++ b/drivers/net/wireless/cisco/airo.c @@ -4672,7 +4672,7 @@ static ssize_t proc_write(struct file *file, static int proc_status_open(struct inode *inode, struct file *file) { struct proc_data *data; - struct net_device *dev = PDE_DATA(inode); + struct net_device *dev = pde_data(inode); struct airo_info *apriv = dev->ml_priv; CapabilityRid cap_rid; StatusRid status_rid; @@ -4756,7 +4756,7 @@ static int proc_stats_rid_open(struct inode *inode, u16 rid) { struct proc_data *data; - struct net_device *dev = PDE_DATA(inode); + struct net_device *dev = pde_data(inode); struct airo_info *apriv = dev->ml_priv; StatsRid stats; int i, j; @@ -4819,7 +4819,7 @@ static inline int sniffing_mode(struct airo_info *ai) static void proc_config_on_close(struct inode *inode, struct file *file) { struct proc_data *data = file->private_data; - struct net_device *dev = PDE_DATA(inode); + struct net_device *dev = pde_data(inode); struct airo_info *ai = dev->ml_priv; char *line; @@ -5030,7 +5030,7 @@ static const char *get_rmode(__le16 mode) static int proc_config_open(struct inode *inode, struct file *file) { struct proc_data *data; - struct net_device *dev = PDE_DATA(inode); + struct net_device *dev = pde_data(inode); struct airo_info *ai = dev->ml_priv; int i; __le16 mode; @@ -5120,7 +5120,7 @@ static int proc_config_open(struct inode *inode, struct file *file) static void proc_SSID_on_close(struct inode *inode, struct file *file) { struct proc_data *data = file->private_data; - struct net_device *dev = PDE_DATA(inode); + struct net_device *dev = pde_data(inode); struct airo_info *ai = dev->ml_priv; SsidRid SSID_rid; int i; @@ -5156,7 +5156,7 @@ static void proc_SSID_on_close(struct inode *inode, struct file *file) static void proc_APList_on_close(struct inode *inode, struct file *file) { struct proc_data *data = file->private_data; - struct net_device *dev = PDE_DATA(inode); + struct net_device *dev = pde_data(inode); struct airo_info *ai = dev->ml_priv; APListRid *APList_rid = &ai->APList; int i; @@ -5280,7 +5280,7 @@ static int set_wep_tx_idx(struct airo_info *ai, u16 index, int perm, int lock) static void proc_wepkey_on_close(struct inode *inode, struct file *file) { struct proc_data *data; - struct net_device *dev = PDE_DATA(inode); + struct net_device *dev = pde_data(inode); struct airo_info *ai = dev->ml_priv; int i, rc; char key[16]; @@ -5331,7 +5331,7 @@ static void proc_wepkey_on_close(struct inode *inode, struct file *file) static int proc_wepkey_open(struct inode *inode, struct file *file) { struct proc_data *data; - struct net_device *dev = PDE_DATA(inode); + struct net_device *dev = pde_data(inode); struct airo_info *ai = dev->ml_priv; char *ptr; WepKeyRid wkr; @@ -5379,7 +5379,7 @@ static int proc_wepkey_open(struct inode *inode, struct file *file) static int proc_SSID_open(struct inode *inode, struct file *file) { struct proc_data *data; - struct net_device *dev = PDE_DATA(inode); + struct net_device *dev = pde_data(inode); struct airo_info *ai = dev->ml_priv; int i; char *ptr; @@ -5423,7 +5423,7 @@ static int proc_SSID_open(struct inode *inode, struct file *file) static int proc_APList_open(struct inode *inode, struct file *file) { struct proc_data *data; - struct net_device *dev = PDE_DATA(inode); + struct net_device *dev = pde_data(inode); struct airo_info *ai = dev->ml_priv; int i; char *ptr; @@ -5462,7 +5462,7 @@ static int proc_APList_open(struct inode *inode, struct file *file) static int proc_BSSList_open(struct inode *inode, struct file *file) { struct proc_data *data; - struct net_device *dev = PDE_DATA(inode); + struct net_device *dev = pde_data(inode); struct airo_info *ai = dev->ml_priv; char *ptr; BSSListRid BSSList_rid; diff --git a/drivers/net/wireless/intersil/hostap/hostap_ap.c b/drivers/net/wireless/intersil/hostap/hostap_ap.c index 8bcc1cdcb75b..462ccc7d7d1a 100644 --- a/drivers/net/wireless/intersil/hostap/hostap_ap.c +++ b/drivers/net/wireless/intersil/hostap/hostap_ap.c @@ -69,7 +69,7 @@ static void prism2_send_mgmt(struct net_device *dev, #if !defined(PRISM2_NO_PROCFS_DEBUG) && defined(CONFIG_PROC_FS) static int ap_debug_proc_show(struct seq_file *m, void *v) { - struct ap_data *ap = PDE_DATA(file_inode(m->file)); + struct ap_data *ap = pde_data(file_inode(m->file)); seq_printf(m, "BridgedUnicastFrames=%u\n", ap->bridged_unicast); seq_printf(m, "BridgedMulticastFrames=%u\n", ap->bridged_multicast); @@ -320,7 +320,7 @@ void hostap_deauth_all_stas(struct net_device *dev, struct ap_data *ap, static int ap_control_proc_show(struct seq_file *m, void *v) { - struct ap_data *ap = PDE_DATA(file_inode(m->file)); + struct ap_data *ap = pde_data(file_inode(m->file)); char *policy_txt; struct mac_entry *entry; @@ -352,20 +352,20 @@ static int ap_control_proc_show(struct seq_file *m, void *v) static void *ap_control_proc_start(struct seq_file *m, loff_t *_pos) { - struct ap_data *ap = PDE_DATA(file_inode(m->file)); + struct ap_data *ap = pde_data(file_inode(m->file)); spin_lock_bh(&ap->mac_restrictions.lock); return seq_list_start_head(&ap->mac_restrictions.mac_list, *_pos); } static void *ap_control_proc_next(struct seq_file *m, void *v, loff_t *_pos) { - struct ap_data *ap = PDE_DATA(file_inode(m->file)); + struct ap_data *ap = pde_data(file_inode(m->file)); return seq_list_next(v, &ap->mac_restrictions.mac_list, _pos); } static void ap_control_proc_stop(struct seq_file *m, void *v) { - struct ap_data *ap = PDE_DATA(file_inode(m->file)); + struct ap_data *ap = pde_data(file_inode(m->file)); spin_unlock_bh(&ap->mac_restrictions.lock); } @@ -554,20 +554,20 @@ static int prism2_ap_proc_show(struct seq_file *m, void *v) static void *prism2_ap_proc_start(struct seq_file *m, loff_t *_pos) { - struct ap_data *ap = PDE_DATA(file_inode(m->file)); + struct ap_data *ap = pde_data(file_inode(m->file)); spin_lock_bh(&ap->sta_table_lock); return seq_list_start_head(&ap->sta_list, *_pos); } static void *prism2_ap_proc_next(struct seq_file *m, void *v, loff_t *_pos) { - struct ap_data *ap = PDE_DATA(file_inode(m->file)); + struct ap_data *ap = pde_data(file_inode(m->file)); return seq_list_next(v, &ap->sta_list, _pos); } static void prism2_ap_proc_stop(struct seq_file *m, void *v) { - struct ap_data *ap = PDE_DATA(file_inode(m->file)); + struct ap_data *ap = pde_data(file_inode(m->file)); spin_unlock_bh(&ap->sta_table_lock); } diff --git a/drivers/net/wireless/intersil/hostap/hostap_download.c b/drivers/net/wireless/intersil/hostap/hostap_download.c index 7c6a5a6d1d45..3672291ced5c 100644 --- a/drivers/net/wireless/intersil/hostap/hostap_download.c +++ b/drivers/net/wireless/intersil/hostap/hostap_download.c @@ -227,7 +227,7 @@ static int prism2_download_aux_dump_proc_open(struct inode *inode, struct file * sizeof(struct prism2_download_aux_dump)); if (ret == 0) { struct seq_file *m = file->private_data; - m->private = PDE_DATA(inode); + m->private = pde_data(inode); } return ret; } diff --git a/drivers/net/wireless/intersil/hostap/hostap_proc.c b/drivers/net/wireless/intersil/hostap/hostap_proc.c index 51c847d98755..61f68786056f 100644 --- a/drivers/net/wireless/intersil/hostap/hostap_proc.c +++ b/drivers/net/wireless/intersil/hostap/hostap_proc.c @@ -97,20 +97,20 @@ static int prism2_wds_proc_show(struct seq_file *m, void *v) static void *prism2_wds_proc_start(struct seq_file *m, loff_t *_pos) { - local_info_t *local = PDE_DATA(file_inode(m->file)); + local_info_t *local = pde_data(file_inode(m->file)); read_lock_bh(&local->iface_lock); return seq_list_start(&local->hostap_interfaces, *_pos); } static void *prism2_wds_proc_next(struct seq_file *m, void *v, loff_t *_pos) { - local_info_t *local = PDE_DATA(file_inode(m->file)); + local_info_t *local = pde_data(file_inode(m->file)); return seq_list_next(v, &local->hostap_interfaces, _pos); } static void prism2_wds_proc_stop(struct seq_file *m, void *v) { - local_info_t *local = PDE_DATA(file_inode(m->file)); + local_info_t *local = pde_data(file_inode(m->file)); read_unlock_bh(&local->iface_lock); } @@ -123,7 +123,7 @@ static const struct seq_operations prism2_wds_proc_seqops = { static int prism2_bss_list_proc_show(struct seq_file *m, void *v) { - local_info_t *local = PDE_DATA(file_inode(m->file)); + local_info_t *local = pde_data(file_inode(m->file)); struct list_head *ptr = v; struct hostap_bss_info *bss; @@ -151,21 +151,21 @@ static int prism2_bss_list_proc_show(struct seq_file *m, void *v) static void *prism2_bss_list_proc_start(struct seq_file *m, loff_t *_pos) __acquires(&local->lock) { - local_info_t *local = PDE_DATA(file_inode(m->file)); + local_info_t *local = pde_data(file_inode(m->file)); spin_lock_bh(&local->lock); return seq_list_start_head(&local->bss_list, *_pos); } static void *prism2_bss_list_proc_next(struct seq_file *m, void *v, loff_t *_pos) { - local_info_t *local = PDE_DATA(file_inode(m->file)); + local_info_t *local = pde_data(file_inode(m->file)); return seq_list_next(v, &local->bss_list, _pos); } static void prism2_bss_list_proc_stop(struct seq_file *m, void *v) __releases(&local->lock) { - local_info_t *local = PDE_DATA(file_inode(m->file)); + local_info_t *local = pde_data(file_inode(m->file)); spin_unlock_bh(&local->lock); } @@ -198,7 +198,7 @@ static int prism2_crypt_proc_show(struct seq_file *m, void *v) static ssize_t prism2_pda_proc_read(struct file *file, char __user *buf, size_t count, loff_t *_pos) { - local_info_t *local = PDE_DATA(file_inode(file)); + local_info_t *local = pde_data(file_inode(file)); size_t off; if (local->pda == NULL || *_pos >= PRISM2_PDA_SIZE) @@ -272,7 +272,7 @@ static int prism2_io_debug_proc_read(char *page, char **start, off_t off, #ifndef PRISM2_NO_STATION_MODES static int prism2_scan_results_proc_show(struct seq_file *m, void *v) { - local_info_t *local = PDE_DATA(file_inode(m->file)); + local_info_t *local = pde_data(file_inode(m->file)); unsigned long entry; int i, len; struct hfa384x_hostscan_result *scanres; @@ -322,7 +322,7 @@ static int prism2_scan_results_proc_show(struct seq_file *m, void *v) static void *prism2_scan_results_proc_start(struct seq_file *m, loff_t *_pos) { - local_info_t *local = PDE_DATA(file_inode(m->file)); + local_info_t *local = pde_data(file_inode(m->file)); spin_lock_bh(&local->lock); /* We have a header (pos 0) + N results to show (pos 1...N) */ @@ -333,7 +333,7 @@ static void *prism2_scan_results_proc_start(struct seq_file *m, loff_t *_pos) static void *prism2_scan_results_proc_next(struct seq_file *m, void *v, loff_t *_pos) { - local_info_t *local = PDE_DATA(file_inode(m->file)); + local_info_t *local = pde_data(file_inode(m->file)); ++*_pos; if (*_pos > local->last_scan_results_count) @@ -343,7 +343,7 @@ static void *prism2_scan_results_proc_next(struct seq_file *m, void *v, loff_t * static void prism2_scan_results_proc_stop(struct seq_file *m, void *v) { - local_info_t *local = PDE_DATA(file_inode(m->file)); + local_info_t *local = pde_data(file_inode(m->file)); spin_unlock_bh(&local->lock); } diff --git a/drivers/net/wireless/ray_cs.c b/drivers/net/wireless/ray_cs.c index e3a3dc3e45b4..2987ad9271f6 100644 --- a/drivers/net/wireless/ray_cs.c +++ b/drivers/net/wireless/ray_cs.c @@ -2746,7 +2746,7 @@ static ssize_t int_proc_write(struct file *file, const char __user *buffer, nr = nr * 10 + c; p++; } while (--len); - *(int *)PDE_DATA(file_inode(file)) = nr; + *(int *)pde_data(file_inode(file)) = nr; return count; } diff --git a/drivers/nubus/proc.c b/drivers/nubus/proc.c index 88e1f9a0faaf..1fd667852271 100644 --- a/drivers/nubus/proc.c +++ b/drivers/nubus/proc.c @@ -93,30 +93,30 @@ struct nubus_proc_pde_data { static struct nubus_proc_pde_data * nubus_proc_alloc_pde_data(unsigned char *ptr, unsigned int size) { - struct nubus_proc_pde_data *pde_data; + struct nubus_proc_pde_data *pded; - pde_data = kmalloc(sizeof(*pde_data), GFP_KERNEL); - if (!pde_data) + pded = kmalloc(sizeof(*pded), GFP_KERNEL); + if (!pded) return NULL; - pde_data->res_ptr = ptr; - pde_data->res_size = size; - return pde_data; + pded->res_ptr = ptr; + pded->res_size = size; + return pded; } static int nubus_proc_rsrc_show(struct seq_file *m, void *v) { struct inode *inode = m->private; - struct nubus_proc_pde_data *pde_data; + struct nubus_proc_pde_data *pded; - pde_data = PDE_DATA(inode); - if (!pde_data) + pded = pde_data(inode); + if (!pded) return 0; - if (pde_data->res_size > m->size) + if (pded->res_size > m->size) return -EFBIG; - if (pde_data->res_size) { + if (pded->res_size) { int lanes = (int)proc_get_parent_data(inode); struct nubus_dirent ent; @@ -124,11 +124,11 @@ static int nubus_proc_rsrc_show(struct seq_file *m, void *v) return 0; ent.mask = lanes; - ent.base = pde_data->res_ptr; + ent.base = pded->res_ptr; ent.data = 0; - nubus_seq_write_rsrc_mem(m, &ent, pde_data->res_size); + nubus_seq_write_rsrc_mem(m, &ent, pded->res_size); } else { - unsigned int data = (unsigned int)pde_data->res_ptr; + unsigned int data = (unsigned int)pded->res_ptr; seq_putc(m, data >> 16); seq_putc(m, data >> 8); @@ -142,18 +142,18 @@ void nubus_proc_add_rsrc_mem(struct proc_dir_entry *procdir, unsigned int size) { char name[9]; - struct nubus_proc_pde_data *pde_data; + struct nubus_proc_pde_data *pded; if (!procdir) return; snprintf(name, sizeof(name), "%x", ent->type); if (size) - pde_data = nubus_proc_alloc_pde_data(nubus_dirptr(ent), size); + pded = nubus_proc_alloc_pde_data(nubus_dirptr(ent), size); else - pde_data = NULL; + pded = NULL; proc_create_single_data(name, S_IFREG | 0444, procdir, - nubus_proc_rsrc_show, pde_data); + nubus_proc_rsrc_show, pded); } void nubus_proc_add_rsrc(struct proc_dir_entry *procdir, diff --git a/drivers/parisc/led.c b/drivers/parisc/led.c index cf91cb024be3..1e4a5663d011 100644 --- a/drivers/parisc/led.c +++ b/drivers/parisc/led.c @@ -168,14 +168,14 @@ static int led_proc_show(struct seq_file *m, void *v) static int led_proc_open(struct inode *inode, struct file *file) { - return single_open(file, led_proc_show, PDE_DATA(inode)); + return single_open(file, led_proc_show, pde_data(inode)); } static ssize_t led_proc_write(struct file *file, const char __user *buf, size_t count, loff_t *pos) { - void *data = PDE_DATA(file_inode(file)); + void *data = pde_data(file_inode(file)); char *cur, lbuf[32]; int d; diff --git a/drivers/pci/proc.c b/drivers/pci/proc.c index cb18f8a13ab6..9c7edec64f7e 100644 --- a/drivers/pci/proc.c +++ b/drivers/pci/proc.c @@ -21,14 +21,14 @@ static int proc_initialized; /* = 0 */ static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence) { - struct pci_dev *dev = PDE_DATA(file_inode(file)); + struct pci_dev *dev = pde_data(file_inode(file)); return fixed_size_llseek(file, off, whence, dev->cfg_size); } static ssize_t proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) { - struct pci_dev *dev = PDE_DATA(file_inode(file)); + struct pci_dev *dev = pde_data(file_inode(file)); unsigned int pos = *ppos; unsigned int cnt, size; @@ -114,7 +114,7 @@ static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, loff_t *ppos) { struct inode *ino = file_inode(file); - struct pci_dev *dev = PDE_DATA(ino); + struct pci_dev *dev = pde_data(ino); int pos = *ppos; int size = dev->cfg_size; int cnt, ret; @@ -196,7 +196,7 @@ struct pci_filp_private { static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { - struct pci_dev *dev = PDE_DATA(file_inode(file)); + struct pci_dev *dev = pde_data(file_inode(file)); #ifdef HAVE_PCI_MMAP struct pci_filp_private *fpriv = file->private_data; #endif /* HAVE_PCI_MMAP */ @@ -244,7 +244,7 @@ static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd, #ifdef HAVE_PCI_MMAP static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma) { - struct pci_dev *dev = PDE_DATA(file_inode(file)); + struct pci_dev *dev = pde_data(file_inode(file)); struct pci_filp_private *fpriv = file->private_data; int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM; diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c index 82fa6148216c..098180fb1cfc 100644 --- a/drivers/platform/x86/thinkpad_acpi.c +++ b/drivers/platform/x86/thinkpad_acpi.c @@ -880,14 +880,14 @@ static int dispatch_proc_show(struct seq_file *m, void *v) static int dispatch_proc_open(struct inode *inode, struct file *file) { - return single_open(file, dispatch_proc_show, PDE_DATA(inode)); + return single_open(file, dispatch_proc_show, pde_data(inode)); } static ssize_t dispatch_proc_write(struct file *file, const char __user *userbuf, size_t count, loff_t *pos) { - struct ibm_struct *ibm = PDE_DATA(file_inode(file)); + struct ibm_struct *ibm = pde_data(file_inode(file)); char *kernbuf; int ret; diff --git a/drivers/platform/x86/toshiba_acpi.c b/drivers/platform/x86/toshiba_acpi.c index 352508d30467..f113dec98e21 100644 --- a/drivers/platform/x86/toshiba_acpi.c +++ b/drivers/platform/x86/toshiba_acpi.c @@ -1368,7 +1368,7 @@ static int lcd_proc_show(struct seq_file *m, void *v) static int lcd_proc_open(struct inode *inode, struct file *file) { - return single_open(file, lcd_proc_show, PDE_DATA(inode)); + return single_open(file, lcd_proc_show, pde_data(inode)); } static int set_lcd_brightness(struct toshiba_acpi_dev *dev, int value) @@ -1404,7 +1404,7 @@ static int set_lcd_status(struct backlight_device *bd) static ssize_t lcd_proc_write(struct file *file, const char __user *buf, size_t count, loff_t *pos) { - struct toshiba_acpi_dev *dev = PDE_DATA(file_inode(file)); + struct toshiba_acpi_dev *dev = pde_data(file_inode(file)); char cmd[42]; size_t len; int levels; @@ -1469,13 +1469,13 @@ static int video_proc_show(struct seq_file *m, void *v) static int video_proc_open(struct inode *inode, struct file *file) { - return single_open(file, video_proc_show, PDE_DATA(inode)); + return single_open(file, video_proc_show, pde_data(inode)); } static ssize_t video_proc_write(struct file *file, const char __user *buf, size_t count, loff_t *pos) { - struct toshiba_acpi_dev *dev = PDE_DATA(file_inode(file)); + struct toshiba_acpi_dev *dev = pde_data(file_inode(file)); char *buffer; char *cmd; int lcd_out = -1, crt_out = -1, tv_out = -1; @@ -1580,13 +1580,13 @@ static int fan_proc_show(struct seq_file *m, void *v) static int fan_proc_open(struct inode *inode, struct file *file) { - return single_open(file, fan_proc_show, PDE_DATA(inode)); + return single_open(file, fan_proc_show, pde_data(inode)); } static ssize_t fan_proc_write(struct file *file, const char __user *buf, size_t count, loff_t *pos) { - struct toshiba_acpi_dev *dev = PDE_DATA(file_inode(file)); + struct toshiba_acpi_dev *dev = pde_data(file_inode(file)); char cmd[42]; size_t len; int value; @@ -1628,13 +1628,13 @@ static int keys_proc_show(struct seq_file *m, void *v) static int keys_proc_open(struct inode *inode, struct file *file) { - return single_open(file, keys_proc_show, PDE_DATA(inode)); + return single_open(file, keys_proc_show, pde_data(inode)); } static ssize_t keys_proc_write(struct file *file, const char __user *buf, size_t count, loff_t *pos) { - struct toshiba_acpi_dev *dev = PDE_DATA(file_inode(file)); + struct toshiba_acpi_dev *dev = pde_data(file_inode(file)); char cmd[42]; size_t len; int value; diff --git a/drivers/pnp/isapnp/proc.c b/drivers/pnp/isapnp/proc.c index 1ae458c02656..55ae72a2818b 100644 --- a/drivers/pnp/isapnp/proc.c +++ b/drivers/pnp/isapnp/proc.c @@ -22,7 +22,7 @@ static loff_t isapnp_proc_bus_lseek(struct file *file, loff_t off, int whence) static ssize_t isapnp_proc_bus_read(struct file *file, char __user * buf, size_t nbytes, loff_t * ppos) { - struct pnp_dev *dev = PDE_DATA(file_inode(file)); + struct pnp_dev *dev = pde_data(file_inode(file)); int pos = *ppos; int cnt, size = 256; diff --git a/drivers/pnp/pnpbios/proc.c b/drivers/pnp/pnpbios/proc.c index a806830e3a40..0f0d819b157f 100644 --- a/drivers/pnp/pnpbios/proc.c +++ b/drivers/pnp/pnpbios/proc.c @@ -173,13 +173,13 @@ static int pnpbios_proc_show(struct seq_file *m, void *v) static int pnpbios_proc_open(struct inode *inode, struct file *file) { - return single_open(file, pnpbios_proc_show, PDE_DATA(inode)); + return single_open(file, pnpbios_proc_show, pde_data(inode)); } static ssize_t pnpbios_proc_write(struct file *file, const char __user *buf, size_t count, loff_t *pos) { - void *data = PDE_DATA(file_inode(file)); + void *data = pde_data(file_inode(file)); struct pnp_bios_node *node; int boot = (long)data >> 8; u8 nodenum = (long)data; diff --git a/drivers/scsi/scsi_proc.c b/drivers/scsi/scsi_proc.c index d6982d355739..95aee1ad1383 100644 --- a/drivers/scsi/scsi_proc.c +++ b/drivers/scsi/scsi_proc.c @@ -49,7 +49,7 @@ static DEFINE_MUTEX(global_host_template_mutex); static ssize_t proc_scsi_host_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { - struct Scsi_Host *shost = PDE_DATA(file_inode(file)); + struct Scsi_Host *shost = pde_data(file_inode(file)); ssize_t ret = -ENOMEM; char *page; @@ -79,7 +79,7 @@ static int proc_scsi_show(struct seq_file *m, void *v) static int proc_scsi_host_open(struct inode *inode, struct file *file) { - return single_open_size(file, proc_scsi_show, PDE_DATA(inode), + return single_open_size(file, proc_scsi_show, pde_data(inode), 4 * PAGE_SIZE); } diff --git a/drivers/usb/gadget/function/rndis.c b/drivers/usb/gadget/function/rndis.c index 64de9f1b874c..431d5a7d737e 100644 --- a/drivers/usb/gadget/function/rndis.c +++ b/drivers/usb/gadget/function/rndis.c @@ -1117,7 +1117,7 @@ static int rndis_proc_show(struct seq_file *m, void *v) static ssize_t rndis_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos) { - rndis_params *p = PDE_DATA(file_inode(file)); + rndis_params *p = pde_data(file_inode(file)); u32 speed = 0; int i, fl_speed = 0; @@ -1161,7 +1161,7 @@ static ssize_t rndis_proc_write(struct file *file, const char __user *buffer, static int rndis_proc_open(struct inode *inode, struct file *file) { - return single_open(file, rndis_proc_show, PDE_DATA(inode)); + return single_open(file, rndis_proc_show, pde_data(inode)); } static const struct proc_ops rndis_proc_ops = { diff --git a/drivers/zorro/proc.c b/drivers/zorro/proc.c index 1c9ae08225d8..f916bf60b312 100644 --- a/drivers/zorro/proc.c +++ b/drivers/zorro/proc.c @@ -30,7 +30,7 @@ proc_bus_zorro_lseek(struct file *file, loff_t off, int whence) static ssize_t proc_bus_zorro_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) { - struct zorro_dev *z = PDE_DATA(file_inode(file)); + struct zorro_dev *z = pde_data(file_inode(file)); struct ConfigDev cd; loff_t pos = *ppos; diff --git a/fs/afs/proc.c b/fs/afs/proc.c index 065a28bfa3f1..e1b863449296 100644 --- a/fs/afs/proc.c +++ b/fs/afs/proc.c @@ -227,7 +227,7 @@ static int afs_proc_cell_volumes_show(struct seq_file *m, void *v) static void *afs_proc_cell_volumes_start(struct seq_file *m, loff_t *_pos) __acquires(cell->proc_lock) { - struct afs_cell *cell = PDE_DATA(file_inode(m->file)); + struct afs_cell *cell = pde_data(file_inode(m->file)); rcu_read_lock(); return seq_hlist_start_head_rcu(&cell->proc_volumes, *_pos); @@ -236,7 +236,7 @@ static void *afs_proc_cell_volumes_start(struct seq_file *m, loff_t *_pos) static void *afs_proc_cell_volumes_next(struct seq_file *m, void *v, loff_t *_pos) { - struct afs_cell *cell = PDE_DATA(file_inode(m->file)); + struct afs_cell *cell = pde_data(file_inode(m->file)); return seq_hlist_next_rcu(v, &cell->proc_volumes, _pos); } @@ -322,7 +322,7 @@ static void *afs_proc_cell_vlservers_start(struct seq_file *m, loff_t *_pos) { struct afs_vl_seq_net_private *priv = m->private; struct afs_vlserver_list *vllist; - struct afs_cell *cell = PDE_DATA(file_inode(m->file)); + struct afs_cell *cell = pde_data(file_inode(m->file)); loff_t pos = *_pos; rcu_read_lock(); diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index cf2fd9fc7d98..9f86dd947032 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -2834,7 +2834,7 @@ out: static void *ext4_mb_seq_groups_start(struct seq_file *seq, loff_t *pos) { - struct super_block *sb = PDE_DATA(file_inode(seq->file)); + struct super_block *sb = pde_data(file_inode(seq->file)); ext4_group_t group; if (*pos < 0 || *pos >= ext4_get_groups_count(sb)) @@ -2845,7 +2845,7 @@ static void *ext4_mb_seq_groups_start(struct seq_file *seq, loff_t *pos) static void *ext4_mb_seq_groups_next(struct seq_file *seq, void *v, loff_t *pos) { - struct super_block *sb = PDE_DATA(file_inode(seq->file)); + struct super_block *sb = pde_data(file_inode(seq->file)); ext4_group_t group; ++*pos; @@ -2857,7 +2857,7 @@ static void *ext4_mb_seq_groups_next(struct seq_file *seq, void *v, loff_t *pos) static int ext4_mb_seq_groups_show(struct seq_file *seq, void *v) { - struct super_block *sb = PDE_DATA(file_inode(seq->file)); + struct super_block *sb = pde_data(file_inode(seq->file)); ext4_group_t group = (ext4_group_t) ((unsigned long) v); int i; int err, buddy_loaded = 0; @@ -2985,7 +2985,7 @@ int ext4_seq_mb_stats_show(struct seq_file *seq, void *offset) static void *ext4_mb_seq_structs_summary_start(struct seq_file *seq, loff_t *pos) __acquires(&EXT4_SB(sb)->s_mb_rb_lock) { - struct super_block *sb = PDE_DATA(file_inode(seq->file)); + struct super_block *sb = pde_data(file_inode(seq->file)); unsigned long position; read_lock(&EXT4_SB(sb)->s_mb_rb_lock); @@ -2998,7 +2998,7 @@ __acquires(&EXT4_SB(sb)->s_mb_rb_lock) static void *ext4_mb_seq_structs_summary_next(struct seq_file *seq, void *v, loff_t *pos) { - struct super_block *sb = PDE_DATA(file_inode(seq->file)); + struct super_block *sb = pde_data(file_inode(seq->file)); unsigned long position; ++*pos; @@ -3010,7 +3010,7 @@ static void *ext4_mb_seq_structs_summary_next(struct seq_file *seq, void *v, lof static int ext4_mb_seq_structs_summary_show(struct seq_file *seq, void *v) { - struct super_block *sb = PDE_DATA(file_inode(seq->file)); + struct super_block *sb = pde_data(file_inode(seq->file)); struct ext4_sb_info *sbi = EXT4_SB(sb); unsigned long position = ((unsigned long) v); struct ext4_group_info *grp; @@ -3058,7 +3058,7 @@ static int ext4_mb_seq_structs_summary_show(struct seq_file *seq, void *v) static void ext4_mb_seq_structs_summary_stop(struct seq_file *seq, void *v) __releases(&EXT4_SB(sb)->s_mb_rb_lock) { - struct super_block *sb = PDE_DATA(file_inode(seq->file)); + struct super_block *sb = pde_data(file_inode(seq->file)); read_unlock(&EXT4_SB(sb)->s_mb_rb_lock); } diff --git a/fs/jbd2/journal.c b/fs/jbd2/journal.c index 0b86a4365b66..f13d548e4a7f 100644 --- a/fs/jbd2/journal.c +++ b/fs/jbd2/journal.c @@ -1212,7 +1212,7 @@ static const struct seq_operations jbd2_seq_info_ops = { static int jbd2_seq_info_open(struct inode *inode, struct file *file) { - journal_t *journal = PDE_DATA(inode); + journal_t *journal = pde_data(inode); struct jbd2_stats_proc_session *s; int rc, size; diff --git a/fs/proc/proc_net.c b/fs/proc/proc_net.c index 39b823ab2564..e1cfeda397f3 100644 --- a/fs/proc/proc_net.c +++ b/fs/proc/proc_net.c @@ -138,7 +138,7 @@ EXPORT_SYMBOL_GPL(proc_create_net_data); * @parent: The parent directory in which to create. * @ops: The seq_file ops with which to read the file. * @write: The write method with which to 'modify' the file. - * @data: Data for retrieval by PDE_DATA(). + * @data: Data for retrieval by pde_data(). * * Create a network namespaced proc file in the @parent directory with the * specified @name and @mode that allows reading of a file that displays a @@ -153,7 +153,7 @@ EXPORT_SYMBOL_GPL(proc_create_net_data); * modified by the @write function. @write should return 0 on success. * * The @data value is accessible from the @show and @write functions by calling - * PDE_DATA() on the file inode. The network namespace must be accessed by + * pde_data() on the file inode. The network namespace must be accessed by * calling seq_file_net() on the seq_file struct. */ struct proc_dir_entry *proc_create_net_data_write(const char *name, umode_t mode, @@ -230,7 +230,7 @@ EXPORT_SYMBOL_GPL(proc_create_net_single); * @parent: The parent directory in which to create. * @show: The seqfile show method with which to read the file. * @write: The write method with which to 'modify' the file. - * @data: Data for retrieval by PDE_DATA(). + * @data: Data for retrieval by pde_data(). * * Create a network-namespaced proc file in the @parent directory with the * specified @name and @mode that allows reading of a file that displays a @@ -245,7 +245,7 @@ EXPORT_SYMBOL_GPL(proc_create_net_single); * modified by the @write function. @write should return 0 on success. * * The @data value is accessible from the @show and @write functions by calling - * PDE_DATA() on the file inode. The network namespace must be accessed by + * pde_data() on the file inode. The network namespace must be accessed by * calling seq_file_single_net() on the seq_file struct. */ struct proc_dir_entry *proc_create_net_single_write(const char *name, umode_t mode, diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h index b6e7005cc1b2..81d6e4ec2294 100644 --- a/include/linux/proc_fs.h +++ b/include/linux/proc_fs.h @@ -120,8 +120,6 @@ static inline void *pde_data(const struct inode *inode) return inode->i_private; } -#define PDE_DATA(i) pde_data(i) - extern void *proc_get_parent_data(const struct inode *); extern void proc_remove(struct proc_dir_entry *); extern void remove_proc_entry(const char *, struct proc_dir_entry *); @@ -202,7 +200,7 @@ proc_create_data(const char *name, umode_t mode, struct proc_dir_entry *parent, static inline void proc_set_size(struct proc_dir_entry *de, loff_t size) {} static inline void proc_set_user(struct proc_dir_entry *de, kuid_t uid, kgid_t gid) {} -static inline void *PDE_DATA(const struct inode *inode) {BUG(); return NULL;} +static inline void *pde_data(const struct inode *inode) {BUG(); return NULL;} static inline void *proc_get_parent_data(const struct inode *inode) { BUG(); return NULL; } static inline void proc_remove(struct proc_dir_entry *de) {} diff --git a/include/linux/seq_file.h b/include/linux/seq_file.h index 72dbb44a4573..88cc16444b43 100644 --- a/include/linux/seq_file.h +++ b/include/linux/seq_file.h @@ -209,7 +209,7 @@ static const struct file_operations __name ## _fops = { \ #define DEFINE_PROC_SHOW_ATTRIBUTE(__name) \ static int __name ## _open(struct inode *inode, struct file *file) \ { \ - return single_open(file, __name ## _show, PDE_DATA(inode)); \ + return single_open(file, __name ## _show, pde_data(inode)); \ } \ \ static const struct proc_ops __name ## _proc_ops = { \ diff --git a/ipc/util.c b/ipc/util.c index fa2d86ef3fb8..a2208d0f26b2 100644 --- a/ipc/util.c +++ b/ipc/util.c @@ -894,7 +894,7 @@ static int sysvipc_proc_open(struct inode *inode, struct file *file) if (!iter) return -ENOMEM; - iter->iface = PDE_DATA(inode); + iter->iface = pde_data(inode); iter->ns = get_ipc_ns(current->nsproxy->ipc_ns); iter->pid_ns = get_pid_ns(task_active_pid_ns(current)); diff --git a/kernel/irq/proc.c b/kernel/irq/proc.c index ee595ec09778..623b8136e9af 100644 --- a/kernel/irq/proc.c +++ b/kernel/irq/proc.c @@ -137,7 +137,7 @@ static inline int irq_select_affinity_usr(unsigned int irq) static ssize_t write_irq_affinity(int type, struct file *file, const char __user *buffer, size_t count, loff_t *pos) { - unsigned int irq = (int)(long)PDE_DATA(file_inode(file)); + unsigned int irq = (int)(long)pde_data(file_inode(file)); cpumask_var_t new_value; int err; @@ -190,12 +190,12 @@ static ssize_t irq_affinity_list_proc_write(struct file *file, static int irq_affinity_proc_open(struct inode *inode, struct file *file) { - return single_open(file, irq_affinity_proc_show, PDE_DATA(inode)); + return single_open(file, irq_affinity_proc_show, pde_data(inode)); } static int irq_affinity_list_proc_open(struct inode *inode, struct file *file) { - return single_open(file, irq_affinity_list_proc_show, PDE_DATA(inode)); + return single_open(file, irq_affinity_list_proc_show, pde_data(inode)); } static const struct proc_ops irq_affinity_proc_ops = { @@ -265,7 +265,7 @@ out: static int default_affinity_open(struct inode *inode, struct file *file) { - return single_open(file, default_affinity_show, PDE_DATA(inode)); + return single_open(file, default_affinity_show, pde_data(inode)); } static const struct proc_ops default_affinity_proc_ops = { diff --git a/kernel/resource.c b/kernel/resource.c index 5ad3eba619ba..9c08d6e9eef2 100644 --- a/kernel/resource.c +++ b/kernel/resource.c @@ -99,7 +99,7 @@ enum { MAX_IORES_LEVEL = 5 }; static void *r_start(struct seq_file *m, loff_t *pos) __acquires(resource_lock) { - struct resource *p = PDE_DATA(file_inode(m->file)); + struct resource *p = pde_data(file_inode(m->file)); loff_t l = 0; read_lock(&resource_lock); for (p = p->child; p && l < *pos; p = r_next(m, p, &l)) @@ -115,7 +115,7 @@ static void r_stop(struct seq_file *m, void *v) static int r_show(struct seq_file *m, void *v) { - struct resource *root = PDE_DATA(file_inode(m->file)); + struct resource *root = pde_data(file_inode(m->file)); struct resource *r = v, *p; unsigned long long start, end; int width = root->end < 0x10000 ? 4 : 8; diff --git a/net/atm/proc.c b/net/atm/proc.c index 4369ffa3302a..9bf736290e48 100644 --- a/net/atm/proc.c +++ b/net/atm/proc.c @@ -108,7 +108,7 @@ out: static inline void *vcc_walk(struct seq_file *seq, loff_t l) { struct vcc_state *state = seq->private; - int family = (uintptr_t)(PDE_DATA(file_inode(seq->file))); + int family = (uintptr_t)(pde_data(file_inode(seq->file))); return __vcc_walk(&state->sk, family, &state->bucket, l) ? state : NULL; @@ -324,7 +324,7 @@ static ssize_t proc_dev_atm_read(struct file *file, char __user *buf, page = get_zeroed_page(GFP_KERNEL); if (!page) return -ENOMEM; - dev = PDE_DATA(file_inode(file)); + dev = pde_data(file_inode(file)); if (!dev->ops->proc_read) length = -EINVAL; else { diff --git a/net/bluetooth/af_bluetooth.c b/net/bluetooth/af_bluetooth.c index 1661979b6a6e..ee319779781e 100644 --- a/net/bluetooth/af_bluetooth.c +++ b/net/bluetooth/af_bluetooth.c @@ -611,7 +611,7 @@ EXPORT_SYMBOL(bt_sock_wait_ready); static void *bt_seq_start(struct seq_file *seq, loff_t *pos) __acquires(seq->private->l->lock) { - struct bt_sock_list *l = PDE_DATA(file_inode(seq->file)); + struct bt_sock_list *l = pde_data(file_inode(seq->file)); read_lock(&l->lock); return seq_hlist_start_head(&l->head, *pos); @@ -619,7 +619,7 @@ static void *bt_seq_start(struct seq_file *seq, loff_t *pos) static void *bt_seq_next(struct seq_file *seq, void *v, loff_t *pos) { - struct bt_sock_list *l = PDE_DATA(file_inode(seq->file)); + struct bt_sock_list *l = pde_data(file_inode(seq->file)); return seq_hlist_next(v, &l->head, pos); } @@ -627,14 +627,14 @@ static void *bt_seq_next(struct seq_file *seq, void *v, loff_t *pos) static void bt_seq_stop(struct seq_file *seq, void *v) __releases(seq->private->l->lock) { - struct bt_sock_list *l = PDE_DATA(file_inode(seq->file)); + struct bt_sock_list *l = pde_data(file_inode(seq->file)); read_unlock(&l->lock); } static int bt_seq_show(struct seq_file *seq, void *v) { - struct bt_sock_list *l = PDE_DATA(file_inode(seq->file)); + struct bt_sock_list *l = pde_data(file_inode(seq->file)); if (v == SEQ_START_TOKEN) { seq_puts(seq, "sk RefCnt Rmem Wmem User Inode Parent"); diff --git a/net/can/bcm.c b/net/can/bcm.c index bc88d901a1c0..95d209b52e6a 100644 --- a/net/can/bcm.c +++ b/net/can/bcm.c @@ -193,7 +193,7 @@ static int bcm_proc_show(struct seq_file *m, void *v) { char ifname[IFNAMSIZ]; struct net *net = m->private; - struct sock *sk = (struct sock *)PDE_DATA(m->file->f_inode); + struct sock *sk = (struct sock *)pde_data(m->file->f_inode); struct bcm_sock *bo = bcm_sk(sk); struct bcm_op *op; diff --git a/net/can/proc.c b/net/can/proc.c index b3099f0a3cb8..bbce97825f13 100644 --- a/net/can/proc.c +++ b/net/can/proc.c @@ -305,7 +305,7 @@ static inline void can_rcvlist_proc_show_one(struct seq_file *m, int idx, static int can_rcvlist_proc_show(struct seq_file *m, void *v) { /* double cast to prevent GCC warning */ - int idx = (int)(long)PDE_DATA(m->file->f_inode); + int idx = (int)(long)pde_data(m->file->f_inode); struct net_device *dev; struct can_dev_rcv_lists *dev_rcv_lists; struct net *net = m->private; diff --git a/net/core/neighbour.c b/net/core/neighbour.c index 213cb7b26b7a..6c2016f7f3d1 100644 --- a/net/core/neighbour.c +++ b/net/core/neighbour.c @@ -3364,7 +3364,7 @@ EXPORT_SYMBOL(neigh_seq_stop); static void *neigh_stat_seq_start(struct seq_file *seq, loff_t *pos) { - struct neigh_table *tbl = PDE_DATA(file_inode(seq->file)); + struct neigh_table *tbl = pde_data(file_inode(seq->file)); int cpu; if (*pos == 0) @@ -3381,7 +3381,7 @@ static void *neigh_stat_seq_start(struct seq_file *seq, loff_t *pos) static void *neigh_stat_seq_next(struct seq_file *seq, void *v, loff_t *pos) { - struct neigh_table *tbl = PDE_DATA(file_inode(seq->file)); + struct neigh_table *tbl = pde_data(file_inode(seq->file)); int cpu; for (cpu = *pos; cpu < nr_cpu_ids; ++cpu) { @@ -3401,7 +3401,7 @@ static void neigh_stat_seq_stop(struct seq_file *seq, void *v) static int neigh_stat_seq_show(struct seq_file *seq, void *v) { - struct neigh_table *tbl = PDE_DATA(file_inode(seq->file)); + struct neigh_table *tbl = pde_data(file_inode(seq->file)); struct neigh_statistics *st = v; if (v == SEQ_START_TOKEN) { diff --git a/net/core/pktgen.c b/net/core/pktgen.c index 560a5e712dc3..84b62cd7bc57 100644 --- a/net/core/pktgen.c +++ b/net/core/pktgen.c @@ -546,7 +546,7 @@ static ssize_t pgctrl_write(struct file *file, const char __user *buf, static int pgctrl_open(struct inode *inode, struct file *file) { - return single_open(file, pgctrl_show, PDE_DATA(inode)); + return single_open(file, pgctrl_show, pde_data(inode)); } static const struct proc_ops pktgen_proc_ops = { @@ -1811,7 +1811,7 @@ static ssize_t pktgen_if_write(struct file *file, static int pktgen_if_open(struct inode *inode, struct file *file) { - return single_open(file, pktgen_if_show, PDE_DATA(inode)); + return single_open(file, pktgen_if_show, pde_data(inode)); } static const struct proc_ops pktgen_if_proc_ops = { @@ -1948,7 +1948,7 @@ out: static int pktgen_thread_open(struct inode *inode, struct file *file) { - return single_open(file, pktgen_thread_show, PDE_DATA(inode)); + return single_open(file, pktgen_thread_show, pde_data(inode)); } static const struct proc_ops pktgen_thread_proc_ops = { diff --git a/net/ipv4/netfilter/ipt_CLUSTERIP.c b/net/ipv4/netfilter/ipt_CLUSTERIP.c index b518f20c9a24..f8e176c77d1c 100644 --- a/net/ipv4/netfilter/ipt_CLUSTERIP.c +++ b/net/ipv4/netfilter/ipt_CLUSTERIP.c @@ -776,7 +776,7 @@ static int clusterip_proc_open(struct inode *inode, struct file *file) if (!ret) { struct seq_file *sf = file->private_data; - struct clusterip_config *c = PDE_DATA(inode); + struct clusterip_config *c = pde_data(inode); sf->private = c; @@ -788,7 +788,7 @@ static int clusterip_proc_open(struct inode *inode, struct file *file) static int clusterip_proc_release(struct inode *inode, struct file *file) { - struct clusterip_config *c = PDE_DATA(inode); + struct clusterip_config *c = pde_data(inode); int ret; ret = seq_release(inode, file); @@ -802,7 +802,7 @@ static int clusterip_proc_release(struct inode *inode, struct file *file) static ssize_t clusterip_proc_write(struct file *file, const char __user *input, size_t size, loff_t *ofs) { - struct clusterip_config *c = PDE_DATA(file_inode(file)); + struct clusterip_config *c = pde_data(file_inode(file)); #define PROC_WRITELEN 10 char buffer[PROC_WRITELEN+1]; unsigned long nodenum; diff --git a/net/ipv4/raw.c b/net/ipv4/raw.c index a53f256bf9d3..9eb5fc247868 100644 --- a/net/ipv4/raw.c +++ b/net/ipv4/raw.c @@ -971,7 +971,7 @@ struct proto raw_prot = { static struct sock *raw_get_first(struct seq_file *seq) { struct sock *sk; - struct raw_hashinfo *h = PDE_DATA(file_inode(seq->file)); + struct raw_hashinfo *h = pde_data(file_inode(seq->file)); struct raw_iter_state *state = raw_seq_private(seq); for (state->bucket = 0; state->bucket < RAW_HTABLE_SIZE; @@ -987,7 +987,7 @@ found: static struct sock *raw_get_next(struct seq_file *seq, struct sock *sk) { - struct raw_hashinfo *h = PDE_DATA(file_inode(seq->file)); + struct raw_hashinfo *h = pde_data(file_inode(seq->file)); struct raw_iter_state *state = raw_seq_private(seq); do { @@ -1016,7 +1016,7 @@ static struct sock *raw_get_idx(struct seq_file *seq, loff_t pos) void *raw_seq_start(struct seq_file *seq, loff_t *pos) __acquires(&h->lock) { - struct raw_hashinfo *h = PDE_DATA(file_inode(seq->file)); + struct raw_hashinfo *h = pde_data(file_inode(seq->file)); read_lock(&h->lock); return *pos ? raw_get_idx(seq, *pos - 1) : SEQ_START_TOKEN; @@ -1039,7 +1039,7 @@ EXPORT_SYMBOL_GPL(raw_seq_next); void raw_seq_stop(struct seq_file *seq, void *v) __releases(&h->lock) { - struct raw_hashinfo *h = PDE_DATA(file_inode(seq->file)); + struct raw_hashinfo *h = pde_data(file_inode(seq->file)); read_unlock(&h->lock); } diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c index b3f34e366b27..b53476e78c84 100644 --- a/net/ipv4/tcp_ipv4.c +++ b/net/ipv4/tcp_ipv4.c @@ -3002,7 +3002,7 @@ static unsigned short seq_file_family(const struct seq_file *seq) #endif /* Iterated from proc fs */ - afinfo = PDE_DATA(file_inode(seq->file)); + afinfo = pde_data(file_inode(seq->file)); return afinfo->family; } diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c index 464590ea922e..090360939401 100644 --- a/net/ipv4/udp.c +++ b/net/ipv4/udp.c @@ -2960,7 +2960,7 @@ static struct sock *udp_get_first(struct seq_file *seq, int start) if (state->bpf_seq_afinfo) afinfo = state->bpf_seq_afinfo; else - afinfo = PDE_DATA(file_inode(seq->file)); + afinfo = pde_data(file_inode(seq->file)); for (state->bucket = start; state->bucket <= afinfo->udp_table->mask; ++state->bucket) { @@ -2993,7 +2993,7 @@ static struct sock *udp_get_next(struct seq_file *seq, struct sock *sk) if (state->bpf_seq_afinfo) afinfo = state->bpf_seq_afinfo; else - afinfo = PDE_DATA(file_inode(seq->file)); + afinfo = pde_data(file_inode(seq->file)); do { sk = sk_next(sk); @@ -3050,7 +3050,7 @@ void udp_seq_stop(struct seq_file *seq, void *v) if (state->bpf_seq_afinfo) afinfo = state->bpf_seq_afinfo; else - afinfo = PDE_DATA(file_inode(seq->file)); + afinfo = pde_data(file_inode(seq->file)); if (state->bucket <= afinfo->udp_table->mask) spin_unlock_bh(&afinfo->udp_table->hash[state->bucket].lock); diff --git a/net/netfilter/x_tables.c b/net/netfilter/x_tables.c index 25524e393349..54a489f16b17 100644 --- a/net/netfilter/x_tables.c +++ b/net/netfilter/x_tables.c @@ -1517,7 +1517,7 @@ EXPORT_SYMBOL_GPL(xt_unregister_table); #ifdef CONFIG_PROC_FS static void *xt_table_seq_start(struct seq_file *seq, loff_t *pos) { - u8 af = (unsigned long)PDE_DATA(file_inode(seq->file)); + u8 af = (unsigned long)pde_data(file_inode(seq->file)); struct net *net = seq_file_net(seq); struct xt_pernet *xt_net; @@ -1529,7 +1529,7 @@ static void *xt_table_seq_start(struct seq_file *seq, loff_t *pos) static void *xt_table_seq_next(struct seq_file *seq, void *v, loff_t *pos) { - u8 af = (unsigned long)PDE_DATA(file_inode(seq->file)); + u8 af = (unsigned long)pde_data(file_inode(seq->file)); struct net *net = seq_file_net(seq); struct xt_pernet *xt_net; @@ -1540,7 +1540,7 @@ static void *xt_table_seq_next(struct seq_file *seq, void *v, loff_t *pos) static void xt_table_seq_stop(struct seq_file *seq, void *v) { - u_int8_t af = (unsigned long)PDE_DATA(file_inode(seq->file)); + u_int8_t af = (unsigned long)pde_data(file_inode(seq->file)); mutex_unlock(&xt[af].mutex); } @@ -1584,7 +1584,7 @@ static void *xt_mttg_seq_next(struct seq_file *seq, void *v, loff_t *ppos, [MTTG_TRAV_NFP_UNSPEC] = MTTG_TRAV_NFP_SPEC, [MTTG_TRAV_NFP_SPEC] = MTTG_TRAV_DONE, }; - uint8_t nfproto = (unsigned long)PDE_DATA(file_inode(seq->file)); + uint8_t nfproto = (unsigned long)pde_data(file_inode(seq->file)); struct nf_mttg_trav *trav = seq->private; if (ppos != NULL) @@ -1633,7 +1633,7 @@ static void *xt_mttg_seq_start(struct seq_file *seq, loff_t *pos, static void xt_mttg_seq_stop(struct seq_file *seq, void *v) { - uint8_t nfproto = (unsigned long)PDE_DATA(file_inode(seq->file)); + uint8_t nfproto = (unsigned long)pde_data(file_inode(seq->file)); struct nf_mttg_trav *trav = seq->private; switch (trav->class) { diff --git a/net/netfilter/xt_hashlimit.c b/net/netfilter/xt_hashlimit.c index 9c5cfd74a0ee..0859b8f76764 100644 --- a/net/netfilter/xt_hashlimit.c +++ b/net/netfilter/xt_hashlimit.c @@ -1052,7 +1052,7 @@ static struct xt_match hashlimit_mt_reg[] __read_mostly = { static void *dl_seq_start(struct seq_file *s, loff_t *pos) __acquires(htable->lock) { - struct xt_hashlimit_htable *htable = PDE_DATA(file_inode(s->file)); + struct xt_hashlimit_htable *htable = pde_data(file_inode(s->file)); unsigned int *bucket; spin_lock_bh(&htable->lock); @@ -1069,7 +1069,7 @@ static void *dl_seq_start(struct seq_file *s, loff_t *pos) static void *dl_seq_next(struct seq_file *s, void *v, loff_t *pos) { - struct xt_hashlimit_htable *htable = PDE_DATA(file_inode(s->file)); + struct xt_hashlimit_htable *htable = pde_data(file_inode(s->file)); unsigned int *bucket = v; *pos = ++(*bucket); @@ -1083,7 +1083,7 @@ static void *dl_seq_next(struct seq_file *s, void *v, loff_t *pos) static void dl_seq_stop(struct seq_file *s, void *v) __releases(htable->lock) { - struct xt_hashlimit_htable *htable = PDE_DATA(file_inode(s->file)); + struct xt_hashlimit_htable *htable = pde_data(file_inode(s->file)); unsigned int *bucket = v; if (!IS_ERR(bucket)) @@ -1125,7 +1125,7 @@ static void dl_seq_print(struct dsthash_ent *ent, u_int8_t family, static int dl_seq_real_show_v2(struct dsthash_ent *ent, u_int8_t family, struct seq_file *s) { - struct xt_hashlimit_htable *ht = PDE_DATA(file_inode(s->file)); + struct xt_hashlimit_htable *ht = pde_data(file_inode(s->file)); spin_lock(&ent->lock); /* recalculate to show accurate numbers */ @@ -1140,7 +1140,7 @@ static int dl_seq_real_show_v2(struct dsthash_ent *ent, u_int8_t family, static int dl_seq_real_show_v1(struct dsthash_ent *ent, u_int8_t family, struct seq_file *s) { - struct xt_hashlimit_htable *ht = PDE_DATA(file_inode(s->file)); + struct xt_hashlimit_htable *ht = pde_data(file_inode(s->file)); spin_lock(&ent->lock); /* recalculate to show accurate numbers */ @@ -1155,7 +1155,7 @@ static int dl_seq_real_show_v1(struct dsthash_ent *ent, u_int8_t family, static int dl_seq_real_show(struct dsthash_ent *ent, u_int8_t family, struct seq_file *s) { - struct xt_hashlimit_htable *ht = PDE_DATA(file_inode(s->file)); + struct xt_hashlimit_htable *ht = pde_data(file_inode(s->file)); spin_lock(&ent->lock); /* recalculate to show accurate numbers */ @@ -1169,7 +1169,7 @@ static int dl_seq_real_show(struct dsthash_ent *ent, u_int8_t family, static int dl_seq_show_v2(struct seq_file *s, void *v) { - struct xt_hashlimit_htable *htable = PDE_DATA(file_inode(s->file)); + struct xt_hashlimit_htable *htable = pde_data(file_inode(s->file)); unsigned int *bucket = (unsigned int *)v; struct dsthash_ent *ent; @@ -1183,7 +1183,7 @@ static int dl_seq_show_v2(struct seq_file *s, void *v) static int dl_seq_show_v1(struct seq_file *s, void *v) { - struct xt_hashlimit_htable *htable = PDE_DATA(file_inode(s->file)); + struct xt_hashlimit_htable *htable = pde_data(file_inode(s->file)); unsigned int *bucket = v; struct dsthash_ent *ent; @@ -1197,7 +1197,7 @@ static int dl_seq_show_v1(struct seq_file *s, void *v) static int dl_seq_show(struct seq_file *s, void *v) { - struct xt_hashlimit_htable *htable = PDE_DATA(file_inode(s->file)); + struct xt_hashlimit_htable *htable = pde_data(file_inode(s->file)); unsigned int *bucket = v; struct dsthash_ent *ent; diff --git a/net/netfilter/xt_recent.c b/net/netfilter/xt_recent.c index 0446307516cd..7ddb9a78e3fc 100644 --- a/net/netfilter/xt_recent.c +++ b/net/netfilter/xt_recent.c @@ -551,7 +551,7 @@ static int recent_seq_open(struct inode *inode, struct file *file) if (st == NULL) return -ENOMEM; - st->table = PDE_DATA(inode); + st->table = pde_data(inode); return 0; } @@ -559,7 +559,7 @@ static ssize_t recent_mt_proc_write(struct file *file, const char __user *input, size_t size, loff_t *loff) { - struct recent_table *t = PDE_DATA(file_inode(file)); + struct recent_table *t = pde_data(file_inode(file)); struct recent_entry *e; char buf[sizeof("+b335:1d35:1e55:dead:c0de:1715:5afe:c0de")]; const char *c = buf; diff --git a/net/sunrpc/auth_gss/svcauth_gss.c b/net/sunrpc/auth_gss/svcauth_gss.c index b87565b64928..c2ba9d4cd2c7 100644 --- a/net/sunrpc/auth_gss/svcauth_gss.c +++ b/net/sunrpc/auth_gss/svcauth_gss.c @@ -1433,7 +1433,7 @@ static bool use_gss_proxy(struct net *net) static ssize_t write_gssp(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { - struct net *net = PDE_DATA(file_inode(file)); + struct net *net = pde_data(file_inode(file)); char tbuf[20]; unsigned long i; int res; @@ -1461,7 +1461,7 @@ static ssize_t write_gssp(struct file *file, const char __user *buf, static ssize_t read_gssp(struct file *file, char __user *buf, size_t count, loff_t *ppos) { - struct net *net = PDE_DATA(file_inode(file)); + struct net *net = pde_data(file_inode(file)); struct sunrpc_net *sn = net_generic(net, sunrpc_net_id); unsigned long p = *ppos; char tbuf[10]; diff --git a/net/sunrpc/cache.c b/net/sunrpc/cache.c index 59641803472c..bb1177395b99 100644 --- a/net/sunrpc/cache.c +++ b/net/sunrpc/cache.c @@ -1536,7 +1536,7 @@ static ssize_t write_flush(struct file *file, const char __user *buf, static ssize_t cache_read_procfs(struct file *filp, char __user *buf, size_t count, loff_t *ppos) { - struct cache_detail *cd = PDE_DATA(file_inode(filp)); + struct cache_detail *cd = pde_data(file_inode(filp)); return cache_read(filp, buf, count, ppos, cd); } @@ -1544,14 +1544,14 @@ static ssize_t cache_read_procfs(struct file *filp, char __user *buf, static ssize_t cache_write_procfs(struct file *filp, const char __user *buf, size_t count, loff_t *ppos) { - struct cache_detail *cd = PDE_DATA(file_inode(filp)); + struct cache_detail *cd = pde_data(file_inode(filp)); return cache_write(filp, buf, count, ppos, cd); } static __poll_t cache_poll_procfs(struct file *filp, poll_table *wait) { - struct cache_detail *cd = PDE_DATA(file_inode(filp)); + struct cache_detail *cd = pde_data(file_inode(filp)); return cache_poll(filp, wait, cd); } @@ -1560,21 +1560,21 @@ static long cache_ioctl_procfs(struct file *filp, unsigned int cmd, unsigned long arg) { struct inode *inode = file_inode(filp); - struct cache_detail *cd = PDE_DATA(inode); + struct cache_detail *cd = pde_data(inode); return cache_ioctl(inode, filp, cmd, arg, cd); } static int cache_open_procfs(struct inode *inode, struct file *filp) { - struct cache_detail *cd = PDE_DATA(inode); + struct cache_detail *cd = pde_data(inode); return cache_open(inode, filp, cd); } static int cache_release_procfs(struct inode *inode, struct file *filp) { - struct cache_detail *cd = PDE_DATA(inode); + struct cache_detail *cd = pde_data(inode); return cache_release(inode, filp, cd); } @@ -1591,14 +1591,14 @@ static const struct proc_ops cache_channel_proc_ops = { static int content_open_procfs(struct inode *inode, struct file *filp) { - struct cache_detail *cd = PDE_DATA(inode); + struct cache_detail *cd = pde_data(inode); return content_open(inode, filp, cd); } static int content_release_procfs(struct inode *inode, struct file *filp) { - struct cache_detail *cd = PDE_DATA(inode); + struct cache_detail *cd = pde_data(inode); return content_release(inode, filp, cd); } @@ -1612,14 +1612,14 @@ static const struct proc_ops content_proc_ops = { static int open_flush_procfs(struct inode *inode, struct file *filp) { - struct cache_detail *cd = PDE_DATA(inode); + struct cache_detail *cd = pde_data(inode); return open_flush(inode, filp, cd); } static int release_flush_procfs(struct inode *inode, struct file *filp) { - struct cache_detail *cd = PDE_DATA(inode); + struct cache_detail *cd = pde_data(inode); return release_flush(inode, filp, cd); } @@ -1627,7 +1627,7 @@ static int release_flush_procfs(struct inode *inode, struct file *filp) static ssize_t read_flush_procfs(struct file *filp, char __user *buf, size_t count, loff_t *ppos) { - struct cache_detail *cd = PDE_DATA(file_inode(filp)); + struct cache_detail *cd = pde_data(file_inode(filp)); return read_flush(filp, buf, count, ppos, cd); } @@ -1636,7 +1636,7 @@ static ssize_t write_flush_procfs(struct file *filp, const char __user *buf, size_t count, loff_t *ppos) { - struct cache_detail *cd = PDE_DATA(file_inode(filp)); + struct cache_detail *cd = pde_data(file_inode(filp)); return write_flush(filp, buf, count, ppos, cd); } diff --git a/net/sunrpc/stats.c b/net/sunrpc/stats.c index c964b48eaaba..52908f9e6eab 100644 --- a/net/sunrpc/stats.c +++ b/net/sunrpc/stats.c @@ -66,7 +66,7 @@ static int rpc_proc_show(struct seq_file *seq, void *v) { static int rpc_proc_open(struct inode *inode, struct file *file) { - return single_open(file, rpc_proc_show, PDE_DATA(inode)); + return single_open(file, rpc_proc_show, pde_data(inode)); } static const struct proc_ops rpc_proc_ops = { diff --git a/sound/core/info.c b/sound/core/info.c index a451b24199c3..782fba87cc04 100644 --- a/sound/core/info.c +++ b/sound/core/info.c @@ -234,7 +234,7 @@ static int snd_info_entry_mmap(struct file *file, struct vm_area_struct *vma) static int snd_info_entry_open(struct inode *inode, struct file *file) { - struct snd_info_entry *entry = PDE_DATA(inode); + struct snd_info_entry *entry = pde_data(inode); struct snd_info_private_data *data; int mode, err; @@ -365,7 +365,7 @@ static int snd_info_seq_show(struct seq_file *seq, void *p) static int snd_info_text_entry_open(struct inode *inode, struct file *file) { - struct snd_info_entry *entry = PDE_DATA(inode); + struct snd_info_entry *entry = pde_data(inode); struct snd_info_private_data *data; int err; -- cgit v1.2.3 From 0a4ee518185e902758191d968600399f3bc2be31 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 21 Jan 2022 22:14:34 -0800 Subject: mm: remove cleancache Patch series "remove Xen tmem leftovers". Since the removal of the Xen tmem driver in 2019, the cleancache hooks are entirely unused, as are large parts of frontswap. This series against linux-next (with the folio changes included) removes cleancaches, and cuts down frontswap to the bits actually used by zswap. This patch (of 13): The cleancache subsystem is unused since the removal of Xen tmem driver in commit 814bbf49dcd0 ("xen: remove tmem driver"). [akpm@linux-foundation.org: remove now-unreachable code] Link: https://lkml.kernel.org/r/20211224062246.1258487-1-hch@lst.de Link: https://lkml.kernel.org/r/20211224062246.1258487-2-hch@lst.de Signed-off-by: Christoph Hellwig Reviewed-by: Juergen Gross Acked-by: Geert Uytterhoeven Cc: Konrad Rzeszutek Wilk Cc: Hugh Dickins Cc: Seth Jennings Cc: Dan Streetman Cc: Vitaly Wool Cc: Matthew Wilcox (Oracle) Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/vm/cleancache.rst | 296 -------------------------------- Documentation/vm/frontswap.rst | 12 +- Documentation/vm/index.rst | 1 - MAINTAINERS | 7 - arch/arm/configs/bcm2835_defconfig | 1 - arch/arm/configs/qcom_defconfig | 1 - arch/m68k/configs/amiga_defconfig | 1 - arch/m68k/configs/apollo_defconfig | 1 - arch/m68k/configs/atari_defconfig | 1 - arch/m68k/configs/bvme6000_defconfig | 1 - arch/m68k/configs/hp300_defconfig | 1 - arch/m68k/configs/mac_defconfig | 1 - arch/m68k/configs/multi_defconfig | 1 - arch/m68k/configs/mvme147_defconfig | 1 - arch/m68k/configs/mvme16x_defconfig | 1 - arch/m68k/configs/q40_defconfig | 1 - arch/m68k/configs/sun3_defconfig | 1 - arch/m68k/configs/sun3x_defconfig | 1 - arch/s390/configs/debug_defconfig | 1 - arch/s390/configs/defconfig | 1 - block/bdev.c | 5 - fs/btrfs/extent_io.c | 10 -- fs/btrfs/super.c | 2 - fs/ext4/readpage.c | 6 - fs/ext4/super.c | 3 - fs/f2fs/data.c | 13 -- fs/mpage.c | 7 - fs/ntfs3/ntfs_fs.h | 1 - fs/ocfs2/super.c | 2 - fs/super.c | 3 - include/linux/cleancache.h | 124 -------------- include/linux/fs.h | 5 - mm/Kconfig | 22 --- mm/Makefile | 1 - mm/cleancache.c | 315 ----------------------------------- mm/filemap.c | 11 -- mm/truncate.c | 15 +- 37 files changed, 4 insertions(+), 873 deletions(-) delete mode 100644 Documentation/vm/cleancache.rst delete mode 100644 include/linux/cleancache.h delete mode 100644 mm/cleancache.c (limited to 'arch/arm') diff --git a/Documentation/vm/cleancache.rst b/Documentation/vm/cleancache.rst deleted file mode 100644 index 68cba9131c31..000000000000 --- a/Documentation/vm/cleancache.rst +++ /dev/null @@ -1,296 +0,0 @@ -.. _cleancache: - -========== -Cleancache -========== - -Motivation -========== - -Cleancache is a new optional feature provided by the VFS layer that -potentially dramatically increases page cache effectiveness for -many workloads in many environments at a negligible cost. - -Cleancache can be thought of as a page-granularity victim cache for clean -pages that the kernel's pageframe replacement algorithm (PFRA) would like -to keep around, but can't since there isn't enough memory. So when the -PFRA "evicts" a page, it first attempts to use cleancache code to -put the data contained in that page into "transcendent memory", memory -that is not directly accessible or addressable by the kernel and is -of unknown and possibly time-varying size. - -Later, when a cleancache-enabled filesystem wishes to access a page -in a file on disk, it first checks cleancache to see if it already -contains it; if it does, the page of data is copied into the kernel -and a disk access is avoided. - -Transcendent memory "drivers" for cleancache are currently implemented -in Xen (using hypervisor memory) and zcache (using in-kernel compressed -memory) and other implementations are in development. - -:ref:`FAQs ` are included below. - -Implementation Overview -======================= - -A cleancache "backend" that provides transcendent memory registers itself -to the kernel's cleancache "frontend" by calling cleancache_register_ops, -passing a pointer to a cleancache_ops structure with funcs set appropriately. -The functions provided must conform to certain semantics as follows: - -Most important, cleancache is "ephemeral". Pages which are copied into -cleancache have an indefinite lifetime which is completely unknowable -by the kernel and so may or may not still be in cleancache at any later time. -Thus, as its name implies, cleancache is not suitable for dirty pages. -Cleancache has complete discretion over what pages to preserve and what -pages to discard and when. - -Mounting a cleancache-enabled filesystem should call "init_fs" to obtain a -pool id which, if positive, must be saved in the filesystem's superblock; -a negative return value indicates failure. A "put_page" will copy a -(presumably about-to-be-evicted) page into cleancache and associate it with -the pool id, a file key, and a page index into the file. (The combination -of a pool id, a file key, and an index is sometimes called a "handle".) -A "get_page" will copy the page, if found, from cleancache into kernel memory. -An "invalidate_page" will ensure the page no longer is present in cleancache; -an "invalidate_inode" will invalidate all pages associated with the specified -file; and, when a filesystem is unmounted, an "invalidate_fs" will invalidate -all pages in all files specified by the given pool id and also surrender -the pool id. - -An "init_shared_fs", like init_fs, obtains a pool id but tells cleancache -to treat the pool as shared using a 128-bit UUID as a key. On systems -that may run multiple kernels (such as hard partitioned or virtualized -systems) that may share a clustered filesystem, and where cleancache -may be shared among those kernels, calls to init_shared_fs that specify the -same UUID will receive the same pool id, thus allowing the pages to -be shared. Note that any security requirements must be imposed outside -of the kernel (e.g. by "tools" that control cleancache). Or a -cleancache implementation can simply disable shared_init by always -returning a negative value. - -If a get_page is successful on a non-shared pool, the page is invalidated -(thus making cleancache an "exclusive" cache). On a shared pool, the page -is NOT invalidated on a successful get_page so that it remains accessible to -other sharers. The kernel is responsible for ensuring coherency between -cleancache (shared or not), the page cache, and the filesystem, using -cleancache invalidate operations as required. - -Note that cleancache must enforce put-put-get coherency and get-get -coherency. For the former, if two puts are made to the same handle but -with different data, say AAA by the first put and BBB by the second, a -subsequent get can never return the stale data (AAA). For get-get coherency, -if a get for a given handle fails, subsequent gets for that handle will -never succeed unless preceded by a successful put with that handle. - -Last, cleancache provides no SMP serialization guarantees; if two -different Linux threads are simultaneously putting and invalidating a page -with the same handle, the results are indeterminate. Callers must -lock the page to ensure serial behavior. - -Cleancache Performance Metrics -============================== - -If properly configured, monitoring of cleancache is done via debugfs in -the `/sys/kernel/debug/cleancache` directory. The effectiveness of cleancache -can be measured (across all filesystems) with: - -``succ_gets`` - number of gets that were successful - -``failed_gets`` - number of gets that failed - -``puts`` - number of puts attempted (all "succeed") - -``invalidates`` - number of invalidates attempted - -A backend implementation may provide additional metrics. - -.. _faq: - -FAQ -=== - -* Where's the value? (Andrew Morton) - -Cleancache provides a significant performance benefit to many workloads -in many environments with negligible overhead by improving the -effectiveness of the pagecache. Clean pagecache pages are -saved in transcendent memory (RAM that is otherwise not directly -addressable to the kernel); fetching those pages later avoids "refaults" -and thus disk reads. - -Cleancache (and its sister code "frontswap") provide interfaces for -this transcendent memory (aka "tmem"), which conceptually lies between -fast kernel-directly-addressable RAM and slower DMA/asynchronous devices. -Disallowing direct kernel or userland reads/writes to tmem -is ideal when data is transformed to a different form and size (such -as with compression) or secretly moved (as might be useful for write- -balancing for some RAM-like devices). Evicted page-cache pages (and -swap pages) are a great use for this kind of slower-than-RAM-but-much- -faster-than-disk transcendent memory, and the cleancache (and frontswap) -"page-object-oriented" specification provides a nice way to read and -write -- and indirectly "name" -- the pages. - -In the virtual case, the whole point of virtualization is to statistically -multiplex physical resources across the varying demands of multiple -virtual machines. This is really hard to do with RAM and efforts to -do it well with no kernel change have essentially failed (except in some -well-publicized special-case workloads). Cleancache -- and frontswap -- -with a fairly small impact on the kernel, provide a huge amount -of flexibility for more dynamic, flexible RAM multiplexing. -Specifically, the Xen Transcendent Memory backend allows otherwise -"fallow" hypervisor-owned RAM to not only be "time-shared" between multiple -virtual machines, but the pages can be compressed and deduplicated to -optimize RAM utilization. And when guest OS's are induced to surrender -underutilized RAM (e.g. with "self-ballooning"), page cache pages -are the first to go, and cleancache allows those pages to be -saved and reclaimed if overall host system memory conditions allow. - -And the identical interface used for cleancache can be used in -physical systems as well. The zcache driver acts as a memory-hungry -device that stores pages of data in a compressed state. And -the proposed "RAMster" driver shares RAM across multiple physical -systems. - -* Why does cleancache have its sticky fingers so deep inside the - filesystems and VFS? (Andrew Morton and Christoph Hellwig) - -The core hooks for cleancache in VFS are in most cases a single line -and the minimum set are placed precisely where needed to maintain -coherency (via cleancache_invalidate operations) between cleancache, -the page cache, and disk. All hooks compile into nothingness if -cleancache is config'ed off and turn into a function-pointer- -compare-to-NULL if config'ed on but no backend claims the ops -functions, or to a compare-struct-element-to-negative if a -backend claims the ops functions but a filesystem doesn't enable -cleancache. - -Some filesystems are built entirely on top of VFS and the hooks -in VFS are sufficient, so don't require an "init_fs" hook; the -initial implementation of cleancache didn't provide this hook. -But for some filesystems (such as btrfs), the VFS hooks are -incomplete and one or more hooks in fs-specific code are required. -And for some other filesystems, such as tmpfs, cleancache may -be counterproductive. So it seemed prudent to require a filesystem -to "opt in" to use cleancache, which requires adding a hook in -each filesystem. Not all filesystems are supported by cleancache -only because they haven't been tested. The existing set should -be sufficient to validate the concept, the opt-in approach means -that untested filesystems are not affected, and the hooks in the -existing filesystems should make it very easy to add more -filesystems in the future. - -The total impact of the hooks to existing fs and mm files is only -about 40 lines added (not counting comments and blank lines). - -* Why not make cleancache asynchronous and batched so it can more - easily interface with real devices with DMA instead of copying each - individual page? (Minchan Kim) - -The one-page-at-a-time copy semantics simplifies the implementation -on both the frontend and backend and also allows the backend to -do fancy things on-the-fly like page compression and -page deduplication. And since the data is "gone" (copied into/out -of the pageframe) before the cleancache get/put call returns, -a great deal of race conditions and potential coherency issues -are avoided. While the interface seems odd for a "real device" -or for real kernel-addressable RAM, it makes perfect sense for -transcendent memory. - -* Why is non-shared cleancache "exclusive"? And where is the - page "invalidated" after a "get"? (Minchan Kim) - -The main reason is to free up space in transcendent memory and -to avoid unnecessary cleancache_invalidate calls. If you want inclusive, -the page can be "put" immediately following the "get". If -put-after-get for inclusive becomes common, the interface could -be easily extended to add a "get_no_invalidate" call. - -The invalidate is done by the cleancache backend implementation. - -* What's the performance impact? - -Performance analysis has been presented at OLS'09 and LCA'10. -Briefly, performance gains can be significant on most workloads, -especially when memory pressure is high (e.g. when RAM is -overcommitted in a virtual workload); and because the hooks are -invoked primarily in place of or in addition to a disk read/write, -overhead is negligible even in worst case workloads. Basically -cleancache replaces I/O with memory-copy-CPU-overhead; on older -single-core systems with slow memory-copy speeds, cleancache -has little value, but in newer multicore machines, especially -consolidated/virtualized machines, it has great value. - -* How do I add cleancache support for filesystem X? (Boaz Harrash) - -Filesystems that are well-behaved and conform to certain -restrictions can utilize cleancache simply by making a call to -cleancache_init_fs at mount time. Unusual, misbehaving, or -poorly layered filesystems must either add additional hooks -and/or undergo extensive additional testing... or should just -not enable the optional cleancache. - -Some points for a filesystem to consider: - - - The FS should be block-device-based (e.g. a ram-based FS such - as tmpfs should not enable cleancache) - - To ensure coherency/correctness, the FS must ensure that all - file removal or truncation operations either go through VFS or - add hooks to do the equivalent cleancache "invalidate" operations - - To ensure coherency/correctness, either inode numbers must - be unique across the lifetime of the on-disk file OR the - FS must provide an "encode_fh" function. - - The FS must call the VFS superblock alloc and deactivate routines - or add hooks to do the equivalent cleancache calls done there. - - To maximize performance, all pages fetched from the FS should - go through the do_mpag_readpage routine or the FS should add - hooks to do the equivalent (cf. btrfs) - - Currently, the FS blocksize must be the same as PAGESIZE. This - is not an architectural restriction, but no backends currently - support anything different. - - A clustered FS should invoke the "shared_init_fs" cleancache - hook to get best performance for some backends. - -* Why not use the KVA of the inode as the key? (Christoph Hellwig) - -If cleancache would use the inode virtual address instead of -inode/filehandle, the pool id could be eliminated. But, this -won't work because cleancache retains pagecache data pages -persistently even when the inode has been pruned from the -inode unused list, and only invalidates the data page if the file -gets removed/truncated. So if cleancache used the inode kva, -there would be potential coherency issues if/when the inode -kva is reused for a different file. Alternately, if cleancache -invalidated the pages when the inode kva was freed, much of the value -of cleancache would be lost because the cache of pages in cleanache -is potentially much larger than the kernel pagecache and is most -useful if the pages survive inode cache removal. - -* Why is a global variable required? - -The cleancache_enabled flag is checked in all of the frequently-used -cleancache hooks. The alternative is a function call to check a static -variable. Since cleancache is enabled dynamically at runtime, systems -that don't enable cleancache would suffer thousands (possibly -tens-of-thousands) of unnecessary function calls per second. So the -global variable allows cleancache to be enabled by default at compile -time, but have insignificant performance impact when cleancache remains -disabled at runtime. - -* Does cleanache work with KVM? - -The memory model of KVM is sufficiently different that a cleancache -backend may have less value for KVM. This remains to be tested, -especially in an overcommitted system. - -* Does cleancache work in userspace? It sounds useful for - memory hungry caches like web browsers. (Jamie Lokier) - -No plans yet, though we agree it sounds useful, at least for -apps that bypass the page cache (e.g. O_DIRECT). - -Last updated: Dan Magenheimer, April 13 2011 diff --git a/Documentation/vm/frontswap.rst b/Documentation/vm/frontswap.rst index 1979f430c1c5..e2e5ab3e375e 100644 --- a/Documentation/vm/frontswap.rst +++ b/Documentation/vm/frontswap.rst @@ -8,12 +8,6 @@ Frontswap provides a "transcendent memory" interface for swap pages. In some environments, dramatic performance savings may be obtained because swapped pages are saved in RAM (or a RAM-like device) instead of a swap disk. -(Note, frontswap -- and :ref:`cleancache` (merged at 3.0) -- are the "frontends" -and the only necessary changes to the core kernel for transcendent memory; -all other supporting code -- the "backends" -- is implemented as drivers. -See the LWN.net article `Transcendent memory in a nutshell`_ -for a detailed overview of frontswap and related kernel parts) - .. _Transcendent memory in a nutshell: https://lwn.net/Articles/454795/ Frontswap is so named because it can be thought of as the opposite of @@ -87,11 +81,9 @@ This interface is ideal when data is transformed to a different form and size (such as with compression) or secretly moved (as might be useful for write-balancing for some RAM-like devices). Swap pages (and evicted page-cache pages) are a great use for this kind of slower-than-RAM- -but-much-faster-than-disk "pseudo-RAM device" and the frontswap (and -cleancache) interface to transcendent memory provides a nice way to read -and write -- and indirectly "name" -- the pages. +but-much-faster-than-disk "pseudo-RAM device". -Frontswap -- and cleancache -- with a fairly small impact on the kernel, +Frontswap with a fairly small impact on the kernel, provides a huge amount of flexibility for more dynamic, flexible RAM utilization in various system configurations: diff --git a/Documentation/vm/index.rst b/Documentation/vm/index.rst index 932440805453..44365c4574a3 100644 --- a/Documentation/vm/index.rst +++ b/Documentation/vm/index.rst @@ -15,7 +15,6 @@ algorithms. If you are looking for advice on simply allocating memory, see the active_mm arch_pgtable_helpers balance - cleancache damon/index free_page_reporting frontswap diff --git a/MAINTAINERS b/MAINTAINERS index 6c08cbe953fe..45f8750f6e30 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4705,13 +4705,6 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git for-next/cla F: include/linux/cfi.h F: kernel/cfi.c -CLEANCACHE API -M: Konrad Rzeszutek Wilk -L: linux-kernel@vger.kernel.org -S: Maintained -F: include/linux/cleancache.h -F: mm/cleancache.c - CLK API M: Russell King L: linux-clk@vger.kernel.org diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig index 383c632eba7b..a9ed79b7f871 100644 --- a/arch/arm/configs/bcm2835_defconfig +++ b/arch/arm/configs/bcm2835_defconfig @@ -31,7 +31,6 @@ CONFIG_ARCH_BCM2835=y CONFIG_PREEMPT_VOLUNTARY=y CONFIG_AEABI=y CONFIG_KSM=y -CONFIG_CLEANCACHE=y CONFIG_CMA=y CONFIG_SECCOMP=y CONFIG_KEXEC=y diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index 0daa9c0d298e..9981566f2096 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -27,7 +27,6 @@ CONFIG_PCIE_QCOM=y CONFIG_SMP=y CONFIG_PREEMPT=y CONFIG_HIGHMEM=y -CONFIG_CLEANCACHE=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CPU_IDLE=y diff --git a/arch/m68k/configs/amiga_defconfig b/arch/m68k/configs/amiga_defconfig index a4b6c7108465..bc9952f8be66 100644 --- a/arch/m68k/configs/amiga_defconfig +++ b/arch/m68k/configs/amiga_defconfig @@ -45,7 +45,6 @@ CONFIG_IOSCHED_BFQ=m CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_COMPACTION is not set -CONFIG_CLEANCACHE=y CONFIG_ZPOOL=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/m68k/configs/apollo_defconfig b/arch/m68k/configs/apollo_defconfig index 2db721965520..a77269c6e5ba 100644 --- a/arch/m68k/configs/apollo_defconfig +++ b/arch/m68k/configs/apollo_defconfig @@ -41,7 +41,6 @@ CONFIG_IOSCHED_BFQ=m CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_COMPACTION is not set -CONFIG_CLEANCACHE=y CONFIG_ZPOOL=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/m68k/configs/atari_defconfig b/arch/m68k/configs/atari_defconfig index c266a704eecd..7a74efa6b9a1 100644 --- a/arch/m68k/configs/atari_defconfig +++ b/arch/m68k/configs/atari_defconfig @@ -48,7 +48,6 @@ CONFIG_IOSCHED_BFQ=m CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_COMPACTION is not set -CONFIG_CLEANCACHE=y CONFIG_ZPOOL=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/m68k/configs/bvme6000_defconfig b/arch/m68k/configs/bvme6000_defconfig index f644f08dd6ed..a5323bf2eb33 100644 --- a/arch/m68k/configs/bvme6000_defconfig +++ b/arch/m68k/configs/bvme6000_defconfig @@ -38,7 +38,6 @@ CONFIG_IOSCHED_BFQ=m CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_COMPACTION is not set -CONFIG_CLEANCACHE=y CONFIG_ZPOOL=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/m68k/configs/hp300_defconfig b/arch/m68k/configs/hp300_defconfig index e4924650b687..5e80aa0869d5 100644 --- a/arch/m68k/configs/hp300_defconfig +++ b/arch/m68k/configs/hp300_defconfig @@ -40,7 +40,6 @@ CONFIG_IOSCHED_BFQ=m CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_COMPACTION is not set -CONFIG_CLEANCACHE=y CONFIG_ZPOOL=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig index 24113871ea76..e84326a3f62d 100644 --- a/arch/m68k/configs/mac_defconfig +++ b/arch/m68k/configs/mac_defconfig @@ -39,7 +39,6 @@ CONFIG_IOSCHED_BFQ=m CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_COMPACTION is not set -CONFIG_CLEANCACHE=y CONFIG_ZPOOL=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/m68k/configs/multi_defconfig b/arch/m68k/configs/multi_defconfig index 6a7e4be70eea..337552f43339 100644 --- a/arch/m68k/configs/multi_defconfig +++ b/arch/m68k/configs/multi_defconfig @@ -59,7 +59,6 @@ CONFIG_IOSCHED_BFQ=m CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_COMPACTION is not set -CONFIG_CLEANCACHE=y CONFIG_ZPOOL=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/m68k/configs/mvme147_defconfig b/arch/m68k/configs/mvme147_defconfig index 1d223247aff0..7b688f7d272a 100644 --- a/arch/m68k/configs/mvme147_defconfig +++ b/arch/m68k/configs/mvme147_defconfig @@ -37,7 +37,6 @@ CONFIG_IOSCHED_BFQ=m CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_COMPACTION is not set -CONFIG_CLEANCACHE=y CONFIG_ZPOOL=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/m68k/configs/mvme16x_defconfig b/arch/m68k/configs/mvme16x_defconfig index 961f789f96c9..7c2cb31d63dd 100644 --- a/arch/m68k/configs/mvme16x_defconfig +++ b/arch/m68k/configs/mvme16x_defconfig @@ -38,7 +38,6 @@ CONFIG_IOSCHED_BFQ=m CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_COMPACTION is not set -CONFIG_CLEANCACHE=y CONFIG_ZPOOL=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig index ff4b5e469390..ca43897af26d 100644 --- a/arch/m68k/configs/q40_defconfig +++ b/arch/m68k/configs/q40_defconfig @@ -39,7 +39,6 @@ CONFIG_IOSCHED_BFQ=m CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_COMPACTION is not set -CONFIG_CLEANCACHE=y CONFIG_ZPOOL=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/m68k/configs/sun3_defconfig b/arch/m68k/configs/sun3_defconfig index 5f228621d0cc..e3d515f37144 100644 --- a/arch/m68k/configs/sun3_defconfig +++ b/arch/m68k/configs/sun3_defconfig @@ -35,7 +35,6 @@ CONFIG_IOSCHED_BFQ=m CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_COMPACTION is not set -CONFIG_CLEANCACHE=y CONFIG_ZPOOL=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/m68k/configs/sun3x_defconfig b/arch/m68k/configs/sun3x_defconfig index a600cb9e68c2..d601606c969b 100644 --- a/arch/m68k/configs/sun3x_defconfig +++ b/arch/m68k/configs/sun3x_defconfig @@ -35,7 +35,6 @@ CONFIG_IOSCHED_BFQ=m CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m # CONFIG_COMPACTION is not set -CONFIG_CLEANCACHE=y CONFIG_ZPOOL=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/s390/configs/debug_defconfig b/arch/s390/configs/debug_defconfig index 354e51dcb3e2..7fe8975b49ec 100644 --- a/arch/s390/configs/debug_defconfig +++ b/arch/s390/configs/debug_defconfig @@ -96,7 +96,6 @@ CONFIG_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTREMOVE=y CONFIG_KSM=y CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y CONFIG_CMA_DEBUG=y CONFIG_CMA_DEBUGFS=y diff --git a/arch/s390/configs/defconfig b/arch/s390/configs/defconfig index 8dee6c3782f3..466780c465f5 100644 --- a/arch/s390/configs/defconfig +++ b/arch/s390/configs/defconfig @@ -91,7 +91,6 @@ CONFIG_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTREMOVE=y CONFIG_KSM=y CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=7 diff --git a/block/bdev.c b/block/bdev.c index 8bf93a19041b..102837a37051 100644 --- a/block/bdev.c +++ b/block/bdev.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include "../fs/internal.h" @@ -88,10 +87,6 @@ void invalidate_bdev(struct block_device *bdev) lru_add_drain_all(); /* make sure all lru add caches are flushed */ invalidate_mapping_pages(mapping, 0, -1); } - /* 99% of the time, we don't need to flush the cleancache on the bdev. - * But, for the strange corners, lets be cautious - */ - cleancache_invalidate_inode(mapping); } EXPORT_SYMBOL(invalidate_bdev); diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c index d6d48ecf823c..409bad3928db 100644 --- a/fs/btrfs/extent_io.c +++ b/fs/btrfs/extent_io.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include "misc.h" #include "extent_io.h" @@ -3578,15 +3577,6 @@ int btrfs_do_readpage(struct page *page, struct extent_map **em_cached, goto out; } - if (!PageUptodate(page)) { - if (cleancache_get_page(page) == 0) { - BUG_ON(blocksize != PAGE_SIZE); - unlock_extent(tree, start, end); - unlock_page(page); - goto out; - } - } - if (page->index == last_byte >> PAGE_SHIFT) { size_t zero_offset = offset_in_page(last_byte); diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c index 0ec09fe01be6..4d947ba32da9 100644 --- a/fs/btrfs/super.c +++ b/fs/btrfs/super.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -1374,7 +1373,6 @@ static int btrfs_fill_super(struct super_block *sb, goto fail_close; } - cleancache_init_fs(sb); sb->s_flags |= SB_ACTIVE; return 0; diff --git a/fs/ext4/readpage.c b/fs/ext4/readpage.c index 3db923403505..4cd62f1d848c 100644 --- a/fs/ext4/readpage.c +++ b/fs/ext4/readpage.c @@ -43,7 +43,6 @@ #include #include #include -#include #include "ext4.h" @@ -350,11 +349,6 @@ int ext4_mpage_readpages(struct inode *inode, } else if (fully_mapped) { SetPageMappedToDisk(page); } - if (fully_mapped && blocks_per_page == 1 && - !PageUptodate(page) && cleancache_get_page(page) == 0) { - SetPageUptodate(page); - goto confused; - } /* * This page will go to BIO. Do we need to send this diff --git a/fs/ext4/super.c b/fs/ext4/super.c index db9fe4843529..eee0d9ebfa6c 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -39,7 +39,6 @@ #include #include #include -#include #include #include #include @@ -3149,8 +3148,6 @@ done: EXT4_BLOCKS_PER_GROUP(sb), EXT4_INODES_PER_GROUP(sb), sbi->s_mount_opt, sbi->s_mount_opt2); - - cleancache_init_fs(sb); return err; } diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index 0a1d236212f8..8c417864c66a 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -2035,12 +2034,6 @@ got_it: block_nr = map->m_pblk + block_in_file - map->m_lblk; SetPageMappedToDisk(page); - if (!PageUptodate(page) && (!PageSwapCache(page) && - !cleancache_get_page(page))) { - SetPageUptodate(page); - goto confused; - } - if (!f2fs_is_valid_blkaddr(F2FS_I_SB(inode), block_nr, DATA_GENERIC_ENHANCE_READ)) { ret = -EFSCORRUPTED; @@ -2096,12 +2089,6 @@ submit_and_realloc: ClearPageError(page); *last_block_in_bio = block_nr; goto out; -confused: - if (bio) { - __submit_bio(F2FS_I_SB(inode), bio, DATA); - bio = NULL; - } - unlock_page(page); out: *bio_ret = bio; return ret; diff --git a/fs/mpage.c b/fs/mpage.c index 334e7d09aa65..87f5cfef6caa 100644 --- a/fs/mpage.c +++ b/fs/mpage.c @@ -29,7 +29,6 @@ #include #include #include -#include #include "internal.h" /* @@ -284,12 +283,6 @@ static struct bio *do_mpage_readpage(struct mpage_readpage_args *args) SetPageMappedToDisk(page); } - if (fully_mapped && blocks_per_page == 1 && !PageUptodate(page) && - cleancache_get_page(page) == 0) { - SetPageUptodate(page); - goto confused; - } - /* * This page will go to BIO. Do we need to send this BIO off first? */ diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h index 8aaec7e0804e..fb825059d488 100644 --- a/fs/ntfs3/ntfs_fs.h +++ b/fs/ntfs3/ntfs_fs.h @@ -11,7 +11,6 @@ #include #include -#include #include #include #include diff --git a/fs/ocfs2/super.c b/fs/ocfs2/super.c index 1286b88b6fa1..2772dec9dcea 100644 --- a/fs/ocfs2/super.c +++ b/fs/ocfs2/super.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #define CREATE_TRACE_POINTS @@ -2283,7 +2282,6 @@ static int ocfs2_initialize_super(struct super_block *sb, mlog_errno(status); goto bail; } - cleancache_init_shared_fs(sb); osb->ocfs2_wq = alloc_ordered_workqueue("ocfs2_wq", WQ_MEM_RECLAIM); if (!osb->ocfs2_wq) { diff --git a/fs/super.c b/fs/super.c index a6405d44d4ca..7af820ba5ad5 100644 --- a/fs/super.c +++ b/fs/super.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -260,7 +259,6 @@ static struct super_block *alloc_super(struct file_system_type *type, int flags, s->s_time_gran = 1000000000; s->s_time_min = TIME64_MIN; s->s_time_max = TIME64_MAX; - s->cleancache_poolid = CLEANCACHE_NO_POOL; s->s_shrink.seeks = DEFAULT_SEEKS; s->s_shrink.scan_objects = super_cache_scan; @@ -330,7 +328,6 @@ void deactivate_locked_super(struct super_block *s) { struct file_system_type *fs = s->s_type; if (atomic_dec_and_test(&s->s_active)) { - cleancache_invalidate_fs(s); unregister_shrinker(&s->s_shrink); fs->kill_sb(s); diff --git a/include/linux/cleancache.h b/include/linux/cleancache.h deleted file mode 100644 index 5f5730c1d324..000000000000 --- a/include/linux/cleancache.h +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _LINUX_CLEANCACHE_H -#define _LINUX_CLEANCACHE_H - -#include -#include -#include - -#define CLEANCACHE_NO_POOL -1 -#define CLEANCACHE_NO_BACKEND -2 -#define CLEANCACHE_NO_BACKEND_SHARED -3 - -#define CLEANCACHE_KEY_MAX 6 - -/* - * cleancache requires every file with a page in cleancache to have a - * unique key unless/until the file is removed/truncated. For some - * filesystems, the inode number is unique, but for "modern" filesystems - * an exportable filehandle is required (see exportfs.h) - */ -struct cleancache_filekey { - union { - ino_t ino; - __u32 fh[CLEANCACHE_KEY_MAX]; - u32 key[CLEANCACHE_KEY_MAX]; - } u; -}; - -struct cleancache_ops { - int (*init_fs)(size_t); - int (*init_shared_fs)(uuid_t *uuid, size_t); - int (*get_page)(int, struct cleancache_filekey, - pgoff_t, struct page *); - void (*put_page)(int, struct cleancache_filekey, - pgoff_t, struct page *); - void (*invalidate_page)(int, struct cleancache_filekey, pgoff_t); - void (*invalidate_inode)(int, struct cleancache_filekey); - void (*invalidate_fs)(int); -}; - -extern int cleancache_register_ops(const struct cleancache_ops *ops); -extern void __cleancache_init_fs(struct super_block *); -extern void __cleancache_init_shared_fs(struct super_block *); -extern int __cleancache_get_page(struct page *); -extern void __cleancache_put_page(struct page *); -extern void __cleancache_invalidate_page(struct address_space *, struct page *); -extern void __cleancache_invalidate_inode(struct address_space *); -extern void __cleancache_invalidate_fs(struct super_block *); - -#ifdef CONFIG_CLEANCACHE -#define cleancache_enabled (1) -static inline bool cleancache_fs_enabled_mapping(struct address_space *mapping) -{ - return mapping->host->i_sb->cleancache_poolid >= 0; -} -static inline bool cleancache_fs_enabled(struct page *page) -{ - return cleancache_fs_enabled_mapping(page->mapping); -} -#else -#define cleancache_enabled (0) -#define cleancache_fs_enabled(_page) (0) -#define cleancache_fs_enabled_mapping(_page) (0) -#endif - -/* - * The shim layer provided by these inline functions allows the compiler - * to reduce all cleancache hooks to nothingness if CONFIG_CLEANCACHE - * is disabled, to a single global variable check if CONFIG_CLEANCACHE - * is enabled but no cleancache "backend" has dynamically enabled it, - * and, for the most frequent cleancache ops, to a single global variable - * check plus a superblock element comparison if CONFIG_CLEANCACHE is enabled - * and a cleancache backend has dynamically enabled cleancache, but the - * filesystem referenced by that cleancache op has not enabled cleancache. - * As a result, CONFIG_CLEANCACHE can be enabled by default with essentially - * no measurable performance impact. - */ - -static inline void cleancache_init_fs(struct super_block *sb) -{ - if (cleancache_enabled) - __cleancache_init_fs(sb); -} - -static inline void cleancache_init_shared_fs(struct super_block *sb) -{ - if (cleancache_enabled) - __cleancache_init_shared_fs(sb); -} - -static inline int cleancache_get_page(struct page *page) -{ - if (cleancache_enabled && cleancache_fs_enabled(page)) - return __cleancache_get_page(page); - return -1; -} - -static inline void cleancache_put_page(struct page *page) -{ - if (cleancache_enabled && cleancache_fs_enabled(page)) - __cleancache_put_page(page); -} - -static inline void cleancache_invalidate_page(struct address_space *mapping, - struct page *page) -{ - /* careful... page->mapping is NULL sometimes when this is called */ - if (cleancache_enabled && cleancache_fs_enabled_mapping(mapping)) - __cleancache_invalidate_page(mapping, page); -} - -static inline void cleancache_invalidate_inode(struct address_space *mapping) -{ - if (cleancache_enabled && cleancache_fs_enabled_mapping(mapping)) - __cleancache_invalidate_inode(mapping); -} - -static inline void cleancache_invalidate_fs(struct super_block *sb) -{ - if (cleancache_enabled) - __cleancache_invalidate_fs(sb); -} - -#endif /* _LINUX_CLEANCACHE_H */ diff --git a/include/linux/fs.h b/include/linux/fs.h index 9617dea24978..f3daaea16554 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -1535,11 +1535,6 @@ struct super_block { const struct dentry_operations *s_d_op; /* default d_op for dentries */ - /* - * Saved pool identifier for cleancache (-1 means none) - */ - int cleancache_poolid; - struct shrinker s_shrink; /* per-sb shrinker handle */ /* Number of inodes with nlink == 0 but still referenced */ diff --git a/mm/Kconfig b/mm/Kconfig index a99bd499ef51..430240289b02 100644 --- a/mm/Kconfig +++ b/mm/Kconfig @@ -444,28 +444,6 @@ config USE_PERCPU_NUMA_NODE_ID config HAVE_SETUP_PER_CPU_AREA bool -config CLEANCACHE - bool "Enable cleancache driver to cache clean pages if tmem is present" - help - Cleancache can be thought of as a page-granularity victim cache - for clean pages that the kernel's pageframe replacement algorithm - (PFRA) would like to keep around, but can't since there isn't enough - memory. So when the PFRA "evicts" a page, it first attempts to use - cleancache code to put the data contained in that page into - "transcendent memory", memory that is not directly accessible or - addressable by the kernel and is of unknown and possibly - time-varying size. And when a cleancache-enabled - filesystem wishes to access a page in a file on disk, it first - checks cleancache to see if it already contains it; if it does, - the page is copied into the kernel and a disk access is avoided. - When a transcendent memory driver is available (such as zcache or - Xen transcendent memory), a significant I/O reduction - may be achieved. When none is available, all cleancache calls - are reduced to a single pointer-compare-against-NULL resulting - in a negligible performance hit. - - If unsure, say Y to enable cleancache - config FRONTSWAP bool "Enable frontswap to cache swap pages if tmem is present" depends on SWAP diff --git a/mm/Makefile b/mm/Makefile index 588d3113f3b0..70d4309c9ce3 100644 --- a/mm/Makefile +++ b/mm/Makefile @@ -104,7 +104,6 @@ obj-$(CONFIG_DEBUG_KMEMLEAK) += kmemleak.o obj-$(CONFIG_DEBUG_RODATA_TEST) += rodata_test.o obj-$(CONFIG_DEBUG_VM_PGTABLE) += debug_vm_pgtable.o obj-$(CONFIG_PAGE_OWNER) += page_owner.o -obj-$(CONFIG_CLEANCACHE) += cleancache.o obj-$(CONFIG_MEMORY_ISOLATION) += page_isolation.o obj-$(CONFIG_ZPOOL) += zpool.o obj-$(CONFIG_ZBUD) += zbud.o diff --git a/mm/cleancache.c b/mm/cleancache.c deleted file mode 100644 index db7eee9c0886..000000000000 --- a/mm/cleancache.c +++ /dev/null @@ -1,315 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Cleancache frontend - * - * This code provides the generic "frontend" layer to call a matching - * "backend" driver implementation of cleancache. See - * Documentation/vm/cleancache.rst for more information. - * - * Copyright (C) 2009-2010 Oracle Corp. All rights reserved. - * Author: Dan Magenheimer - */ - -#include -#include -#include -#include -#include -#include - -/* - * cleancache_ops is set by cleancache_register_ops to contain the pointers - * to the cleancache "backend" implementation functions. - */ -static const struct cleancache_ops *cleancache_ops __read_mostly; - -/* - * Counters available via /sys/kernel/debug/cleancache (if debugfs is - * properly configured. These are for information only so are not protected - * against increment races. - */ -static u64 cleancache_succ_gets; -static u64 cleancache_failed_gets; -static u64 cleancache_puts; -static u64 cleancache_invalidates; - -static void cleancache_register_ops_sb(struct super_block *sb, void *unused) -{ - switch (sb->cleancache_poolid) { - case CLEANCACHE_NO_BACKEND: - __cleancache_init_fs(sb); - break; - case CLEANCACHE_NO_BACKEND_SHARED: - __cleancache_init_shared_fs(sb); - break; - } -} - -/* - * Register operations for cleancache. Returns 0 on success. - */ -int cleancache_register_ops(const struct cleancache_ops *ops) -{ - if (cmpxchg(&cleancache_ops, NULL, ops)) - return -EBUSY; - - /* - * A cleancache backend can be built as a module and hence loaded after - * a cleancache enabled filesystem has called cleancache_init_fs. To - * handle such a scenario, here we call ->init_fs or ->init_shared_fs - * for each active super block. To differentiate between local and - * shared filesystems, we temporarily initialize sb->cleancache_poolid - * to CLEANCACHE_NO_BACKEND or CLEANCACHE_NO_BACKEND_SHARED - * respectively in case there is no backend registered at the time - * cleancache_init_fs or cleancache_init_shared_fs is called. - * - * Since filesystems can be mounted concurrently with cleancache - * backend registration, we have to be careful to guarantee that all - * cleancache enabled filesystems that has been mounted by the time - * cleancache_register_ops is called has got and all mounted later will - * get cleancache_poolid. This is assured by the following statements - * tied together: - * - * a) iterate_supers skips only those super blocks that has started - * ->kill_sb - * - * b) if iterate_supers encounters a super block that has not finished - * ->mount yet, it waits until it is finished - * - * c) cleancache_init_fs is called from ->mount and - * cleancache_invalidate_fs is called from ->kill_sb - * - * d) we call iterate_supers after cleancache_ops has been set - * - * From a) it follows that if iterate_supers skips a super block, then - * either the super block is already dead, in which case we do not need - * to bother initializing cleancache for it, or it was mounted after we - * initiated iterate_supers. In the latter case, it must have seen - * cleancache_ops set according to d) and initialized cleancache from - * ->mount by itself according to c). This proves that we call - * ->init_fs at least once for each active super block. - * - * From b) and c) it follows that if iterate_supers encounters a super - * block that has already started ->init_fs, it will wait until ->mount - * and hence ->init_fs has finished, then check cleancache_poolid, see - * that it has already been set and therefore do nothing. This proves - * that we call ->init_fs no more than once for each super block. - * - * Combined together, the last two paragraphs prove the function - * correctness. - * - * Note that various cleancache callbacks may proceed before this - * function is called or even concurrently with it, but since - * CLEANCACHE_NO_BACKEND is negative, they will all result in a noop - * until the corresponding ->init_fs has been actually called and - * cleancache_ops has been set. - */ - iterate_supers(cleancache_register_ops_sb, NULL); - return 0; -} -EXPORT_SYMBOL(cleancache_register_ops); - -/* Called by a cleancache-enabled filesystem at time of mount */ -void __cleancache_init_fs(struct super_block *sb) -{ - int pool_id = CLEANCACHE_NO_BACKEND; - - if (cleancache_ops) { - pool_id = cleancache_ops->init_fs(PAGE_SIZE); - if (pool_id < 0) - pool_id = CLEANCACHE_NO_POOL; - } - sb->cleancache_poolid = pool_id; -} -EXPORT_SYMBOL(__cleancache_init_fs); - -/* Called by a cleancache-enabled clustered filesystem at time of mount */ -void __cleancache_init_shared_fs(struct super_block *sb) -{ - int pool_id = CLEANCACHE_NO_BACKEND_SHARED; - - if (cleancache_ops) { - pool_id = cleancache_ops->init_shared_fs(&sb->s_uuid, PAGE_SIZE); - if (pool_id < 0) - pool_id = CLEANCACHE_NO_POOL; - } - sb->cleancache_poolid = pool_id; -} -EXPORT_SYMBOL(__cleancache_init_shared_fs); - -/* - * If the filesystem uses exportable filehandles, use the filehandle as - * the key, else use the inode number. - */ -static int cleancache_get_key(struct inode *inode, - struct cleancache_filekey *key) -{ - int (*fhfn)(struct inode *, __u32 *fh, int *, struct inode *); - int len = 0, maxlen = CLEANCACHE_KEY_MAX; - struct super_block *sb = inode->i_sb; - - key->u.ino = inode->i_ino; - if (sb->s_export_op != NULL) { - fhfn = sb->s_export_op->encode_fh; - if (fhfn) { - len = (*fhfn)(inode, &key->u.fh[0], &maxlen, NULL); - if (len <= FILEID_ROOT || len == FILEID_INVALID) - return -1; - if (maxlen > CLEANCACHE_KEY_MAX) - return -1; - } - } - return 0; -} - -/* - * "Get" data from cleancache associated with the poolid/inode/index - * that were specified when the data was put to cleanache and, if - * successful, use it to fill the specified page with data and return 0. - * The pageframe is unchanged and returns -1 if the get fails. - * Page must be locked by caller. - * - * The function has two checks before any action is taken - whether - * a backend is registered and whether the sb->cleancache_poolid - * is correct. - */ -int __cleancache_get_page(struct page *page) -{ - int ret = -1; - int pool_id; - struct cleancache_filekey key = { .u.key = { 0 } }; - - if (!cleancache_ops) { - cleancache_failed_gets++; - goto out; - } - - VM_BUG_ON_PAGE(!PageLocked(page), page); - pool_id = page->mapping->host->i_sb->cleancache_poolid; - if (pool_id < 0) - goto out; - - if (cleancache_get_key(page->mapping->host, &key) < 0) - goto out; - - ret = cleancache_ops->get_page(pool_id, key, page->index, page); - if (ret == 0) - cleancache_succ_gets++; - else - cleancache_failed_gets++; -out: - return ret; -} -EXPORT_SYMBOL(__cleancache_get_page); - -/* - * "Put" data from a page to cleancache and associate it with the - * (previously-obtained per-filesystem) poolid and the page's, - * inode and page index. Page must be locked. Note that a put_page - * always "succeeds", though a subsequent get_page may succeed or fail. - * - * The function has two checks before any action is taken - whether - * a backend is registered and whether the sb->cleancache_poolid - * is correct. - */ -void __cleancache_put_page(struct page *page) -{ - int pool_id; - struct cleancache_filekey key = { .u.key = { 0 } }; - - if (!cleancache_ops) { - cleancache_puts++; - return; - } - - VM_BUG_ON_PAGE(!PageLocked(page), page); - pool_id = page->mapping->host->i_sb->cleancache_poolid; - if (pool_id >= 0 && - cleancache_get_key(page->mapping->host, &key) >= 0) { - cleancache_ops->put_page(pool_id, key, page->index, page); - cleancache_puts++; - } -} -EXPORT_SYMBOL(__cleancache_put_page); - -/* - * Invalidate any data from cleancache associated with the poolid and the - * page's inode and page index so that a subsequent "get" will fail. - * - * The function has two checks before any action is taken - whether - * a backend is registered and whether the sb->cleancache_poolid - * is correct. - */ -void __cleancache_invalidate_page(struct address_space *mapping, - struct page *page) -{ - /* careful... page->mapping is NULL sometimes when this is called */ - int pool_id = mapping->host->i_sb->cleancache_poolid; - struct cleancache_filekey key = { .u.key = { 0 } }; - - if (!cleancache_ops) - return; - - if (pool_id >= 0) { - VM_BUG_ON_PAGE(!PageLocked(page), page); - if (cleancache_get_key(mapping->host, &key) >= 0) { - cleancache_ops->invalidate_page(pool_id, - key, page->index); - cleancache_invalidates++; - } - } -} -EXPORT_SYMBOL(__cleancache_invalidate_page); - -/* - * Invalidate all data from cleancache associated with the poolid and the - * mappings's inode so that all subsequent gets to this poolid/inode - * will fail. - * - * The function has two checks before any action is taken - whether - * a backend is registered and whether the sb->cleancache_poolid - * is correct. - */ -void __cleancache_invalidate_inode(struct address_space *mapping) -{ - int pool_id = mapping->host->i_sb->cleancache_poolid; - struct cleancache_filekey key = { .u.key = { 0 } }; - - if (!cleancache_ops) - return; - - if (pool_id >= 0 && cleancache_get_key(mapping->host, &key) >= 0) - cleancache_ops->invalidate_inode(pool_id, key); -} -EXPORT_SYMBOL(__cleancache_invalidate_inode); - -/* - * Called by any cleancache-enabled filesystem at time of unmount; - * note that pool_id is surrendered and may be returned by a subsequent - * cleancache_init_fs or cleancache_init_shared_fs. - */ -void __cleancache_invalidate_fs(struct super_block *sb) -{ - int pool_id; - - pool_id = sb->cleancache_poolid; - sb->cleancache_poolid = CLEANCACHE_NO_POOL; - - if (cleancache_ops && pool_id >= 0) - cleancache_ops->invalidate_fs(pool_id); -} -EXPORT_SYMBOL(__cleancache_invalidate_fs); - -static int __init init_cleancache(void) -{ -#ifdef CONFIG_DEBUG_FS - struct dentry *root = debugfs_create_dir("cleancache", NULL); - - debugfs_create_u64("succ_gets", 0444, root, &cleancache_succ_gets); - debugfs_create_u64("failed_gets", 0444, root, &cleancache_failed_gets); - debugfs_create_u64("puts", 0444, root, &cleancache_puts); - debugfs_create_u64("invalidates", 0444, root, &cleancache_invalidates); -#endif - return 0; -} -module_init(init_cleancache) diff --git a/mm/filemap.c b/mm/filemap.c index 60866ae711e2..b50910ac2c88 100644 --- a/mm/filemap.c +++ b/mm/filemap.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include @@ -151,16 +150,6 @@ static void filemap_unaccount_folio(struct address_space *mapping, { long nr; - /* - * if we're uptodate, flush out into the cleancache, otherwise - * invalidate any existing cleancache entries. We can't leave - * stale data around in the cleancache once our page is gone - */ - if (folio_test_uptodate(folio) && folio_test_mappedtodisk(folio)) - cleancache_put_page(&folio->page); - else - cleancache_invalidate_page(mapping, &folio->page); - VM_BUG_ON_FOLIO(folio_mapped(folio), folio); if (!IS_ENABLED(CONFIG_DEBUG_VM) && unlikely(folio_mapped(folio))) { int mapcount; diff --git a/mm/truncate.c b/mm/truncate.c index 5e243d7269c0..9dbf0b75da5d 100644 --- a/mm/truncate.c +++ b/mm/truncate.c @@ -22,7 +22,6 @@ #include /* grr. try_to_release_page, do_invalidatepage */ #include -#include #include #include "internal.h" @@ -264,7 +263,6 @@ bool truncate_inode_partial_folio(struct folio *folio, loff_t start, loff_t end) */ folio_zero_range(folio, offset, length); - cleancache_invalidate_page(folio->mapping, &folio->page); if (folio_has_private(folio)) do_invalidatepage(&folio->page, offset, length); if (!folio_test_large(folio)) @@ -351,7 +349,7 @@ void truncate_inode_pages_range(struct address_space *mapping, bool same_folio; if (mapping_empty(mapping)) - goto out; + return; /* * 'start' and 'end' always covers the range of pages to be fully @@ -442,9 +440,6 @@ void truncate_inode_pages_range(struct address_space *mapping, folio_batch_release(&fbatch); index++; } - -out: - cleancache_invalidate_inode(mapping); } EXPORT_SYMBOL(truncate_inode_pages_range); @@ -498,10 +493,6 @@ void truncate_inode_pages_final(struct address_space *mapping) xa_unlock_irq(&mapping->i_pages); } - /* - * Cleancache needs notification even if there are no pages or shadow - * entries. - */ truncate_inode_pages(mapping, 0); } EXPORT_SYMBOL(truncate_inode_pages_final); @@ -661,7 +652,7 @@ int invalidate_inode_pages2_range(struct address_space *mapping, int did_range_unmap = 0; if (mapping_empty(mapping)) - goto out; + return 0; folio_batch_init(&fbatch); index = start; @@ -725,8 +716,6 @@ int invalidate_inode_pages2_range(struct address_space *mapping, if (dax_mapping(mapping)) { unmap_mapping_pages(mapping, start, end - start + 1, false); } -out: - cleancache_invalidate_inode(mapping); return ret; } EXPORT_SYMBOL_GPL(invalidate_inode_pages2_range); -- cgit v1.2.3 From 4ed308c445a1e3abac8f6c17928c1cb533867e38 Mon Sep 17 00:00:00 2001 From: "Steven Rostedt (Google)" Date: Tue, 25 Jan 2022 09:19:10 -0500 Subject: ftrace: Have architectures opt-in for mcount build time sorting First S390 complained that the sorting of the mcount sections at build time caused the kernel to crash on their architecture. Now PowerPC is complaining about it too. And also ARM64 appears to be having issues. It may be necessary to also update the relocation table for the values in the mcount table. Not only do we have to sort the table, but also update the relocations that may be applied to the items in the table. If the system is not relocatable, then it is fine to sort, but if it is, some architectures may have issues (although x86 does not as it shifts all addresses the same). Add a HAVE_BUILDTIME_MCOUNT_SORT that an architecture can set to say it is safe to do the sorting at build time. Also update the config to compile in build time sorting in the sorttable code in scripts/ to depend on CONFIG_BUILDTIME_MCOUNT_SORT. Link: https://lore.kernel.org/all/944D10DA-8200-4BA9-8D0A-3BED9AA99F82@linux.ibm.com/ Link: https://lkml.kernel.org/r/20220127153821.3bc1ac6e@gandalf.local.home Cc: Ingo Molnar Cc: Andrew Morton Cc: Russell King Cc: Yinan Liu Cc: Ard Biesheuvel Cc: Kees Cook Reported-by: Sachin Sant Reviewed-by: Mark Rutland Tested-by: Mark Rutland [arm64] Tested-by: Sachin Sant Fixes: 72b3942a173c ("scripts: ftrace - move the sort-processing in ftrace_init") Signed-off-by: Steven Rostedt (Google) --- arch/arm/Kconfig | 1 + arch/x86/Kconfig | 1 + kernel/trace/Kconfig | 8 +++++++- scripts/Makefile | 2 +- 4 files changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fabe39169b12..4c97cb40eebb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -83,6 +83,7 @@ config ARM select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 select HAVE_CONTEXT_TRACKING select HAVE_C_RECORDMCOUNT + select HAVE_BUILDTIME_MCOUNT_SORT select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL select HAVE_DMA_CONTIGUOUS if MMU select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index ebe8fc76949a..9f5bd41bf660 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -186,6 +186,7 @@ config X86 select HAVE_CONTEXT_TRACKING_OFFSTACK if HAVE_CONTEXT_TRACKING select HAVE_C_RECORDMCOUNT select HAVE_OBJTOOL_MCOUNT if STACK_VALIDATION + select HAVE_BUILDTIME_MCOUNT_SORT select HAVE_DEBUG_KMEMLEAK select HAVE_DMA_CONTIGUOUS select HAVE_DYNAMIC_FTRACE diff --git a/kernel/trace/Kconfig b/kernel/trace/Kconfig index 752ed89a293b..a5eb5e7fd624 100644 --- a/kernel/trace/Kconfig +++ b/kernel/trace/Kconfig @@ -70,10 +70,16 @@ config HAVE_C_RECORDMCOUNT help C version of recordmcount available? +config HAVE_BUILDTIME_MCOUNT_SORT + bool + help + An architecture selects this if it sorts the mcount_loc section + at build time. + config BUILDTIME_MCOUNT_SORT bool default y - depends on BUILDTIME_TABLE_SORT && !S390 + depends on HAVE_BUILDTIME_MCOUNT_SORT && DYNAMIC_FTRACE help Sort the mcount_loc section at build time. diff --git a/scripts/Makefile b/scripts/Makefile index ecd3acacd0ec..ce5aa9030b74 100644 --- a/scripts/Makefile +++ b/scripts/Makefile @@ -25,7 +25,7 @@ HOSTCFLAGS_sorttable.o += -I$(srctree)/tools/arch/x86/include HOSTCFLAGS_sorttable.o += -DUNWINDER_ORC_ENABLED endif -ifdef CONFIG_DYNAMIC_FTRACE +ifdef CONFIG_BUILDTIME_MCOUNT_SORT HOSTCFLAGS_sorttable.o += -DMCOUNT_SORT_ENABLED endif -- cgit v1.2.3