From dfedd2ac4725317735bae5f8085d2d4c301959e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 20 Sep 2020 21:57:48 +0200 Subject: arm64: dts: imx8mq-librem5: align GPIO hog names with dtschema dtschema expects GPIO hogs to end with 'hog' suffix. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index e3c6d1272198..64fc546b110f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -250,7 +250,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic_5v>; - pmic-5v { + pmic-5v-hog { gpio-hog; gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; input; -- cgit v1.2.3 From e8c471588890f9939b23d628e65b7dcb3a856f7a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 2 Oct 2020 18:39:45 +0200 Subject: arm64: dts: renesas: Align GPIO hog names with dtschema The convention for node names is to use hyphens, not underscores. dtschema for pca95xx expects GPIO hogs to end with 'hog' suffix. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201002163945.7885-1-krzk@kernel.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts | 2 +- arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts | 2 +- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 14 +++++++------- 3 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts index cef9da4376a3..e5922329a4b8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts @@ -118,7 +118,7 @@ }; &pca9654 { - pcie_sata_switch { + pcie-sata-switch-hog { gpio-hog; gpios = <7 GPIO_ACTIVE_HIGH>; output-low; /* enable SATA by default */ diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts index 5cef64605464..d7e621101af7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts @@ -55,7 +55,7 @@ }; &pca9654 { - pcie_sata_switch { + pcie-sata-switch-hog { gpio-hog; gpios = <7 GPIO_ACTIVE_HIGH>; output-low; /* enable SATA by default */ diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 202177706cde..e9ed2597f1c2 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -143,49 +143,49 @@ interrupt-parent = <&gpio6>; interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - audio_out_off { + audio-out-off-hog { gpio-hog; gpios = <0 GPIO_ACTIVE_HIGH>; /* P00 */ output-high; line-name = "Audio_Out_OFF"; }; - hub_pwen { + hub-pwen-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; output-high; line-name = "HUB pwen"; }; - hub_rst { + hub-rst-hog { gpio-hog; gpios = <7 GPIO_ACTIVE_HIGH>; output-high; line-name = "HUB rst"; }; - otg_extlpn { + otg-extlpn-hog { gpio-hog; gpios = <9 GPIO_ACTIVE_HIGH>; output-high; line-name = "OTG EXTLPn"; }; - otg_offvbusn { + otg-offvbusn-hog { gpio-hog; gpios = <8 GPIO_ACTIVE_HIGH>; output-low; line-name = "OTG OFFVBUSn"; }; - sd-wifi-mux { + sd-wifi-mux-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; output-low; /* Connect WL1837 */ line-name = "SD WiFi mux"; }; - snd_rst { + snd-rst-hog { gpio-hog; gpios = <15 GPIO_ACTIVE_HIGH>; /* P17 */ output-high; -- cgit v1.2.3 From ca3b4330a5437d877e9b0093ba8b746e73695fb0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 5 Oct 2020 13:29:51 +0200 Subject: arm64: dts: renesas: r8a77961: Add MSIOF nodes Add the device nodes for all Clock-Synchronized Serial Interface with FIFO (MSIOF) instances on R-Car M3-W+. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201005112951.22532-1-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 62 +++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 1ba30313c8b8..b0c4b8150d37 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1187,6 +1187,68 @@ status = "disabled"; }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a77961", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a77961", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a77961", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a77961", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + vin0: video@e6ef0000 { reg = <0 0xe6ef0000 0 0x1000>; /* placeholder */ -- cgit v1.2.3 From 67d3dcf12a3d245b6fd6ca5672893f7ae4e137ed Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 15 Oct 2020 14:23:49 +0100 Subject: arm64: dts: renesas: hihope-rzg2-ex: Drop rxc-skew-ps from ethernet-phy node HiHope RZG2[HMN] boards uses Realtek phy and the driver does not support rxc-skew-ps property. So remove rxc-skew-ps from ethernet-phy node. Fixes: 7433f1fb8ec8fe ("arm64: dts: renesas: Add HiHope RZ/G2M sub board support") Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20201015132350.8360-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi index 178401a34cbf..b9e46aed5336 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi @@ -23,7 +23,6 @@ status = "okay"; phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio2>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -- cgit v1.2.3 From 53e573dc39fba1834f3e4fa002cb754b61a30701 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 15 Oct 2020 14:23:50 +0100 Subject: arm64: dts: renesas: cat875: Remove rxc-skew-ps from ethernet-phy node The CAT875 sub board from Silicon Linux uses Realtek phy and the driver does not support rxc-skew-ps property. Fixes: 6b170cd3ed02949f ("arm64: dts: renesas: cat875: Add ethernet support") Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20201015132350.8360-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/cat875.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi index 33daa9570684..801ea54b027c 100644 --- a/arch/arm64/boot/dts/renesas/cat875.dtsi +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi @@ -21,7 +21,6 @@ status = "okay"; phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio2>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -- cgit v1.2.3 From 622007d172fbb1d7556329bafd72dc28c0baf1b8 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 20 Oct 2020 13:51:31 +0100 Subject: arm64: dts: renesas: aistarvision-mipi-adapter-2.1: Add parent macro for each sensor For HiHope RZ/G2H the OV5645 sensor is populated on i2c2 whereas the imx219 sensor is populated on i2c3 so add support for handling such cases by adding a parent macro for each sensor. Also update r8a774c0-ek874-mipi-2.1.dts to incorporate the changes. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201020125134.22625-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi | 4 +++- arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi b/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi index dac6ff49020f..7ce986f0a06f 100644 --- a/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi +++ b/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi @@ -61,7 +61,7 @@ }; }; -&MIPI_PARENT_I2C { +&MIPI_OV5645_PARENT_I2C { ov5645: ov5645@3c { compatible = "ovti,ov5645"; reg = <0x3c>; @@ -77,7 +77,9 @@ }; }; }; +}; +&MIPI_IMX219_PARENT_I2C { imx219: imx219@10 { compatible = "sony,imx219"; reg = <0x10>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts index f0829e905506..e7b4a929bb17 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts @@ -8,7 +8,8 @@ /dts-v1/; #include "r8a774c0-ek874.dts" -#define MIPI_PARENT_I2C i2c3 +#define MIPI_OV5645_PARENT_I2C i2c3 +#define MIPI_IMX219_PARENT_I2C i2c3 #include "aistarvision-mipi-adapter-2.1.dtsi" / { -- cgit v1.2.3 From 05e6ae33cf9834dd2f0ff35001828ca09fe5af26 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 20 Oct 2020 13:51:32 +0100 Subject: arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2H MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for AISTARVISION MIPI Adapter V2.1 board connected to HiHope RZ/G2H board. Common file hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi is created which will be used by RZ/G2{HMN}, by default the CSI20 node is tied to ov5645 camera endpoint and the imx219 camera endpoint is tied to CSI40. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Acked-by: Niklas Söderlund Link: https://lore.kernel.org/r/20201020125134.22625-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + ...hope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi | 109 +++++++++++++++++++++ .../renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts | 16 +++ 3 files changed, 126 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index dffefe030a76..f98e9e2e520d 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb +dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi new file mode 100644 index 000000000000..c62ddb9b2ba5 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2[HMN] MIPI common parts + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#define MIPI_OV5645_PARENT_I2C i2c2 +#define MIPI_IMX219_PARENT_I2C i2c3 +#include "aistarvision-mipi-adapter-2.1.dtsi" + +&csi20 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + csi20_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&ov5645_ep>; + }; + }; + }; +}; + +&csi40 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&imx219_ep>; + }; + }; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&imx219 { + port { + imx219_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + remote-endpoint = <&csi40_in>; + }; + }; +}; + +&ov5645 { + enable-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; + + port { + ov5645_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi20_in>; + }; + }; +}; + +&pfc { + i2c3_pins: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; +}; + +&vin0 { + status = "okay"; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; + +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&vin6 { + status = "okay"; +}; + +&vin7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts new file mode 100644 index 000000000000..46adb6efb5e6 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2H board + * connected with aistarvision-mipi-v2-adapter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774e1-hihope-rzg2h-ex.dts" +#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2H with sub board connected with aistarvision-mipi-v2-adapter board"; + compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1"; +}; -- cgit v1.2.3 From 661495164934e15bc8a192f8eafa1ec9655e74f0 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 20 Oct 2020 13:51:33 +0100 Subject: arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2M Add support for AISTARVISION MIPI Adapter V2.1 board connected to HiHope RZ/G2M board. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201020125134.22625-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts | 29 ++++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index f98e9e2e520d..ca095c7e8ee1 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-beacon-rzg2m-kit.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb +dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts new file mode 100644 index 000000000000..5c91e0d7e67b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2M board + * connected with aistarvision-mipi-v2-adapter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774a1-hihope-rzg2m-ex.dts" +#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2M with sub board connected with aistarvision-mipi-v2-adapter board"; + compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; +}; + +/* + * On RZ/G2M SoC LSI V1.3 CSI40 supports only 4 lane mode. + * HiHope RZ/G2M Rev.4.0 board is based on LSI V1.3 so disable csi40 and + * imx219 as the imx219 endpoint driver supports only 2 lane mode. + */ +&csi40 { + status = "disabled"; +}; + +&imx219 { + status = "disabled"; +}; -- cgit v1.2.3 From bdf0c8ea8c63d9e288ff06fc300e2eb8bd332d1c Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 20 Oct 2020 13:51:34 +0100 Subject: arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2N Add support for AISTARVISION MIPI Adapter V2.1 board connected to HiHope RZ/G2N board. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201020125134.22625-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index ca095c7e8ee1..2b043b59c669 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb +dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts new file mode 100644 index 000000000000..ce8e3bcc7dc9 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2N board + * connected with aistarvision-mipi-v2-adapter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774b1-hihope-rzg2n-ex.dts" +#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2N with sub board connected with aistarvision-mipi-v2-adapter board"; + compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1"; +}; -- cgit v1.2.3 From f74cdb1c4e9b25e3e06f8d354371d53b97ae8482 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 26 Aug 2020 11:02:17 +0200 Subject: arm64: dts: mt8173-elm: Remove ddc property from panel The elm and hana devices uses an Embedded DisplayPort (eDP) as interface for its panel, so the DDC channel specified in the binding is useless. Signed-off-by: Enric Balletbo i Serra Tested-by: Bilal Wasim Link: https://lore.kernel.org/r/20200826090218.682931-1-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 44a0346133cd..21452c51a20a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -87,7 +87,6 @@ panel: panel { compatible = "lg,lp120up1"; power-supply = <&panel_fixed_3v3>; - ddc-i2c-bus = <&i2c0>; backlight = <&backlight>; port { -- cgit v1.2.3 From 4c7a6260775d596bb4ded0c0e2b3d317e0b37014 Mon Sep 17 00:00:00 2001 From: Hanks Chen Date: Thu, 30 Jul 2020 21:30:15 +0800 Subject: arm64: dts: add dts nodes for MT6779 this adds initial MT6779 dts settings for board support, including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc. Signed-off-by: Hanks Chen Link: https://lore.kernel.org/r/1596115816-11758-3-git-send-email-hanks.chen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 ++++ arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 ++++++++++++++++++++++++++++ 3 files changed, 303 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 3ee682c266cc..66eeba60acac 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts new file mode 100644 index 000000000000..164f5cbb3821 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Mars.C + * + */ + +/dts-v1/; +#include "mt6779.dtsi" + +/ { + model = "MediaTek MT6779 EVB"; + compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi new file mode 100644 index 000000000000..370f309d32de --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Mars.C + * + */ + +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt6779"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x200>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x300>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x400>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x500>; + }; + + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + reg = <0x600>; + }; + + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + reg = <0x700>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@0c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c040000 0 0x200000>; /* GICR */ + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 \ + &cpu2 &cpu3 &cpu4 &cpu5>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; + + }; + + sysirq: intpol-controller@0c53a650 { + compatible = "mediatek,mt6779-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x0c53a650 0 0x50>; + }; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt6779-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: clock-controller@10001000 { + compatible = "mediatek,mt6779-infracfg_ao", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6779-pinctrl", "syscon"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", + "iocfg_lt", "iocfg_tl", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 210>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + apmixed: clock-controller@1000c000 { + compatible = "mediatek,mt6779-apmixed", "syscon"; + reg = <0 0x1000c000 0 0xe00>; + #clock-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + audio: clock-controller@11210000 { + compatible = "mediatek,mt6779-audio", "syscon"; + reg = <0 0x11210000 0 0x1000>; + #clock-cells = <1>; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible = "mediatek,mt6779-mfgcfg", "syscon"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt6779-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: clock-controller@15020000 { + compatible = "mediatek,mt6779-imgsys", "syscon"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt6779-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@17000000 { + compatible = "mediatek,mt6779-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: clock-controller@1a000000 { + compatible = "mediatek,mt6779-camsys", "syscon"; + reg = <0 0x1a000000 0 0x10000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@1b000000 { + compatible = "mediatek,mt6779-ipesys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + }; +}; -- cgit v1.2.3 From e55c56df43dd11de4a6c08e3ea52ca45b51c8800 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Sun, 18 Oct 2020 21:42:25 +0200 Subject: arm64: dts: mediatek: mt8183: fix gce incorrect mbox-cells value The binding documentation says: - #mbox-cells: Should be 2. <&phandle channel priority> phandle: Label name of a gce node. channel: Channel of mailbox. Be equal to the thread id of GCE. priority: Priority of GCE thread. Fix the value of #mbox-cells. Fixes: d3c306e31bc7 ("arm64: dts: add gce node for mt8183") Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201018194225.3361182-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 9cfd961c45eb..08a914d3a643 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -363,7 +363,7 @@ compatible = "mediatek,mt8183-gce"; reg = <0 0x10238000 0 0x4000>; interrupts = ; - #mbox-cells = <3>; + #mbox-cells = <2>; clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; }; -- cgit v1.2.3 From 204b9cd58f4c27c1b43bfbeab4ad418504a3ae6b Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 12 Oct 2020 22:52:18 +0200 Subject: arm64: dts: mediatek: mt8516: add auxadc node Add node for the auxadc IP. The IP is compatible with the one found in MT8173 SoC. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201012205218.3010868-2-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 89af661e7f63..943c426e9aaf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -470,5 +470,15 @@ #phy-cells = <1>; }; }; + + auxadc: adc@11003000 { + compatible = "mediatek,mt8516-auxadc", + "mediatek,mt8173-auxadc"; + reg = <0 0x11003000 0 0x1000>; + clocks = <&topckgen CLK_TOP_AUX_ADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; }; }; -- cgit v1.2.3 From 5fae271026990f684da7e364ec5abc9df1d0563d Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 14 Oct 2020 18:24:03 +0200 Subject: arm64: dts: mediatek: mt8516: rename usb phy The USB phy node is named usb0_phy but there is only one phy with 2 ports on MT8516. Rename the phy to make it more obvious it can also support the usb1 node. The usb1 node will be added in a follow-up commit. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201014162404.1312544-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 2 +- arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 943c426e9aaf..50049b6c1ba7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -455,7 +455,7 @@ status = "disabled"; }; - usb0_phy: usb@11110000 { + usb_phy: usb@11110000 { compatible = "mediatek,generic-tphy-v1"; reg = <0 0x11110000 0 0x800>; #address-cells = <2>; diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index 29d8cf6df46b..3e5a8dfda0c0 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -195,7 +195,7 @@ }; }; -&usb0_phy { +&usb_phy { status = "okay"; }; -- cgit v1.2.3 From 40fe44cab01cb93e124db5d9a9cc290e1ac3f14e Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 14 Oct 2020 18:24:04 +0200 Subject: arm64: dts: mediatek: mt8516: add usb1 node The MT8516 has 2 USB instances. Add support for the second USB instance. usb1 can only work in host mode. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201014162404.1312544-2-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 50049b6c1ba7..eca7969e15ab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -455,6 +455,20 @@ status = "disabled"; }; + usb1: usb@11190000 { + compatible = "mediatek,mtk-musb"; + reg = <0 0x11190000 0 0x1000>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usb1_port PHY_TYPE_USB2>; + clocks = <&topckgen CLK_TOP_USB>, + <&topckgen CLK_TOP_USBIF>, + <&topckgen CLK_TOP_USB_1P>; + clock-names = "main","mcu","univpll"; + dr_mode = "host"; + status = "disabled"; + }; + usb_phy: usb@11110000 { compatible = "mediatek,generic-tphy-v1"; reg = <0 0x11110000 0 0x800>; @@ -469,6 +483,13 @@ clock-names = "ref"; #phy-cells = <1>; }; + + usb1_port: usb-phy@11110900 { + reg = <0 0x11110900 0 0x100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + }; }; auxadc: adc@11003000 { -- cgit v1.2.3 From 2612afd9b97964b67040e7883148ee7251a42776 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:54 +0300 Subject: arm64: dts: allwinner: h6: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Signed-off-by: Maxime Ripard Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201020115959.2658-25-Sergey.Semin@baikalelectronics.ru --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 28c77d6872f6..28c4a79b8a45 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -680,7 +680,7 @@ status = "disabled"; }; - dwc3: dwc3@5200000 { + dwc3: usb@5200000 { compatible = "snps,dwc3"; reg = <0x05200000 0x10000>; interrupts = ; -- cgit v1.2.3 From 9dcd17be61e4b6343cc612a3f6c30512acee60b9 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Sat, 29 Aug 2020 21:41:39 +0300 Subject: arm64: dts: ti: k3-am65: ringacc: drop ti, dma-ring-reset-quirk Remove obsolete "ti,dma-ring-reset-quirk" Ringacc DT property. Signed-off-by: Grygorii Strashko Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20200829184139.15547-4-grygorii.strashko@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 1 - 2 files changed, 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 533525229a8d..3eeb6e9876db 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -612,7 +612,6 @@ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <818>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,dma-ring-reset-quirk; ti,sci = <&dmsc>; ti,sci-dev-id = <187>; msi-parent = <&inta_main_udmass>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 29aaf8dca6f6..044042b166d9 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -135,7 +135,6 @@ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,dma-ring-reset-quirk; ti,sci = <&dmsc>; ti,sci-dev-id = <195>; msi-parent = <&inta_main_udmass>; -- cgit v1.2.3 From 4af5c6dc255ca64e5263a5254bb7553f05bb682c Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Wed, 14 Oct 2020 21:16:17 +0530 Subject: arm64: dts: ipq6018: update the reserved-memory node Memory region reserved for the TZ is changed long back. Let's update the same to align with the corret region. Its size also increased to 4MB from 2MB. Along with that, bump the Q6 region size to 85MB. Fixes: 1e8277854b49 ("arm64: dts: Add ipq6018 SoC and CP01 board support") Signed-off-by: Kathiravan T Link: https://lore.kernel.org/r/1602690377-21304-1-git-send-email-kathirav@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index a94dac76bf3f..973b2c860ec9 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -156,8 +156,8 @@ no-map; }; - tz: tz@48500000 { - reg = <0x0 0x48500000 0x0 0x00200000>; + tz: memory@4a600000 { + reg = <0x0 0x4a600000 0x0 0x00400000>; no-map; }; @@ -167,7 +167,7 @@ }; q6_region: memory@4ab00000 { - reg = <0x0 0x4ab00000 0x0 0x02800000>; + reg = <0x0 0x4ab00000 0x0 0x05500000>; no-map; }; }; -- cgit v1.2.3 From 228813aaa71113d7a12313b87c4905a9d3f9df37 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 1 Oct 2020 14:18:55 -0700 Subject: arm64: dts: qcom: sc7180: Fix one forgotten interconnect reference In commit e23b1220a246 ("arm64: dts: qcom: sc7180: Increase the number of interconnect cells") we missed increasing the cells on one interconnect. That's no bueno. Fix it. NOTE: it appears that things aren't totally broken without this fix, but clearly something isn't going to be working right. If nothing else, without this fix I see this in the logs: OF: /soc@0/mdss@ae00000: could not get #interconnect-cells for /soc@0/interrupt-controller@17a00000 Fixes: e23b1220a246 ("arm64: dts: qcom: sc7180: Increase the number of interconnect cells") Reviewed-by: Georgi Djakov Reviewed-by: Rob Clark Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20201001141838.1.I08054d1d976eed64ffa1b0e21d568e0dc6040b54@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 6678f1e8e395..a02776ce77a1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2811,7 +2811,7 @@ interrupt-controller; #interrupt-cells = <1>; - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "mdp0-mem"; iommus = <&apps_smmu 0x800 0x2>; -- cgit v1.2.3 From 2709436ecf38d12b70c7bf4eed4ff65ba5f41f04 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 16 Sep 2020 12:41:29 +0200 Subject: arm64: dts: qcom: msm8916: Add RPM power domains MSM8916 has two RPM power domains: VDDCX and VDDMX. So far we have been managing them by voting for raw voltages through the regulator subsystem, but it's better to manage them with corners as actual power domains. Add the device tree node for rpmpd so we can manage them as real power domains instead of using the regulators. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200916104135.25085-5-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index aaa21899f1a6..117804f94c35 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -289,6 +289,35 @@ compatible = "qcom,rpmcc-msm8916"; #clock-cells = <1>; }; + + rpmpd: power-controller { + compatible = "qcom,msm8916-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; }; }; }; -- cgit v1.2.3 From 809f299a969873581c832bbcb1b8cccaf8af2eeb Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 16 Sep 2020 12:41:34 +0200 Subject: arm64: dts: qcom: msm8916: Use power domains for MSS/WCNSS remoteprocs So far we have been making proxy votes for the remote processors through the regulator interface. Now that we have rpmpd it's better to vote for performance states through the power domain interface. This also allows us to move these supplies back to msm8916.dtsi because the device tree binding for RPMPD is independent of the underlying regulator/PMIC. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200916104135.25085-10-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 3 --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 +++++++++ 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index cd626e7db599..513e433aa5f3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -17,13 +17,10 @@ }; &mpss { - cx-supply = <&pm8916_s1>; - mx-supply = <&pm8916_l3>; pll-supply = <&pm8916_l7>; }; &pronto { - vddmx-supply = <&pm8916_l3>; vddpx-supply = <&pm8916_l7>; iris { diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 117804f94c35..74aa50f3db10 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -1292,6 +1293,10 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + power-domains = <&rpmpd MSM8916_VDDCX>, + <&rpmpd MSM8916_VDDMX>; + power-domain-names = "cx", "mx"; + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, <&gcc GCC_BOOT_ROM_AHB_CLK>, @@ -1689,6 +1694,10 @@ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + power-domains = <&rpmpd MSM8916_VDDCX>, + <&rpmpd MSM8916_VDDMX>; + power-domain-names = "cx", "mx"; + qcom,state = <&wcnss_smp2p_out 0>; qcom,state-names = "stop"; -- cgit v1.2.3 From bd1f64bb57f7b6a6f2e8fa9a7b37be55fbc06f73 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 16 Sep 2020 12:41:35 +0200 Subject: arm64: dts: qcom: msm8916-pm8916: Stop using s1/l3 as regulators s1 (VDDCX) and l3 (VDDMX) are now managed by rpmpd as power domains. This allows us to vote for voltage corners instead of voting for raw voltages. But we cannot manage these as regulator and power domain at the same time: The votes by rpmpd would conflict with the ones from the regulator driver. All users of these regulators have been converted to power domains. Make sure that no new users are added by removing s1 and l3 from the regulator definitions. This also allows us to remove the arbitrary voltage constraints we have been using for these regulators. Not all of the voltages listed there would actually have been safe for the boards. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200916104135.25085-11-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 10 ---------- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 10 ---------- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 10 ---------- 4 files changed, 2 insertions(+), 32 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 3c7f97539390..3a9538e1ec97 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -417,11 +417,6 @@ vdd_l4_l5_l6-supply = <&pm8916_s4>; vdd_l7-supply = <&pm8916_s4>; - s1 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1562000>; - }; - s3 { regulator-min-microvolt = <375000>; regulator-max-microvolt = <1562000>; @@ -445,11 +440,6 @@ regulator-max-microvolt = <1200000>; }; - l3 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1525000>; - }; - l4 { regulator-min-microvolt = <1750000>; regulator-max-microvolt = <3337000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index b9d3c5d98dd0..2c204d535d66 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -98,11 +98,6 @@ vdd_l4_l5_l6-supply = <&pm8916_s4>; vdd_l7-supply = <&pm8916_s4>; - s1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1300000>; - }; - s3 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1300000>; @@ -123,11 +118,6 @@ regulator-max-microvolt = <1200000>; }; - l3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1287500>; - }; - l4 { regulator-min-microvolt = <2050000>; regulator-max-microvolt = <2050000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index 513e433aa5f3..539823b2c36e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -50,13 +50,13 @@ smd_rpm_regulators: pm8916-regulators { compatible = "qcom,rpm-pm8916-regulators"; - pm8916_s1: s1 {}; + /* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */ pm8916_s3: s3 {}; pm8916_s4: s4 {}; pm8916_l1: l1 {}; pm8916_l2: l2 {}; - pm8916_l3: l3 {}; + /* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */ pm8916_l4: l4 {}; pm8916_l5: l5 {}; pm8916_l6: l6 {}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index b18d21e42f59..0b0dfd3059de 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -164,11 +164,6 @@ vdd_l4_l5_l6-supply = <&pm8916_s4>; vdd_l7-supply = <&pm8916_s4>; - s1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1300000>; - }; - s3 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1300000>; @@ -189,11 +184,6 @@ regulator-max-microvolt = <1200000>; }; - l3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1287500>; - }; - l4 { regulator-min-microvolt = <2050000>; regulator-max-microvolt = <2050000>; -- cgit v1.2.3 From e8ea5764bdb144847a44de6113dba8d1ab19179e Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:56 +0300 Subject: arm64: dts: exynos: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Link: https://lore.kernel.org/r/20201020115959.2658-27-Sergey.Semin@baikalelectronics.ru Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++-- arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 8eb4576da8f3..0a886bb6c806 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1647,7 +1647,7 @@ ranges; status = "disabled"; - usbdrd_dwc3: dwc3@15400000 { + usbdrd_dwc3: usb@15400000 { compatible = "snps,dwc3"; clocks = <&cmu_fsys CLK_SCLK_USBDRD30>, <&cmu_fsys CLK_ACLK_USBDRD30>, @@ -1700,7 +1700,7 @@ ranges; status = "disabled"; - usbhost_dwc3: dwc3@15a00000 { + usbhost_dwc3: usb@15a00000 { compatible = "snps,dwc3"; clocks = <&cmu_fsys CLK_SCLK_USBHOST30>, <&cmu_fsys CLK_ACLK_USBHOST30>, diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index b9ed6a33e290..48cd3a04fd07 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -654,7 +654,7 @@ #size-cells = <1>; ranges; - dwc3@15400000 { + usb@15400000 { compatible = "snps,dwc3"; reg = <0x15400000 0x10000>; interrupts = ; -- cgit v1.2.3 From 37dd4b7779424cc7e26791c24e9918c52e01e1ee Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 21 Sep 2020 14:27:16 -0700 Subject: arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS When the chip select line is controlled by the QUP, changing CS is a time consuming operation. We have to send a command over to the geni and wait for it to Ack us every time we want to change (both making it high and low). To send this command we have to make a choice in software when we want to control the chip select, we have to either: A) Wait for the Ack via interrupt which slows down all SPI transfers (and incurrs extra processing associated with interrupts). B) Sit in a loop and poll, waiting for the Ack. Neither A) nor B) is a great option. We can avoid all of this by realizing that, at least on some boards, there is no advantage of considering this line to be a geni line. While it's true that geni _can_ control the line, it's also true that the line can be a GPIO and there is no downside of viewing it that way. Setting a GPIO is a simple MMIO operation. This patch provides definitions so a board can easily select the GPIO mode. NOTE: apparently, it's possible to run the geni in "GSI" mode. In GSI the SPI port is allowed to be controlled by more than one user (like firmware and Linux) and also the port can operate sequences of operations in one go. In GSI mode it _would_ be invalid to look at the chip select as a GPIO because that would prevent other users from using it. In theory GSI mode would also avoid some overhead by allowing us to sequence the chip select better. However, I'll argue GSI is not relevant for all boards (and certainly not any boards supported by mainline today). Why? - Apparently to run a SPI chip in GSI mode you need to initialize it (in the bootloader) with a different firmware and then it will always run in GSI mode. Since there is no support for GSI mode in the current Linux driver, it must be that existing boards don't have firmware that's doing that. Note that the kernel device tree describes hardware but also firmware, so it is legitimate to make the assumption that we don't have GSI firmware in a given dts file. - Some boards with sc7180 have SPI connected to the Chrome OS EC or security chip (Cr50). The protocols for talking to cros_ec and cr50 are extremely complex. Both drivers in Linux fully lock the bus across several distinct SPI transfers. While I am not an expert on GSI mode it feels highly unlikely to me that we'd ever be able to enable GSI mode for these devices. From a testing perspective, running "flashrom -p ec -r /tmp/foo.bin" in a loop after this patch shows almost no reduction in time, but the number of interrupts per command goes from 32357 down to 30611 (about a 5% reduction). Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Akash Asthana Link: https://lore.kernel.org/r/20200921142655.v3.1.I997a428f58ef9d48b37a27a028360f34e66c00ec@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 104 +++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a02776ce77a1..6fcffd588a7d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1595,6 +1595,19 @@ }; }; + qup_spi0_cs_gpio: qup-spi0-cs-gpio { + pinmux { + pins = "gpio34", "gpio35", + "gpio36"; + function = "qup00"; + }; + + pinmux-cs { + pins = "gpio37"; + function = "gpio"; + }; + }; + qup_spi1_default: qup-spi1-default { pinmux { pins = "gpio0", "gpio1", @@ -1603,6 +1616,19 @@ }; }; + qup_spi1_cs_gpio: qup-spi1-cs-gpio { + pinmux { + pins = "gpio0", "gpio1", + "gpio2"; + function = "qup01"; + }; + + pinmux-cs { + pins = "gpio3"; + function = "gpio"; + }; + }; + qup_spi3_default: qup-spi3-default { pinmux { pins = "gpio38", "gpio39", @@ -1611,6 +1637,19 @@ }; }; + qup_spi3_cs_gpio: qup-spi3-cs-gpio { + pinmux { + pins = "gpio38", "gpio39", + "gpio40"; + function = "qup03"; + }; + + pinmux-cs { + pins = "gpio41"; + function = "gpio"; + }; + }; + qup_spi5_default: qup-spi5-default { pinmux { pins = "gpio25", "gpio26", @@ -1619,6 +1658,19 @@ }; }; + qup_spi5_cs_gpio: qup-spi5-cs-gpio { + pinmux { + pins = "gpio25", "gpio26", + "gpio27"; + function = "qup05"; + }; + + pinmux-cs { + pins = "gpio28"; + function = "gpio"; + }; + }; + qup_spi6_default: qup-spi6-default { pinmux { pins = "gpio59", "gpio60", @@ -1627,6 +1679,19 @@ }; }; + qup_spi6_cs_gpio: qup-spi6-cs-gpio { + pinmux { + pins = "gpio59", "gpio60", + "gpio61"; + function = "qup10"; + }; + + pinmux-cs { + pins = "gpio62"; + function = "gpio"; + }; + }; + qup_spi8_default: qup-spi8-default { pinmux { pins = "gpio42", "gpio43", @@ -1635,6 +1700,19 @@ }; }; + qup_spi8_cs_gpio: qup-spi8-cs-gpio { + pinmux { + pins = "gpio42", "gpio43", + "gpio44"; + function = "qup12"; + }; + + pinmux-cs { + pins = "gpio45"; + function = "gpio"; + }; + }; + qup_spi10_default: qup-spi10-default { pinmux { pins = "gpio86", "gpio87", @@ -1643,6 +1721,19 @@ }; }; + qup_spi10_cs_gpio: qup-spi10-cs-gpio { + pinmux { + pins = "gpio86", "gpio87", + "gpio88"; + function = "qup14"; + }; + + pinmux-cs { + pins = "gpio89"; + function = "gpio"; + }; + }; + qup_spi11_default: qup-spi11-default { pinmux { pins = "gpio53", "gpio54", @@ -1651,6 +1742,19 @@ }; }; + qup_spi11_cs_gpio: qup-spi11-cs-gpio { + pinmux { + pins = "gpio53", "gpio54", + "gpio55"; + function = "qup15"; + }; + + pinmux-cs { + pins = "gpio56"; + function = "gpio"; + }; + }; + qup_uart0_default: qup-uart0-default { pinmux { pins = "gpio34", "gpio35", -- cgit v1.2.3 From cfbb97fde6941f3ecf19fb303648d4e09be28f42 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 21 Sep 2020 14:27:17 -0700 Subject: arm64: dts: qcom: Switch sc7180-trogdor to control SPI CS via GPIO As talked about in the patch ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS"), on some boards it makes much more sense (and is much more efficient) to think of the SPI Chip Select as a GPIO. Trogdor is one such board where the SPI parts don't run in GSI mode and we do a lot of SPI traffic. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Akash Asthana Link: https://lore.kernel.org/r/20200921142655.v3.2.I3c57d8b6d83d5bdad73a413eea1e249a98d11973@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index bf875589d364..0759896a0df5 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -776,7 +776,20 @@ hp_i2c: &i2c9 { cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; }; +&spi0 { + pinctrl-0 = <&qup_spi0_cs_gpio>; + cs-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; +}; + +&spi6 { + pinctrl-0 = <&qup_spi6_cs_gpio>; + cs-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; +}; + ap_spi_fp: &spi10 { + pinctrl-0 = <&qup_spi10_cs_gpio>; + cs-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + cros_ec_fp: ec@0 { compatible = "google,cros-ec-spi"; reg = <0>; @@ -937,7 +950,7 @@ ap_spi_fp: &spi10 { }; }; -&qup_spi0_default { +&qup_spi0_cs_gpio { pinconf { pins = "gpio34", "gpio35", "gpio36", "gpio37"; drive-strength = <2>; @@ -945,7 +958,7 @@ ap_spi_fp: &spi10 { }; }; -&qup_spi6_default { +&qup_spi6_cs_gpio { pinconf { pins = "gpio59", "gpio60", "gpio61", "gpio62"; drive-strength = <2>; @@ -953,7 +966,7 @@ ap_spi_fp: &spi10 { }; }; -&qup_spi10_default { +&qup_spi10_cs_gpio { pinconf { pins = "gpio86", "gpio87", "gpio88", "gpio89"; drive-strength = <2>; -- cgit v1.2.3 From 04fa4f03e3533f51b4db19cb487435f5862a0514 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 1 Oct 2020 11:11:30 +0200 Subject: arm64: dts: ls1028a: add missing CAN nodes The LS1028A has two FlexCAN controller. These are compatible with the ones from the LX2160A. Add the nodes. The first controller was tested on the Kontron sl28 board. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 73e4f9466887..ac17752ab3ec 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -386,6 +386,24 @@ status = "disabled"; }; + can0: can@2180000 { + compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = ; + clocks = <&sysclk>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@2190000 { + compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = ; + clocks = <&sysclk>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; -- cgit v1.2.3 From 7e2ac9deb1d66401291d456aa27f081bbb9071de Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 1 Oct 2020 11:11:31 +0200 Subject: arm64: dts: freescale: sl28: add CAN node The module supports one CAN controller. Enable it. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index f46eb47cfa4d..17a2f5dacc3f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -60,6 +60,10 @@ }; }; +&can0 { + status = "okay"; +}; + &dspi2 { status = "okay"; }; -- cgit v1.2.3 From a01f7a96a9b0069d1cf9dd1c59d279e497cecdea Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:45 +0100 Subject: arm64: dts: exynos: adjust node names to DT spec in Exynos5433 TM2 The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-11-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 829fea23d4ab..01ab886fd3e9 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -94,7 +94,7 @@ #size-cells = <0>; status = "okay"; - max98504: max98504@31 { + max98504: amplifier@31 { compatible = "maxim,max98504"; reg = <0x31>; maxim,rx-path = <1>; @@ -386,7 +386,7 @@ status = "okay"; clock-frequency = <2500000>; - s2mps13-pmic@66 { + pmic@66 { compatible = "samsung,s2mps13-pmic"; interrupt-parent = <&gpa0>; interrupts = <7 IRQ_TYPE_NONE>; @@ -817,7 +817,7 @@ status = "okay"; clock-frequency = <1000000>; - sii8620@39 { + bridge@39 { reg = <0x39>; compatible = "sil,sii8620"; cvcc10-supply = <&ldo36_reg>; @@ -852,7 +852,7 @@ &hsi2c_8 { status = "okay"; - max77843@66 { + pmic@66 { compatible = "maxim,max77843"; interrupt-parent = <&gpa1>; interrupts = <5 IRQ_TYPE_EDGE_FALLING>; @@ -1231,7 +1231,7 @@ cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>; status = "okay"; - wm5110: wm5110-codec@0 { + wm5110: audio-codec@0 { compatible = "wlf,wm5110"; reg = <0x0>; spi-max-frequency = <20000000>; -- cgit v1.2.3 From 6c215edbdc7129e258a1158fa3284aaa734a38cb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:46 +0100 Subject: arm64: dts: exynos: adjust node names to DT spec in Exynos7 Espresso The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-12-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index 92fecc539c6c..695d4c140646 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -87,7 +87,7 @@ samsung,i2c-max-bus-freq = <200000>; status = "okay"; - s2mps15_pmic@66 { + pmic@66 { compatible = "samsung,s2mps15-pmic"; reg = <0x66>; interrupts = <2 IRQ_TYPE_NONE>; -- cgit v1.2.3 From 29a7bb71a833e092d0012597a00a15ca84837f0b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:47 +0100 Subject: arm64: dts: exynos: remove redundant status=okay in Exynos5433 TM2 New nodes are enabled by default, so status=okay is not needed for them. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-13-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 01ab886fd3e9..97a2f0c7c0cf 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -92,7 +92,6 @@ i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; - status = "okay"; max98504: amplifier@31 { compatible = "maxim,max98504"; -- cgit v1.2.3 From 7ecab1f29baf8b8c43d5f7c891aceacc15c19f22 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 28 Sep 2020 10:21:43 +0800 Subject: arm64: dts: imx8mn-evk: Add cpu-supply to enable cpufreq PMIC driver is ready on i.MX8MN EVK board, assign cpu-supply for each A53 and restore the operating points table to enable cpufreq. Signed-off-by: Anson Huang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 32 ++++++++++++++-------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index 707d8486b4d8..9e5c0af5f540 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -14,6 +14,22 @@ compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; }; +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + &i2c1 { pmic: pmic@25 { compatible = "nxp,pca9450b"; @@ -109,19 +125,3 @@ }; }; }; - -&A53_0 { - /delete-property/operating-points-v2; -}; - -&A53_1 { - /delete-property/operating-points-v2; -}; - -&A53_2 { - /delete-property/operating-points-v2; -}; - -&A53_3 { - /delete-property/operating-points-v2; -}; -- cgit v1.2.3 From 71011f55b0ab160631a31ea1e4b23f9717e5d072 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 29 Oct 2020 17:21:33 +0100 Subject: arm64: dts: freescale: align watchdog node name with dtschema The dtschema expects watchdog device node name to be "watchdog": arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dt.yaml: wdog@2ad0000: $nodename:0: 'wdog@2ad0000' does not match '^watchdog(@.*|-[0-9a-f])?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 6a2c09199047..1393fc7e56bb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -401,7 +401,7 @@ #interrupt-cells = <2>; }; - wdog0: wdog@2ad0000 { + wdog0: watchdog@2ad0000 { compatible = "fsl,ls1012a-wdt", "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 0464b8aa4bc4..d550f00f1f6a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -725,7 +725,7 @@ status = "disabled"; }; - wdog0: wdog@2ad0000 { + wdog0: watchdog@2ad0000 { compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; interrupts = <0 83 0x4>; -- cgit v1.2.3 From 5c22a9af414c463b3f47bc56b5bca5d7b7c6d5f0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 29 Sep 2020 10:40:13 +0200 Subject: arm64: dts: imx8mm: adjust GIC CPU mask to match number of CPUs i.MX 8M Mini has four Cortex-A CPUs, not six. Using higher value is harmless but adjust it to match real HW. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Jacky Bai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index b83f400def8b..ee486597afc0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -194,16 +194,16 @@ pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; }; timer { compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ - , /* Physical Non-Secure */ - , /* Virtual */ - ; /* Hypervisor */ + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ clock-frequency = <8000000>; arm,no-tick-in-suspend; }; -- cgit v1.2.3 From 0656e37a8fa87fca12ef255de018a9d80ba23eb8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 29 Sep 2020 10:40:14 +0200 Subject: arm64: dts: imx8mn: adjust GIC CPU mask to match number of CPUs i.MX 8M Nano has four Cortex-A CPUs, not six. Using higher value is harmless but adjust it to match real HW. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Jacky Bai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 746faf1cf2fb..390fbd2bfa7e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -225,10 +225,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <8000000>; arm,no-tick-in-suspend; }; -- cgit v1.2.3 From 061883e690ebf6fc5a17fdf55249a3b8d5c111fe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 29 Sep 2020 10:40:15 +0200 Subject: arm64: dts: imx8mp: adjust GIC CPU mask to match number of CPUs i.MX 8M Plus has four Cortex-A CPUs, not six. Using higher value is harmless but adjust it to match real HW. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Jacky Bai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 6038f66aefc1..c69c206068a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -202,10 +202,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <8000000>; arm,no-tick-in-suspend; }; -- cgit v1.2.3 From 0f109a3158297ba774cdd4991b4a145738fe6202 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 29 Sep 2020 17:15:22 +0800 Subject: arm64: dts: freescale: Add pmu support on imx8mp Add PMU node to enable pmu support on imx8mp. Signed-off-by: Jacky Bai Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c69c206068a4..479312293036 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -133,6 +133,13 @@ clock-output-names = "clk_ext4"; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; -- cgit v1.2.3 From c13a7d84c4159e58127dbeac287686620a70b770 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 29 Sep 2020 17:15:23 +0800 Subject: arm64: dts: freescale: Add pmu support on imx8mn Add PMU node to enable pmu support on imx8mn. Signed-off-by: Jacky Bai Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 390fbd2bfa7e..d5cb8abb13e8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -186,6 +186,13 @@ clock-output-names = "clk_ext4"; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; -- cgit v1.2.3 From 8668d8b2e67fe7cf65f02becd5d67c0636689e82 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Thu, 1 Oct 2020 17:13:37 +0200 Subject: arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards Kontron Electronics GmbH offers small and powerful SoMs based on the i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR. The matching baseboards have the same form factor and similar interfaces as the other boards from the Kontron "Board-Line" family, including SD card, 1G Ethernet, 100M Ethernet, USB Host/OTG, digital IOs, RS232, RS485, CAN, LVDS or HDMI, RTC and much more. Signed-off-by: Frieder Schrempf Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mm-kontron-n801x-s.dts | 322 +++++++++++++++++++++ .../dts/freescale/imx8mm-kontron-n801x-som.dtsi | 294 +++++++++++++++++++ 3 files changed, 617 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f8d59433af01..e43254f1294d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dts dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts new file mode 100644 index 000000000000..d17abb515835 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx8mm-kontron-n801x-som.dtsi" + +/ { + model = "Kontron i.MX8MM N801X S"; + compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm"; + + aliases { + ethernet1 = &usbnet; + }; + + /* fixed crystal dedicated to mcp2515 */ + osc_can: clock-osc-can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "osc-can"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led1 { + label = "led1"; + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "led2"; + gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + }; + + led3 { + label = "led3"; + gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + }; + + led4 { + label = "led4"; + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + }; + + led5 { + label = "led5"; + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + }; + + led6 { + label = "led6"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + }; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&pwm2 0 5000 0>; + }; + + reg_rst_eth2: regulator-rst-eth2 { + compatible = "regulator-fixed"; + regulator-name = "rst-usb-eth2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_eth2>; + gpio = <&gpio3 2 GPIO_ACTIVE_LOW>; + }; + + reg_vdd_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + clocks = <&osc_can>; + interrupt-parent = <&gpio4>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <100000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_vdd_5v>; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-connection-type = "rgmii"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + reg = <0>; + reset-assert-us = <100>; + reset-deassert-us = <100>; + reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + over-current-active-low; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + usb1@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usbnet: usbether@1 { + compatible = "usb424,ec00"; + reg = <1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + pinctrl_can: cangrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */ + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */ + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usb_eth2: usbeth2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi new file mode 100644 index 000000000000..d0456daefda8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#include "imx8mm.dtsi" + +/ { + model = "Kontron i.MX8MM N801X SoM"; + compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + /* + * There are multiple SoM flavors with different DDR sizes. + * The smallest is 1GB. For larger sizes the bootloader will + * update the reg property. + */ + reg = <0x0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = &uart3; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spi-flash@0 { + compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; + spi-max-frequency = <80000000>; + reg = <0>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + reg_vdd_arm: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + reg_vdd_dram: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_3v3: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_1v8: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_dram: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_snvs: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_snvs: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdda: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_phy: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_sd: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&uart3 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; -- cgit v1.2.3 From 56c6b4ddfd503ff4de31462c92a187ee440b796e Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 7 Oct 2020 09:04:57 -0500 Subject: arm64: dts: imx8mm-beacon-som: Configure supplies on secondary cpus Each cpu core should have a corresponding supply, but only cpu0 does. This patch adds a supply for each of the secondary cpus. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 6de86a4f0ec4..0b8c4e4ad45b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -24,6 +24,18 @@ cpu-supply = <&buck2_reg>; }; +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; -- cgit v1.2.3 From 582b6d8b258d5bdc2dfde133145dc90fb9fea5e0 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 7 Oct 2020 09:24:08 -0500 Subject: arm64: dts: imx8mm-beacon-som: Add QSPI NOR flash support imx8mm-beacon-som has a Quad-SPI NOR flash connected to the FlexSPI bus. This patch enables the FlexSPI bus and configures it to work with the flash part. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-beacon-som.dtsi | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 0b8c4e4ad45b..09ad2d71b8b3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -75,6 +75,22 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -302,6 +318,17 @@ >; }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 -- cgit v1.2.3 From 87e218ae976eeffe660aaae2c90e78d3f514f39a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 2 Oct 2020 18:39:40 +0200 Subject: arm64: dts: mediatek: align GPIO hog names with dtschema The convention for node names is to use hyphens, not underscores. dtschema for pca95xx expects GPIO hogs to end with 'hog' suffix. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201002163940.7837-1-krzk@kernel.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 26 ++++++++++++------------ 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index 3e5a8dfda0c0..63fd70086bb8 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -63,91 +63,91 @@ gpio-controller; #gpio-cells = <2>; - eint20_mux_sel0 { + eint20-mux-sel0-hog { gpio-hog; gpios = <0 0>; input; line-name = "eint20_mux_sel0"; }; - expcon_mux_sel1 { + expcon-mux-sel1-hog { gpio-hog; gpios = <1 0>; input; line-name = "expcon_mux_sel1"; }; - mrg_di_mux_sel2 { + mrg-di-mux-sel2-hog { gpio-hog; gpios = <2 0>; input; line-name = "mrg_di_mux_sel2"; }; - sd_sdio_mux_sel3 { + sd-sdio-mux-sel3-hog { gpio-hog; gpios = <3 0>; input; line-name = "sd_sdio_mux_sel3"; }; - sd_sdio_mux_ctrl7 { + sd-sdio-mux-ctrl7-hog { gpio-hog; gpios = <7 0>; output-low; line-name = "sd_sdio_mux_ctrl7"; }; - hw_id0 { + hw-id0-hog { gpio-hog; gpios = <8 0>; input; line-name = "hw_id0"; }; - hw_id1 { + hw-id1-hog { gpio-hog; gpios = <9 0>; input; line-name = "hw_id1"; }; - hw_id2 { + hw-id2-hog { gpio-hog; gpios = <10 0>; input; line-name = "hw_id2"; }; - fg_int_n { + fg-int-n-hog { gpio-hog; gpios = <11 0>; input; line-name = "fg_int_n"; }; - usba_pwr_en { + usba-pwr-en-hog { gpio-hog; gpios = <12 0>; output-high; line-name = "usba_pwr_en"; }; - wifi_3v3_pg { + wifi-3v3-pg-hog { gpio-hog; gpios = <13 0>; input; line-name = "wifi_3v3_pg"; }; - cam_rst { + cam-rst-hog { gpio-hog; gpios = <14 0>; output-low; line-name = "cam_rst"; }; - cam_pwdn { + cam-pwdn-hog { gpio-hog; gpios = <15 0>; output-low; -- cgit v1.2.3 From b781820927c5fb0dacb2ef986b33e9b3cfc41930 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 12 Oct 2020 20:44:00 +0800 Subject: arm64: dts: imx8mm: Correct WDOG_B pin configuration Different revision of i.MX8MM EVK boards may have different external pull up registor design, some are enabled while some are NOT, to make sure the WDOG_B pin works properly, better to enable internal pull up resistor. Since enabling internal pull up resistor is NOT harmful and having benefit of flexibility on different board design, just enable it for all i.MX8MM boards; And schmitt input is NOT necessary for this WDOG_B output pin, so remove it; Open drain outputs provide more flexibility to a designer as they can be pulled-up to any voltage found in the system, so enable it as well. Signed-off-by: Anson Huang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 09ad2d71b8b3..c74e006ad0e8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -437,7 +437,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index f305a530ff6f..469d5703250b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -468,7 +468,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index 4107fe914d08..38e879d32560 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -555,7 +555,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; }; -- cgit v1.2.3 From fa88e6e406c3c8ae9cd7f3434c6c4e4b103cb19e Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 12 Oct 2020 20:44:01 +0800 Subject: arm64: dts: imx8mn: Correct WDOG_B pin configuration Different revision of i.MX8MN EVK boards may have different external pull up registor design, some are enabled while some are NOT, to make sure the WDOG_B pin works properly, better to enable internal pull up resistor. Since enabling internal pull up resistor is NOT harmful and having benefit of flexibility on different board design, just enable it for all i.MX8MN boards; And schmitt input is NOT necessary for this WDOG_B output pin, so remove it; Open drain outputs provide more flexibility to a designer as they can be pulled-up to any voltage found in the system, so enable it as well. Signed-off-by: Anson Huang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 4aa0dbd578df..fda890589a09 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -340,7 +340,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index a2d0190921e4..dde01daab62e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -545,7 +545,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; }; -- cgit v1.2.3 From fa15cec9cc319d276dc5f4b89b7f1119ea9d013d Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 12 Oct 2020 20:44:02 +0800 Subject: arm64: dts: imx8mp-evk: Correct WDOG_B pin configuration Different revision of i.MX8MP EVK boards may have different external pull up registor design, some are enabled while some are NOT, to make sure the WDOG_B pin works properly, better to enable internal pull up resistor. Since enabling internal pull up resistor is NOT harmful and having benefit of flexibility on different board design, just enable it for all i.MX8MP boards; And schmitt input is NOT necessary for this WDOG_B output pin, so remove it; Open drain outputs provide more flexibility to a designer as they can be pulled-up to any voltage found in the system, so enable it as well. Signed-off-by: Anson Huang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index ad66f1286d95..908b92bb4dcd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -262,7 +262,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 >; }; }; -- cgit v1.2.3 From 3bd0788c43d97293a4630e2f36ab31520db16a4a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 19 Oct 2020 11:50:36 -0500 Subject: arm64: dts: imx8mm: Add support for micfil The i.MX8M Mini has supports the MICFIL digital interface. It's a 16-bit audio signal from a PDM microphone bitstream. The driver is already in the kernel, but the node is missing. This patch adds the micfil node. Signed-off-by: Adam Ford Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index ee486597afc0..7a1b62f0ccc7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -339,6 +339,25 @@ status = "disabled"; }; + micfil: audio-controller@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x30080000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8MM_CLK_PDM_IPG>, + <&clk IMX8MM_CLK_PDM_ROOT>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>, + <&clk IMX8MM_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; -- cgit v1.2.3 From 57412197faf18683dff057f225c304b2d6dbe129 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 19 Oct 2020 11:50:37 -0500 Subject: arm64: dts: imx8mm: Add node for SPDIF The i.MX8M Mini can support SPDIF which is compatible to the IP used on the i.MX35. Add the node. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 7a1b62f0ccc7..033fee525982 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -358,6 +358,30 @@ status = "disabled"; }; + spdif1: spdif@30090000 { + compatible = "fsl,imx35-spdif"; + reg = <0x30090000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ + <&clk IMX8MM_CLK_24M>, /* rxtx0 */ + <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MM_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; -- cgit v1.2.3 From da2445049fafff0274d2a596a45e86021b01779b Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:57 +0300 Subject: arm64: dts: layerscape: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 1393fc7e56bb..a168e06ac50a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -454,7 +454,7 @@ <&clockgen 4 3>; }; - usb0: usb3@2f00000 { + usb0: usb@2f00000 { compatible = "snps,dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = <0 60 0x4>; @@ -475,7 +475,7 @@ status = "disabled"; }; - usb1: usb2@8600000 { + usb1: usb@8600000 { compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; reg = <0x0 0x8600000 0x0 0x1000>; interrupts = <0 139 0x4>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index d550f00f1f6a..d5d219311161 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -750,7 +750,7 @@ <&clockgen 4 0>; }; - usb0: usb3@2f00000 { + usb0: usb@2f00000 { compatible = "snps,dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = <0 60 0x4>; @@ -761,7 +761,7 @@ status = "disabled"; }; - usb1: usb3@3000000 { + usb1: usb@3000000 { compatible = "snps,dwc3"; reg = <0x0 0x3000000 0x0 0x10000>; interrupts = <0 61 0x4>; @@ -772,7 +772,7 @@ status = "disabled"; }; - usb2: usb3@3100000 { + usb2: usb@3100000 { compatible = "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <0 63 0x4>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index ff5805206a28..b2c5189e59fa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -420,7 +420,7 @@ status = "disabled"; }; - usb0: usb3@3100000 { + usb0: usb@3100000 { compatible = "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; @@ -431,7 +431,7 @@ status = "disabled"; }; - usb1: usb3@3110000 { + usb1: usb@3110000 { compatible = "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index bf72918fe545..4d3f72d126e7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -860,7 +860,7 @@ dma-coherent; }; - usb0: usb3@3100000 { + usb0: usb@3100000 { status = "disabled"; compatible = "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; @@ -871,7 +871,7 @@ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; - usb1: usb3@3110000 { + usb1: usb@3110000 { status = "disabled"; compatible = "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; -- cgit v1.2.3 From d7ffc7d48e437c016a65eff6d156b39884ab2594 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Fri, 30 Oct 2020 18:25:30 +0100 Subject: arm64: dts: allwinner: h6: PineH64 model B: Add wifi PineH64 model B contains RTL8723CS wifi+bt combo module. Since bluetooth support is not yet squared away, only wifi is enabled for now. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Tested-by: Acked-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201030172530.1096394-1-jernej.skrabec@siol.net --- .../boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts index f4c8966a6497..7fea1e4e2d49 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts @@ -10,6 +10,12 @@ compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; /delete-node/ reg_gmac_3v3; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ + post-power-on-delay-ms = <200>; + }; }; &hdmi_connector { @@ -19,3 +25,12 @@ &emac { phy-supply = <®_aldo2>; }; + +&mmc1 { + vmmc-supply = <®_cldo3>; + vqmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; -- cgit v1.2.3 From b306d9cec8de054c7ace45dd0e4c9cac4991d65f Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Fri, 30 Oct 2020 15:46:44 +0100 Subject: arm64: dts: allwinner: h6: Add I2S1 node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Allwinner H6 I2S1 node connected to HDMI interface. Signed-off-by: Jernej Skrabec Signed-off-by: Marcus Cooper Signed-off-by: Clément Péron Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201030144648.397824-12-peron.clem@gmail.com --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 28c4a79b8a45..8a62a9fbe347 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -609,6 +609,19 @@ }; }; + i2s1: i2s@5091000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-h6-i2s"; + reg = <0x05091000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + resets = <&ccu RST_BUS_I2S1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spdif: spdif@5093000 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-h6-spdif"; -- cgit v1.2.3 From 796c994e0b63400f6450a10e0a75c45e59191304 Mon Sep 17 00:00:00 2001 From: Marcus Cooper Date: Fri, 30 Oct 2020 15:46:45 +0100 Subject: arm64: dts: allwinner: a64: Add I2S2 node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the I2S2 node connected to the HDMI interface. Signed-off-by: Jernej Skrabec Signed-off-by: Marcus Cooper Signed-off-by: Clément Péron Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201030144648.397824-13-peron.clem@gmail.com --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index dc238814013c..51cc30e84e26 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -846,6 +846,20 @@ status = "disabled"; }; + i2s2: i2s@1c22800 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-a64-i2s", + "allwinner,sun8i-h3-i2s"; + reg = <0x01c22800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S2>; + dma-names = "rx", "tx"; + dmas = <&dma 27>, <&dma 27>; + status = "disabled"; + }; + dai: dai@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-codec-i2s"; -- cgit v1.2.3 From 09e006cfb43e8ec38afe28278b210dab72e6cac8 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 14 Oct 2020 22:00:30 +0200 Subject: arm64: dts: rockchip: Add basic support for Kobol's Helios64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The hardware is described in detail on Kobol's wiki at https://wiki.kobol.io/helios64/intro/. Up to now the following peripherals are working: - UART - Micro-SD card - eMMC - ethernet port 1 - status LED - temperature sensor on i2c bus 2 Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20201014200030.845759-3-uwe@kleine-koenig.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3399-kobol-helios64.dts | 372 +++++++++++++++++++++ 2 files changed, 373 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 26661c7b736b..28b26a874313 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts new file mode 100644 index 000000000000..2a561be724b2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Aditya Prayoga + */ + +/* + * The Kobol Helios64 is a board designed to operate as a NAS and optionally + * ships with an enclosing that can host five 2.5" hard disks. + * + * See https://wiki.kobol.io/helios64/intro/ for further details. + */ + +/dts-v1/; +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Kobol Helios64"; + compatible = "kobol,helios64", "rockchip,rk3399"; + + avdd_1v8_s0: avdd-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "avdd_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys_s3>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_grn_led_on &sys_red_led_on>; + + led-0 { + label = "helios64:green:status"; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-1 { + label = "helios64:red:fault"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + vcc1v8_sys_s0: vcc1v8-sys-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc1v8_sys_s3>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v0_sd"; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + vin-supply = <&vcc3v3_sys_s3>; + }; + + vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin_bkup>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc12v_dcin_bkup: vcc12v-dcin-bkup { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin_bkup"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +/* + * The system doesn't run stable with cpu freq enabled, so disallow the lower + * frequencies until this problem is properly understood and resolved. + */ +&cluster0_opp { + /delete-node/ opp00; + /delete-node/ opp01; + /delete-node/ opp02; + /delete-node/ opp03; + /delete-node/ opp04; +}; + +&cluster1_opp { + /delete-node/ opp00; + /delete-node/ opp01; + /delete-node/ opp02; + /delete-node/ opp03; + /delete-node/ opp04; + /delete-node/ opp05; + /delete-node/ opp06; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clock-parents = <&clkin_gmac>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + clock_in_out = "input"; + phy-mode = "rgmii"; + phy-supply = <&vcc_lan>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins &gphy_reset>; + rx_delay = <0x20>; + tx_delay = <0x28>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys_s3>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys_s3>; + vddio-supply = <&vcc3v0_s3>; + wakeup-source; + #clock-cells = <1>; + + regulators { + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_sys_s3: DCDC_REG4 { + regulator-name = "vcc1v8_sys_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio_s0: LDO_REG4 { + regulator-name = "vcc_sdio_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v0_s3: LDO_REG8 { + regulator-name = "vcc3v0_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + temp@4c { + compatible = "national,lm75"; + reg = <0x4c>; + }; +}; + +&io_domains { + audio-supply = <&vcc1v8_sys_s0>; + bt656-supply = <&vcc1v8_sys_s0>; + gpio1830-supply = <&vcc3v0_s3>; + sdmmc-supply = <&vcc_sdio_s0>; + status = "okay"; +}; + +&pinctrl { + gmac { + gphy_reset: gphy-reset { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + leds { + sys_grn_led_on: sys-grn-led-on { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + sys_red_led_on: sys-red-led-on { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + vcc3v0-sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc3v0_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vqmmc-supply = <&vcc1v8_sys_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio_s0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; -- cgit v1.2.3 From 437145dbcdee5b62f94b6fd846a22a8671c28843 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Wed, 28 Oct 2020 17:28:25 -0700 Subject: arm64: dts: qcom: sc7180: Add soc-specific qfprom compat string Add the soc-specific compatible string so that it can be matched more specifically now that the driver cares which SoC it's on. Signed-off-by: Evan Green Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20201028172737.v3.2.Ia3b68ac843df93c692627a3a92b947b3a5785863@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 6fcffd588a7d..f5ef2cb6e68c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -660,7 +660,7 @@ }; qfprom: efuse@784000 { - compatible = "qcom,qfprom"; + compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; reg = <0 0x00784000 0 0x8ff>, <0 0x00780000 0 0x7a0>, <0 0x00782000 0 0x100>, -- cgit v1.2.3 From 721d10be5ccd7194446db40f1b9534cfe7088d73 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 3 Nov 2020 03:54:31 +0300 Subject: arm64: dts: qcom: enable rtc on qrb5165-rb5 board Enable PMIC's RTC device on RB5 board. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201103005432.1181832-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 1b6406927509..a53eccf2b695 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -97,7 +97,7 @@ }; }; - rtc@6000 { + pm8150_rtc: rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>; reg-names = "rtc", "alarm"; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 1528a865f1f8..fec31655141c 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -459,6 +459,10 @@ "PM3003A_MODE"; }; +&pm8150_rtc { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; -- cgit v1.2.3 From db5f5da2efd720be29e403fea964599032c542ec Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 3 Nov 2020 03:54:32 +0300 Subject: arm64: dts: qcom: enable rtc on sm8250-mtp board Enable PMIC's RTC device on SM8250-MTP board. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201103005432.1181832-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index fd194ed7fbc8..c85cab9c9b41 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -378,6 +378,10 @@ /* rtc6226 @ 64 */ }; +&pm8150_rtc { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; -- cgit v1.2.3 From c422aa82abb75436bc31e0da7970aa1f9248b090 Mon Sep 17 00:00:00 2001 From: Stanimir Varbanov Date: Mon, 2 Nov 2020 13:35:29 +0200 Subject: arm64: dts: sdm845: Add interconnect properties for Venus Populate Venus DT node with interconnect properties. Reviewed-by: Georgi Djakov Signed-off-by: Stanimir Varbanov Link: https://lore.kernel.org/r/20201102113529.16152-1-stanimir.varbanov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 40e8c11f23ab..aca7e9c954e0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3661,6 +3661,9 @@ iommus = <&apps_smmu 0x10a0 0x8>, <&apps_smmu 0x10b0 0x0>; memory-region = <&venus_mem>; + interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; + interconnect-names = "video-mem", "cpu-cfg"; video-core0 { compatible = "venus-decoder"; -- cgit v1.2.3 From ab8e32da3a39e558d2fa2bc46a25eb2f0e885a16 Mon Sep 17 00:00:00 2001 From: Alexandru Stan Date: Wed, 21 Oct 2020 22:04:44 -0700 Subject: arm64: dts: qcom: trogdor: Add brightness-levels We want userspace to represent the human perceived brightness. Since the led drivers and the leds themselves don't have a linear response to the value we give them in terms of perceived brightness, we'll bake the curve into the dts. The panel also doesn't have a good response under 5%, so we'll avoid sending it anything lower than that. Note: Ideally this patch should be coupled with the driver change from "backlight: pwm_bl: Fix interpolation", but it can work without it, without looking too ugly. Acked-by: Daniel Thompson Reviewed-by: Douglas Anderson Signed-off-by: Alexandru Stan Link: https://lore.kernel.org/r/20201021220404.v3.2.Ie4d84af5a85e8dcb8f575845518fa39f324a827d@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 0759896a0df5..8653a38a3e42 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -179,6 +179,15 @@ backlight: backlight { compatible = "pwm-backlight"; + /* The panels don't seem to like anything below ~ 5% */ + brightness-levels = < + 196 256 324 400 484 576 676 784 900 1024 1156 1296 + 1444 1600 1764 1936 2116 2304 2500 2704 2916 3136 + 3364 3600 3844 4096 + >; + num-interpolated-steps = <64>; + default-brightness-level = <951>; + pwms = <&cros_ec_pwm 1>; enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; power-supply = <&ppvar_sys>; -- cgit v1.2.3 From 37f7a7b68004807d230fedcf090b09ea501086a9 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 4 Nov 2020 23:41:30 -0600 Subject: arm64: dts: allwinner: pinephone: Remove AC power supply The AXP803 in the Pinephone has its ACIN and VBUS pins shorted together. In this configuration, the VBUS control registers take priority over the ACIN control registers, which means the ACIN sysfs knobs have no effect. Remove the AC power supply from the DTS, since VBUS is really the only power supply. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105054135.24860-2-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 5780713b0dba..3776f168d023 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -251,10 +251,6 @@ #include "axp803.dtsi" -&ac_power_supply { - status = "okay"; -}; - &battery_power_supply { status = "okay"; }; -- cgit v1.2.3 From 3cf9bf3b25505d8e2a0366c35b0af6b48e7a3c40 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 4 Nov 2020 23:41:31 -0600 Subject: arm64: dts: allwinner: pinephone: Set ALDO3 to exactly 3v0 ALDO3 is used as the power supply for the LRADC keys voltage divider, in addition to supplying AVCC and VCC-PLL. While AVCC and VCC-PLL will accept any voltage between 2v7 and 3v3, LRADC needs a precise 3v0 input to maintain the expected 2:3 ratio between the internal 2v0 reference voltage and the external supply. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105054135.24860-3-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 3776f168d023..555837722be2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -270,8 +270,8 @@ ®_aldo3 { regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; regulator-name = "vcc-pll-avcc"; }; -- cgit v1.2.3 From 085d96b88403edfc0a8ee340b7e6122c34f039c2 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 4 Nov 2020 23:41:32 -0600 Subject: arm64: dts: allwinner: pinephone: Add LED flash All revisions of the PinePhone have an SGM3140 LED flash. The gpios were swapped on v1.0 of the board, but this was fixed in later revisions. Signed-off-by: Luca Weiss Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105054135.24860-4-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts | 5 +++++ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 5 +++++ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts | 5 +++++ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 11 +++++++++++ 4 files changed, 26 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts index 0c42272106af..3d5a2ae9aa39 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts @@ -9,3 +9,8 @@ model = "Pine64 PinePhone Developer Batch (1.0)"; compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64"; }; + +&sgm3140 { + enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ + flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts index 3e99a87e9ce5..c9b9f6e9ee8c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts @@ -28,3 +28,8 @@ num-interpolated-steps = <50>; default-brightness-level = <400>; }; + +&sgm3140 { + enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ + flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts index a9f5b670c9b8..94e4f11e0215 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts @@ -38,3 +38,8 @@ interrupt-parent = <&pio>; interrupts = <1 1 IRQ_TYPE_EDGE_RISING>; /* PB1 */ }; + +&sgm3140 { + enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ + flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 555837722be2..8285391a0265 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -49,6 +49,17 @@ }; }; + sgm3140: led-controller { + compatible = "sgmicro,sgm3140"; + vin-supply = <®_dcdc1>; + + sgm3140_flash: led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + }; + }; + speaker_amp: audio-amplifier { compatible = "simple-audio-amplifier"; enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ -- cgit v1.2.3 From a966ef6297dd6829714ba5f6abd9ab2d67f8a935 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 4 Nov 2020 23:41:33 -0600 Subject: arm64: dts: allwinner: pinephone: Add light/proximity sensor Pinephone has STK3311-X proximity sensor. Add support for it. Signed-off-by: Ondrej Jirman Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105054135.24860-5-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 8285391a0265..8617b79d33e6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -160,6 +160,16 @@ vddio-supply = <®_dldo1>; }; + /* Light/proximity sensor */ + stk3311@48 { + compatible = "sensortek,stk3311"; + reg = <0x48>; + interrupt-parent = <&pio>; + interrupts = <1 0 IRQ_TYPE_EDGE_FALLING>; /* PB0 */ + vdd-supply = <®_ldo_io0>; + leda-supply = <®_dldo1>; + }; + /* Accelerometer/gyroscope */ mpu6050@68 { compatible = "invensense,mpu6050"; -- cgit v1.2.3 From 4fcf6f34879908a67454d3cdcf0f6b593947f96d Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 4 Nov 2020 23:41:34 -0600 Subject: arm64: dts: allwinner: pinephone: Add WiFi support The PinePhone has a Realtek rtl8723cs WiFi module. On mainboard revisions 1.0 and 1.1, the reset input is always pulled high, so no power sequence is needed. On mainboard revision 1.2, the reset input is connected to PL2. Signed-off-by: Ondrej Jirman Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105054135.24860-6-samuel@sholland.org --- .../dts/allwinner/sun50i-a64-pinephone-1.2.dts | 9 +++++++++ .../boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 31 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts index 94e4f11e0215..acc0ab53b9c1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts @@ -8,6 +8,11 @@ / { model = "Pine64 PinePhone (1.2)"; compatible = "pine64,pinephone-1.2", "allwinner,sun50i-a64"; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + }; }; &backlight { @@ -39,6 +44,10 @@ interrupts = <1 1 IRQ_TYPE_EDGE_RISING>; /* PB1 */ }; +&mmc1 { + mmc-pwrseq = <&wifi_pwrseq>; +}; + &sgm3140 { enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 8617b79d33e6..07f66f4cefac 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -13,6 +13,7 @@ / { aliases { + ethernet0 = &rtl8723cs; serial0 = &uart0; }; @@ -49,6 +50,13 @@ }; }; + reg_vbat_wifi: vbat-wifi { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vbat-wifi"; + }; + sgm3140: led-controller { compatible = "sgmicro,sgm3140"; vin-supply = <®_dcdc1>; @@ -216,6 +224,20 @@ status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_vbat_wifi>; + vqmmc-supply = <®_dldo4>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723cs: wifi@1 { + reg = <1>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; -- cgit v1.2.3 From 976843d5e8203829adb99bc40bc6f556997881c8 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 4 Nov 2020 23:41:35 -0600 Subject: arm64: dts: allwinner: pinephone: Add Bluetooth support The PinePhone has a Realtek rtl8723cs Bluetooth controller. Signed-off-by: Ondrej Jirman Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105054135.24860-7-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 07f66f4cefac..2da69450eec1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -447,6 +447,19 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723cs-bt"; + device-wake-gpios = <&pio 7 6 GPIO_ACTIVE_LOW>; /* PH6 */ + enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + host-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + }; +}; + /* Connected to the modem (hardware flow control can't be used) */ &uart3 { pinctrl-names = "default"; -- cgit v1.2.3 From 8e9c052a483db5f9ae098d9b686ed80e2e98a8c5 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 26 Oct 2020 13:41:01 +0000 Subject: arm64: dts: meson: remove empty lines from aml-s905x-cc v2 dts Fixes: 63fafc5a046b ("arm64: dts: meson: initial support for aml-s905x-cc v2") Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201026134101.10594-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts index 675eaa87963e..9a3c08e6e6cc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts @@ -84,7 +84,6 @@ regulator-always-on; }; - vcck: regulator-vcck { compatible = "regulator-fixed"; regulator-name = "VCCK"; @@ -124,7 +123,6 @@ regulator-always-on; }; - vddio_card: regulator-vddio-card { compatible = "regulator-gpio"; regulator-name = "VDDIO_CARD"; @@ -195,7 +193,6 @@ }; }; - &aiu { status = "okay"; }; @@ -207,7 +204,6 @@ hdmi-phandle = <&hdmi_tx>; }; - ðmac { status = "okay"; }; -- cgit v1.2.3 From 7bd5175918eb4b294c0979c75056f20fd90a50bf Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sun, 1 Nov 2020 02:10:12 +0000 Subject: arm64: dts: meson: add watchdog to g12-common dtsi G12 vendor kernels show the watchdog on the same address as AXG so add the node to meson-g12-common.dtsi. GX boards inherit the same from meson-gx.dtsi. v2 fix typo in node name (s/wtd/wdt) Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201101021012.24519-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 1e83ec5b8c91..314095b79a45 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -2179,6 +2179,12 @@ amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; }; + watchdog: wdt@f0d0 { + compatible = "amlogic,meson-gxbb-wdt"; + reg = <0x0 0xf0d0 0x0 0x10>; + clocks = <&xtal>; + }; + spicc0: spi@13000 { compatible = "amlogic,meson-g12a-spicc"; reg = <0x0 0x13000 0x0 0x44>; -- cgit v1.2.3 From 98c03b6eef3f9c7d8153f96870968615ab489a6b Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Thu, 29 Oct 2020 14:40:17 +0100 Subject: arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards Add the nodes relevant to PCIe PHY and PCIe support. PCIe is used for the WiFi interface (Broadcom Limited BCM4358 802.11ac Wireless LAN SoC). [mszyprow: rewrote commit message, reworked board/generic dts/dtsi split] Signed-off-by: Jaehoon Chung Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201029134017.27400-7-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 2 +- .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 24 ++++++++++++++- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 36 ++++++++++++++++++++++ 3 files changed, 60 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi index 9df7c65593a1..32a6518517e5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -329,7 +329,7 @@ }; pcie_bus: pcie_bus { - samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6"; samsung,pin-function = ; samsung,pin-pud = ; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 97a2f0c7c0cf..5ec447f0cf5d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -968,6 +968,25 @@ bus-width = <4>; }; +&pcie { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_bus &pcie_wlanen>; + vdd10-supply = <&ldo6_reg>; + vdd18-supply = <&ldo7_reg>; + assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>, + <&cmu_top CLK_MOUT_SCLK_PCIE_100>; + assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>, + <&cmu_top CLK_MOUT_BUS_PLL_USER>; + assigned-clock-rates = <0>, <100000000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; +}; + +&pcie_phy { + status = "okay"; +}; + &ppmu_d0_general { status = "okay"; events { @@ -1084,8 +1103,11 @@ pinctrl-names = "default"; pinctrl-0 = <&initial_ese>; + pcie_wlanen: pcie-wlanen { + PIN(INPUT, gpj2-0, UP, FAST_SR4); + }; + initial_ese: initial-state { - PIN(INPUT, gpj2-0, DOWN, FAST_SR1); PIN(INPUT, gpj2-1, DOWN, FAST_SR1); PIN(INPUT, gpj2-2, DOWN, FAST_SR1); }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 0a886bb6c806..7853a908fe39 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1029,6 +1029,11 @@ reg = <0x145f0000 0x1038>; }; + syscon_fsys: syscon@156f0000 { + compatible = "syscon"; + reg = <0x156f0000 0x1044>; + }; + gsc_0: video-scaler@13c00000 { compatible = "samsung,exynos5433-gsc"; reg = <0x13c00000 0x1000>; @@ -1830,6 +1835,37 @@ status = "disabled"; }; }; + + pcie_phy: pcie-phy@15680000 { + compatible = "samsung,exynos5433-pcie-phy"; + reg = <0x15680000 0x1000>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,fsys-sysreg = <&syscon_fsys>; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie: pcie@15700000 { + compatible = "samsung,exynos5433-pcie"; + reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, + <0x0c000000 0x1000>; + reg-names = "dbi", "elbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = ; + clocks = <&cmu_fsys CLK_PCIE>, + <&cmu_fsys CLK_PCLK_PCIE_PHY>; + clock-names = "pcie", "pcie_bus"; + num-lanes = <1>; + num-viewport = <3>; + bus-range = <0x00 0xff>; + phys = <&pcie_phy>; + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; + status = "disabled"; + }; }; timer: timer { -- cgit v1.2.3 From 030eea2a1127700af0176345b404db943232a908 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 5 Nov 2020 21:20:55 -0600 Subject: arm64: dts: allwinner: pinephone: Use generic sensor node names Instead of duplicating part of the compatible string in the node name, use generic names as recommended by (and listed in) section 2.2.2 of the Devicetree Specification. Suggested-by: Maxime Ripard Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201106032055.51530-1-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 2da69450eec1..2dfe9bae8c67 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -161,7 +161,7 @@ status = "okay"; /* Magnetometer */ - lis3mdl: lis3mdl@1e { + lis3mdl: magnetometer@1e { compatible = "st,lis3mdl-magn"; reg = <0x1e>; vdd-supply = <®_dldo1>; @@ -169,7 +169,7 @@ }; /* Light/proximity sensor */ - stk3311@48 { + light-sensor@48 { compatible = "sensortek,stk3311"; reg = <0x48>; interrupt-parent = <&pio>; @@ -179,7 +179,7 @@ }; /* Accelerometer/gyroscope */ - mpu6050@68 { + accelerometer@68 { compatible = "invensense,mpu6050"; reg = <0x68>; interrupt-parent = <&pio>; -- cgit v1.2.3 From c20e6dd9a953d62f14399dabf457dce61dd5611f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 4 Jul 2020 00:14:13 +0200 Subject: arm64: dts: rockchip: add adc joystick to Odroid Go Advance Add the now usable adc-joystick node that describes the analog joystick connected to two saradc channels from the rk3326 soc. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20200703221413.269800-1-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts index 35bd6b904b9c..e21372b8e904 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts @@ -18,6 +18,30 @@ stdout-path = "serial2:115200n8"; }; + adc-joystick { + compatible = "adc-joystick"; + io-channels = <&saradc 1>, + <&saradc 2>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <10>; + abs-fuzz = <10>; + abs-range = <172 772>; + linux,code = ; + }; + + axis@1 { + reg = <1>; + abs-flat = <10>; + abs-fuzz = <10>; + abs-range = <278 815>; + linux,code = ; + }; + }; + backlight: backlight { compatible = "pwm-backlight"; power-supply = <&vcc_bl>; -- cgit v1.2.3 From 73bc7510ea0dafb4ff1ae6808759627a8ec51f5a Mon Sep 17 00:00:00 2001 From: PaweÅ‚ Chmiel Date: Sat, 7 Nov 2020 14:39:25 +0100 Subject: arm64: dts: exynos: Include common syscon restart/poweroff for Exynos7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Exynos7 uses the same syscon reboot and poweroff nodes as other Exynos SoCs, so instead of duplicating code we can just include common dtsi file, which already contains definitions of them. After this change, poweroff node will be also available, previously this dts file did contain only reboot node. Fixes: fb026cb65247 ("arm64: dts: Add reboot node for exynos7") Fixes: b9024cbc937d ("arm64: dts: Add initial device tree support for exynos7") Signed-off-by: PaweÅ‚ Chmiel Link: https://lore.kernel.org/r/20201107133926.37187-1-pawel.mikolaj.chmiel@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 48cd3a04fd07..fa3ad6bcf562 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -481,13 +481,6 @@ pmu_system_controller: system-controller@105c0000 { compatible = "samsung,exynos7-pmu", "syscon"; reg = <0x105c0000 0x5000>; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&pmu_system_controller>; - offset = <0x0400>; - mask = <0x1>; - }; }; rtc: rtc@10590000 { @@ -687,3 +680,4 @@ }; #include "exynos7-pinctrl.dtsi" +#include "arm/exynos-syscon-restart.dtsi" -- cgit v1.2.3 From e1e47fbca668507a81bb388fcae044b89d112ecc Mon Sep 17 00:00:00 2001 From: PaweÅ‚ Chmiel Date: Sat, 7 Nov 2020 14:39:26 +0100 Subject: arm64: dts: exynos: Correct psci compatible used on Exynos7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's not possible to reboot or poweroff Exynos7420 using PSCI. Instead we need to use syscon reboot/poweroff drivers, like it's done for other Exynos SoCs. This was confirmed by checking vendor source and testing it on Samsung Galaxy S6 device based on this SoC. To be able to use custom restart/poweroff handlers instead of PSCI functions, we need to correct psci compatible. This also requires us to provide function ids for CPU_ON and CPU_OFF. Fixes: fb026cb65247 ("arm64: dts: Add reboot node for exynos7") Fixes: b9024cbc937d ("arm64: dts: Add initial device tree support for exynos7") Signed-off-by: PaweÅ‚ Chmiel Link: https://lore.kernel.org/r/20201107133926.37187-2-pawel.mikolaj.chmiel@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index fa3ad6bcf562..661f9c1027e8 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -79,8 +79,10 @@ }; psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci"; method = "smc"; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; }; soc: soc@0 { -- cgit v1.2.3 From 7a180f56e01443be526061bd8ec8cf6e2c4f988d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Sep 2020 14:02:12 +0530 Subject: arm64: dts: rockchip: Add Engicam EDIMM2.2 Starter Kit Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out SOM's like PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi Link: https://lore.kernel.org/r/20200929083217.25406-3-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/px30-engicam-common.dtsi | 39 ++++++++++++++++++++++ .../boot/dts/rockchip/px30-engicam-edimm2.2.dtsi | 7 ++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi new file mode 100644 index 000000000000..bd5bde989e8d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/ { + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; /* +5V */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&gmac { + clock_in_out = "output"; + phy-supply = <&vcc_3v3>; /* +3V3_SOM */ + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdmmc { + cap-sd-highspeed; + card-detect-delay = <800>; + vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */ + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m1_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi new file mode 100644 index 000000000000..cb00988953e9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi" -- cgit v1.2.3 From d92a7c331f53ccf6da4e0cb6b49470444cb150ce Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Tue, 29 Sep 2020 14:02:13 +0530 Subject: arm64: dts: rockchip: Add Engicam PX30.Core SOM PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. General features: - Rockchip PX30 - Up to 2GB DDR4 - eMMC 4 GB expandible - rest of PX30 features PX30.Core needs to mount on top of Engicam baseboards for creating complete platform boards. Possible baseboards are, - EDIMM2.2 - C.TOUCH 2.0 Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi Link: https://lore.kernel.org/r/20200929083217.25406-4-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/px30-engicam-px30-core.dtsi | 232 +++++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi new file mode 100644 index 000000000000..db22f776c68f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons + * Copyright (c) 2020 Amarula Solutons(India) + */ + +#include +#include + +/ { + compatible = "engicam,px30-core", "rockchip,px30"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name = "vcc_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name = "vcc3v0_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; -- cgit v1.2.3 From 0935d7e9b1b26230e01dc5f0ed8d2af3771ced57 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Sep 2020 14:02:14 +0530 Subject: arm64: dts: rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam. PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200929083217.25406-5-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/px30-engicam-px30-core-edimm2.2.dts | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 28b26a874313..abf9dc621314 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts new file mode 100644 index 000000000000..e54d1e480daa --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-edimm2.2.dtsi" +#include "px30-engicam-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; + compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core", + "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; +}; -- cgit v1.2.3 From 746c750a8bc4994638d014834389205c3e3bcc14 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Sep 2020 14:02:16 +0530 Subject: arm64: dts: rockchip: Add Engicam C.TOUCH 2.0 Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose carrier board with capacitive touch interface. Genaral features: - TFT 10.1" industrial, 1280x800 LVDS display - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector SOM's like PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi Link: https://lore.kernel.org/r/20200929083217.25406-7-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi new file mode 100644 index 000000000000..58425b1e559f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi" -- cgit v1.2.3 From e786f756d52707f3c36ca0efe949407a8b978493 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Sep 2020 14:02:17 +0530 Subject: arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi Link: https://lore.kernel.org/r/20200929083217.25406-8-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/px30-engicam-px30-core-ctouch2.dts | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index abf9dc621314..5a53979b7057 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts new file mode 100644 index 000000000000..5a0ecb8faecf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-ctouch2.dtsi" +#include "px30-engicam-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core C.TOUCH 2.0"; + compatible = "engicam,px30-core-ctouch2", "engicam,px30-core", + "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; +}; -- cgit v1.2.3 From 92494cea405fd2136033c70abd6abf6739b12a2f Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 21 Oct 2020 14:53:32 +0100 Subject: arm64: dts: renesas: r8a77965: Add DRIF support Add the DRIF controller nodes for r8a77965 (a.k.a. R-Car M3-N). Signed-off-by: Fabrizio Castro Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20201021135332.4928-6-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 120 ++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index c355460e5f7f..d098eb3ec73a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1550,6 +1550,126 @@ }; }; + drif00: rif@e6f40000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f40000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>; + clock-names = "fck"; + dmas = <&dmac1 0x20>, <&dmac2 0x20>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 515>; + renesas,bonding = <&drif01>; + status = "disabled"; + }; + + drif01: rif@e6f50000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f50000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>; + clock-names = "fck"; + dmas = <&dmac1 0x22>, <&dmac2 0x22>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 514>; + renesas,bonding = <&drif00>; + status = "disabled"; + }; + + drif10: rif@e6f60000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f60000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 513>; + clock-names = "fck"; + dmas = <&dmac1 0x24>, <&dmac2 0x24>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 513>; + renesas,bonding = <&drif11>; + status = "disabled"; + }; + + drif11: rif@e6f70000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f70000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 512>; + clock-names = "fck"; + dmas = <&dmac1 0x26>, <&dmac2 0x26>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 512>; + renesas,bonding = <&drif10>; + status = "disabled"; + }; + + drif20: rif@e6f80000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f80000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 511>; + clock-names = "fck"; + dmas = <&dmac1 0x28>, <&dmac2 0x28>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 511>; + renesas,bonding = <&drif21>; + status = "disabled"; + }; + + drif21: rif@e6f90000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f90000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 510>; + clock-names = "fck"; + dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 510>; + renesas,bonding = <&drif20>; + status = "disabled"; + }; + + drif30: rif@e6fa0000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fa0000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 509>; + clock-names = "fck"; + dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 509>; + renesas,bonding = <&drif31>; + status = "disabled"; + }; + + drif31: rif@e6fb0000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fb0000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 508>; + clock-names = "fck"; + dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 508>; + renesas,bonding = <&drif30>; + status = "disabled"; + }; + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required -- cgit v1.2.3 From 9b81018185965a306158b471db75ba0aca90ec9f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 19 Aug 2020 15:43:43 +0200 Subject: arm64: dts: renesas: rcar-gen3: Convert EtherAVB to explicit delay handling Some EtherAVB variants support internal clock delay configuration, which can add larger delays than the delays that are typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" properties). Historically, the EtherAVB driver configured these delays based on the "rgmii-*id" PHY mode. This was wrong, as these are meant solely for the PHY, not for the MAC. Hence properties were introduced for explicit configuration of these delays. Convert the R-Car Gen3 DTS files from the old to the new scheme: - Add default "rx-internal-delay-ps" and "tx-internal-delay-ps" properties to the SoC .dtsi files, to be overridden by board files where needed, - Convert board files from "rgmii-*id" PHY modes to "rgmii", adding the appropriate "rx-internal-delay-ps" and/or "tx-internal-delay-ps" overrides. Notes: - R-Car E3 and D3 do not support TX internal delay handling, - On R-Car D3, TX internal delay handling must always be enabled, hence this fixes a bug on Draak, - On R-Car V3H, RX internal delay handling must always be enabled. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200819134344.27813-7-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 3 ++- arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 3 ++- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1 + arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 +- arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 +- 12 files changed, 20 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 18ce0face72b..644308dd886c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -1250,6 +1250,8 @@ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index f379c8d1511d..53b9aa26c9b1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -1126,6 +1126,8 @@ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index b0c4b8150d37..9266c60f21fa 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1012,6 +1012,8 @@ power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index d098eb3ec73a..4a913df17b1d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -988,6 +988,8 @@ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 5c28f303e911..874a7fc2730b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -81,7 +81,8 @@ renesas,no-ether-link; phy-handle = <&phy0>; - phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1800>; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 668a1ece9af0..7417cf5fea0f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -102,7 +102,8 @@ renesas,no-ether-link; phy-handle = <&phy0>; - phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1800>; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index baf8cc821564..5a5d5649332a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -615,6 +615,8 @@ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_rt 3>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index d6cae90d7fd9..ec7ca72399ec 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -667,6 +667,8 @@ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <2000>; iommus = <&ipmmu_ds1 33>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 33d7e657bd9c..87d41bc076a9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -938,6 +938,7 @@ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index cd7ca9774196..e1af7c4782f4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -628,6 +628,7 @@ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <1800>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 1bf77957d2c2..6c643ed74fc5 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -324,7 +324,7 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index a2e085db87c5..8f8d7371d8e2 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -144,7 +144,7 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { -- cgit v1.2.3 From a5200e63af57d05ed8bf0ffd9a6ffefc40e01e89 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 19 Aug 2020 15:43:44 +0200 Subject: arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling Some EtherAVB variants support internal clock delay configuration, which can add larger delays than the delays that are typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" properties). Historically, the EtherAVB driver configured these delays based on the "rgmii-*id" PHY mode. This was wrong, as these are meant solely for the PHY, not for the MAC. Hence properties were introduced for explicit configuration of these delays. Convert the RZ/G2 DTS files from the old to the new scheme: - Add default "rx-internal-delay-ps" and "tx-internal-delay-ps" properties to the SoC .dtsi files, to be overridden by board files where needed, - Convert board files from "rgmii-*id" PHY modes to "rgmii", adding the appropriate "rx-internal-delay-ps" and/or "tx-internal-delay-ps" overrides. Notes: - RZ/G2E does not support TX internal delay handling. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200819134344.27813-8-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 3 ++- arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 ++ 6 files changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 97272f5fa0ab..8ac167aa18f0 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -55,7 +55,8 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1800>; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi index b9e46aed5336..202c4fc88bd5 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi @@ -19,7 +19,7 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index c15f1c571eb0..d37ec42a1caa 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1115,6 +1115,8 @@ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 39a1a26ffb54..83523916d360 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -989,6 +989,8 @@ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index f27d9b2eb996..e0e54342cd4c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -960,6 +960,7 @@ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 9cbf963aa068..31ae3530cf3d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1212,6 +1212,8 @@ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From a511d8be4ea4c59b7eb2c65bd787b7bb90350893 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 20 Sep 2020 14:49:04 +0100 Subject: arm64: dts: renesas: cat874: Move connector node out of hd3ss3220 device Move connector node out of hd3ss3220 device in order to comply with usb connector bindings. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200920134905.4370-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 67 ++++++++++++++++++------- 1 file changed, 50 insertions(+), 17 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts index 26aee004a44e..ea87cb5a459c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -129,6 +129,29 @@ #clock-cells = <0>; clock-frequency = <74250000>; }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; }; &audio_clk_a { @@ -186,20 +209,19 @@ interrupt-parent = <&gpio6>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hd3ss3220_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; }; }; }; @@ -405,9 +427,20 @@ status = "okay"; usb-role-switch; - port { - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_ep>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; }; }; }; -- cgit v1.2.3 From ca8edef172109821aa100763e38d6d8d49bcdf56 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 20 Sep 2020 14:49:05 +0100 Subject: arm64: dts: renesas: beacon-renesom-baseboard: Move connector node out of hd3ss3220 device Move connector node out of hd3ss3220 device in order to comply with usb connector bindings. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200920134905.4370-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/beacon-renesom-baseboard.dtsi | 67 ++++++++++++++++------ 1 file changed, 50 insertions(+), 17 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 66c9153b3101..e66b5b36e489 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -223,6 +223,29 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; }; &audio_clk_a { @@ -427,20 +450,19 @@ interrupt-parent = <&gpio6>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hd3ss3220_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; }; }; }; @@ -714,9 +736,20 @@ status = "okay"; usb-role-switch; - port { - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_ep>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; }; }; }; -- cgit v1.2.3 From f8a1620cb59bbf5d2706290ab2de7021f4eece7c Mon Sep 17 00:00:00 2001 From: Eugeniu Rosca Date: Thu, 29 Oct 2020 14:37:40 +0100 Subject: arm64: dts: renesas: r8a77961: Add CAN{0,1} placeholder nodes With the same background and purpose as described in v4.20-rc1 commit 92bc66bfce99cd ("arm64: dts: renesas: r8a77965: Add CAN{0,1} placeholder nodes"), add can0 and can1 placeholder nodes. Signed-off-by: Eugeniu Rosca Link: https://lore.kernel.org/r/20201029133741.25721-1-erosca@de.adit-jv.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 9266c60f21fa..4b737c616257 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1019,6 +1019,16 @@ status = "disabled"; }; + can0: can@e6c30000 { + reg = <0 0xe6c30000 0 0x1000>; + /* placeholder */ + }; + + can1: can@e6c38000 { + reg = <0 0xe6c38000 0 0x1000>; + /* placeholder */ + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 8>; -- cgit v1.2.3 From dd8ecc02743cc337ab56014448bacaa763c33074 Mon Sep 17 00:00:00 2001 From: Eugeniu Rosca Date: Thu, 29 Oct 2020 14:37:41 +0100 Subject: arm64: dts: renesas: r8a77961: ulcb-kf: Initial device tree Create a dedicated DTB for M3-ES3.0 + ULCB + Kingfisher combo. Inspire from the pre-existing ULCB-KF device trees: $ ls -1 arch/arm64/boot/dts/renesas/*ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a77951-ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a77960-ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a77965-ulcb-kf.dts Signed-off-by: Eugeniu Rosca Link: https://lore.kernel.org/r/20201029133741.25721-2-erosca@de.adit-jv.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 2b043b59c669..3b8b03705917 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb.dtb +dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts new file mode 100644 index 000000000000..6ec958348eb0 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the M3ULCB Kingfisher board + * + * Copyright (C) 2020 Eugeniu Rosca + */ + +#include "r8a77961-ulcb.dts" +#include "ulcb-kf.dtsi" + +/ { + model = "Renesas M3ULCB Kingfisher board based on r8a77961"; + compatible = "shimafuji,kingfisher", "renesas,m3ulcb", + "renesas,r8a77961"; +}; -- cgit v1.2.3 From 43bba65761952f58e850d918ee43b648427609bb Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 5 Nov 2020 12:11:27 +0000 Subject: arm64: dts: renesas: hihope-rev4: Add a comment explaining switch SW2404 Switch SW2404 should be at position 1 so that the clock output from CS2000 is connected to AUDIO_CLKB_A. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20201105121127.11830-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/hihope-rev4.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi index 3046c07a288b..929f4a1d3f90 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi @@ -91,7 +91,11 @@ #clock-cells = <1>; clock-frequency = <12288000 11289600>; - /* update to */ + /* + * Update to + * Switch SW2404 should be at position 1 so that clock from + * CS2000 is connected to AUDIO_CLKB_A + */ clocks = <&cpg CPG_MOD 1005>, <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, -- cgit v1.2.3 From 7e5258b0b79d8be916abd064b5f4aa2715580478 Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Mon, 9 Nov 2020 11:47:28 -0700 Subject: arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable split pagetables and per-instance pagetables for drm/msm. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201109184728.2463097-5-jcrouse@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 9 +++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 64fc1bfd66fa..39f23cdcbd02 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -633,6 +633,15 @@ ap_ts_i2c: &i2c14 { status = "okay"; }; +/* + * Cheza fw does not properly program the GPU aperture to allow the + * GPU to update the SMMU pagetables for context switches. Work + * around this by dropping the "qcom,adreno-smmu" compat string. + */ +&adreno_smmu { + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; +}; + &mss_pil { iommus = <&apps_smmu 0x781 0x0>, <&apps_smmu 0x724 0x3>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index aca7e9c954e0..895e7038cdc6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4106,7 +4106,7 @@ }; adreno_smmu: iommu@5040000 { - compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; + compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; reg = <0 0x5040000 0 0x10000>; #iommu-cells = <1>; #global-interrupts = <2>; -- cgit v1.2.3 From c42c3f05faa072d7833fc37b92f3c117128ca98a Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sat, 5 Sep 2020 13:04:26 -0700 Subject: arm: dts: qcom: sc7180: Set the compatible string for the GPU SMMU Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable split pagetables and per-instance pagetables for drm/msm. Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20200905200454.240929-21-robdclark@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f5ef2cb6e68c..861abc399de9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2062,7 +2062,7 @@ }; adreno_smmu: iommu@5040000 { - compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; + compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; reg = <0 0x05040000 0 0x10000>; #iommu-cells = <1>; #global-interrupts = <2>; -- cgit v1.2.3 From d45d3621d679ce74b555bc79bab9055b6f7edb61 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:45:06 +0100 Subject: arm64: dts: exynos: use hyphens in Exynos5433 node names Use hyphens instead of underscores in the Exynos5433 node names which is expected by naming convention, multiple dtschema files and pointed out by dtc W=2 builds. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201105184506.215648-6-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi | 10 +++++----- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 4 ++-- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 8 ++++---- 3 files changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi index d77b88af9582..8997f8f2b96c 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi @@ -87,7 +87,7 @@ status = "disabled"; }; - bus_g2d_400_opp_table: opp_table2 { + bus_g2d_400_opp_table: opp-table2 { compatible = "operating-points-v2"; opp-shared; @@ -117,7 +117,7 @@ }; }; - bus_g2d_266_opp_table: opp_table3 { + bus_g2d_266_opp_table: opp-table3 { compatible = "operating-points-v2"; opp-267000000 { @@ -137,7 +137,7 @@ }; }; - bus_gscl_opp_table: opp_table4 { + bus_gscl_opp_table: opp-table4 { compatible = "operating-points-v2"; opp-333000000 { @@ -151,7 +151,7 @@ }; }; - bus_hevc_opp_table: opp_table5 { + bus_hevc_opp_table: opp-table5 { compatible = "operating-points-v2"; opp-shared; @@ -175,7 +175,7 @@ }; }; - bus_noc2_opp_table: opp_table6 { + bus_noc2_opp_table: opp-table6 { compatible = "operating-points-v2"; opp-400000000 { diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 5ec447f0cf5d..03486a8ffc67 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -860,7 +860,7 @@ muic: max77843-muic { compatible = "maxim,max77843-muic"; - musb_con: musb_connector { + musb_con: musb-connector { compatible = "samsung,usb-connector-11pin", "usb-b-connector"; label = "micro-USB"; @@ -1083,7 +1083,7 @@ PIN(INPUT, gpf5-7, DOWN, FAST_SR1); }; - te_irq: te_irq { + te_irq: te-irq { samsung,pins = "gpf1-3"; samsung,pin-function = <0xf>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 7853a908fe39..dae44be09a09 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -23,7 +23,7 @@ interrupt-parent = <&gic>; - arm_a53_pmu { + arm-a53-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = , , @@ -32,7 +32,7 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; - arm_a57_pmu { + arm-a57-pmu { compatible = "arm,cortex-a57-pmu"; interrupts = , , @@ -137,7 +137,7 @@ }; }; - cluster_a53_opp_table: opp_table0 { + cluster_a53_opp_table: opp-table0 { compatible = "operating-points-v2"; opp-shared; @@ -183,7 +183,7 @@ }; }; - cluster_a57_opp_table: opp_table1 { + cluster_a57_opp_table: opp-table1 { compatible = "operating-points-v2"; opp-shared; -- cgit v1.2.3 From 876553576f27506760b44fbd7bb18a9cee650706 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 7 Nov 2020 00:08:27 +0530 Subject: arm64: dts: sc7180: Add camera clock controller node Add the camera clock controller node supported on SC7180. Reviewed-by: Douglas Anderson Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/1604687907-25712-1-git-send-email-tdas@codeaurora.org [bjorn: Dropped camcc include] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 861abc399de9..3a407d27d0d2 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2896,6 +2896,18 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + camcc: clock-controller@ad00000 { + compatible = "qcom,sc7180-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_XO_CLK>; + clock-names = "bi_tcxo", "iface", "xo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: mdss@ae00000 { compatible = "qcom,sc7180-mdss"; reg = <0 0x0ae00000 0 0x1000>; -- cgit v1.2.3 From ef9a5d188d663753e73a3c8e8910ceab8e9305c4 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 15 Oct 2020 23:57:56 +0530 Subject: arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region The modem firmware memory requirements vary between 32M/140M on no-lte/lte skus respectively, so fixup the modem memory region to reflect the requirements. Reviewed-by: Evan Green Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/1602786476-27833-1-git-send-email-sibis@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi index 44956e3165a1..469aad4e5948 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi @@ -9,6 +9,10 @@ label = "proximity-wifi-lte"; }; +&mpss_mem { + reg = <0x0 0x86000000 0x0 0x8c00000>; +}; + &remoteproc_mpss { firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn", "qcom/sc7180-trogdor/modem/qdsp6sw.mbn"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 8653a38a3e42..781e61ad75a6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -39,7 +39,7 @@ }; mpss_mem: memory@86000000 { - reg = <0x0 0x86000000 0x0 0x8c00000>; + reg = <0x0 0x86000000 0x0 0x2000000>; no-map; }; -- cgit v1.2.3 From 77e9c198b1558f51092eaaaed59ec68a552f990e Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Fri, 16 Oct 2020 17:08:33 +0800 Subject: arm64: dts: qcom: clear the warnings caused by empty dma-ranges The scripts/dtc/checks.c requires that the node have empty "dma-ranges" property must have the same "#address-cells" and "#size-cells" values as the parent node. Otherwise, the following warnings is reported: arch/arm64/boot/dts/qcom/ipq6018.dtsi:185.3-14: Warning \ (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but \ its #address-cells (1) differs from / (2) arch/arm64/boot/dts/qcom/ipq6018.dtsi:185.3-14: Warning \ (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but \ its #size-cells (1) differs from / (2) Arnd Bergmann figured out why it's necessary: Also note that the #address-cells=<1> means that any device under this bus is assumed to only support 32-bit addressing, and DMA will have to go through a slow swiotlb in the absence of an IOMMU. Suggested-by: Arnd Bergmann Reviewed-by: Bjorn Andersson Signed-off-by: Zhen Lei Link: https://lore.kernel.org/r/20201016090833.1892-3-thunder.leizhen@huawei.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 72 +++++++++++++++++------------------ 1 file changed, 36 insertions(+), 36 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 973b2c860ec9..cdc1e3d60c58 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -179,22 +179,22 @@ }; soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x0 0xffffffff>; dma-ranges; compatible = "simple-bus"; prng: qrng@e1000 { compatible = "qcom,prng-ee"; - reg = <0xe3000 0x1000>; + reg = <0x0 0xe3000 0x0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; cryptobam: dma@704000 { compatible = "qcom,bam-v1.7.0"; - reg = <0x00704000 0x20000>; + reg = <0x0 0x00704000 0x0 0x20000>; interrupts = ; clocks = <&gcc GCC_CRYPTO_AHB_CLK>; clock-names = "bam_clk"; @@ -206,7 +206,7 @@ crypto: crypto@73a000 { compatible = "qcom,crypto-v5.1"; - reg = <0x0073a000 0x6000>; + reg = <0x0 0x0073a000 0x0 0x6000>; clocks = <&gcc GCC_CRYPTO_AHB_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_CLK>; @@ -217,7 +217,7 @@ tlmm: pinctrl@1000000 { compatible = "qcom,ipq6018-pinctrl"; - reg = <0x01000000 0x300000>; + reg = <0x0 0x01000000 0x0 0x300000>; interrupts = ; gpio-controller; #gpio-cells = <2>; @@ -235,7 +235,7 @@ gcc: gcc@1800000 { compatible = "qcom,gcc-ipq6018"; - reg = <0x01800000 0x80000>; + reg = <0x0 0x01800000 0x0 0x80000>; clocks = <&xo>, <&sleep_clk>; clock-names = "xo", "sleep_clk"; #clock-cells = <1>; @@ -244,17 +244,17 @@ tcsr_mutex_regs: syscon@1905000 { compatible = "syscon"; - reg = <0x01905000 0x8000>; + reg = <0x0 0x01905000 0x0 0x8000>; }; tcsr_q6: syscon@1945000 { compatible = "syscon"; - reg = <0x01945000 0xe000>; + reg = <0x0 0x01945000 0x0 0xe000>; }; blsp_dma: dma@7884000 { compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x2b000>; + reg = <0x0 0x07884000 0x0 0x2b000>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "bam_clk"; @@ -264,7 +264,7 @@ blsp1_uart3: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b1000 0x200>; + reg = <0x0 0x078b1000 0x0 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -276,7 +276,7 @@ compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x078b5000 0x600>; + reg = <0x0 0x078b5000 0x0 0x600>; interrupts = ; spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, @@ -291,7 +291,7 @@ compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x078b6000 0x600>; + reg = <0x0 0x078b6000 0x0 0x600>; interrupts = ; spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, @@ -306,7 +306,7 @@ compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x078b6000 0x600>; + reg = <0x0 0x078b6000 0x0 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; @@ -321,7 +321,7 @@ compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x078b7000 0x600>; + reg = <0x0 0x078b7000 0x0 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; @@ -336,24 +336,24 @@ compatible = "qcom,msm-qgic2"; interrupt-controller; #interrupt-cells = <0x3>; - reg = <0x0b000000 0x1000>, /*GICD*/ - <0x0b002000 0x1000>, /*GICC*/ - <0x0b001000 0x1000>, /*GICH*/ - <0x0b004000 0x1000>; /*GICV*/ + reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ + <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ + <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ + <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ interrupts = ; }; watchdog@b017000 { compatible = "qcom,kpss-wdt"; interrupts = ; - reg = <0x0b017000 0x40>; + reg = <0x0 0x0b017000 0x0 0x40>; clocks = <&sleep_clk>; timeout-sec = <10>; }; apcs_glb: mailbox@b111000 { compatible = "qcom,ipq6018-apcs-apps-global"; - reg = <0x0b111000 0x1000>; + reg = <0x0 0x0b111000 0x0 0x1000>; #clock-cells = <1>; clocks = <&a53pll>, <&xo>; clock-names = "pll", "xo"; @@ -362,7 +362,7 @@ a53pll: clock@b116000 { compatible = "qcom,ipq6018-a53pll"; - reg = <0x0b116000 0x40>; + reg = <0x0 0x0b116000 0x0 0x40>; #clock-cells = <0>; clocks = <&xo>; clock-names = "xo"; @@ -377,68 +377,68 @@ }; timer@b120000 { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; compatible = "arm,armv7-timer-mem"; - reg = <0x0b120000 0x1000>; + reg = <0x0 0x0b120000 0x0 0x1000>; clock-frequency = <19200000>; frame@b120000 { frame-number = <0>; interrupts = , ; - reg = <0x0b121000 0x1000>, - <0x0b122000 0x1000>; + reg = <0x0 0x0b121000 0x0 0x1000>, + <0x0 0x0b122000 0x0 0x1000>; }; frame@b123000 { frame-number = <1>; interrupts = ; - reg = <0xb123000 0x1000>; + reg = <0x0 0xb123000 0x0 0x1000>; status = "disabled"; }; frame@b124000 { frame-number = <2>; interrupts = ; - reg = <0x0b124000 0x1000>; + reg = <0x0 0x0b124000 0x0 0x1000>; status = "disabled"; }; frame@b125000 { frame-number = <3>; interrupts = ; - reg = <0x0b125000 0x1000>; + reg = <0x0 0x0b125000 0x0 0x1000>; status = "disabled"; }; frame@b126000 { frame-number = <4>; interrupts = ; - reg = <0x0b126000 0x1000>; + reg = <0x0 0x0b126000 0x0 0x1000>; status = "disabled"; }; frame@b127000 { frame-number = <5>; interrupts = ; - reg = <0x0b127000 0x1000>; + reg = <0x0 0x0b127000 0x0 0x1000>; status = "disabled"; }; frame@b128000 { frame-number = <6>; interrupts = ; - reg = <0x0b128000 0x1000>; + reg = <0x0 0x0b128000 0x0 0x1000>; status = "disabled"; }; }; q6v5_wcss: remoteproc@cd00000 { compatible = "qcom,ipq8074-wcss-pil"; - reg = <0x0cd00000 0x4040>, - <0x004ab000 0x20>; + reg = <0x0 0x0cd00000 0x0 0x4040>, + <0x0 0x004ab000 0x0 0x20>; reg-names = "qdsp6", "rmb"; interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, -- cgit v1.2.3 From ba73ce9d9ac581c152be92bf22d08d7b78531583 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Fri, 6 Nov 2020 14:01:32 -0800 Subject: arm64: dts: qcom: sc7180: Add sc7180-lazor-r2/r3 Add configs for lazor rev2 and rev3. There are no relevant deltas between rev1 and rev2, so just add the rev2 compatible string to the rev1 config. One important delta in rev3 is a switch of the power supply for the onboard USB hub from 'pp3300_l7c' to 'pp3300_a' + a load switch. The actual regulator switch is done by the patch 'arm64: dts: qcom: sc7180-trogdor: Make pp3300_a the default supply for pp3300_hub', since it affects the entire trogdor platform. Here we only add the .dts files for lazor rev3 and replace the generic compatible entries in the rev1 .dts files. Reviewed-by: Douglas Anderson Signed-off-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/20201106140125.v3.1.I5a75056d573808f40fed22ab7d28ea6be5819f84@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 3 +++ .../arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts | 4 ++-- .../boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts | 4 ++-- .../arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts | 17 +++++++++++++++++ .../boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts | 15 +++++++++++++++ 7 files changed, 59 insertions(+), 6 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index fb4631f898fd..3573f7a7b762 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -26,6 +26,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts index c3f426c3c30a..919bfaea6189 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts @@ -8,8 +8,8 @@ #include "sc7180-trogdor-lazor-r1.dts" / { - model = "Google Lazor (rev1+) with KB Backlight"; - compatible = "google,lazor-sku2", "qcom,sc7180"; + model = "Google Lazor (rev1 - 2) with KB Backlight"; + compatible = "google,lazor-rev1-sku2", "google,lazor-rev2-sku2", "qcom,sc7180"; }; &keyboard_backlight { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts index 73e59cf7752a..5a67e5baafec 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts @@ -9,8 +9,8 @@ #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google Lazor (rev1+) with LTE"; - compatible = "google,lazor-sku0", "qcom,sc7180"; + model = "Google Lazor (rev1 - 2) with LTE"; + compatible = "google,lazor-rev1-sku0", "google,lazor-rev2-sku0", "qcom,sc7180"; }; &keyboard_backlight { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts index 3151ae31c1cc..9354d4c5ef7d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts @@ -10,6 +10,6 @@ #include "sc7180-trogdor-lazor.dtsi" / { - model = "Google Lazor (rev1+)"; - compatible = "google,lazor", "qcom,sc7180"; + model = "Google Lazor (rev1 - 2)"; + compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts new file mode 100644 index 000000000000..6985beb97e53 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +#include "sc7180-trogdor-lazor-r3.dts" + +/ { + model = "Google Lazor (rev3+) with KB Backlight"; + compatible = "google,lazor-sku2", "qcom,sc7180"; +}; + +&keyboard_backlight { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts new file mode 100644 index 000000000000..43836fc4d403 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +#include "sc7180-trogdor-lazor-r3.dts" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Lazor (rev3+) with LTE"; + compatible = "google,lazor-sku0", "qcom,sc7180"; +}; + +&keyboard_backlight { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts new file mode 100644 index 000000000000..1b9d2f46359e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor-lazor.dtsi" + +/ { + model = "Google Lazor (rev3+)"; + compatible = "google,lazor", "qcom,sc7180"; +}; -- cgit v1.2.3 From 2315ae70af95589e67d8d119c3b3fcaa8746dae8 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Fri, 30 Oct 2020 16:17:11 +0530 Subject: arm64: dts: qcom: sc7180: Add gpu cooling support Add cooling-cells property and the cooling maps for the gpu tzones to support GPU cooling. Signed-off-by: Akhil P Oommen Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1604054832-3114-2-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 3a407d27d0d2..4e7e58c63285 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2,7 +2,7 @@ /* * SC7180 SoC device tree source * - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -2011,6 +2011,8 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + #cooling-cells = <2>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; @@ -4037,16 +4039,16 @@ }; gpuss0-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { gpuss0_alert0: trip-point0 { - temperature = <90000>; + temperature = <95000>; hysteresis = <2000>; - type = "hot"; + type = "passive"; }; gpuss0_crit: gpuss0_crit { @@ -4055,19 +4057,26 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss1-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens0 14>; trips { gpuss1_alert0: trip-point0 { - temperature = <90000>; + temperature = <95000>; hysteresis = <2000>; - type = "hot"; + type = "passive"; }; gpuss1_crit: gpuss1_crit { @@ -4076,6 +4085,13 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; aoss1-thermal { -- cgit v1.2.3 From 183d4cafa711acd4ca2b1d682c8b867d549f2bc4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:01 +0200 Subject: arm64: dts: qcom: pm8994: Add VADC node Add VADC note and some of its channels to allow for voltage/temperature reading. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-2-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8994.dtsi | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 7e4f777746cb..ea2a3d53f859 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 +#include +#include #include #include -#include &spmi_bus { @@ -35,6 +36,39 @@ }; + pm8994_vadc: adc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@7 { + reg = ; + qcom,pre-scaling = <1 3>; + label = "vph_pwr"; + }; + adc-chan@8 { + reg = ; + label = "die_temp"; + }; + adc-chan@9 { + reg = ; + label = "ref_625mv"; + }; + adc-chan@a { + reg = ; + label = "ref_1250mv"; + }; + adc-chan@e { + reg = ; + }; + adc-chan@f { + reg = ; + }; + }; + pm8994_gpios: gpios@c000 { compatible = "qcom,pm8994-gpio"; reg = <0xc000>; -- cgit v1.2.3 From 4778b2f1a3f0c97caa184a695b308b874cb2d3cd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:02 +0200 Subject: arm64: dts: qcom: pm8994: Add temperature alarm node Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-3-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8994.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index ea2a3d53f859..7825208b0d8b 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -36,6 +36,15 @@ }; + pm8994_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8994_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + pm8994_vadc: adc@3100 { compatible = "qcom,spmi-vadc"; reg = <0x3100>; -- cgit v1.2.3 From 0763f58540419874ebeb25eb9869638666d62ed4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:03 +0200 Subject: arm64: dts: qcom: pm8994: Add thermal-zones for temp alarm This will shut down the platform in case the PMIC overheats. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-4-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8994.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 7825208b0d8b..9ab5657f7d23 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -4,6 +4,30 @@ #include #include +/ { + thermal-zones { + pm8994 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&pm8994_temp>; + + trips { + pm8994_alert0: pm8994-alert0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + pm8994_crit: pm8994-crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pmic@0 { -- cgit v1.2.3 From 8939304880dee9c57b7bd41e4679d4741a85d6e7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:04 +0200 Subject: arm64: dts: qcom: pm8994: Fix up spmi-gpio node Add a common compatible and switch to gpio-ranges. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-5-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8994.dtsi | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 9ab5657f7d23..5ffdf37d8e31 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -103,32 +103,13 @@ }; pm8994_gpios: gpios@c000 { - compatible = "qcom,pm8994-gpio"; + compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8994_gpios 0 0 22>; #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>, - <0 0xc4 0 IRQ_TYPE_NONE>, - <0 0xc5 0 IRQ_TYPE_NONE>, - <0 0xc6 0 IRQ_TYPE_NONE>, - <0 0xc7 0 IRQ_TYPE_NONE>, - <0 0xc8 0 IRQ_TYPE_NONE>, - <0 0xc9 0 IRQ_TYPE_NONE>, - <0 0xca 0 IRQ_TYPE_NONE>, - <0 0xcb 0 IRQ_TYPE_NONE>, - <0 0xcc 0 IRQ_TYPE_NONE>, - <0 0xcd 0 IRQ_TYPE_NONE>, - <0 0xce 0 IRQ_TYPE_NONE>, - <0 0xcf 0 IRQ_TYPE_NONE>, - <0 0xd0 0 IRQ_TYPE_NONE>, - <0 0xd1 0 IRQ_TYPE_NONE>, - <0 0xd2 0 IRQ_TYPE_NONE>, - <0 0xd3 0 IRQ_TYPE_NONE>, - <0 0xd4 0 IRQ_TYPE_NONE>, - <0 0xd5 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; pm8994_mpps: mpps@a000 { -- cgit v1.2.3 From 211ea9b34919bfbab208073a675d15ec68156dc9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:05 +0200 Subject: arm64: dts: qcom: msm8992: Add support for SDHCI2 This will let us use SD cards on our devices. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-6-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 59 +++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 8626b3a50eda..6242c56a2bfa 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -269,6 +269,29 @@ status = "disabled"; }; + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + cd-gpios = <&tlmm 100 0>; + bus-width = <4>; + status = "disabled"; + }; + blsp1_uart2: serial@f991e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991e000 0x1000>; @@ -573,6 +596,42 @@ drive-strength = <2>; bias-disable; }; + + sdc2_clk_on: sdc2-clk-on { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + sdc2_clk_off: sdc2-clk-off { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_data_on: sdc2-data-on { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_data_off: sdc2-data-off { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; }; }; -- cgit v1.2.3 From f3d1939f115d696acf61f24d97443b42408d2449 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:06 +0200 Subject: arm64: dts: qcom: msm8994: Add SDHCI2 node Add SDHCI2 to enable use of uSD cards on msm8994. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-7-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 59 +++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 6707f898607f..65089d7670f6 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -305,6 +305,29 @@ status = "disabled"; }; + sdhc2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + cd-gpios = <&tlmm 100 0>; + bus-width = <4>; + status = "disabled"; + }; + blsp1_dma: dma@f9904000 { compatible = "qcom,bam-v1.7.0"; reg = <0xf9904000 0x19000>; @@ -683,6 +706,42 @@ pins = "sdc1_rclk"; bias-pull-down; }; + + sdc2_clk_on: sdc2-clk-on { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <10>; + }; + + sdc2_clk_off: sdc2-clk-off { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_data_on: sdc2-data-on { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_data_off: sdc2-data-off { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; }; }; -- cgit v1.2.3 From b97def9c0557a9354c718b13d09a81f26e128129 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:07 +0200 Subject: arm64: dts: qcom: msm8992: Add BLSP_I2C1 support This will be required to support touchscreen on Lumia devices. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-8-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 6242c56a2bfa..81426577f2bd 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -305,6 +305,22 @@ status = "disabled"; }; + blsp_i2c1: i2c@f9923000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9923000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_i2c2: i2c@f9924000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9924000 0x500>; @@ -525,6 +541,20 @@ bias-pull-down; }; + i2c1_default: i2c1-default { + function = "blsp_i2c1"; + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + + i2c1_sleep: i2c1-sleep { + function = "gpio"; + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + i2c2_default: i2c2-default { function = "blsp_i2c2"; pins = "gpio6", "gpio7"; -- cgit v1.2.3 From a0b3e3629748f1535f4945f213134182fc008160 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:08 +0200 Subject: arm64: dts: qcom: talkman: Add Synaptics RMI4 touchscreen This adds touchscreen capabilities to the Lumia 950. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-9-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8992-msft-lumia-talkman.dts | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts index 3cc01f02219d..c337a86a5c77 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts @@ -32,6 +32,34 @@ }; }; +&blsp_i2c1 { + status = "okay"; + + rmi4-i2c-dev@4b { + compatible = "syna,rmi4-i2c"; + reg = <0x4b>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + syna,clip-x-low = <0>; + syna,clip-x-high = <1440>; + syna,clip-y-low = <0>; + syna,clip-y-high = <2560>; + }; + }; +}; + &sdhc_1 { status = "okay"; -- cgit v1.2.3 From d9be0bc95f25d49ae260b9ad8ad9040931758fbd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:09 +0200 Subject: arm64: dts: qcom: msm8994: Add USB support This is a very basic dwc3 configuration (no PHYs yet), but it works. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-10-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 65089d7670f6..8612a11c3584 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -282,6 +282,37 @@ }; }; + usb3: usb@f92f8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0xf92f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; + + dwc3@f9200000 { + compatible = "snps,dwc3"; + reg = <0xf9200000 0xcc00>; + interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + sdhc1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; -- cgit v1.2.3 From 1865bb197843e19e3a0f949a3c88b06a8d7abd94 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:10 +0200 Subject: arm64: dts: qcom: msm8992: Add USB support This is a very basic dwc3 configuration (no PHYs yet), but it works. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-11-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 81426577f2bd..0c422af47917 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -242,6 +242,37 @@ }; }; + usb3: usb@f92f8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0xf92f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; + + dwc3@f9200000 { + compatible = "snps,dwc3"; + reg = <0xf9200000 0xcc00>; + interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + sdhc_1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; -- cgit v1.2.3 From 2704ff5f02c884bd4b774da089d139f17f8e32ae Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:11 +0200 Subject: arm64: dts: qcom: Add support for Microsoft Lumia 950 XL (Cityman) Add device tree support for Microsoft Lumia 950 XL smartphone. It is based on the msm8994 chipset and is able to boot Linux using a custom EDK2 implementation. EL2 core startup is possible with spin-table, but for now, we'll stick with PSCI. The board currently supports: * Screen console via EFIFB * SDHCI * I2C * UART * PSCI core bringup Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-12-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8994-msft-lumia-cityman.dts | 73 ++++++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 3573f7a7b762..90887aac28e2 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-talkman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-cityman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts new file mode 100644 index 000000000000..ed9034b96013 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "msm8994.dtsi" +#include "pm8994.dtsi" +#include "pmi8994.dtsi" + +/ { + model = "Microsoft Lumia 950 XL"; + compatible = "microsoft,cityman", "qcom,msm8994"; + + /* + * Most Lumia 950XL users use GRUB to load their kernels, + * hence there is no need for msm-id and friends. + */ + + /* + * This enables graphical output via bootloader-enabled display. + * acpi=no is required due to WP platforms having ACPI support, but + * only for Windows-based OSes. + */ + chosen { + bootargs = "earlycon=efifb console=efifb acpi=no"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; +}; + +&blsp_i2c1 { + status = "okay"; + + rmi4-i2c-dev@4b { + compatible = "syna,rmi4-i2c"; + reg = <0x4b>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + syna,clip-x-low = <0>; + syna,clip-x-high = <1440>; + syna,clip-y-low = <0>; + syna,clip-y-high = <2660>; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_uart2 { + status = "okay"; +}; + +&sdhc1 { + status = "okay"; +}; -- cgit v1.2.3 From a8fbc8bd8d1f8d4143c164e5f31704dd37baa386 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:03 +0530 Subject: arm64: dts: sdm845: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 895e7038cdc6..6465a6653ad9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4487,7 +4487,7 @@ }; }; - slimbam: dma@17184000 { + slimbam: dma-controller@17184000 { compatible = "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0 0x17184000 0 0x2a000>; -- cgit v1.2.3 From b831fba3b0e184930747761adc9fdaccc3c49ff4 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:04 +0530 Subject: arm64: dts: sdm630: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-3-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index deb928d303c2..37d5cc32f6b6 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -830,7 +830,7 @@ status = "disabled"; }; - blsp1_dma: dma@c144000 { + blsp1_dma: dma-controller@c144000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0c144000 0x1f000>; interrupts = ; @@ -944,7 +944,7 @@ status = "disabled"; }; - blsp2_dma: dma@c184000 { + blsp2_dma: dma-controller@c184000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0c184000 0x1f000>; interrupts = ; -- cgit v1.2.3 From 6bd61ef47eaec2775b8444dde80ae672bb797717 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:05 +0530 Subject: arm64: dts: qcs404: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-4-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index b654b802e95c..339790ba585d 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -801,7 +801,7 @@ status = "disabled"; }; - blsp1_dma: dma@7884000 { + blsp1_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07884000 0x25000>; interrupts = ; @@ -1045,7 +1045,7 @@ status = "disabled"; }; - blsp2_dma: dma@7ac4000 { + blsp2_dma: dma-controller@7ac4000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07ac4000 0x17000>; interrupts = ; -- cgit v1.2.3 From eaf61213901d2b9a4040f217498ecbea61f8e0a5 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:06 +0530 Subject: arm64: dts: msm8916: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-5-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 74aa50f3db10..402e891a84ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1425,7 +1425,7 @@ status = "disabled"; }; - blsp_dma: dma@7884000 { + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07884000 0x23000>; interrupts = ; -- cgit v1.2.3 From 828896c562339292f5b7c04dc95a9e8ea150544f Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:07 +0530 Subject: arm64: dts: msm8994: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-6-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 8612a11c3584..6e083a2f690b 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -359,7 +359,7 @@ status = "disabled"; }; - blsp1_dma: dma@f9904000 { + blsp1_dma: dma-controller@f9904000 { compatible = "qcom,bam-v1.7.0"; reg = <0xf9904000 0x19000>; interrupts = ; @@ -455,7 +455,7 @@ status = "disabled"; }; - blsp2_dma: dma@f9944000 { + blsp2_dma: dma-controller@f9944000 { compatible = "qcom,bam-v1.7.0"; reg = <0xf9944000 0x19000>; interrupts = ; -- cgit v1.2.3 From b5af3036e84c801416b699930b2b578fbe755cd1 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:08 +0530 Subject: arm64: dts: msm8996: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-7-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index fd6ae5464dea..7eef07e73e25 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1990,7 +1990,7 @@ }; }; - slimbam: dma@9184000 { + slimbam: dma-controller@9184000 { compatible = "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0x09184000 0x32000>; -- cgit v1.2.3 From 94ed1811aff0c4027d877d2ecf66da0d62369d99 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:09 +0530 Subject: arm64: dts: msm8998: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-8-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index c45870600909..ebdaaf1dfca4 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1754,7 +1754,7 @@ status = "disabled"; }; - blsp1_dma: dma@c144000 { + blsp1_dma: dma-controller@c144000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0c144000 0x25000>; interrupts = ; -- cgit v1.2.3 From 58acbcdcdc33c9c7b8601b5057a272009e4fe2f6 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:10 +0530 Subject: arm64: dts: ipq6018: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-9-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index cdc1e3d60c58..540460457420 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -192,7 +192,7 @@ clock-names = "core"; }; - cryptobam: dma@704000 { + cryptobam: dma-controller@704000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x00704000 0x0 0x20000>; interrupts = ; @@ -252,7 +252,7 @@ reg = <0x0 0x01945000 0x0 0xe000>; }; - blsp_dma: dma@7884000 { + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x07884000 0x0 0x2b000>; interrupts = ; -- cgit v1.2.3 From b7fbf46cb81c2bb432d648f52e4cd591a09593bc Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:11 +0530 Subject: arm64: dts: ipq8074: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-10-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 829e37ac82f6..a32e5e79ab0b 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -276,7 +276,7 @@ status = "disabled"; }; - blsp_dma: dma@7884000 { + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07884000 0x2b000>; interrupts = ; @@ -372,7 +372,7 @@ status = "disabled"; }; - qpic_bam: dma@7984000 { + qpic_bam: dma-controller@7984000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07984000 0x1a000>; interrupts = ; -- cgit v1.2.3 From ead9f7d7ea9e20843e29e688b53859cea20044ee Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 11 Nov 2020 07:37:01 -0800 Subject: arm64: dts: qcom: sc7180: Assign numbers to eMMC and SD After many years of struggle, commit fa2d0aa96941 ("mmc: core: Allow setting slot index via device tree alias") finally allows the use of aliases to number SD/MMC slots. Let's do that for sc7180 SoCs so that if eMMC and SD are both used they have consistent numbers across boots and kernel changes. Picking numbers can be tricky. Do we call these "1" and "2" to match the name in documentation or "0" and "1" with the assertion that we should always start at 0 and count up? While the "start counting at 0" makes sense if there are not already well-defined numbers for all sd/mmc controllers, in the case of sc7180 there _are_ well defined numbers. IMO it is less confusing to use those and match the docs. Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20201111073652.1.Ia5bccd9eab7d74ea1ea9a7780e3cdbf662f5a464@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 4e7e58c63285..625e922c273d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -31,6 +31,8 @@ chosen { }; aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; -- cgit v1.2.3 From 50301e8815c681bc5de8ca7050c4b426923d4e19 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Mon, 2 Nov 2020 15:46:50 +0200 Subject: arm64: dts: ti: k3-am65: mark dss as dma-coherent DSS is IO coherent on AM65, so we should mark it as such with 'dma-coherent' property in the DT file. Fixes: fc539b90eda2 ("arm64: dts: ti: am654: Add DSS node") Signed-off-by: Tomi Valkeinen Signed-off-by: Nishanth Menon Acked-by: Nikhil Devshatwar Cc: stable@vger.kernel.org # v5.8+ Link: https://lore.kernel.org/r/20201102134650.55321-1-tomi.valkeinen@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 3eeb6e9876db..baa3f4c8f91e 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -866,6 +866,8 @@ status = "disabled"; + dma-coherent; + dss_ports: ports { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 5bb9e0f6e8505e31159963150104569d9b8a8911 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:37:55 -0500 Subject: arm64: dts: ti: k3-am65-mcu: Add MCU domain R5F cluster node The AM65x SoCs have a single dual-core Arm Cortex-R5F processor (R5FSS) subsystem/cluster. This R5F cluster (MCU_R5FSS0) is present within the MCU domain, and can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - TCMA and TCMB (further interleaved into two banks). There are some IP integration differences from standard Arm R5F clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for this R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A53 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: am65x-mcu-r5f0_0-fw (LockStep mode and for Core0 in Split mode) am65x-mcu-r5f0_1-fw (Core1 in Split mode) Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-2-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 42 ++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 044042b166d9..7454c8cec0cc 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for AM6 SoC Family MCU Domain peripherals * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { @@ -268,4 +268,44 @@ }; }; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,am654-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,am654-r5f"; + reg = <0x41000000 0x00008000>, + <0x41010000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <159>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 159 1>; + firmware-name = "am65x-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,am654-r5f"; + reg = <0x41400000 0x00008000>, + <0x41410000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <245>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 245 1>; + firmware-name = "am65x-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; }; -- cgit v1.2.3 From 10332cd6bcf287e22dac875d121b73adb762f96b Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:37:56 -0500 Subject: arm64: dts: ti: k3-am654-base-board: Add mailboxes to R5Fs Add the required 'mboxes' property to both the R5F processors on all the TI K3 AM65x boards. The mailboxes and some shared memory are required for running the Remote Processor Messaging (RPMsg) stack between the host processor and each of the R5Fs. The chosen sub-mailboxes match the values used in the current firmware images. This can be changed, if needed, as per the system integration needs after making appropriate changes on the firmware side as well. Note that the R5F Core1 resources are needed and used only when the R5F cluster is configured for Split-mode. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-3-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index d12dd89f3405..0cb5b9cb65ba 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -441,6 +441,14 @@ status = "disabled"; }; +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; -- cgit v1.2.3 From 954ec5139db091ff51cec4bf57c42f9deebc8747 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:37:57 -0500 Subject: arm64: dts: ti: k3-am654-base-board: Add DDR carveout memory nodes for R5Fs The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. Four carveout reserved memory nodes have been added with two each (1 MB and 15 MB in size) used for each of the MCU R5F remote processor devices on all the TI K3 AM65x boards. These nodes are assigned to the respective rproc device nodes as well. The current carveout addresses and sizes are defined statically for each device. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. Note that the R5F1 carveouts are needed only if the corresponding R5F cluster is running in Split (non-LockStep) mode. The corresponding reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-4-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 29 ++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 0cb5b9cb65ba..23a1f266d1d4 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -29,11 +29,36 @@ #address-cells = <2>; #size-cells = <2>; ranges; + secure_ddr: secure-ddr@9e800000 { reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ alignment = <0x1000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0 0xa0100000 0 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0 0xa1000000 0 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0 0xa1100000 0 0xf00000>; + no-map; + }; }; gpio-keys { @@ -442,10 +467,14 @@ }; &mcu_r5fss0_core0 { + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; }; -- cgit v1.2.3 From f82c5e0a8bc1311aee140bfed0888fc9a99afde0 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:37:58 -0500 Subject: arm64: dts: ti: k3-am654-base-board: Reserve memory for IPC between R5F cores Add a reserved memory node to reserve a portion of the DDR memory to be used for performing inter-processor communication between all the MCU R5F remote processors running RTOS on all the TI AM654 boards. This memory shall be exercised only if the MCU R5FSS cluster is configured for Split mode. A single 1 MB of memory at 0xa2000000 is reserved for this purpose, and this accounts for all the vrings and vring buffers between pair of these R5F remote processors. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-5-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 23a1f266d1d4..17f3a85360e6 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -59,6 +59,12 @@ reg = <0 0xa1100000 0 0xf00000>; no-map; }; + + rtos_ipc_memory_region: ipc-memories@a2000000 { + reg = <0x00 0xa2000000 0x00 0x00100000>; + alignment = <0x1000>; + no-map; + }; }; gpio-keys { -- cgit v1.2.3 From dd74c9459cf2c87c3143b4b9005b7c9056fccdb0 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:37:59 -0500 Subject: arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MCU R5FSS0 Core0: j7-mcu-r5f0_0-fw (both in LockStep and Split modes) MCU R5FSS0 Core1: j7-mcu-r5f0_1-fw (needed only in Split mode) Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-6-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 42 ++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index e581cb1d87ee..6c44afae9187 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -353,4 +353,44 @@ ti,cpts-periodic-outputs = <2>; }; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721e-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721e-r5f"; + reg = <0x41000000 0x00008000>, + <0x41010000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <250>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 250 1>; + firmware-name = "j7-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721e-r5f"; + reg = <0x41400000 0x00008000>, + <0x41410000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <251>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 251 1>; + firmware-name = "j7-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; }; -- cgit v1.2.3 From df445ff9de893146107d37e0cd5e542f800d9b39 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:38:00 -0500 Subject: arm64: dts: ti: k3-j721e-main: Add MAIN domain R5F cluster nodes The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT nodes for these two MAIN domain R5F cluster/subsystems, the two R5F cores are each added as child nodes to the corresponding main cluster node. Both the clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MAIN R5FSS0 Core0: j7-main-r5f0_0-fw (both in LockStep and Split modes) MAIN R5FSS0 Core1: j7-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: j7-main-r5f1_0-fw (both in LockStep and Split modes) MAIN R5FSS1 Core1: j7-main-r5f1_1-fw (needed only in Split mode) Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-7-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 82 ++++++++++++++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index e2a96b2c423c..b5cae2e03a09 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J721E SoC Family Main Domain peripherals * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ */ #include #include @@ -1581,6 +1581,86 @@ assigned-clock-parents = <&k3_clks 253 5>; }; + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j721e-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, + <0x5d00000 0x00 0x5d00000 0x20000>; + power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@5c00000 { + compatible = "ti,j721e-r5f"; + reg = <0x5c00000 0x00008000>, + <0x5c10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <245>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 245 1>; + firmware-name = "j7-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@5d00000 { + compatible = "ti,j721e-r5f"; + reg = <0x5d00000 0x00008000>, + <0x5d10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <246>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 246 1>; + firmware-name = "j7-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@5e00000 { + compatible = "ti,j721e-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5e00000 0x00 0x5e00000 0x20000>, + <0x5f00000 0x00 0x5f00000 0x20000>; + power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@5e00000 { + compatible = "ti,j721e-r5f"; + reg = <0x5e00000 0x00008000>, + <0x5e10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <247>; + ti,sci-proc-ids = <0x08 0xff>; + resets = <&k3_reset 247 1>; + firmware-name = "j7-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@5f00000 { + compatible = "ti,j721e-r5f"; + reg = <0x5f00000 0x00008000>, + <0x5f10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <248>; + ti,sci-proc-ids = <0x09 0xff>; + resets = <&k3_reset 248 1>; + firmware-name = "j7-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + c66_0: dsp@4d80800000 { compatible = "ti,j721e-c66-dsp"; reg = <0x4d 0x80800000 0x00 0x00048000>, -- cgit v1.2.3 From 2879b593c3784e5eafc67cae915d8b7d680455f3 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:38:01 -0500 Subject: arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to R5Fs Add the required 'mboxes' property to all the R5F processors for the TI J721E common processor board. The mailboxes and some shared memory are required for running the Remote Processor Messaging (RPMsg) stack between the host processor and each of the R5Fs. The nodes are therefore added in the common k3-j721e-som-p0.dtsi file so that all of these can be co-located. The chosen sub-mailboxes match the values used in the current firmware images. This can be changed, if needed, as per the system integration needs after making appropriate changes on the firmware side as well. Note that any R5F Core1 resources are needed and used only when that R5F cluster is configured for Split-mode. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-8-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 5dc3ba739131..c48f4ffd1435 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -208,6 +208,30 @@ status = "disabled"; }; +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; +}; + &c66_0 { mboxes = <&mailbox0_cluster3 &mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, -- cgit v1.2.3 From 0f191152bcba6758804eed4f6463f9bd32bdbfdb Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:38:02 -0500 Subject: arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for R5Fs Two carveout reserved memory nodes each have been added for each of the R5F remote processor devices within both the MCU and MAIN domains for the TI J721E EVM boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables either to allocate the memory for firmware memory segments. Note that the R5F1 carveouts are needed only if the R5F cluster is running in Split (non-LockStep) mode. The reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-9-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 84 +++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index c48f4ffd1435..57720e6a04c5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -26,6 +26,78 @@ no-map; }; + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + c66_1_dma_memory_region: c66-dma-memory@a6000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6000000 0x00 0x100000>; @@ -210,26 +282,38 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; }; &c66_0 { -- cgit v1.2.3 From cfbf17e69ae82f647c287366b7573e532fc281ee Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 4 Nov 2020 16:25:19 -0600 Subject: arm64: dts: ti: k3-am65*/j721e*: Fix unit address format error for dss node Fix the node address to follow the device tree convention. This fixes the dtc warning: : Warning (simple_bus_reg): /bus@100000/dss@04a00000: simple-bus unit address format error, expected "4a00000" Fixes: 76921f15acc0 ("arm64: dts: ti: k3-j721e-main: Add DSS node") Fixes: fc539b90eda2 ("arm64: dts: ti: am654: Add DSS node") Signed-off-by: Nishanth Menon Reviewed-by: Jyri Sarha Reviewed-by: Tomi Valkeinen Cc: Jyri Sarha Cc: Tomi Valkeinen Link: https://lore.kernel.org/r/20201104222519.12308-1-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index baa3f4c8f91e..a664c91675de 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -833,7 +833,7 @@ }; }; - dss: dss@04a00000 { + dss: dss@4a00000 { compatible = "ti,am65x-dss"; reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index b5cae2e03a09..620e69e42974 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1278,7 +1278,7 @@ }; }; - dss: dss@04a00000 { + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ -- cgit v1.2.3 From e6b4516815b61a9e6d27a31edf385d34c8009691 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Thu, 29 Oct 2020 10:39:50 +0530 Subject: arm64: dts: ti: k3-j7200-mcu-wakeup: Enable ADC support J7200 has a single instance of 8 channel ADC in MCU domain. Add DT node for the same. Signed-off-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Reviewed-by: Sekhar Nori Link: https://lore.kernel.org/r/20201029050950.4500-1-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 6 ++++++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index ef03e7636b66..7d2ff1c3b50f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -213,3 +213,9 @@ dr_mode = "otg"; maximum-speed = "high-speed"; }; + +&tscadc0 { + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index eb2a78a53512..bb1fe9c12e44 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -270,4 +270,23 @@ mux-controls = <&hbmc_mux 0>; }; }; + + tscadc0: tscadc@40200000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40200000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 1>; + assigned-clocks = <&k3_clks 0 3>; + assigned-clock-rates = <60000000>; + clock-names = "adc_tsc_fck"; + dmas = <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names = "fifo0", "fifo1"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; }; -- cgit v1.2.3 From af03de2b9b908e776c233744b84ce9dbb70dcafb Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 13 Nov 2020 15:18:22 -0600 Subject: arm64: dts: ti: k3-am65*: Cleanup disabled nodes at SoC dtsi level The device tree standard states that when the status property is not present under a node, the okay value is assumed. There are many reasons for doing the same, the number of strings in the device tree, default power management functionality, etc. are a few of the reasons. In general, after a few rounds of discussions [1] there are few options one could take when dealing with SoC dtsi and board dts a. SoC dtsi provide nodes as a super-set default (aka enabled) state and to prevent messy board files, when more boards are added per SoC, we optimize and disable commonly un-used nodes in board-common.dtsi b. SoC dtsi disables all hardware dependent nodes by default and board dts files enable nodes based on a need basis. c. Subjectively pick and choose which nodes we will disable by default in SoC dtsi and over the years we can optimize things and change default state depending on the need. While there are pros and cons on each of these approaches, the right thing to do will be to stick with device tree default standards and work within those established rules. So, we choose to go with option (a). Lets cleanup defaults of am654 SoC dtsi before this gets more harder to cleanup later on and new SoCs are added. The dtb generated is identical with the patch and it is just cleanup to ensure we have a clean usage model NOTE: There is a known risk of omission that new board dts developers might miss reviewing both the board schematics in addition to all the DT nodes of the SoC when setting appropriate nodes status to disable or reserved in the board dts. This can expose issues in drivers that may not anticipate an incomplete node (example: missing appropriate board properties) being in an "okay" state. These cases are considered bugs and need to be fixed in the drivers as and when identified. [1] https://lore.kernel.org/linux-arm-kernel/20201027130701.GE5639@atomide.com/ Signed-off-by: Nishanth Menon Reviewed-by: Tomi Valkeinen Reviewed-by: Tony Lindgren Cc: Jyri Sarha Cc: Tomi Valkeinen Cc: Peter Ujfalusi Cc: Tony Lindgren Link: https://lore.kernel.org/r/20201113211826.13087-2-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 -------- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index a664c91675de..c842b9803f2d 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -769,8 +769,6 @@ clocks = <&k3_clks 104 0>; clock-names = "fck"; power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp1: mcasp@2b10000 { @@ -788,8 +786,6 @@ clocks = <&k3_clks 105 0>; clock-names = "fck"; power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp2: mcasp@2b20000 { @@ -807,8 +803,6 @@ clocks = <&k3_clks 106 0>; clock-names = "fck"; power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; cal: cal@6f03000 { @@ -864,8 +858,6 @@ interrupts = ; - status = "disabled"; - dma-coherent; dss_ports: ports { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 17f3a85360e6..0dec781982b1 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -529,3 +529,19 @@ phy-mode = "rgmii-rxid"; phy-handle = <&phy0>; }; + +&mcasp0 { + status = "disabled"; +}; + +&mcasp1 { + status = "disabled"; +}; + +&mcasp2 { + status = "disabled"; +}; + +&dss { + status = "disabled"; +}; -- cgit v1.2.3 From 5d1bedf252db3ec2becb9f43c55e0f33af1fd7fc Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 13 Nov 2020 15:18:23 -0600 Subject: arm64: dts: ti: k3-j721e*: Cleanup disabled nodes at SoC dtsi level The device tree standard states that when the status property is not present under a node, the okay value is assumed. There are many reasons for doing the same, the number of strings in the device tree, default power management functionality, etc. are a few of the reasons. In general, after a few rounds of discussions [1] there are few options one could take when dealing with SoC dtsi and board dts a. SoC dtsi provide nodes as a super-set default (aka enabled) state and to prevent messy board files, when more boards are added per SoC, we optimize and disable commonly un-used nodes in board-common.dtsi b. SoC dtsi disables all hardware dependent nodes by default and board dts files enable nodes based on a need basis. c. Subjectively pick and choose which nodes we will disable by default in SoC dtsi and over the years we can optimize things and change default state depending on the need. While there are pros and cons on each of these approaches, the right thing to do will be to stick with device tree default standards and work within those established rules. So, we choose to go with option (a). Lets cleanup defaults of j721e SoC dtsi before this gets more harder to cleanup later on and new SoCs are added. The only functional difference between the dtb generated is status='okay' is no longer necessary for mcasp10 and depends on the default state. NOTE: There is a known risk of omission that new board dts developers might miss reviewing both the board schematics in addition to all the DT nodes of the SoC when setting appropriate nodes status to disable or reserved in the board dts. This can expose issues in drivers that may not anticipate an incomplete node (example: missing appropriate board properties) being in an "okay" state. These cases are considered bugs and need to be fixed in the drivers as and when identified. [1] https://lore.kernel.org/linux-arm-kernel/20201027130701.GE5639@atomide.com/ Signed-off-by: Nishanth Menon Reviewed-by: Tomi Valkeinen Reviewed-by: Tony Lindgren Cc: Jyri Sarha Cc: Tomi Valkeinen Cc: Peter Ujfalusi Cc: Tony Lindgren Link: https://lore.kernel.org/r/20201113211826.13087-3-nm@ti.com --- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 48 +++++++++++++++++++++- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 26 ------------ 2 files changed, 47 insertions(+), 27 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 52e121155563..9416528caa8a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -540,6 +540,46 @@ <&k3_clks 152 18>; /* PLL23_HSDIV0 */ }; +&mcasp0 { + status = "disabled"; +}; + +&mcasp1 { + status = "disabled"; +}; + +&mcasp2 { + status = "disabled"; +}; + +&mcasp3 { + status = "disabled"; +}; + +&mcasp4 { + status = "disabled"; +}; + +&mcasp5 { + status = "disabled"; +}; + +&mcasp6 { + status = "disabled"; +}; + +&mcasp7 { + status = "disabled"; +}; + +&mcasp8 { + status = "disabled"; +}; + +&mcasp9 { + status = "disabled"; +}; + &mcasp10 { #sound-dai-cells = <0>; @@ -556,8 +596,10 @@ >; tx-num-evt = <0>; rx-num-evt = <0>; +}; - status = "okay"; +&mcasp11 { + status = "disabled"; }; &serdes0 { @@ -639,3 +681,7 @@ &pcie3_ep { status = "disabled"; }; + +&dss { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 620e69e42974..137966c6be1f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1327,8 +1327,6 @@ "common_s1", "common_s2"; - status = "disabled"; - dss_ports: ports { #address-cells = <1>; #size-cells = <0>; @@ -1350,8 +1348,6 @@ clocks = <&k3_clks 174 1>; clock-names = "fck"; power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp1: mcasp@2b10000 { @@ -1369,8 +1365,6 @@ clocks = <&k3_clks 175 1>; clock-names = "fck"; power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp2: mcasp@2b20000 { @@ -1388,8 +1382,6 @@ clocks = <&k3_clks 176 1>; clock-names = "fck"; power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp3: mcasp@2b30000 { @@ -1407,8 +1399,6 @@ clocks = <&k3_clks 177 1>; clock-names = "fck"; power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp4: mcasp@2b40000 { @@ -1426,8 +1416,6 @@ clocks = <&k3_clks 178 1>; clock-names = "fck"; power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp5: mcasp@2b50000 { @@ -1445,8 +1433,6 @@ clocks = <&k3_clks 179 1>; clock-names = "fck"; power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp6: mcasp@2b60000 { @@ -1464,8 +1450,6 @@ clocks = <&k3_clks 180 1>; clock-names = "fck"; power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp7: mcasp@2b70000 { @@ -1483,8 +1467,6 @@ clocks = <&k3_clks 181 1>; clock-names = "fck"; power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp8: mcasp@2b80000 { @@ -1502,8 +1484,6 @@ clocks = <&k3_clks 182 1>; clock-names = "fck"; power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp9: mcasp@2b90000 { @@ -1521,8 +1501,6 @@ clocks = <&k3_clks 183 1>; clock-names = "fck"; power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp10: mcasp@2ba0000 { @@ -1540,8 +1518,6 @@ clocks = <&k3_clks 184 1>; clock-names = "fck"; power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp11: mcasp@2bb0000 { @@ -1559,8 +1535,6 @@ clocks = <&k3_clks 185 1>; clock-names = "fck"; power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; watchdog0: watchdog@2200000 { -- cgit v1.2.3 From bfbf9be725d8effdbb60eb2ece44c06ae87a54de Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 13 Nov 2020 15:18:24 -0600 Subject: arm64: dts: ti: am65/j721e: Fix up un-necessary status set to "okay" for crypto The default state of a device tree node is "okay". There is no specific use of explicitly adding status = "okay" in the SoC dtsi. Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Reviewed-by: Keerthy Acked-by: Tero Kristo Cc: Keerthy Link: https://lore.kernel.org/r/20201113211826.13087-4-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 - arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 -- 2 files changed, 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index c842b9803f2d..116818912ba2 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -119,7 +119,6 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; - status = "okay"; dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 137966c6be1f..19e602afdb05 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -345,8 +345,6 @@ #size-cells = <2>; ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; - status = "okay"; - dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>; dma-names = "tx", "rx1", "rx2"; -- cgit v1.2.3 From 90e6c38848f8e86047e0e758c0725b155e2e349b Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 13 Nov 2020 15:18:25 -0600 Subject: arm64: dts: ti: k3-am654-base-board: Fix up un-necessary status set to "okay" for USB The default state of a device tree node is "okay". There is no specific use of explicitly adding status = "okay" in the board dts. Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Acked-by: Roger Quadros Cc: Roger Quadros Link: https://lore.kernel.org/r/20201113211826.13087-5-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 0dec781982b1..c8c9aa98b561 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -356,14 +356,6 @@ disable-wp; }; -&dwc3_1 { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - &usb1 { pinctrl-names = "default"; pinctrl-0 = <&usb1_pins_default>; -- cgit v1.2.3 From 4cc34aa8a208665aa0362a615deefc3db6a5d7bd Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 13 Nov 2020 15:18:26 -0600 Subject: arm64: dts: ti: am65/j721e/j7200: Mark firmware used uart as "reserved" Follow the device tree standards that states to set the status="reserved" if an device is operational, but used by a non-linux firmware in the system. Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Acked-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20201113211826.13087-6-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 2 +- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 4 ++-- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index c8c9aa98b561..fe3043943906 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -242,7 +242,7 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ - status = "disabled"; + status = "reserved"; }; &main_uart0 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 7d2ff1c3b50f..96fa26365248 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -79,7 +79,7 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ - status = "disabled"; + status = "reserved"; }; &main_uart0 { @@ -89,7 +89,7 @@ &main_uart2 { /* MAIN UART 2 is used by R5F firmware */ - status = "disabled"; + status = "reserved"; }; &main_uart3 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 9416528caa8a..5754892f8501 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -221,7 +221,7 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ - status = "disabled"; + status = "reserved"; }; &main_uart0 { -- cgit v1.2.3 From 1d7a01c40840d844fb5d353c151f0ee0a7680c2f Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 26 Oct 2020 18:26:35 -0500 Subject: arm64: dts: ti: k3-j7200-main: Add hwspinlock node The Main NavSS block on J7200 SoCs contains a HwSpinlock IP instance that is same as the IP on AM65x and J721E SoCs. Add the DT node for this on J7200 SoCs. The node is present within the Main NavSS block, and is added as a child node under the main_navss interconnect node. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Praneeth Bajjuri Link: https://lore.kernel.org/r/20201026232637.15681-2-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 72d6496e88dd..4c53a3036066 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -115,6 +115,12 @@ interrupts = ; }; + hwspinlock: spinlock@30e00000 { + compatible = "ti,am654-hwspinlock"; + reg = <0x00 0x30e00000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + main_ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; reg = <0x00 0x3c000000 0x00 0x400000>, -- cgit v1.2.3 From d15d1cfbd765b4b2a113b6025e8edc7db4a7800a Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 26 Oct 2020 18:26:36 -0500 Subject: arm64: dts: ti: k3-j7200-main: Add mailbox cluster nodes The J7200 Main NavSS block contains a Mailbox IP instance with multiple clusters, and follows the same integration style as on J721E SoCs. Add all the Mailbox clusters as their own nodes under the MAIN NavSS interconnect node instead of creating an almost empty parent node for the new K3 mailbox IP and the clusters as its child nodes. All these nodes are enabled by default in the base dtsi file, but any cluster that does not define any child sub-mailbox nodes should be disabled in the corresponding board dts files. NOTE: The NavSS only has a limited number of interrupts, so none of the interrupts generated by a Mailbox IP are added by default. Only the needed interrupts that are targeted towards the A72 GIC will have to be added later on in the board dts files alongside the corresponding sub-mailbox child nodes. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Praneeth Bajjuri Link: https://lore.kernel.org/r/20201026232637.15681-3-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 108 ++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 4c53a3036066..b0094212aa82 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -121,6 +121,114 @@ #hwlock-cells = <1>; }; + mailbox0_cluster0: mailbox@31f80000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f80000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster1: mailbox@31f81000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f81000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster2: mailbox@31f82000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f82000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster3: mailbox@31f83000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f83000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster4: mailbox@31f84000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f84000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster5: mailbox@31f85000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f85000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster6: mailbox@31f86000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f86000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster7: mailbox@31f87000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f87000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster8: mailbox@31f88000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f88000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster9: mailbox@31f89000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f89000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster10: mailbox@31f8a000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8a000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster11: mailbox@31f8b000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8b000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + main_ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; reg = <0x00 0x3c000000 0x00 0x400000>, -- cgit v1.2.3 From 6804a987de733c805675973e3afde128fe7a7cfa Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 26 Oct 2020 18:26:37 -0500 Subject: arm64: dts: ti: k3-j7200-som-p0: Add IPC sub-mailbox nodes Add the sub-mailbox nodes that are used to communicate between MPU and various remote processors present in the J7200 SoCs to the J7200 common processor board. These include the R5F remote processors in the dual-R5F clusters in the MCU domain (MCU_R5FSS0) and the MAIN domain (MAIN_R5FSS0). These sub-mailbox nodes utilize the System Mailbox clusters 0 and 1. All the remaining mailbox clusters are currently not used on A72 core, and so are disabled. The nodes are added in the k3-j7200-som-p0.dtsi file to co-locate these alongside future reserved-memory nodes required for remoteprocs. The sub-mailbox nodes added match the hard-coded mailbox configuration used within the TI RTOS IPC software packages. A sub-mailbox node is added for each of the R5F cores to accommodate the R5F processor sub-systems running in Split mode. Only the sub-mailbox node for the first R5F core in each cluster is used in case of Lockstep mode for that R5F cluster. NOTE: The GIC_SPI interrupts to be used are dynamically allocated and managed by the System Firmware through the ti-sci-intr irqchip driver. So, only valid interrupts that are used by the sub-mailbox devices (each cluster's User 0 IRQ output) are enabled. This is done to minimize the number of NavSS Interrupt Router outputs utilized. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Praneeth Bajjuri Link: https://lore.kernel.org/r/20201026232637.15681-4-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 68 +++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 6a98ba499bc2..fbd17d38f6b6 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -63,3 +63,71 @@ reg = <0x00 0x00 0x4000000>; }; }; + +&mailbox0_cluster0 { + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "disabled"; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + status = "disabled"; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +}; -- cgit v1.2.3 From f74e93032df229a8358617e586ba89f744d5dbcd Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 15 Nov 2020 19:29:50 +0000 Subject: arm64: dts: exynos: Drop incorrect use of io-channel-ranges property This property is for consumers of io-channels. Here it is used in providers of those channels. Note dt-schema will currently flag this as an error due to a dependency between this property and io-channels. Signed-off-by: Jonathan Cameron Link: https://lore.kernel.org/r/20201115192951.1073632-9-jic23@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1 - arch/arm64/boot/dts/exynos/exynos7.dtsi | 1 - 2 files changed, 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index dae44be09a09..6433f9ee35e1 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1450,7 +1450,6 @@ clock-names = "adc"; clocks = <&cmu_peric CLK_PCLK_ADCIF>; #io-channel-cells = <1>; - io-channel-ranges; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 661f9c1027e8..10244e59d56d 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -562,7 +562,6 @@ clocks = <&clock_peric0 PCLK_ADCIF>; clock-names = "adc"; #io-channel-cells = <1>; - io-channel-ranges; status = "disabled"; }; -- cgit v1.2.3 From bb1f7cf68a2d47c5008050177884be9662673537 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Wed, 30 Sep 2020 13:44:14 +0530 Subject: arm64: dts: qcom: sm8150: Add LLC support for sm8150 Add LLCC system cache controller entry for sm8150 to support sm8150 for LLCC. Signed-off-by: Souradeep Chowdhury Link: https://lore.kernel.org/r/8f0e818485941076d62a8dc9f711b0fb868ba080.1601452132.git.schowdhu@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index f0a872e02686..838586140c48 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -490,6 +490,13 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + system-cache-controller@9200000 { + compatible = "qcom,sm8150-llcc"; + reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; -- cgit v1.2.3 From 4815623259f533aec4513c72da20a0ac1c80233b Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 9 Jun 2020 15:40:21 -0400 Subject: arm64: dts: qcom: sm8150: add apps_smmu node Add the apps_smmu node for sm8150. For UFS, now that the kernel initializes the iommu, the stream mappings set by the bootloader are cleared. Adding the iommus property is required so that new mappings are created for UFS. Signed-off-by: Jonathan Marek Reviewed-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/20200609194030.17756-4-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 838586140c48..0d932c7d5e95 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -509,6 +509,8 @@ resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; + iommus = <&apps_smmu 0x300 0>; + clock-names = "core_clk", "bus_aggr_clk", @@ -929,6 +931,7 @@ compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = ; + iommus = <&apps_smmu 0x140 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_ssphy>; @@ -994,6 +997,94 @@ cell-index = <0>; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + remoteproc_adsp: remoteproc@17300000 { compatible = "qcom,sm8150-adsp-pas"; reg = <0x0 0x17300000 0x0 0x4040>; -- cgit v1.2.3 From a89441fcd09d754439ad37c9e804f9232cba8223 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 9 Jun 2020 15:40:22 -0400 Subject: arm64: dts: qcom: sm8250: add apps_smmu node Add the apps_smmu node for sm8250. For UFS, now that the kernel initializes the iommu, the stream mappings set by the bootloader are cleared. Adding the iommus property is required so that new mappings are created for UFS. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200609194030.17756-5-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 107 +++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index d057d85a19fb..457c3e65c0b6 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1172,6 +1172,8 @@ power-domains = <&gcc UFS_PHY_GDSC>; + iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; + clock-names = "core_clk", "bus_aggr_clk", @@ -2156,6 +2158,111 @@ }; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + adsp: remoteproc@17300000 { compatible = "qcom,sm8250-adsp-pas"; reg = <0 0x17300000 0 0x100>; -- cgit v1.2.3 From 0c9dde0d201548d2297a8cd8d7eac25c76b875ef Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 9 Jun 2020 15:40:23 -0400 Subject: arm64: dts: qcom: sm8150: Add secondary USB and PHY nodes Add dts nodes for the secondary USB controller and related PHY nodes. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200609194030.17756-6-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 89 ++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 0d932c7d5e95..e40bec6f3623 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -845,6 +845,19 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; + usb_2_hsphy: phy@88e3000 { + compatible = "qcom,sm8150-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + }; + usb_1_qmpphy: phy@88e9000 { compatible = "qcom,sm8150-qmp-usb3-phy"; reg = <0 0x088e9000 0 0x18c>, @@ -894,6 +907,37 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + usb_2_qmpphy: phy@88eb000 { + compatible = "qcom,sm8150-qmp-usb3-uni-phy"; + reg = <0 0x088eb000 0 0x200>; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + usb_2_ssphy: lane@88eb200 { + reg = <0 0x088eb200 0 0x200>, + <0 0x088eb400 0 0x200>, + <0 0x088eb800 0 0x800>, + <0 0x088eb600 0 0x200>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; @@ -946,6 +990,51 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + usb_2: usb@a8f8800 { + compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep", "xo"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + usb_2_dwc3: dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x160 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_2_hsphy>, <&usb_2_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sm8150-aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x100000>; -- cgit v1.2.3 From 46a6f297d7dd62ddf03aaf2882f73a6ba20f99d1 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 9 Jun 2020 15:40:24 -0400 Subject: arm64: dts: qcom: sm8250: Add USB and PHY device nodes Add device nodes for the USB3 controller, QMP SS PHY and SNPS HS PHY. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200609194030.17756-7-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 180 +++++++++++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 457c3e65c0b6..cd47622e34bb 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1462,6 +1462,96 @@ }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8250-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_2_hsphy: phy@88e4000 { + compatible = "qcom,sm8250-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e4000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + }; + + usb_1_qmpphy: phy@88e9000 { + compatible = "qcom,sm8250-qmp-usb3-phy"; + reg = <0 0x088e9000 0 0x200>, + <0 0x088e8000 0 0x20>; + reg-names = "reg-base", "dp_com"; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "com_aux"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + usb_1_ssphy: lanes@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x400>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + + usb_2_qmpphy: phy@88eb000 { + compatible = "qcom,sm8250-qmp-usb3-uni-phy"; + reg = <0 0x088eb000 0 0x200>; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_EN>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + usb_2_ssphy: lane@88eb200 { + reg = <0 0x088eb200 0 0x200>, + <0 0x088eb400 0 0x200>, + <0 0x088eb800 0 0x800>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + dc_noc: interconnect@90c0000 { compatible = "qcom,sm8250-dc-noc"; reg = <0 0x090c0000 0 0x4200>; @@ -1483,6 +1573,96 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + usb_1: usb@a6f8800 { + compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_EN>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep", "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_2: usb@a8f8800 { + compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_EN>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep", "xo"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&pdc 13 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + usb_2_dwc3: dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x20 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_2_hsphy>, <&usb_2_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8250-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; -- cgit v1.2.3 From 0ab1b2d10afe60178e82cdde3ab7f3d5f458b8f7 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 9 Jun 2020 15:40:25 -0400 Subject: arm64: dts: qcom: add sm8150 hdk dts Add initial HDK855 dts, based on sm8150-mtp, with a few changes. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200609194030.17756-8-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 463 ++++++++++++++++++++++++++++++++ 2 files changed, 464 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8150-hdk.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 90887aac28e2..acddf4b0699c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -45,5 +45,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts new file mode 100644 index 000000000000..fb2cf3d987a1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include "sm8150.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 HDK"; + compatible = "qcom,sm8150-hdk", "qcom,sm8150"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>; + vdd-l6-l9-supply = <&vreg_s8c_1p3>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vdda_wcss_pll: + vreg_l1a_0p75: ldo1 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + vdd_pdphy: + vdda_usb_hs_3p1: + vreg_l2a_3p1: ldo2 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3a_0p8: ldo3 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = ; + }; + + vdd_usb_hs_core: + vdda_csi_0_0p9: + vdda_csi_1_0p9: + vdda_csi_2_0p9: + vdda_csi_3_0p9: + vdda_dsi_0_0p9: + vdda_dsi_1_0p9: + vdda_dsi_0_pll_0p9: + vdda_dsi_1_pll_0p9: + vdda_pcie_1ln_core: + vdda_pcie_2ln_core: + vdda_pll_hv_cc_ebi01: + vdda_pll_hv_cc_ebi23: + vdda_qrefs_0p875_5: + vdda_sp_sensor: + vdda_ufs_2ln_core_1: + vdda_ufs_2ln_core_2: + vdda_usb_ss_dp_core_1: + vdda_usb_ss_dp_core_2: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vreg_l5a_0p875: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vddpx_10: + vreg_l9a_1p2: ldo9 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l10a_2p5: ldo10 { + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l11a_0p8: ldo11 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc_cs_1p8: + vdda_gfx_cs_1p8: + vdda_usb_hs_1p8: + vdda_qrefs_vref_1p8: + vddpx_10_a: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_2p7: ldo13 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p7: ldo15 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1704000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + }; + + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p3>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + vdd-flash-supply = <&vreg_bob>; + vdd-rgb-supply = <&vreg_bob>; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vdda_wcss_adcdac_1: + vdda_wcss_adcdac_22: + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_hv_refgen0: + vdda_qlink_hv_ck: + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vddpx_5: + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vddpx_6: + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + }; + + pm8009-rpmh-regulators { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vreg_bob>; + + vdd-l2-supply = <&vreg_s8c_1p3>; + vdd-l5-l6-supply = <&vreg_bob>; + + vreg_l2f_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l5f_2p85: ldo5 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6f_2p85: ldo6 { + regulator-initial-mode = ; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <2856000>; + }; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&pon { + pwrkey { + status = "okay"; + }; + + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + +&remoteproc_adsp { + status = "okay"; + + firmware-name = "qcom/sm8150/adsp.mbn"; +}; + +&remoteproc_cdsp { + status = "okay"; + + firmware-name = "qcom/sm8150/cdsp.mbn"; +}; + +&remoteproc_slpi { + status = "okay"; + + firmware-name = "qcom/sm8150/slpi.mbn"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <126 4>; +}; + +&uart2 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10a_2p5>; + vcc-max-microamp = <750000>; + vccq-supply = <&vreg_l9a_1p2>; + vccq-max-microamp = <700000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <750000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs_2ln_core_1>; + vdda-max-microamp = <90200>; + vdda-pll-supply = <&vreg_l3c_1p2>; + vdda-pll-max-microamp = <19000>; +}; + +&usb_1_hsphy { + status = "okay"; + vdda-pll-supply = <&vdd_usb_hs_core>; + vdda33-supply = <&vdda_usb_hs_3p1>; + vdda18-supply = <&vdda_usb_hs_1p8>; +}; + +&usb_2_hsphy { + status = "okay"; + vdda-pll-supply = <&vdd_usb_hs_core>; + vdda33-supply = <&vdda_usb_hs_3p1>; + vdda18-supply = <&vdda_usb_hs_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +}; + +&usb_2_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; -- cgit v1.2.3 From 91ed0e90fc491b427aa50eaa8efb40090355153a Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 9 Jun 2020 15:40:26 -0400 Subject: arm64: dts: qcom: add sm8250 hdk dts Add initial HDK865 dts, based on sm8250-mtp, with a few changes. Notably, regulator configs are changed a bit. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200609194030.17756-9-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 454 ++++++++++++++++++++++++++++++++ 2 files changed, 455 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8250-hdk.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index acddf4b0699c..5113fac80b7a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -47,4 +47,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts new file mode 100644 index 000000000000..b5026e422aa6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include "sm8250.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8250 HDK"; + compatible = "qcom,sm8250-hdk", "qcom,sm8250"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + vreg_s6c_0p88: smpc6-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s6c_0p88"; + + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; + vdd-l6-l9-supply = <&vreg_s8c_1p3>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s5a_1p9: smps5 { + regulator-name = "vreg_s5a_1p9"; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_s6a_0p95: smps6 { + regulator-name = "vreg_s6a_0p95"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + vreg_l2a_3p1: ldo2 { + regulator-name = "vreg_l2a_3p1"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3a_0p9: ldo3 { + regulator-name = "vreg_l3a_0p9"; + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = ; + }; + + vreg_l5a_0p88: ldo5 { + regulator-name = "vreg_l5a_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p7: ldo7 { + regulator-name = "vreg_l7a_1p7"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p2: ldo9 { + regulator-name = "vreg_l9a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p8: ldo10 { + regulator-name = "vreg_l10a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_ts_3p0: ldo13 { + regulator-name = "vreg_l13a_ts_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_3p3: ldo16 { + regulator-name = "vreg_l16a_3p3"; + regulator-min-microvolt = <3024000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l17a_2p96: ldo17 { + regulator-name = "vreg_l17a_2p96"; + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l18a_0p92: ldo18 { + regulator-name = "vreg_l18a_0p92"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p3>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_s8c_1p3: smps8 { + regulator-name = "vreg_s8c_1p3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p2: ldo2 { + regulator-name = "vreg_l2c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-name = "vreg_l4c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_cam_vcm0_2p85: ldo7 { + regulator-name = "vreg_l7c_cam_vcm0_2p85"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p0: ldo10 { + regulator-name = "vreg_l10c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-name = "vreg_l11c_3p3"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + }; + + pm8009-rpmh-regulators { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vreg_bob>; + vdd-l2-supply = <&vreg_s8c_1p3>; + vdd-l5-l6-supply = <&vreg_bob>; + vdd-l7-supply = <&vreg_s4a_1p8>; + + vreg_l1f_cam_dvdd1_1p1: ldo1 { + regulator-name = "vreg_l1f_cam_dvdd1_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + }; + + vreg_l2f_cam_dvdd0_1p2: ldo2 { + regulator-name = "vreg_l2f_cam_dvdd0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3f_cam_dvdd2_1p05: ldo3 { + regulator-name = "vreg_l3f_cam_dvdd2_1p05"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + }; + + vreg_l5f_cam_avdd0_2p85: ldo5 { + regulator-name = "vreg_l5f_cam_avdd0_2p85"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6f_cam_avdd1_2p8: ldo6 { + regulator-name = "vreg_l6f_cam_avdd1_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l7f_1p8: ldo7 { + regulator-name = "vreg_l7f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&pon { + pwrkey { + status = "okay"; + }; + + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + +&tlmm { + gpio-reserved-ranges = <28 4>, <40 4>; +}; + +&uart2 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + vcc-supply = <&vreg_l17a_2p96>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l6a_1p2>; + vccq-max-microamp = <800000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <800000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-max-microamp = <89900>; + vdda-pll-supply = <&vreg_l9a_1p2>; + vdda-pll-max-microamp = <18800>; +}; + +&usb_1_hsphy { + status = "okay"; + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda33-supply = <&vreg_l2a_3p1>; + vdda18-supply = <&vreg_l12a_1p8>; +}; + +&usb_2_hsphy { + status = "okay"; + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda33-supply = <&vreg_l2a_3p1>; + vdda18-supply = <&vreg_l12a_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l9a_1p2>; + vdda-pll-supply = <&vreg_l18a_0p92>; +}; + +&usb_2_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l9a_1p2>; + vdda-pll-supply = <&vreg_l18a_0p92>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; -- cgit v1.2.3 From c4cf0300be84c2233ffa1b7516be66b167bc81f5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 28 Oct 2020 22:09:54 +0300 Subject: arm64: dts: qcom: sm8250: Add support for SDC2 Add support for SDC2 which can be used to interface uSD card. Signed-off-by: Manivannan Sadhasivam [DB: minor fixes: clocks, iommus, opps] Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201028190955.1264526-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 45 ++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index cd47622e34bb..f4af58f66740 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1552,6 +1552,51 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x4a0 0x0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + status = "disabled"; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + dc_noc: interconnect@90c0000 { compatible = "qcom,sm8250-dc-noc"; reg = <0 0x090c0000 0 0x4200>; -- cgit v1.2.3 From 53a8ccf1c7e5c901342f7dcf43bb7ddb6027984b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 28 Oct 2020 22:09:55 +0300 Subject: arm64: dts: qcom: rb5: Add support for uSD card Add support for uSD card on RB5 using the SDHC2 interface. Signed-off-by: Manivannan Sadhasivam [DB: disabled 1.8V support to get SDHC to work] Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201028190955.1264526-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 41 ++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index fec31655141c..bc8d63a59598 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -18,6 +18,7 @@ aliases { serial0 = &uart12; + sdhc2 = &sdhc_2; }; chosen { @@ -475,6 +476,20 @@ status = "okay"; }; +&sdhc_2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_2p96>; + cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + bus-width = <4>; + /* there seem to be issues with HS400-1.8V mode, so disable it */ + no-1-8-v; + no-sdio; + no-emmc; +}; + /* CAN */ &spi0 { status = "okay"; @@ -663,6 +678,32 @@ "HST_BLE_SNS_UART_RX", "HST_WLAN_UART_TX", "HST_WLAN_UART_RX"; + + sdc2_default_state: sdc2-default { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + sdc2_card_det_n: sd-card-det-n { + pins = "gpio77"; + function = "gpio"; + bias-pull-up; + }; }; &uart12 { -- cgit v1.2.3 From 8530939383f5770120cbdb107393012d4239654e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 10 Oct 2020 16:21:25 +0300 Subject: arm64: dts: qcom: sm8250: add iommus entry to QUP nodes Enable IOMMUs configuration for QUP nodes to stop SM8250 boards from rebooting when using I2C DMA transfers. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201010132125.416064-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index f4af58f66740..fee55fccc67e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -456,6 +456,7 @@ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; #address-cells = <2>; #size-cells = <2>; + iommus = <&apps_smmu 0x63 0x0>; ranges; status = "disabled"; @@ -662,6 +663,7 @@ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; #address-cells = <2>; #size-cells = <2>; + iommus = <&apps_smmu 0x5a3 0x0>; ranges; status = "disabled"; @@ -924,6 +926,7 @@ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; #address-cells = <2>; #size-cells = <2>; + iommus = <&apps_smmu 0x43 0x0>; ranges; status = "disabled"; -- cgit v1.2.3 From d371a931540bc36fd1199de3ec365a1187b7b282 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 30 Sep 2020 14:21:33 +0300 Subject: arm64: dts: qcom: sm8250: correct compatible for sm8250-mtp Qualcomm boards should define two compatible strings: one for board, anoter one for SoC family. sm8250-mtp.dts lists just the board compatible, which makes it incompatible with qcom.yaml schema. Reviewed-by: Vinod Koul Signed-off-by: Dmitry Baryshkov Fixes: 60378f1a171e ("arm64: dts: qcom: sm8250: Add sm8250 dts file") Link: https://lore.kernel.org/r/20200930112133.2091505-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index c85cab9c9b41..dea00f19711d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -14,7 +14,7 @@ / { model = "Qualcomm Technologies, Inc. SM8250 MTP"; - compatible = "qcom,sm8250-mtp"; + compatible = "qcom,sm8250-mtp", "qcom,sm8250"; aliases { serial0 = &uart12; -- cgit v1.2.3 From 65389ce636241c1226fa03b553f32c9ba178d549 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 21 Sep 2020 12:28:06 +0530 Subject: arm64: dts: qcom: sm8250: Add support for PRNG EE RNG (Random Number Generator) in SM8250 features PRNG EE (Execution Environment), hence add devicetree support for it. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200921065806.10928-1-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index fee55fccc67e..f1a3138bcbba 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -429,6 +429,13 @@ #mbox-cells = <2>; }; + rng: rng@793000 { + compatible = "qcom,prng-ee"; + reg = <0 0x00793000 0 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + qup_opp_table: qup-opp-table { compatible = "operating-points-v2"; -- cgit v1.2.3 From 52c90664f122eee2509dee934499b561b1a8959f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 17 Sep 2020 13:56:22 +0530 Subject: arm64: dts: qcom: qrb5165-rb5: Add USB support RB5 makes use of the two USB controllers onboard. USB0 is connected to the Type C port and USB1 is connected to USB3.1 HUB which exposes following downstream ports: * 2 Type A ports * 2 HS/SS ports on the expansion connector * USB to LAN device Hence, enable these two controllers with the required PHYs. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200917082622.6823-4-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 46 ++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index bc8d63a59598..d9f52703ba2a 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -729,3 +729,49 @@ vdda-pll-supply = <&vreg_l9a_1p2>; vdda-pll-max-microamp = <18800>; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda33-supply = <&vreg_l2a_3p1>; + vdda18-supply = <&vreg_l12a_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l9a_1p2>; + vdda-pll-supply = <&vreg_l18a_0p92>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda33-supply = <&vreg_l2a_3p1>; + vdda18-supply = <&vreg_l12a_1p8>; +}; + +&usb_2_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l9a_1p2>; + vdda-pll-supply = <&vreg_l18a_0p92>; +}; -- cgit v1.2.3 From 256958086de9f06291042b106b05804a450d5e8e Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 8 Sep 2020 09:15:00 -0400 Subject: arm64: dts: qcom: add sm8250 fastrpc nodes Add fastrpc nodes for sDSP, cDSP, and aDSP. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200908131500.19891-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 115 ++++++++++++++++++++++++++++++++++- 1 file changed, 113 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index f1a3138bcbba..a679f6864065 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1429,8 +1429,35 @@ mboxes = <&ipcc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_GLINK_QMP>; - label = "lpass"; + label = "slpi"; qcom,remote-pid = <3>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "sdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0541 0x0>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0542 0x0>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0543 0x0>; + /* note: shared-cb = <4> in downstream */ + }; + }; }; }; @@ -1467,8 +1494,66 @@ mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP>; - label = "lpass"; + label = "cdsp"; qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1001 0x0460>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1002 0x0460>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x0460>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x0460>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x0460>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x0460>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x0460>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1008 0x0460>; + }; + + /* note: secure cb9 in downstream */ + }; }; }; @@ -2534,6 +2619,32 @@ label = "lpass"; qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1803 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1804 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1805 0x0>; + }; + }; }; }; -- cgit v1.2.3 From d5276bfa0ca6af7f65896c222b1b60493d189f27 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 20 Nov 2020 12:09:13 -0800 Subject: arm64: dts: qcom: sc7180: Remove double pull-up on p-sensor-int-l This interrupt has an external pull-up so we don't need to pull it up again. Drop the internal pull here. Note I don't think this really changes anything, just noticed while looking at this irq pin. Reviewed-by: Douglas Anderson Cc: Douglas Anderson Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20201120200913.618274-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 781e61ad75a6..60a478a814d8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -1332,7 +1332,8 @@ ap_spi_fp: &spi10 { pinconf { pins = "gpio24"; - bias-pull-up; + /* Has external pullup */ + bias-disable; }; }; -- cgit v1.2.3 From fee5dc31a588fffa543f3dfaaeebed55263b4ad2 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 20 Nov 2020 10:38:25 -0800 Subject: arm64: dts: qcom: sc7180: Add prox sensor to LTE sku Lazor boards There's a proximity sensor on Lazor devices, but only for LTE SKUs. Enable it only on the Lazor LTE SKUs and also configure it properly so it works. Cc: Douglas Anderson Cc: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20201120183825.547310-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 7 ++++++- arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 5 ----- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 - 5 files changed, 22 insertions(+), 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts index 5a67e5baafec..e16ba7b01f25 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts @@ -13,6 +13,14 @@ compatible = "google,lazor-rev1-sku0", "google,lazor-rev2-sku0", "qcom,sc7180"; }; +&ap_sar_sensor { + status = "okay"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; + &keyboard_backlight { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts index 43836fc4d403..0881f8dd02c9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts @@ -13,6 +13,14 @@ compatible = "google,lazor-sku0", "qcom,sc7180"; }; +&ap_sar_sensor { + status = "okay"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; + &keyboard_backlight { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 180ef9e04306..89e5cd29ec09 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -30,7 +30,12 @@ ap_h1_spi: &spi0 {}; }; &ap_sar_sensor { - status = "okay"; + semtech,cs0-ground; + semtech,combined-sensors = <3>; + semtech,resolution = "fine"; + semtech,startup-sensor = <0>; + semtech,proxraw-strength = <8>; + semtech,avg-pos-strength = <64>; }; ap_ts_pen_1v8: &i2c4 { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 0a281c24841c..59d67fb0efe8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -34,11 +34,6 @@ ap_h1_spi: &spi0 {}; }; }; -&ap_sar_sensor_i2c { - /* Not hooked up */ - status = "disabled"; -}; - ap_ts_pen_1v8: &i2c4 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 60a478a814d8..3eb1ff2483be 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -654,7 +654,6 @@ edp_brij_i2c: &i2c2 { }; ap_sar_sensor_i2c: &i2c5 { - status = "okay"; clock-frequency = <400000>; ap_sar_sensor: proximity@28 { -- cgit v1.2.3 From e76be113d4a72573b8d892ca65642e5f171a1f81 Mon Sep 17 00:00:00 2001 From: Michael Srba Date: Sun, 15 Nov 2020 20:50:58 +0100 Subject: arm64: dts: qcom: msm8916-samsung-a3u: add nodes for touchscreen This patch wires up touchscreen support on Samsung Galaxy A3 2015. Reviewed-by: Stephan Gerhold Signed-off-by: Michael Srba Link: https://lore.kernel.org/r/20201115195058.27097-1-michael.srba@seznam.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index 086f07ead5cb..661f41ad978b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -28,6 +28,27 @@ "0", "0", "1"; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen@20 { + compatible = "zinitix,bt541"; + + reg = <0x20>; + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <540>; + touchscreen-size-y = <960>; + + vdd-supply = <®_vdd_tsp>; + vddo-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default>; + }; +}; + &dsi0 { panel@0 { reg = <0>; @@ -59,4 +80,12 @@ drive-strength = <2>; bias-disable; }; + + ts_int_default: ts-int-default { + pins = "gpio13"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; }; -- cgit v1.2.3 From 0af8bbdb6bb83b2b3cf0d005f1cfff5afe75c7c1 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 13 Nov 2020 22:59:12 +0500 Subject: arm64: dts: qcom: msm8916-longcheer-l8150: Enable PM8916 vibrator L8150 has a vibrator connected to PM8916. Add it to the device tree. Reviewed-by: Stephan Gerhold Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20201113175917.189123-1-nikitos.tr@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 2c204d535d66..d106bdbfda68 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -61,6 +61,10 @@ linux,code = ; }; +&pm8916_vib { + status = "okay"; +}; + &pronto { status = "okay"; }; -- cgit v1.2.3 From 6eb815289a3794264eee597c2daa311e051ff6fc Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 13 Nov 2020 22:59:13 +0500 Subject: arm64: dts: msm8916-longcheer-l8150: Add touchscreen L8150 has RMI4 compatible Synaptics touchscreen on blsp_i2c5. It is powered by fixed regulator. Add both to the device tree. Reviewed-by: Stephan Gerhold Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20201113175917.189123-2-nikitos.tr@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index d106bdbfda68..21f2e8e0d05e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -5,6 +5,7 @@ #include "msm8916-pm8916.dtsi" #include #include +#include / { model = "Longcheer L8150"; @@ -50,6 +51,52 @@ linux,code = ; }; }; + + reg_ctp: regulator-ctp { + compatible = "regulator-fixed"; + regulator-name = "ctp"; + + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&msmgpio 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&ctp_pwr_en_default>; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + rmi4@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <®_ctp>; + vio-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_default>; + + syna,startup-delay-ms = <10>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; // Allow sleeping + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; // Touchscreen + }; + }; }; &blsp1_uart2 { @@ -201,6 +248,14 @@ }; &msmgpio { + ctp_pwr_en_default: ctp-pwr-en-default { + pins = "gpio17"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + gpio_keys_default: gpio-keys-default { pins = "gpio107"; function = "gpio"; @@ -209,6 +264,14 @@ bias-pull-up; }; + tp_int_default: tp-int-default { + pins = "gpio13"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + usb_vbus_default: usb-vbus-default { pins = "gpio62"; function = "gpio"; -- cgit v1.2.3 From 6bd2cae7ddd6e7b454d4d8267d9a8952856f8283 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 13 Nov 2020 22:59:14 +0500 Subject: arm64: dts: msm8916-longcheer-l8150: Add position sensors L8150 has: - BMC156 accelerometer and magnetic sensor - BMG160 gyroscope sensor Add them to the device tree. Reviewed-by: Stephan Gerhold Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20201113175917.189123-3-nikitos.tr@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 21f2e8e0d05e..79a2475e3cd5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -67,6 +67,44 @@ }; }; +&blsp_i2c2 { + status = "okay"; + + accelerometer@10 { + compatible = "bosch,bmc150_accel"; + reg = <0x10>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + + magnetometer@12 { + compatible = "bosch,bmc150_magn"; + reg = <0x12>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + }; + + gyroscope@68 { + compatible = "bosch,bmg160"; + reg = <0x68>; + + interrupt-parent = <&msmgpio>; + interrupts = <23 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&gyro_int_default>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + }; +}; + &blsp_i2c5 { status = "okay"; @@ -264,6 +302,14 @@ bias-pull-up; }; + gyro_int_default: gyro-int-default { + pins = "gpio23"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + tp_int_default: tp-int-default { pins = "gpio13"; function = "gpio"; -- cgit v1.2.3 From 6b4ad4be646994e7e8c5707c87cc38725fd31e1b Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 13 Nov 2020 22:59:15 +0500 Subject: arm64: dts: qcom: msm8916-longcheer-l8150: Add flash LED L8150 uses SGM3785 Flash LED driver. It is similar to SGM3140 but can also be controlled with PWM. Since SoC doesn't have PWM, add led to the device tree using sgm3140 driver. Reviewed-by: Stephan Gerhold Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20201113175917.189123-4-nikitos.tr@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 79a2475e3cd5..2b8670dd4b71 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -6,6 +6,7 @@ #include #include #include +#include / { model = "Longcheer L8150"; @@ -65,6 +66,21 @@ pinctrl-names = "default"; pinctrl-0 = <&ctp_pwr_en_default>; }; + + flash-led-controller { + compatible = "sgmicro,sgm3140"; + flash-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>; + enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&camera_flash_default>; + + flash_led: led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + }; + }; }; &blsp_i2c2 { @@ -286,6 +302,14 @@ }; &msmgpio { + camera_flash_default: camera-flash-default { + pins = "gpio31", "gpio32"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + ctp_pwr_en_default: ctp-pwr-en-default { pins = "gpio17"; function = "gpio"; -- cgit v1.2.3 From 38260b9e6310505f984bf3e026f4a4b6682c3526 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 13 Nov 2020 22:59:16 +0500 Subject: arm64: dts: qcom: msm8916-longcheer-l8150: Add notification LED L8150 uses aw2013 LED contriller for notification LED on the front of the device. Add it to the device tree Reviewed-by: Stephan Gerhold Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20201113175917.189123-5-nikitos.tr@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 2b8670dd4b71..1e893c0b6fbc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -83,6 +83,40 @@ }; }; +&blsp_i2c1 { + status = "okay"; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + #address-cells = <1>; + #size-cells = <0>; + + vcc-supply = <&pm8916_l17>; + + led@0 { + reg = <0>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + + led@1 { + reg = <1>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + + led@2 { + reg = <2>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + }; +}; + &blsp_i2c2 { status = "okay"; -- cgit v1.2.3 From 4e8692c2ee3d4ac6b669f7e306364d77a574c810 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 13 Nov 2020 22:59:17 +0500 Subject: arm64: dts: qcom: msm8916-samsung-a2015: Disable muic i2c pin bias Some versions of the firmware leave i2c gpios in a wrong state. Add pinctrl that disables pin bias since external pull-up resistors are present. Reviewed-by: Stephan Gerhold Fixes: 1329c1ab0730 ("arm64: dts: qcom: Add device tree for Samsung Galaxy A3U/A5U") Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20201113175917.189123-6-nikitos.tr@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 0b0dfd3059de..f91269492d72 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -78,6 +78,9 @@ sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&muic_i2c_default>; + #address-cells = <1>; #size-cells = <0>; @@ -304,6 +307,14 @@ }; }; + muic_i2c_default: muic-i2c-default { + pins = "gpio105", "gpio106"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + muic_int_default: muic-int-default { pins = "gpio12"; function = "gpio"; -- cgit v1.2.3 From 26664c593adc047da121e9c78f706fefac77b132 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 11 Nov 2020 12:03:43 -0800 Subject: arm64: dts: qcom: sc7180: Set 'polling-delay-passive' for thermal zones back to 250 ms Commit 22337b91022d ("arm64: dts: qcom: sc7180: Changed polling mode in Thermal-zones node") sets both 'polling-delay' and 'polling-delay-passive' to zero with the rationale that TSENS interrupts are enabled. A TSENS interrupt fires when the temperature of a thermal zone reaches a trip point, which makes regular polling below the passive trip point temperature unnecessary. However the situation is different when passive cooling is active, regular polling is still needed to trigger a periodic evaluation of the thermal zone by the thermal governor. Change 'polling-delay-passive' back to the original value of 250 ms. Commit 2315ae70af95 ("arm64: dts: qcom: sc7180: Add gpu cooling support") recently changed the value for the GPU thermal zones from zero to 100 ms, also set it to 250 ms for uniformity. If some zones really need different values these can be changed in dedicated patches. Reviewed-by: Douglas Anderson Fixes: 22337b91022d ("arm64: dts: qcom: sc7180: Changed polling mode in Thermal-zones node") Signed-off-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/20201111120334.1.Ifc04ea235c3c370e3b21ec3b4d5dead83cc403b4@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 50 ++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 25 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 625e922c273d..c0efb101b0d6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3522,7 +3522,7 @@ thermal-zones { cpu0-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 1>; @@ -3571,7 +3571,7 @@ }; cpu1-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 2>; @@ -3620,7 +3620,7 @@ }; cpu2-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 3>; @@ -3669,7 +3669,7 @@ }; cpu3-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 4>; @@ -3718,7 +3718,7 @@ }; cpu4-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 5>; @@ -3767,7 +3767,7 @@ }; cpu5-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 6>; @@ -3816,7 +3816,7 @@ }; cpu6-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 9>; @@ -3857,7 +3857,7 @@ }; cpu7-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 10>; @@ -3898,7 +3898,7 @@ }; cpu8-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 11>; @@ -3939,7 +3939,7 @@ }; cpu9-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 12>; @@ -3980,7 +3980,7 @@ }; aoss0-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 0>; @@ -4001,7 +4001,7 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 7>; @@ -4021,7 +4021,7 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 8>; @@ -4041,7 +4041,7 @@ }; gpuss0-thermal { - polling-delay-passive = <100>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 13>; @@ -4069,7 +4069,7 @@ }; gpuss1-thermal { - polling-delay-passive = <100>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 14>; @@ -4097,7 +4097,7 @@ }; aoss1-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 0>; @@ -4118,7 +4118,7 @@ }; cwlan-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 1>; @@ -4139,7 +4139,7 @@ }; audio-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 2>; @@ -4160,7 +4160,7 @@ }; ddr-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 3>; @@ -4181,7 +4181,7 @@ }; q6-hvx-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 4>; @@ -4202,7 +4202,7 @@ }; camera-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 5>; @@ -4223,7 +4223,7 @@ }; mdm-core-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 6>; @@ -4244,7 +4244,7 @@ }; mdm-dsp-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 7>; @@ -4265,7 +4265,7 @@ }; npu-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 8>; @@ -4286,7 +4286,7 @@ }; video-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 9>; -- cgit v1.2.3 From 2802821a66f99955afd75ec76209064bfb678697 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Mon, 23 Nov 2020 09:35:38 -0500 Subject: arm64: dts: qcom: fix serial output for sm8250-hdk The uart2 node has been renamed, apply the change to sm8250-hdk dts too so that serial output works. Fixes: 91ed0e90fc49 ("arm64: dts: qcom: add sm8250 hdk dts") Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20201123143538.14198-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index b5026e422aa6..c3a2c5aa6fe9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -17,7 +17,7 @@ compatible = "qcom,sm8250-hdk", "qcom,sm8250"; aliases { - serial0 = &uart2; + serial0 = &uart12; }; chosen { @@ -387,7 +387,7 @@ gpio-reserved-ranges = <28 4>, <40 4>; }; -&uart2 { +&uart12 { status = "okay"; }; -- cgit v1.2.3 From c25b846425e34929c6201ef0592444147e65fbb3 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:29 +0800 Subject: arm64: dts: hisilicon: normalize the node name of the ITS devices Change the node name of the ITS devices to match "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$". Although "interrupt-controller" is allowed, but "msi-controller" is preferred. Otherwise, "interrupt-controller@b7000000: False schema does not allow" will be reported by arm,gic-v3.yaml. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 8 ++++---- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++++-------- 3 files changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index bc49955360db..f7e3a7af4634 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -242,28 +242,28 @@ <0x0 0xfe020000 0 0x10000>; /* GICV */ interrupts = ; - its_peri: interrupt-controller@8c000000 { + its_peri: msi-controller@8c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0x8c000000 0x0 0x40000>; }; - its_m3: interrupt-controller@a3000000 { + its_m3: msi-controller@a3000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0xa3000000 0x0 0x40000>; }; - its_pcie: interrupt-controller@b7000000 { + its_pcie: msi-controller@b7000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0xb7000000 0x0 0x40000>; }; - its_dsa: interrupt-controller@c6000000 { + its_dsa: msi-controller@c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 50ceaa959bdc..a2fba458e047 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -242,7 +242,7 @@ <0x0 0xfe020000 0 0x10000>; /* GICV */ interrupts = ; - its_dsa: interrupt-controller@c6000000 { + its_dsa: msi-controller@c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 4773a533fce5..892691bb2adb 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -924,56 +924,56 @@ <0x0 0xfe020000 0x0 0x10000>; /* GICV */ interrupts = ; - p0_its_peri_a: interrupt-controller@4c000000 { + p0_its_peri_a: msi-controller@4c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0x4c000000 0x0 0x40000>; }; - p0_its_peri_b: interrupt-controller@6c000000 { + p0_its_peri_b: msi-controller@6c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0x6c000000 0x0 0x40000>; }; - p0_its_dsa_a: interrupt-controller@c6000000 { + p0_its_dsa_a: msi-controller@c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0xc6000000 0x0 0x40000>; }; - p0_its_dsa_b: interrupt-controller@8,c6000000 { + p0_its_dsa_b: msi-controller@8c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x8 0xc6000000 0x0 0x40000>; }; - p1_its_peri_a: interrupt-controller@400,4c000000 { + p1_its_peri_a: msi-controller@4004c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x4c000000 0x0 0x40000>; }; - p1_its_peri_b: interrupt-controller@400,6c000000 { + p1_its_peri_b: msi-controller@4006c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x6c000000 0x0 0x40000>; }; - p1_its_dsa_a: interrupt-controller@400,c6000000 { + p1_its_dsa_a: msi-controller@400c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0xc6000000 0x0 0x40000>; }; - p1_its_dsa_b: interrupt-controller@408,c6000000 { + p1_its_dsa_b: msi-controller@408c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; -- cgit v1.2.3 From 24402ce1e26e303ce2049e783a4fc3f6e122e169 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:30 +0800 Subject: arm64: dts: hisilicon: separate each group of data in the property "reg" Do not write the "reg" of multiple groups of data into a uint32 array, use <> to separate them. Otherwise, the errors similar to the following will be reported by reg.yaml. soc: dsa@c7000000:reg:0: [0, 3305111552, 0, 8978432, 0, 3338665984, 0, \ 6291456] is too long Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 148 +++++++++++++++---------------- 2 files changed, 76 insertions(+), 76 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index a2fba458e047..941d527dcb86 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -434,8 +434,8 @@ #size-cells = <0>; compatible = "hisilicon,hns-dsaf-v2"; mode = "6port-16rss"; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x600000>; + reg = <0x0 0xc5000000 0x0 0x890000>, + <0x0 0xc7000000 0x0 0x600000>; reg-names = "ppe-base", "dsaf-base"; interrupt-parent = <&mbigen_dsaf0>; subctrl-syscon = <&dsa_subctrl>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 892691bb2adb..36a873d15089 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1321,8 +1321,8 @@ #size-cells = <0>; compatible = "hisilicon,hns-dsaf-v2"; mode = "6port-16rss"; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x600000>; + reg = <0x0 0xc5000000 0x0 0x890000>, + <0x0 0xc7000000 0x0 0x600000>; reg-names = "ppe-base", "dsaf-base"; interrupt-parent = <&mbigen_dsaf0>; subctrl-syscon = <&dsa_subctrl>; @@ -1720,24 +1720,24 @@ }; p0_sec_a: crypto@d2000000 { compatible = "hisilicon,hip07-sec"; - reg = <0x0 0xd0000000 0x0 0x10000 - 0x0 0xd2000000 0x0 0x10000 - 0x0 0xd2010000 0x0 0x10000 - 0x0 0xd2020000 0x0 0x10000 - 0x0 0xd2030000 0x0 0x10000 - 0x0 0xd2040000 0x0 0x10000 - 0x0 0xd2050000 0x0 0x10000 - 0x0 0xd2060000 0x0 0x10000 - 0x0 0xd2070000 0x0 0x10000 - 0x0 0xd2080000 0x0 0x10000 - 0x0 0xd2090000 0x0 0x10000 - 0x0 0xd20a0000 0x0 0x10000 - 0x0 0xd20b0000 0x0 0x10000 - 0x0 0xd20c0000 0x0 0x10000 - 0x0 0xd20d0000 0x0 0x10000 - 0x0 0xd20e0000 0x0 0x10000 - 0x0 0xd20f0000 0x0 0x10000 - 0x0 0xd2100000 0x0 0x10000>; + reg = <0x0 0xd0000000 0x0 0x10000>, + <0x0 0xd2000000 0x0 0x10000>, + <0x0 0xd2010000 0x0 0x10000>, + <0x0 0xd2020000 0x0 0x10000>, + <0x0 0xd2030000 0x0 0x10000>, + <0x0 0xd2040000 0x0 0x10000>, + <0x0 0xd2050000 0x0 0x10000>, + <0x0 0xd2060000 0x0 0x10000>, + <0x0 0xd2070000 0x0 0x10000>, + <0x0 0xd2080000 0x0 0x10000>, + <0x0 0xd2090000 0x0 0x10000>, + <0x0 0xd20a0000 0x0 0x10000>, + <0x0 0xd20b0000 0x0 0x10000>, + <0x0 0xd20c0000 0x0 0x10000>, + <0x0 0xd20d0000 0x0 0x10000>, + <0x0 0xd20e0000 0x0 0x10000>, + <0x0 0xd20f0000 0x0 0x10000>, + <0x0 0xd2100000 0x0 0x10000>; interrupt-parent = <&p0_mbigen_sec_a>; iommus = <&p0_smmu_alg_a 0x600>; dma-coherent; @@ -1761,24 +1761,24 @@ }; p0_sec_b: crypto@8,d2000000 { compatible = "hisilicon,hip07-sec"; - reg = <0x8 0xd0000000 0x0 0x10000 - 0x8 0xd2000000 0x0 0x10000 - 0x8 0xd2010000 0x0 0x10000 - 0x8 0xd2020000 0x0 0x10000 - 0x8 0xd2030000 0x0 0x10000 - 0x8 0xd2040000 0x0 0x10000 - 0x8 0xd2050000 0x0 0x10000 - 0x8 0xd2060000 0x0 0x10000 - 0x8 0xd2070000 0x0 0x10000 - 0x8 0xd2080000 0x0 0x10000 - 0x8 0xd2090000 0x0 0x10000 - 0x8 0xd20a0000 0x0 0x10000 - 0x8 0xd20b0000 0x0 0x10000 - 0x8 0xd20c0000 0x0 0x10000 - 0x8 0xd20d0000 0x0 0x10000 - 0x8 0xd20e0000 0x0 0x10000 - 0x8 0xd20f0000 0x0 0x10000 - 0x8 0xd2100000 0x0 0x10000>; + reg = <0x8 0xd0000000 0x0 0x10000>, + <0x8 0xd2000000 0x0 0x10000>, + <0x8 0xd2010000 0x0 0x10000>, + <0x8 0xd2020000 0x0 0x10000>, + <0x8 0xd2030000 0x0 0x10000>, + <0x8 0xd2040000 0x0 0x10000>, + <0x8 0xd2050000 0x0 0x10000>, + <0x8 0xd2060000 0x0 0x10000>, + <0x8 0xd2070000 0x0 0x10000>, + <0x8 0xd2080000 0x0 0x10000>, + <0x8 0xd2090000 0x0 0x10000>, + <0x8 0xd20a0000 0x0 0x10000>, + <0x8 0xd20b0000 0x0 0x10000>, + <0x8 0xd20c0000 0x0 0x10000>, + <0x8 0xd20d0000 0x0 0x10000>, + <0x8 0xd20e0000 0x0 0x10000>, + <0x8 0xd20f0000 0x0 0x10000>, + <0x8 0xd2100000 0x0 0x10000>; interrupt-parent = <&p0_mbigen_sec_b>; iommus = <&p0_smmu_alg_b 0x600>; dma-coherent; @@ -1802,24 +1802,24 @@ }; p1_sec_a: crypto@400,d2000000 { compatible = "hisilicon,hip07-sec"; - reg = <0x400 0xd0000000 0x0 0x10000 - 0x400 0xd2000000 0x0 0x10000 - 0x400 0xd2010000 0x0 0x10000 - 0x400 0xd2020000 0x0 0x10000 - 0x400 0xd2030000 0x0 0x10000 - 0x400 0xd2040000 0x0 0x10000 - 0x400 0xd2050000 0x0 0x10000 - 0x400 0xd2060000 0x0 0x10000 - 0x400 0xd2070000 0x0 0x10000 - 0x400 0xd2080000 0x0 0x10000 - 0x400 0xd2090000 0x0 0x10000 - 0x400 0xd20a0000 0x0 0x10000 - 0x400 0xd20b0000 0x0 0x10000 - 0x400 0xd20c0000 0x0 0x10000 - 0x400 0xd20d0000 0x0 0x10000 - 0x400 0xd20e0000 0x0 0x10000 - 0x400 0xd20f0000 0x0 0x10000 - 0x400 0xd2100000 0x0 0x10000>; + reg = <0x400 0xd0000000 0x0 0x10000>, + <0x400 0xd2000000 0x0 0x10000>, + <0x400 0xd2010000 0x0 0x10000>, + <0x400 0xd2020000 0x0 0x10000>, + <0x400 0xd2030000 0x0 0x10000>, + <0x400 0xd2040000 0x0 0x10000>, + <0x400 0xd2050000 0x0 0x10000>, + <0x400 0xd2060000 0x0 0x10000>, + <0x400 0xd2070000 0x0 0x10000>, + <0x400 0xd2080000 0x0 0x10000>, + <0x400 0xd2090000 0x0 0x10000>, + <0x400 0xd20a0000 0x0 0x10000>, + <0x400 0xd20b0000 0x0 0x10000>, + <0x400 0xd20c0000 0x0 0x10000>, + <0x400 0xd20d0000 0x0 0x10000>, + <0x400 0xd20e0000 0x0 0x10000>, + <0x400 0xd20f0000 0x0 0x10000>, + <0x400 0xd2100000 0x0 0x10000>; interrupt-parent = <&p1_mbigen_sec_a>; iommus = <&p1_smmu_alg_a 0x600>; dma-coherent; @@ -1843,24 +1843,24 @@ }; p1_sec_b: crypto@408,d2000000 { compatible = "hisilicon,hip07-sec"; - reg = <0x408 0xd0000000 0x0 0x10000 - 0x408 0xd2000000 0x0 0x10000 - 0x408 0xd2010000 0x0 0x10000 - 0x408 0xd2020000 0x0 0x10000 - 0x408 0xd2030000 0x0 0x10000 - 0x408 0xd2040000 0x0 0x10000 - 0x408 0xd2050000 0x0 0x10000 - 0x408 0xd2060000 0x0 0x10000 - 0x408 0xd2070000 0x0 0x10000 - 0x408 0xd2080000 0x0 0x10000 - 0x408 0xd2090000 0x0 0x10000 - 0x408 0xd20a0000 0x0 0x10000 - 0x408 0xd20b0000 0x0 0x10000 - 0x408 0xd20c0000 0x0 0x10000 - 0x408 0xd20d0000 0x0 0x10000 - 0x408 0xd20e0000 0x0 0x10000 - 0x408 0xd20f0000 0x0 0x10000 - 0x408 0xd2100000 0x0 0x10000>; + reg = <0x408 0xd0000000 0x0 0x10000>, + <0x408 0xd2000000 0x0 0x10000>, + <0x408 0xd2010000 0x0 0x10000>, + <0x408 0xd2020000 0x0 0x10000>, + <0x408 0xd2030000 0x0 0x10000>, + <0x408 0xd2040000 0x0 0x10000>, + <0x408 0xd2050000 0x0 0x10000>, + <0x408 0xd2060000 0x0 0x10000>, + <0x408 0xd2070000 0x0 0x10000>, + <0x408 0xd2080000 0x0 0x10000>, + <0x408 0xd2090000 0x0 0x10000>, + <0x408 0xd20a0000 0x0 0x10000>, + <0x408 0xd20b0000 0x0 0x10000>, + <0x408 0xd20c0000 0x0 0x10000>, + <0x408 0xd20d0000 0x0 0x10000>, + <0x408 0xd20e0000 0x0 0x10000>, + <0x408 0xd20f0000 0x0 0x10000>, + <0x408 0xd2100000 0x0 0x10000>; interrupt-parent = <&p1_mbigen_sec_b>; iommus = <&p1_smmu_alg_b 0x600>; dma-coherent; -- cgit v1.2.3 From 8c563f55ee1d0241b834dd4b43be11cf7a47732b Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:31 +0800 Subject: arm64: dts: hisilicon: write the values of property-units into a uint32 array Use <> to separate the values of property-units will be treated as multiple arrays. The errors similar to the following will be reported by property-units.yaml. ufs@ff3c0000: freq-table-hz: [[0, 0], [0, 0]] is too long Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 3 ++- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 3 ++- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 9 ++++----- 3 files changed, 8 insertions(+), 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 994140fbc916..3f6b1715835a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1045,7 +1045,8 @@ clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; + freq-table-hz = <0 0 + 0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 2dcffa3ed218..668977d1acba 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -667,7 +667,8 @@ clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; + freq-table-hz = <0 0 + 0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 12bc1d3ed424..993998ac27c5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -91,11 +91,10 @@ gmacphyrst: reset-controller { compatible = "ti,syscon-reset"; #reset-cells = <1>; - ti,reset-bits = - <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | - DEASSERT_SET|STATUS_NONE)>, - <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | - DEASSERT_SET|STATUS_NONE)>; + ti,reset-bits = < + 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) + 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) + >; }; }; -- cgit v1.2.3 From 60780744d959b70fee31c053dbe7ae4a0387a8b2 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:32 +0800 Subject: arm64: dts: hisilicon: remove unused property pinctrl-names uart1 and uart5 are not used as pinctrl, so the property "pinctrl-names" can be deleted. In fact, the property "pinctrl-names" depends on the property "pinctrl-0". So the errors similar to the following will be reported by pinctrl-consumer.yaml. serial@fdf00000: 'pinctrl-0' is a dependency of 'pinctrl-names' Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 668977d1acba..85b0dfb35d6d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -213,7 +213,6 @@ clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>, <&crg_ctrl HI3670_PCLK>; clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; status = "disabled"; }; @@ -260,7 +259,6 @@ clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>, <&crg_ctrl HI3670_PCLK>; clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; status = "disabled"; }; -- cgit v1.2.3 From ee6ff04f7fe93e46b54d0b2782c7642bb1573f77 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:33 +0800 Subject: arm64: dts: hisilicon: place clock-names "biu" before "ciu" Look at the clock-names schema defined in synopsys-dw-mshc.yaml: clock-names: items: - const: biu - const: ciu The "biu" needs to be placed before the "ciu". Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 993998ac27c5..e24969d53c8f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -304,7 +304,7 @@ interrupts = ; clocks = <&crg HISTB_SDIO0_CIU_CLK>, <&crg HISTB_SDIO0_BIU_CLK>; - clock-names = "ciu", "biu"; + clock-names = "biu", "ciu"; resets = <&crg 0x9c 4>; reset-names = "reset"; status = "disabled"; -- cgit v1.2.3 From d7d45d5d116739eea6174798a0147b8e51a2e719 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:34 +0800 Subject: arm64: dts: hisilicon: normalize the node name of the SMMU devices Change the node name of the SMMU devices to match "^iommu@[0-9a-f]*". Otherwise, the errors similar to the following will be reported by arm,smmu-v3.yaml. smmu_pcie: $nodename:0: 'smmu_pcie' does not match '^iommu@[0-9a-f]*' Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 941d527dcb86..2f1930d4457f 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -330,7 +330,7 @@ * when iommu-map entry is used along with the PCIe node. * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html */ - smmu0: smmu_pcie { + smmu0: iommu@a0040000 { compatible = "arm,smmu-v3"; reg = <0x0 0xa0040000 0x0 0x20000>; #iommu-cells = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 36a873d15089..ba90b2585355 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1161,7 +1161,7 @@ * when iommu-map entry is used along with the PCIe node. * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html */ - smmu0: smmu_pcie { + smmu0: iommu@a0040000 { compatible = "arm,smmu-v3"; reg = <0x0 0xa0040000 0x0 0x20000>; #iommu-cells = <1>; @@ -1170,7 +1170,7 @@ hisilicon,broken-prefetch-cmd; status = "disabled"; }; - p0_smmu_alg_a: smmu_alg@d0040000 { + p0_smmu_alg_a: iommu@d0040000 { compatible = "arm,smmu-v3"; reg = <0x0 0xd0040000 0x0 0x20000>; interrupt-parent = <&p0_mbigen_smmu_alg_a>; @@ -1183,7 +1183,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p0_smmu_alg_b: smmu_alg@8,d0040000 { + p0_smmu_alg_b: iommu@8d0040000 { compatible = "arm,smmu-v3"; reg = <0x8 0xd0040000 0x0 0x20000>; interrupt-parent = <&p0_mbigen_smmu_alg_b>; @@ -1196,7 +1196,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_a: smmu_alg@400,d0040000 { + p1_smmu_alg_a: iommu@400d0040000 { compatible = "arm,smmu-v3"; reg = <0x400 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_a>; @@ -1209,7 +1209,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_b: smmu_alg@408,d0040000 { + p1_smmu_alg_b: iommu@408d0040000 { compatible = "arm,smmu-v3"; reg = <0x408 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_b>; -- cgit v1.2.3 From 4d2b9b98e3265a464445f9bbaa6d24213845a594 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:35 +0800 Subject: arm64: dts: hisilicon: normalize the node name of the usb devices Change the node name of the usb devices to match "^usb(@.*)?". These errors are detected by generic-ehci.yaml and generic-ohci.yaml. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index e24969d53c8f..11a72891e2a3 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -584,7 +584,7 @@ status = "disabled"; }; - ohci: ohci@9880000 { + ohci: usb@9880000 { compatible = "generic-ohci"; reg = <0x9880000 0x10000>; interrupts = ; @@ -599,7 +599,7 @@ status = "disabled"; }; - ehci: ehci@9890000 { + ehci: usb@9890000 { compatible = "generic-ehci"; reg = <0x9890000 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 2f1930d4457f..2d401d74a01f 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -373,7 +373,7 @@ #clock-cells = <0>; }; - usb_ohci: ohci@a7030000 { + usb_ohci: usb@a7030000 { compatible = "generic-ohci"; reg = <0x0 0xa7030000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; @@ -382,7 +382,7 @@ status = "disabled"; }; - usb_ehci: ehci@a7020000 { + usb_ehci: usb@a7020000 { compatible = "generic-ehci"; reg = <0x0 0xa7020000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index ba90b2585355..7832d9cdec21 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1253,7 +1253,7 @@ status = "disabled"; }; - usb_ohci: ohci@a7030000 { + usb_ohci: usb@a7030000 { compatible = "generic-ohci"; reg = <0x0 0xa7030000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; @@ -1262,7 +1262,7 @@ status = "disabled"; }; - usb_ehci: ehci@a7020000 { + usb_ehci: usb@a7020000 { compatible = "generic-ehci"; reg = <0x0 0xa7020000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; -- cgit v1.2.3 From bf69b8622b940feaf61a266e304e90722875b588 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:36 +0800 Subject: arm64: dts: hisilicon: normalize the node name of the UART devices Change the node name of the UART devices to match "^serial(@[0-9a-f,]+)*$". Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index f7e3a7af4634..26caf09e9511 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -296,7 +296,7 @@ clock-frequency = <200000000>; }; - uart0: uart@80300000 { + uart0: serial@80300000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; interrupts = ; @@ -307,7 +307,7 @@ status = "disabled"; }; - uart1: uart@80310000 { + uart1: serial@80310000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80310000 0x0 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 2d401d74a01f..7980709e21ff 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -359,7 +359,7 @@ status = "disabled"; }; - uart0: lpc-uart@2f8 { + uart0: serial@2f8 { compatible = "ns16550a"; clock-frequency = <1843200>; reg = <0x01 0x2f8 0x08>; -- cgit v1.2.3 From c85731abd6946234c9359212fff1d5f0b3013852 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:37 +0800 Subject: arm64: dts: hisilicon: list all clocks required by spi-pl022.yaml The arm,pl022 binding need to specify two clocks: "sspclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++---- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3f6b1715835a..edb80abf45b3 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -971,8 +971,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; - clock-names = "apb_pclk"; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>; + clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>; num-cs = <1>; @@ -986,8 +986,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; - clock-names = "apb_pclk"; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>; + clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>; num-cs = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 11a72891e2a3..1c7dda972c92 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -291,8 +291,8 @@ interrupts = ; num-cs = <1>; cs-gpios = <&gpio7 1 0>; - clocks = <&crg HISTB_SPI0_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 014735a9bc73..c6580c9f068e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -725,8 +725,8 @@ interrupts = <0 50 4>; bus-id = <0>; enable-dma = <0>; - clocks = <&sys_ctrl HI6220_SPI_CLK>; - clock-names = "apb_pclk"; + clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>; + clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; num-cs = <1>; -- cgit v1.2.3 From 58dd4736b8c716984a15a996e432484921e1c1e9 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:38 +0800 Subject: arm64: dts: hisilicon: list all clocks required by pl011.yaml The arm,pl011 binding need to specify two clocks: "uartclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 1c7dda972c92..81d09434c5c6 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -216,8 +216,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; interrupts = ; - clocks = <&sysctrl HISTB_UART0_CLK>; - clock-names = "apb_pclk"; + clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; @@ -225,8 +225,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x8b02000 0x1000>; interrupts = ; - clocks = <&crg HISTB_UART2_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; -- cgit v1.2.3 From c4cbd0356c60c71dd717bd0c3825bb0646a6d347 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:39 +0800 Subject: arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yaml The snps,dw-apb-uart binding need to specify two clocks: "baudclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 26caf09e9511..c073d6d8b55c 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -300,8 +300,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk200mhz>, <&refclk200mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -311,8 +311,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x0 0x80310000 0x0 0x10000>; interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk200mhz>, <&refclk200mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; -- cgit v1.2.3 From 4dc5288f5a5a60daaf9fbc56bed9b127f6e7e60f Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Wed, 11 Nov 2020 12:15:50 +0300 Subject: arm64: dts: hi3660: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index edb80abf45b3..49c19c6879f9 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1169,7 +1169,7 @@ }; }; - dwc3: dwc3@ff100000 { + dwc3: usb@ff100000 { compatible = "snps,dwc3"; reg = <0x0 0xff100000 0x0 0x100000>; -- cgit v1.2.3 From 25df3e1f64f54cfb4b23ff3ed1292c3eba94b22e Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Mon, 9 Nov 2020 17:05:29 +0800 Subject: arm64: dts: hisilicon: Use generic "ngpios" rather than "snps,nr-gpios" This is to remove similar errors as below: OF: /.../gpio-port@0: could not find phandle Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support") explained the reason of above errors well and added the generic "ngpios" property, let's use it. Signed-off-by: Jisheng Zhang Reviewed-by: Linus Walleij Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index c073d6d8b55c..405acaa3e9dd 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -335,7 +335,7 @@ compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - snps,nr-gpios = <32>; + ngpios = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -354,7 +354,7 @@ compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - snps,nr-gpios = <32>; + ngpios = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; -- cgit v1.2.3 From 6acb71fd344adb08633b2b1d8261a876fbd2bb18 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Mon, 23 Nov 2020 23:10:03 -0500 Subject: arm64: dts: qcom: sort sm8150 usb_2 node Fix an error introduced resolving conflicts with camnoc_virt node. Fixes: 0c9dde0d2015 ("arm64: dts: qcom: sm8150: Add secondary USB and PHY nodes") Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20201124041003.3600-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index e40bec6f3623..c06e0adefcf3 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -983,13 +983,6 @@ }; }; - camnoc_virt: interconnect@ac00000 { - compatible = "qcom,sm8150-camnoc-virt"; - reg = <0 0x0ac00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - usb_2: usb@a8f8800 { compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; reg = <0 0x0a8f8800 0 0x400>; @@ -1035,6 +1028,13 @@ }; }; + camnoc_virt: interconnect@ac00000 { + compatible = "qcom,sm8150-camnoc-virt"; + reg = <0 0x0ac00000 0 0x1000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sm8150-aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x100000>; -- cgit v1.2.3 From 4785cff7cb9c8bcbff3891013d2f8eb973d676f3 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Sat, 21 Nov 2020 19:41:49 -0800 Subject: arm64: dts: sdm845: Add iommus property to qup The SMMU that sits in front of the QUP needs to be programmed properly so that the i2c geni driver can allocate DMA descriptors. Failure to do this leads to faults when using devices such as an i2c touchscreen where the transaction is larger than 32 bytes and we use a DMA buffer. arm-smmu 15000000.iommu: Unexpected global fault, this could be serious arm-smmu 15000000.iommu: GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x000006c0, GFSYNR2 0x00000000 Add the right SID and mask so this works. Reviewed-by: Vinod Koul Tested-by: Caleb Connolly Tested-by: Vinod Koul Signed-off-by: Stephen Boyd [bjorn: Define for second QUP as well, be more specific in sdm845.dtsi] Link: https://lore.kernel.org/r/20201122034149.626045-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 39f23cdcbd02..216a74f0057c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -653,10 +653,12 @@ ap_ts_i2c: &i2c14 { &qupv3_id_0 { status = "okay"; + iommus = <&apps_smmu 0x0 0x3>; }; &qupv3_id_1 { status = "okay"; + iommus = <&apps_smmu 0x6c0 0x3>; }; &sdhc_2 { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 6465a6653ad9..d6b7b1bfa202 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1120,6 +1120,7 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x3 0x0>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -1460,6 +1461,7 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x6c3 0x0>; #address-cells = <2>; #size-cells = <2>; ranges; -- cgit v1.2.3 From 036e11092599131a10e34150b5b855ea86ccc546 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 20 Nov 2020 21:56:03 -0800 Subject: arm64: dts: qcom: sm8150-mtp: Specify remoteproc firmware Point the various remoteprocs of SM8150 MTP to a place with the platform specific firmware. Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201121055603.582281-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 6c6325c3af59..3719af2207d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -369,14 +369,22 @@ &remoteproc_adsp { status = "okay"; + firmware-name = "qcom/sm8150/adsp.mdt"; }; &remoteproc_cdsp { status = "okay"; + firmware-name = "qcom/sm8150/cdsp.mdt"; +}; + +&remoteproc_mpss { + status = "okay"; + firmware-name = "qcom/sm8150/modem.mdt"; }; &remoteproc_slpi { status = "okay"; + firmware-name = "qcom/sm8150/slpi.mdt"; }; &tlmm { -- cgit v1.2.3 From 05090bb9e53da0d4e913452c450cb5f55baad45a Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Fri, 20 Nov 2020 21:58:07 -0800 Subject: arm64: dts: qcom: sm8150: Add wifi node Add a node for the WCN3990 WiFi module. Reviewed-by: Vinod Koul Signed-off-by: Jonathan Marek [bjorn: Extracted patch from larger "misc" patch, added qdss clock] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201121055808.582401-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index c06e0adefcf3..8dac11c6012e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1393,6 +1393,29 @@ #freq-domain-cells = <1>; }; + + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0 0x18800000 0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_mem>; + clock-names = "cxo_ref_clk_pin", "qdss"; + clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x0640 0x1>; + status = "disabled"; + }; }; timer { -- cgit v1.2.3 From c5a0609b064ceb5ffdec9c71825d4fc6a001c068 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Fri, 20 Nov 2020 21:58:08 -0800 Subject: arm64: dts: qcom: sm8150-mtp: Enable WiFi node Enable the WiFi node and specify its supply regulators. Reviewed-by: Vinod Koul Signed-off-by: Jonathan Marek [bjorn: Extracted patch from larger HDK patch] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201121055808.582401-2-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 3719af2207d9..3774f8e63416 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -437,3 +437,12 @@ &usb_1_dwc3 { dr_mode = "peripheral"; }; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vdda_wcss_pll>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vdda_wcss_adcdac_1>; + vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; +}; -- cgit v1.2.3 From e9fd12df325e757b9ab52729260847776b9b2831 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Mon, 23 Nov 2020 09:40:16 -0500 Subject: arm64: dts: qcom: fix indentation error in sm8250 cpu nodes Use tabs instead of 6 spaces. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20201123144016.19596-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index a679f6864065..65acd1f381eb 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -93,10 +93,10 @@ qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; L3_0: l3-cache { - compatible = "cache"; + compatible = "cache"; }; }; }; @@ -110,8 +110,8 @@ qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; @@ -124,8 +124,8 @@ qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; @@ -138,8 +138,8 @@ qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; @@ -152,8 +152,8 @@ qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; @@ -166,8 +166,8 @@ qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; @@ -181,8 +181,8 @@ qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; @@ -195,8 +195,8 @@ qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; }; -- cgit v1.2.3 From 95e6f8467c83c4074a6f6b47bad00653549ff90a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sun, 22 Nov 2020 23:23:05 -0600 Subject: arm64: dts: qcom: sdm845: Limit ipa iommu streams The Android and Windows firmware does not accept the use of 3 as a mask to cover the IPA streams. But with 0x721 being related to WiFi and 0x723 being unsed the mapping can be reduced to just cover 0x720 and 0x722, which is accepted. Acked-by: Alex Elder Tested-by: Alex Elder Fixes: e9e89c45bfeb ("arm64: dts: sdm845: add IPA iommus property") Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201123052305.157686-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d6b7b1bfa202..957ee80704e7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2143,7 +2143,8 @@ ipa: ipa@1e40000 { compatible = "qcom,sdm845-ipa"; - iommus = <&apps_smmu 0x720 0x3>; + iommus = <&apps_smmu 0x720 0x0>, + <&apps_smmu 0x722 0x0>; reg = <0 0x1e40000 0 0x7000>, <0 0x1e47000 0 0x2000>, <0 0x1e04000 0 0x2c000>; -- cgit v1.2.3 From 7ee3eae868335626f83f551daee2fa98735acb74 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 8 Oct 2020 18:10:25 +0530 Subject: arm64: dts: qcom: pm6150x: add ADC_TM definitions Add ADC_TM peripheral definitions for PM6150 and PM6150L. Add ADC peripheral definition for PM6150l, which is needed for ADC_TM. Signed-off-by: Jishnu Prakash Link: https://lore.kernel.org/r/1602160825-10414-2-git-send-email-jprakash@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150.dtsi | 10 ++++++++++ arch/arm64/boot/dts/qcom/pm6150l.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 34 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 57af0b4a384d..8ab4f1f78bbf 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -52,6 +52,16 @@ }; }; + pm6150_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pm6150_gpio: gpios@c000 { compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index f84027b505d1..b49860cd1387 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -11,6 +11,30 @@ #address-cells = <1>; #size-cells = <0>; + pm6150l_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@6 { + reg = ; + label = "die_temp"; + }; + }; + + pm6150l_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pm6150l_gpio: gpios@c000 { compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio"; reg = <0xc000>; -- cgit v1.2.3 From bb06eb3607e97842b3475446069e177ed0e6b26b Mon Sep 17 00:00:00 2001 From: Antony Wang Date: Fri, 30 Oct 2020 08:48:43 -0700 Subject: arm64: qcom: sc7180: trogdor: Add ADC nodes and thermal zone for charger thermistor Trogdor has a thermistor to monitor the temperature of the charger IC. Add the ADC (monitor) nodes and a thermal zone for this thermistor. Signed-off-by: Antony Wang [mka: tweaked commit message] Signed-off-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/20201030084840.1.If389f211a8532b83095ff8c66ec181424440f8d6@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 3eb1ff2483be..e854a12f45f2 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -13,6 +13,23 @@ #include "pm6150.dtsi" #include "pm6150l.dtsi" +/ { + thermal-zones { + charger-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm6150_adc_tm 1>; + + trips { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; +}; + /* * Reserved memory changes * @@ -741,6 +758,25 @@ hp_i2c: &i2c9 { status = "okay"; }; +&pm6150_adc { + charger-thermistor@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150_adc_tm { + status = "okay"; + + charger-thermistor@1 { + reg = <1>; + io-channels = <&pm6150_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &pm6150_pwrkey { status = "disabled"; }; -- cgit v1.2.3 From d4b85bc550f49e46cf1d945a342d316c814e94c5 Mon Sep 17 00:00:00 2001 From: Terry Hsiao Date: Mon, 16 Nov 2020 16:30:14 +0800 Subject: arm64: dts: qcom: sc7180-trogdor: add "pen-insert" label for trogdor Add a label to the "pen-insert" node in sc7180-trogdor.dtsi Reviewed-by: Douglas Anderson Signed-off-by: Terry Hsiao Link: https://lore.kernel.org/r/20201116083014.547-1-terry_hsiao@compal.corp-partner.google.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index e854a12f45f2..e9b1182b3715 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -218,7 +218,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pen_pdct_l>; - pen-insert { + pen_insert: pen-insert { label = "Pen Insert"; /* Insert = low, eject = high */ -- cgit v1.2.3 From 8fd01e01fd6f8ba67e4ed8c5be0ab76d06156287 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Tue, 24 Nov 2020 11:51:15 +0530 Subject: arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite Tweak the DDR/L3 bandwidth votes on the lite variant of the SC7180 SoC since the gold cores only support frequencies upto 2.1 GHz. Reviewed-by: Douglas Anderson Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/1606198876-3515-1-git-send-email-sibis@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-lite.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-lite.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi new file mode 100644 index 000000000000..d8ed1d7b4ec7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SC7180 lite device tree source + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +&cpu6_opp10 { + opp-peak-kBps = <7216000 22425600>; +}; + +&cpu6_opp11 { + opp-peak-kBps = <7216000 22425600>; +}; + +&cpu6_opp12 { + opp-peak-kBps = <8532000 23347200>; +}; -- cgit v1.2.3 From 3c9c31c2523ecd5b609a2eecb5ad524ef4fc931c Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Tue, 24 Nov 2020 11:51:16 +0530 Subject: arm64: dts: qcom: sc7180: Add DDR/L3 votes for the pro variant Add DDR/L3 bandwidth votes for the pro variant of SC7180 SoC, as it support frequencies upto 2.5 GHz. Reviewed-by: Douglas Anderson Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/1606198876-3515-2-git-send-email-sibis@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index c0efb101b0d6..98210fdcbe25 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -527,6 +527,11 @@ opp-hz = /bits/ 64 <2400000000>; opp-peak-kBps = <8532000 23347200>; }; + + cpu6_opp16: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <8532000 23347200>; + }; }; memory@80000000 { -- cgit v1.2.3 From 74790cf981afd9806939427ad7701f3022ee5c06 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 Nov 2020 16:20:46 +0100 Subject: arm64: zynqmp: Move gic node to axi bus The reason for this change is that after change from amba to axi U-Boot started to show error like: Unable to update property /axi/ethernet@ff0e0000:mac-address, err=FDT_ERR_NOTFOUND Unable to update property /axi/ethernet@ff0e0000:local-mac-address, err=FDT_ERR_NOTFOUND The reason is implementation in fdt_nodename_eq_() which is taken from dtc to the kernel and to the U-Boot. Especially DTC commit d2a9da045897 ("libfdt: Make unit address optional for finding nodes") which is in DTC from 2007. The part of commit description is " This is contrary to traditional OF-like finddevice() behaviour, which allows the unit address to be omitted (which is useful when the device name is unambiguous without the address)." The kernel commit dfff9066e60e ("arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml") changed amba-apu/amba to axi@0/axi but fdt_nodename_eq_() detects /axi/ as match for /axi@0/ because of commit above. That's why it easier to fix one DT inside the kernel by moving GIC node from own bus to generic axi bus as is done by others SoCs. This will avoid incorrect match because the unit address is omitted. Reported-by: Paul Thomas Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f767fe007e446a2299fda9905e75b723c650a424.1605021644.git.michal.simek@xilinx.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 31 ++++++++++++------------------- 1 file changed, 12 insertions(+), 19 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 771f60e0346d..515b15ed634a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -182,25 +182,6 @@ ranges; }; - amba_apu: axi@0 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0 0xffffffff>; - - gic: interrupt-controller@f9010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - reg = <0x0 0xf9010000 0x10000>, - <0x0 0xf9020000 0x20000>, - <0x0 0xf9040000 0x20000>, - <0x0 0xf9060000 0x20000>; - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <1 9 0xf04>; - }; - }; - amba: axi { compatible = "simple-bus"; #address-cells = <2>; @@ -339,6 +320,18 @@ power-domains = <&zynqmp_firmware PD_GDMA>; }; + gic: interrupt-controller@f9010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + reg = <0x0 0xf9010000 0x0 0x10000>, + <0x0 0xf9020000 0x0 0x20000>, + <0x0 0xf9040000 0x0 0x20000>, + <0x0 0xf9060000 0x0 0x20000>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <1 9 0xf04>; + }; + /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. -- cgit v1.2.3 From 48ab2996f6837aa888ccc0671de7ef3e3185992e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 29 Sep 2020 13:43:22 +0200 Subject: arm64: dts: zynqmp: Fix pcie ranges description DT schema is checking tuples which should be properly separated. The patch is doing this separation to avoid the following warning: ..yaml: axi: pcie@fd0e0000:ranges: [[33554432, 0, 3758096384, 0, 3758096384, 0, 268435456, 1124073472, 6, 0, 6, 0, 2, 0]] is not valid under any of the given schemas (Possible causes of the failure): ...dt.yaml: axi: pcie@fd0e0000:ranges: True was expected ...dt.yaml: axi: pcie@fd0e0000:ranges:0: [33554432, 0, 3758096384, 0, 3758096384, 0, 268435456, 1124073472, 6, 0, 6, 0, 2, 0] is too long Signed-off-by: Michal Simek Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/f59a63d8cb941592de6d2dee8afa6f120b2e40c8.1601379794.git.michal.simek@xilinx.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 515b15ed634a..66dad22b8a76 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -535,8 +535,8 @@ <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ - 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ + ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ + <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, -- cgit v1.2.3 From 9854bc7dfa5f7661538b08dc44d5e6c8876832fb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 12 Nov 2020 13:52:34 +0100 Subject: arm64: dts: zynqmp: Wire mailbox with zynqmp-power driver The support to driver was added by commit ffdbae28d9d1 ("drivers: soc: xilinx: Use mailbox IPI callback") that's why also enable it via DT by default. It setups communication with firmware via IPI interface. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5d3523150890e494df308ee69523d0f0e7b33b22.1605185549.git.michal.simek@xilinx.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 66dad22b8a76..68923fbd0e89 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -99,6 +99,29 @@ }; }; + zynqmp_ipi { + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = <0 35 4>; + xlnx,ipi-id = <0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipi_mailbox_pmu1: mailbox@ff990400 { + reg = <0x0 0xff9905c0 0x0 0x20>, + <0x0 0xff9905e0 0x0 0x20>, + <0x0 0xff990e80 0x0 0x20>, + <0x0 0xff990ea0 0x0 0x20>; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <4>; + }; + }; + dcc: dcc { compatible = "arm,dcc"; status = "disabled"; @@ -128,6 +151,8 @@ compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; + mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; + mbox-names = "tx", "rx"; }; zynqmp_clk: clock-controller { -- cgit v1.2.3 From 3b4c137856d94f94231415793f45a104a19c3604 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 13 Oct 2020 10:58:51 +0100 Subject: arm64: tegra: Add missing CPU PMUs on Tegra186 Add the description of CPU PMUs for both the Denver and A57 clusters, which enables the perf subsystem. Signed-off-by: Marc Zyngier Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 0c46ab7bbbf3..a55d7ac95323 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1534,7 +1534,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + denver_0: cpu@0 { compatible = "nvidia,tegra186-denver"; device_type = "cpu"; i-cache-size = <0x20000>; @@ -1547,7 +1547,7 @@ reg = <0x000>; }; - cpu@1 { + denver_1: cpu@1 { compatible = "nvidia,tegra186-denver"; device_type = "cpu"; i-cache-size = <0x20000>; @@ -1560,7 +1560,7 @@ reg = <0x001>; }; - cpu@2 { + ca57_0: cpu@2 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>; @@ -1573,7 +1573,7 @@ reg = <0x100>; }; - cpu@3 { + ca57_1: cpu@3 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>; @@ -1586,7 +1586,7 @@ reg = <0x101>; }; - cpu@4 { + ca57_2: cpu@4 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>; @@ -1599,7 +1599,7 @@ reg = <0x102>; }; - cpu@5 { + ca57_3: cpu@5 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>; @@ -1631,6 +1631,22 @@ }; }; + pmu_denver { + compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3"; + interrupts = , + ; + interrupt-affinity = <&denver_0 &denver_1>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; + }; + thermal-zones { a57 { polling-delay = <0>; -- cgit v1.2.3 From 776a3c04da9fa144241476f4a0d263899d6cad26 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Mon, 5 Oct 2020 14:32:56 +0100 Subject: arm64: tegra: Fix GIC400 missing GICH/GICV register regions GIC400 has full support for virtualization, and yet the tegra186 DT doesn't expose the GICH/GICV regions (despite exposing the maintenance interrupt that only makes sense for virtualization). Add the missing regions, based on the hunch that the HW doesn't use the CPU build-in interfaces, but instead the external ones provided by the GIC. KVM's virtual GIC now works with this change. Signed-off-by: Marc Zyngier Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index a55d7ac95323..98544d16d01b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -845,7 +845,9 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x03881000 0x0 0x1000>, - <0x0 0x03882000 0x0 0x2000>; + <0x0 0x03882000 0x0 0x2000>, + <0x0 0x03884000 0x0 0x2000>, + <0x0 0x03886000 0x0 0x2000>; interrupts = ; interrupt-parent = <&gic>; -- cgit v1.2.3 From 6b26c1a034885923822f6c4d94f8644d32bc2481 Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Mon, 26 Oct 2020 12:09:02 +0530 Subject: arm64: tegra: Fix DT binding for IO High Voltage entry Fix the device-tree entry that represents I/O High Voltage property by replacing 'nvidia,io-high-voltage' with 'nvidia,io-hv' as the former entry is deprecated. Fixes: dbb72e2c305b ("arm64: tegra: Add configuration for PCIe C5 sideband signals") Signed-off-by: Vidya Sagar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 93438d2b9469..6946fb210e48 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -378,7 +378,7 @@ nvidia,schmitt = ; nvidia,lpdr = ; nvidia,enable-input = ; - nvidia,io-high-voltage = ; + nvidia,io-hv = ; nvidia,tristate = ; nvidia,pull = ; }; @@ -390,7 +390,7 @@ nvidia,schmitt = ; nvidia,lpdr = ; nvidia,enable-input = ; - nvidia,io-high-voltage = ; + nvidia,io-hv = ; nvidia,tristate = ; nvidia,pull = ; }; -- cgit v1.2.3 From 5aaa0de991c7604b94b4765c3f8d054e31363cf1 Mon Sep 17 00:00:00 2001 From: Nicolas Chauvet Date: Sun, 27 Sep 2020 17:09:53 +0200 Subject: arm64: tegra: Add missing hot temperatures to Tegra132 thermal-zones According to dmesg, thermal-zones for mem and cpu are missing hot temperatures properties. throttrip: pll: missing hot temperature ... throttrip: mem: missing hot temperature ... Adding them will clear the messages. Signed-off-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index e40281510c0c..cd913e59ba26 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -925,6 +925,11 @@ hysteresis = <1000>; type = "critical"; }; + mem_throttle_trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; }; cooling-maps { @@ -975,6 +980,11 @@ hysteresis = <1000>; type = "critical"; }; + pllx_throttle_trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; }; cooling-maps { -- cgit v1.2.3 From 3146cd55b00172c33d04638ee4a9287767d289eb Mon Sep 17 00:00:00 2001 From: Nicolas Chauvet Date: Sun, 27 Sep 2020 17:09:54 +0200 Subject: arm64: tegra: Add missing gpu-throt-level to Tegra210 soctherm On Jetson TX1 the following message can be seen: tegra_soctherm 700e2000.thermal-sensor: throttle-cfg: heavy: no throt prop or invalid prop This patch will fix the invalid prop issue according to the binding. Signed-off-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index d47c88950d38..a17ffdbba37c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1724,6 +1724,7 @@ throttle_heavy: heavy { nvidia,priority = <100>; nvidia,cpu-throt-percent = <85>; + nvidia,gpu-throt-level = ; #cooling-cells = <2>; }; -- cgit v1.2.3 From fdf278257e6de4a5754f58778efb3dfc3a646b0e Mon Sep 17 00:00:00 2001 From: Nicolas Chauvet Date: Sun, 27 Sep 2020 17:09:55 +0200 Subject: arm64: tegra: Add missing hot temperatures to Tegra210 thermal-zones According to dmesg, thermal-zones for mem and cpu are missing hot temperatures properties. throttrip: pll: missing hot temperature ... throttrip: mem: missing hot temperature ... Adding them will clear the messages. Signed-off-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a17ffdbba37c..f31f75d9727d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1781,6 +1781,12 @@ type = "active"; }; + mem-hot-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + mem-shutdown-trip { temperature = <103000>; hysteresis = <0>; @@ -1843,6 +1849,12 @@ hysteresis = <0>; type = "critical"; }; + + pllx-throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; }; cooling-maps { -- cgit v1.2.3 From 1289bd9fec206dd8a854d6dba841e8d8a0d84f3e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 20 Nov 2020 16:19:29 +0100 Subject: arm64: tegra: Hook up edp interrupt on Tegra132 SOCTHERM For some reason this was never hooked up. Do it now so that over-current interrupts can be logged. Reported-by: Nicolas Chauvet Suggested-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index cd913e59ba26..0ce958a4f879 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -865,7 +865,9 @@ reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */ <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ reg-names = "soctherm-reg", "ccroc-reg"; - interrupts = ; + interrupts = , + ; + interrupt-names = "thermal", "edp"; clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, <&tegra_car TEGRA124_CLK_SOC_THERM>; clock-names = "tsensor", "soctherm"; -- cgit v1.2.3 From b6e136c7e6ad4e379e58b3838ef3d8a8c669cd6d Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Thu, 5 Nov 2020 15:54:03 +0530 Subject: arm64: tegra: Rename ADMA device nodes for Tegra210 DMA device nodes should follow regex pattern of "^dma-controller(@.*)?$". This is a preparatory patch to use YAML doc format for ADMA. Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 4c9c2a054642..69102dcea8b0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -119,7 +119,7 @@ aconnect@702c0000 { status = "okay"; - dma@702e2000 { + dma-controller@702e2000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 859241db4b4d..6a877decffc1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -629,7 +629,7 @@ aconnect@702c0000 { status = "okay"; - dma@702e2000 { + dma-controller@702e2000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index bd78378248a6..131c064d6991 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1717,7 +1717,7 @@ aconnect@702c0000 { status = "okay"; - dma@702e2000 { + dma-controller@702e2000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index f31f75d9727d..6d2a9d259319 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1344,7 +1344,7 @@ ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; status = "disabled"; - adma: dma@702e2000 { + adma: dma-controller@702e2000 { compatible = "nvidia,tegra210-adma"; reg = <0x702e2000 0x2000>; interrupt-parent = <&agic>; -- cgit v1.2.3 From 2961f69f151c0a6771f55cef46398fe49ca20902 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Thu, 12 Nov 2020 16:08:32 +0100 Subject: arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit They don't descibe hardware fully yet but it's enough to boot a system. Some missing blocks: 1. PMC (Power Management Controller?) 2. Ethernet 3. Crypto 4. Thermal Asus DTS is missing defining full NAND partitions layout and buttons. Further changes will fill those gaps as soon as required bindings will be found / tested / added. Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/Makefile | 1 + arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 2 + .../broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts | 66 ++++++++ arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 187 +++++++++++++++++++++ 4 files changed, 256 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/Makefile create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index cb7de8d99223..998e240aa698 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -5,5 +5,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ bcm2837-rpi-cm3-io3.dtb +subdir-y += bcm4908 subdir-y += northstar2 subdir-y += stingray diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile new file mode 100644 index 000000000000..ef26c23603ce --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts new file mode 100644 index 000000000000..13c6b86eef21 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include + +#include "bcm4908.dtsi" + +/ { + compatible = "asus,gt-ac5300", "brcm,bcm4908"; + model = "Asus GT-AC5300"; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00 0x00 0x40000000>; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + wifi { + label = "WiFi"; + linux,code = ; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + + brightness { + label = "LEDs"; + linux,code = ; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&nandcs { + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + brcm,nand-has-wp; + + #address-cells = <1>; + #size-cells = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "cferom"; + reg = <0x0 0x100000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi new file mode 100644 index 000000000000..f873dc44ce9c --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include + +/dts-v1/; + +/ { + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x0>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x81000000 0x4000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + clocks { + periph_clk: periph_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "periph"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x80000000 0x10000>; + + usb@c300 { + compatible = "generic-ehci"; + reg = <0xc300 0x100>; + interrupts = ; + status = "disabled"; + }; + + usb@c400 { + compatible = "generic-ohci"; + reg = <0xc400 0x100>; + interrupts = ; + status = "disabled"; + }; + + usb@d000 { + compatible = "generic-xhci"; + reg = <0xd000 0x8c8>; + interrupts = ; + status = "disabled"; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0xff800000 0x3000>; + + timer: timer@400 { + compatible = "brcm,bcm6328-timer", "syscon"; + reg = <0x400 0x3c>; + }; + + gpio0: gpio-controller@500 { + compatible = "brcm,bcm6345-gpio"; + reg-names = "dirout", "dat"; + reg = <0x500 0x28>, <0x528 0x28>; + + #gpio-cells = <2>; + gpio-controller; + }; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x18>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "periph"; + status = "okay"; + }; + + nand@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + interrupts = ; + interrupt-names = "nand"; + status = "okay"; + + nandcs: nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&timer>; + offset = <0x34>; + mask = <1>; + }; + }; +}; -- cgit v1.2.3 From dccb22d078ebd098115e4f66bde1ee2249c8640b Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Thu, 12 Nov 2020 16:08:30 +0100 Subject: arm64: add config for Broadcom BCM4908 SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add ARCH_BCM4908 config that can be used for compiling DTS files. Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Florian Fainelli --- arch/arm64/Kconfig.platforms | 8 ++++++++ arch/arm64/configs/defconfig | 1 + 2 files changed, 9 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6f2494dd6d60..ec60d32e8d5f 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -43,6 +43,14 @@ config ARCH_BCM2835 This enables support for the Broadcom BCM2837 and BCM2711 SoC. These SoCs are used in the Raspberry Pi 3 and 4 devices. +config ARCH_BCM4908 + bool "Broadcom BCM4908 family" + select GPIOLIB + help + This enables support for the Broadcom BCM4906, BCM4908 and + BCM49408 SoCs. These SoCs use Brahma-B53 cores and can be + found in home routers. + config ARCH_BCM_IPROC bool "Broadcom iProc SoC Family" select COMMON_CLK_IPROC diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..ead6fa942994 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -32,6 +32,7 @@ CONFIG_ARCH_AGILEX=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_ALPINE=y CONFIG_ARCH_BCM2835=y +CONFIG_ARCH_BCM4908=y CONFIG_ARCH_BCM_IPROC=y CONFIG_ARCH_BERLIN=y CONFIG_ARCH_BRCMSTB=y -- cgit v1.2.3 From 066c2a9448681b5fb1cfe459c5a1b9d817b017fb Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 24 Nov 2020 16:48:13 -0800 Subject: arm64: dts: qcom: sc7180-trogdor: Make pp3300_a the default supply for pp3300_hub The trogdor design has two options for supplying the 'pp3300_hub' power rail, it can be supplied by 'pp3300_l7c' or 'pp3300_a'. The 'pp3300_a' path includes a load switch that can be controlled through GPIO84. Initially trogdor boards used 'pp3300_l7c' to power the USB hub, newer revisions (will) use 'pp3300_a' as supply for 'pp3300_hub'. Add a DT node for the 'pp3300_a' path and a pinctrl entry for the GPIO. Make this path the default and keep trogdor rev1, lazor rev0 and rev1 on 'pp3300_l7c'. These earlier revisions also allocated the GPIO to the purpose of controlling the power switch, so there is no need to limit the pinctrl config to newer revisions. Remove the platform-wide 'always/boot-on' properties from 'pp3300_l7c' and add them to the boards that use this supply. Also delete the 'always/boot-on' properties of 'pp3300_hub' for these boards. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20201124164714.v4.1.I0ed4abdd2b2916fbedf76be254bc3457fb8b9655@changeid Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc7180-trogdor-lazor-r0.dts | 11 +++++++ .../boot/dts/qcom/sc7180-trogdor-lazor-r1.dts | 11 +++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 11 +++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 34 ++++++++++++++++++++-- 4 files changed, 64 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts index ae4c23a4fe65..30e3e769d2b4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts @@ -14,6 +14,17 @@ compatible = "google,lazor-rev0", "qcom,sc7180"; }; +&pp3300_hub { + /* pp3300_l7c is used to power the USB hub */ + /delete-property/regulator-always-on; + /delete-property/regulator-boot-on; +}; + +&pp3300_l7c { + regulator-always-on; + regulator-boot-on; +}; + &sn65dsi86_out { /* * Lane 0 was incorrectly mapped on the cable, but we've now decided diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts index 9354d4c5ef7d..c2ef06367baf 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts @@ -13,3 +13,14 @@ model = "Google Lazor (rev1 - 2)"; compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180"; }; + +&pp3300_hub { + /* pp3300_l7c is used to power the USB hub */ + /delete-property/regulator-always-on; + /delete-property/regulator-boot-on; +}; + +&pp3300_l7c { + regulator-always-on; + regulator-boot-on; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 59d67fb0efe8..2cb522d6962e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -53,6 +53,17 @@ ap_ts_pen_1v8: &i2c4 { }; }; +&pp3300_hub { + /* pp3300_l7c is used to power the USB hub */ + /delete-property/regulator-always-on; + /delete-property/regulator-boot-on; +}; + +&pp3300_l7c { + regulator-always-on; + regulator-boot-on; +}; + &sdhc_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index e9b1182b3715..8ed7dd39f6e3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -191,6 +191,24 @@ vin-supply = <&pp3300_a>; }; + pp3300_hub: pp3300-hub { + compatible = "regulator-fixed"; + regulator-name = "pp3300_hub"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_hub>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&pp3300_a>; + }; + /* BOARD-SPECIFIC TOP LEVEL NODES */ backlight: backlight { @@ -495,13 +513,10 @@ regulator-initial-mode = ; }; - pp3300_hub: pp3300_l7c: ldo7 { regulator-min-microvolt = <3304000>; regulator-max-microvolt = <3304000>; regulator-initial-mode = ; - regulator-always-on; - regulator-boot-on; }; pp1800_brij_vccio: @@ -1221,6 +1236,19 @@ ap_spi_fp: &spi10 { }; }; + en_pp3300_hub: en-pp3300-hub { + pinmux { + pins = "gpio84"; + function = "gpio"; + }; + + pinconf { + pins = "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + fpmcu_boot0: fpmcu-boot0 { pinmux { pins = "gpio10"; -- cgit v1.2.3 From 6450da3dab73e25e38b7efd57b0699d3d01bde26 Mon Sep 17 00:00:00 2001 From: JC Kuo Date: Thu, 19 Nov 2020 16:54:03 +0800 Subject: arm64: tegra: Add XUSB pad controller interrupt This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194 XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake event happens. This is required for supporting XUSB host controller ELPG. Signed-off-by: JC Kuo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 98544d16d01b..53ab8e5487e0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -685,6 +685,7 @@ reg = <0x0 0x03520000 0x0 0x1000>, <0x0 0x03540000 0x0 0x1000>; reg-names = "padctl", "ao"; + interrupts = ; resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; reset-names = "padctl"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 6946fb210e48..c84d1f040111 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -801,6 +801,7 @@ reg = <0x03520000 0x1000>, <0x03540000 0x1000>; reg-names = "padctl", "ao"; + interrupts = ; resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; reset-names = "padctl"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 6d2a9d259319..9a7c511913d8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1040,6 +1040,7 @@ padctl: padctl@7009f000 { compatible = "nvidia,tegra210-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; + interrupts = ; resets = <&tegra_car 142>; reset-names = "padctl"; -- cgit v1.2.3 From c84ebdfd26645731cc1d9255df94b66de489093e Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Mon, 23 Nov 2020 12:17:21 -0800 Subject: arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210 Tegra AHCI dt-binding doc is converted from text based to yaml based. dtbs_check valdiation strictly follows reset-names order specified in yaml dt-binding. Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold. Tegra186 has 2 resets sata and sata-cold. This patch changes order of SATA resets to maintain proper resets order for commonly available resets across Tegra124 thru Tegra186 for dtbs_check to pass. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 +++--- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 0ce958a4f879..9928a87f593a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -629,9 +629,9 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "sata", "sata-oob", "cml1", "pll_e"; resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 9a7c511913d8..4fbf8c15b0a1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -979,9 +979,9 @@ <&tegra_car TEGRA210_CLK_SATA_OOB>; clock-names = "sata", "sata-oob"; resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; status = "disabled"; }; -- cgit v1.2.3 From e061fbdf7d78813a352a6c179fca837e1842883b Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Mon, 23 Nov 2020 12:17:24 -0800 Subject: arm64: tegra: Enable AHCI on Jetson TX2 This patch enables AHCI on Jetson TX2. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 4 ++++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 ++++++++++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index c28d51cc5797..6fd2e0542c27 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -285,6 +285,10 @@ }; }; + sata@3507000 { + status = "okay"; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 53ab8e5487e0..58c51965df47 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1504,6 +1504,34 @@ }; }; + sata@3507000 { + compatible = "nvidia,tegra186-ahci"; + reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ + <0x0 0x03500000 0x0 0x00007000>, /* SATA */ + <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ + interrupts = ; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_SATA>; + + clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; + assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, + <&bpmp TEGRA186_CLK_PLLP>; + assigned-clock-rates = <102000000>, + <204000000>; + resets = <&bpmp TEGRA186_RESET_SATA>, + <&bpmp TEGRA186_RESET_SATACOLD>; + reset-names = "sata", "sata-cold"; + status = "disabled"; + }; + bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, -- cgit v1.2.3 From 48f6e195039486bc303118948f49a9873acc888f Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Wed, 18 Nov 2020 13:36:20 +0530 Subject: arm64: tegra: Fix Tegra194 HDA {clock,reset}-names ordering As per the HDA binding doc reorder {clock,reset}-names entries for Tegra194. This also serves as a preparation for converting existing binding doc to json-schema. Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c84d1f040111..25f36d6118f8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -782,13 +782,13 @@ reg = <0x3510000 0x10000>; interrupts = ; clocks = <&bpmp TEGRA194_CLK_HDA>, - <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, - <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; - clock-names = "hda", "hda2codec_2x", "hda2hdmi"; + <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, + <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; resets = <&bpmp TEGRA194_RESET_HDA>, - <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, - <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; - reset-names = "hda", "hda2codec_2x", "hda2hdmi"; + <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, + <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; -- cgit v1.2.3 From 24244cefeddef68da2030dabdcd8079f31c5be25 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Thu, 26 Nov 2020 10:54:22 +0530 Subject: arm64: dts: qcom: sm8150: Add Coresight support Add coresight components found on Qualcomm Technologies, Inc. SM8150 SoC. Signed-off-by: Sai Prakash Ranjan Reviewed-by: Mathieu Poirier Link: https://lore.kernel.org/r/20201126052422.24869-1-saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 591 +++++++++++++++++++++++++++++++++++ 1 file changed, 591 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 8dac11c6012e..5270bda7418f 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -798,6 +798,597 @@ }; }; + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x06002000 0 0x1000>, + <0 0x16280000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06041000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06042000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = <&merge_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel1_in4: endpoint { + remote-endpoint = <&swao_replicator_out>; + }; + }; + }; + }; + + funnel@6043000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06043000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel2_out: endpoint { + remote-endpoint = <&merge_funnel_in2>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + funnel2_in2: endpoint { + remote-endpoint = <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06045000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = <&funnel1_out>; + }; + }; + + port@2 { + reg = <2>; + merge_funnel_in2: endpoint { + remote-endpoint = <&funnel2_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06046000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&replicator1_in>; + }; + }; + }; + + in-ports { + port { + replicator_in0: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@6047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06047000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&replicator_in0>; + }; + }; + }; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&merge_funnel_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06048000 0 0x1000>; + iommus = <&apps_smmu 0x05e0 0x0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out0>; + }; + }; + }; + }; + + replicator@604a000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x0604a000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + replicator1_out: endpoint { + remote-endpoint = <&swao_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + replicator1_in: endpoint { + remote-endpoint = <&replicator_out1>; + }; + }; + }; + }; + + funnel@6b08000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06b08000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + swao_funnel_out: endpoint { + remote-endpoint = <&swao_etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + swao_funnel_in: endpoint { + remote-endpoint = <&replicator1_out>; + }; + }; + }; + }; + + etf@6b09000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06b09000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + swao_etf_out: endpoint { + remote-endpoint = <&swao_replicator_in>; + }; + }; + }; + + in-ports { + port { + swao_etf_in: endpoint { + remote-endpoint = <&swao_funnel_out>; + }; + }; + }; + }; + + replicator@6b0a000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06b0a000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,replicator-loses-context; + + out-ports { + port { + swao_replicator_out: endpoint { + remote-endpoint = <&funnel1_in4>; + }; + }; + }; + + in-ports { + port { + swao_replicator_in: endpoint { + remote-endpoint = <&swao_etf_out>; + }; + }; + }; + }; + + etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07040000 0 0x1000>; + + cpu = <&CPU0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07140000 0 0x1000>; + + cpu = <&CPU1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07240000 0 0x1000>; + + cpu = <&CPU2>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07340000 0 0x1000>; + + cpu = <&CPU3>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07440000 0 0x1000>; + + cpu = <&CPU4>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07540000 0 0x1000>; + + cpu = <&CPU5>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07640000 0 0x1000>; + + cpu = <&CPU6>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07740000 0 0x1000>; + + cpu = <&CPU7>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { /* APSS Funnel */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07800000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07810000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = <&funnel2_in2>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = <&apss_funnel_out>; + }; + }; + }; + }; + remoteproc_cdsp: remoteproc@8300000 { compatible = "qcom,sm8150-cdsp-pas"; reg = <0x0 0x08300000 0x0 0x4040>; -- cgit v1.2.3 From 8f34831d3659d38f480fddccb76d84c6c3e0ac0b Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Wed, 25 Nov 2020 19:54:55 -0600 Subject: arm64: dts: qcom: sc7180: limit IPA iommu streams Recently we learned that Android and Windows firmware don't seem to like using 3 as an iommu mask value for IPA. A simple fix was to specify exactly the streams needed explicitly, rather than implying a range with the mask. Make the same change for the SC7180 platform. See also: https://lore.kernel.org/linux-arm-msm/20201123052305.157686-1-bjorn.andersson@linaro.org/ Fixes: d82fade846aa8 ("arm64: dts: qcom: sc7180: add IPA information") Reviewed-by: Bjorn Andersson Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20201126015457.6557-2-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 98210fdcbe25..d24ebc64c8b8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1401,7 +1401,8 @@ ipa: ipa@1e40000 { compatible = "qcom,sc7180-ipa"; - iommus = <&apps_smmu 0x440 0x3>; + iommus = <&apps_smmu 0x440 0x0>, + <&apps_smmu 0x442 0x0>; reg = <0 0x1e40000 0 0x7000>, <0 0x1e47000 0 0x2000>, <0 0x1e04000 0 0x2c000>; -- cgit v1.2.3 From cfee3ea05cf2c28e24801811b0109689b3303caa Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Wed, 25 Nov 2020 19:54:56 -0600 Subject: arm64: dts: qcom: sc7180: use GIC_SPI for IPA interrupts Use GIC_SPI rather than 0 in the specifiers for the two ARM GIC interrupts used by IPA. Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20201126015457.6557-3-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index d24ebc64c8b8..c7c701e32b9a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1410,8 +1410,8 @@ "ipa-shared", "gsi"; - interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, - <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", -- cgit v1.2.3 From 0fc0f4b6aded9ac5316e1c0d49c3813586415e90 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Wed, 25 Nov 2020 19:54:57 -0600 Subject: arm64: dts: qcom: sdm845: use GIC_SPI for IPA interrupts Use GIC_SPI rather than 0 in the specifiers for the two ARM GIC interrupts used by IPA. Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20201126015457.6557-4-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 957ee80704e7..256a698745ac 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2152,8 +2152,8 @@ "ipa-shared", "gsi"; - interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, - <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", -- cgit v1.2.3 From 0f80b9b8126cf3e352aa6b270ed24c9cd9a6272b Mon Sep 17 00:00:00 2001 From: Yuya Hamamachi Date: Wed, 25 Nov 2020 16:33:03 +0900 Subject: arm64: dts: renesas: r8a77951: Add PCIe EP nodes Add PCIe EP nodes for R8A77951 SoC dtsi. Signed-off-by: Yuya Hamamachi Link: https://lore.kernel.org/r/20201125073303.19057-3-yuya.hamamachi.sx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 38 +++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 644308dd886c..9d60bcf69e4f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2727,6 +2727,44 @@ status = "disabled"; }; + pciec0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a7795-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@ee800000 { + compatible = "renesas,r8a7795-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xee800000 0 0x80000>, + <0x0 0xee900000 0 0x100000>, + <0x0 0xeea00000 0 0x200000>, + <0x0 0xc0000000 0 0x8000000>, + <0x0 0xc8000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 318>; + clock-names = "pcie"; + resets = <&cpg 318>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + status = "disabled"; + }; + imr-lx4@fe860000 { compatible = "renesas,r8a7795-imr-lx4", "renesas,imr-lx4"; -- cgit v1.2.3 From 17fb46bf56864d7a2020f06ff549d5fa8b4426d7 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Fri, 16 Oct 2020 19:18:37 +0200 Subject: arm64: dts: mediatek: mt8516: add efuse node Add node to support e-fuses on MT8516 Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201016171837.3261310-2-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index eca7969e15ab..e6e4d9d60094 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -237,6 +237,13 @@ interrupts = ; }; + efuse: efuse@10009000 { + compatible = "mediatek,mt8516-efuse", "mediatek,efuse"; + reg = <0 0x10009000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + pwrap: pwrap@1000f000 { compatible = "mediatek,mt8516-pwrap"; reg = <0 0x1000f000 0 0x1000>; -- cgit v1.2.3 From 08d73b65abaf154a5d685d5dcd208d191115b24d Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 27 Oct 2020 20:48:14 +0100 Subject: arm64: dts: mediatek: add dtsi for MT8167 The MT8167 SoC provides the following peripherals: GPIO, UART, USB2, SPI, eMMC, SDIO, NAND, Flash, ADC, I2C, PWM, TImers, IR, Ethernet, Audio (I2S, SPDIF, TDM, HDMI), HDMI, DSI, CSI, MDP (Multimedia Data Path), Video encoding (H.264), Video Decoding (H.264, VP8). The MT8167 is compatible with MT8516 but provides multimedia IPs to it. This commit is just adding the basic dtsi file with the support of the following IOs: GPIO, Clocks. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201027194816.1227654-2-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h | 744 ++++++++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8167.dtsi | 61 +++ 2 files changed, 805 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h create mode 100644 arch/arm64/boot/dts/mediatek/mt8167.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h new file mode 100644 index 000000000000..061c3255a973 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h @@ -0,0 +1,744 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + */ +#ifndef __DTS_MT8167_PINFUNC_H +#define __DTS_MT8167_PINFUNC_H + +#include + +#define MT8167_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8167_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1) +#define MT8167_PIN_0_EINT0__FUNC_DPI_CK (MTK_PIN_NO(0) | 2) +#define MT8167_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) +#define MT8167_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) +#define MT8167_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6) +#define MT8167_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7) + +#define MT8167_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8167_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1) +#define MT8167_PIN_1_EINT1__FUNC_DPI_D12 (MTK_PIN_NO(1) | 2) +#define MT8167_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3) +#define MT8167_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) +#define MT8167_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5) +#define MT8167_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6) +#define MT8167_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7) + +#define MT8167_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8167_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1) +#define MT8167_PIN_2_EINT2__FUNC_DPI_D13 (MTK_PIN_NO(2) | 2) +#define MT8167_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3) +#define MT8167_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) +#define MT8167_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5) +#define MT8167_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6) +#define MT8167_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7) + +#define MT8167_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8167_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1) +#define MT8167_PIN_3_EINT3__FUNC_DPI_D14 (MTK_PIN_NO(3) | 2) +#define MT8167_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3) +#define MT8167_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) +#define MT8167_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5) +#define MT8167_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6) +#define MT8167_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7) + +#define MT8167_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8167_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1) +#define MT8167_PIN_4_EINT4__FUNC_DPI_D15 (MTK_PIN_NO(4) | 2) +#define MT8167_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3) +#define MT8167_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) +#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5) +#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6) +#define MT8167_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7) + +#define MT8167_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8167_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1) +#define MT8167_PIN_5_EINT5__FUNC_DPI_D16 (MTK_PIN_NO(5) | 2) +#define MT8167_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3) +#define MT8167_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) +#define MT8167_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5) +#define MT8167_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6) +#define MT8167_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7) + +#define MT8167_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8167_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1) +#define MT8167_PIN_6_EINT6__FUNC_DPI_D17 (MTK_PIN_NO(6) | 2) +#define MT8167_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3) +#define MT8167_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) +#define MT8167_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5) +#define MT8167_PIN_6_EINT6__FUNC_MM_TEST_CK (MTK_PIN_NO(6) | 6) +#define MT8167_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7) + +#define MT8167_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8167_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1) +#define MT8167_PIN_7_EINT7__FUNC_DPI_D6 (MTK_PIN_NO(7) | 2) +#define MT8167_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3) +#define MT8167_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) +#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5) +#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) | 6) +#define MT8167_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) | 7) + +#define MT8167_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8167_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) | 1) +#define MT8167_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) | 2) +#define MT8167_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) | 3) +#define MT8167_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) +#define MT8167_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) | 5) +#define MT8167_PIN_8_EINT8__FUNC_DPI_D7 (MTK_PIN_NO(8) | 6) +#define MT8167_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) | 7) + +#define MT8167_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8167_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) | 1) +#define MT8167_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) | 2) +#define MT8167_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) +#define MT8167_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) +#define MT8167_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) | 5) +#define MT8167_PIN_9_EINT9__FUNC_DPI_D8 (MTK_PIN_NO(9) | 6) +#define MT8167_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) | 7) + +#define MT8167_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8167_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) | 1) +#define MT8167_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) | 2) +#define MT8167_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 3) +#define MT8167_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) +#define MT8167_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) | 5) +#define MT8167_PIN_10_EINT10__FUNC_DPI_D9 (MTK_PIN_NO(10) | 6) +#define MT8167_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) | 7) + +#define MT8167_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8167_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) | 1) +#define MT8167_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) | 2) +#define MT8167_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) | 3) +#define MT8167_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) | 4) +#define MT8167_PIN_11_EINT11__FUNC_DPI_D10 (MTK_PIN_NO(11) | 5) +#define MT8167_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 6) +#define MT8167_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) | 7) + +#define MT8167_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8167_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) | 1) +#define MT8167_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) | 2) +#define MT8167_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) | 3) +#define MT8167_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) | 4) +#define MT8167_PIN_12_EINT12__FUNC_DPI_D11 (MTK_PIN_NO(12) | 5) +#define MT8167_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 6) +#define MT8167_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) | 7) + +#define MT8167_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8167_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) | 3) +#define MT8167_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) | 4) +#define MT8167_PIN_13_EINT13__FUNC_DPI_D0 (MTK_PIN_NO(13) | 5) +#define MT8167_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 6) +#define MT8167_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) | 7) + +#define MT8167_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8167_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) | 2) +#define MT8167_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) | 3) +#define MT8167_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 4) +#define MT8167_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) | 5) +#define MT8167_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) | 6) +#define MT8167_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) | 7) + +#define MT8167_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8167_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) | 2) +#define MT8167_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) | 3) +#define MT8167_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 4) +#define MT8167_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) | 5) +#define MT8167_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) | 6) +#define MT8167_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) | 7) + +#define MT8167_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8167_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) | 2) +#define MT8167_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) | 3) +#define MT8167_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 4) +#define MT8167_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) | 5) +#define MT8167_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) | 6) +#define MT8167_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) | 7) + +#define MT8167_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8167_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) | 2) +#define MT8167_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) | 3) +#define MT8167_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) | 4) +#define MT8167_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 5) +#define MT8167_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) | 6) +#define MT8167_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) | 7) + +#define MT8167_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8167_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 2) +#define MT8167_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) | 3) +#define MT8167_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) | 4) +#define MT8167_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) | 5) +#define MT8167_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) | 6) +#define MT8167_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) | 7) + +#define MT8167_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8167_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) | 1) +#define MT8167_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) | 2) +#define MT8167_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) | 3) +#define MT8167_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) | 4) +#define MT8167_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) | 5) +#define MT8167_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) | 6) +#define MT8167_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) | 7) + +#define MT8167_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8167_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) | 1) +#define MT8167_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 3) +#define MT8167_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) | 4) +#define MT8167_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) | 5) +#define MT8167_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) | 6) +#define MT8167_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) | 7) + +#define MT8167_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8167_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) | 1) +#define MT8167_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 2) +#define MT8167_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) | 3) +#define MT8167_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) | 7) + +#define MT8167_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8167_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) | 2) +#define MT8167_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) | 3) +#define MT8167_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) | 4) +#define MT8167_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) | 5) +#define MT8167_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) | 6) +#define MT8167_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) | 7) + +#define MT8167_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8167_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) | 2) +#define MT8167_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) | 3) +#define MT8167_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) | 4) +#define MT8167_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) | 5) +#define MT8167_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) | 6) +#define MT8167_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) | 7) + +#define MT8167_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8167_PIN_24_EINT24__FUNC_DPI_D20 (MTK_PIN_NO(24) | 1) +#define MT8167_PIN_24_EINT24__FUNC_DPI_DE (MTK_PIN_NO(24) | 2) +#define MT8167_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) | 3) +#define MT8167_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) | 4) +#define MT8167_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) | 5) +#define MT8167_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) | 6) +#define MT8167_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) | 7) + +#define MT8167_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8167_PIN_25_EINT25__FUNC_DPI_D19 (MTK_PIN_NO(25) | 1) +#define MT8167_PIN_25_EINT25__FUNC_DPI_VSYNC (MTK_PIN_NO(25) | 2) +#define MT8167_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 3) +#define MT8167_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) | 4) +#define MT8167_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) | 5) +#define MT8167_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) | 6) +#define MT8167_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) | 7) + +#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) | 1) +#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) | 2) + +#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) | 1) +#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) | 2) + +#define MT8167_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) | 1) +#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) | 4) +#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) | 5) +#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) | 6) + +#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) | 1) + +#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) | 1) + +#define MT8167_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8167_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) | 1) + +#define MT8167_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8167_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) | 1) + +#define MT8167_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8167_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) | 1) + +#define MT8167_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8167_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) | 1) +#define MT8167_PIN_34_URXD2__FUNC_DPI_D5 (MTK_PIN_NO(34) | 2) +#define MT8167_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) | 3) +#define MT8167_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) | 4) +#define MT8167_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) | 6) +#define MT8167_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) | 7) + +#define MT8167_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8167_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) | 1) +#define MT8167_PIN_35_UTXD2__FUNC_DPI_HSYNC (MTK_PIN_NO(35) | 2) +#define MT8167_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) | 3) +#define MT8167_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) | 4) +#define MT8167_PIN_35_UTXD2__FUNC_DPI_D18 (MTK_PIN_NO(35) | 5) +#define MT8167_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) | 6) +#define MT8167_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) | 7) + +#define MT8167_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8167_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) | 1) +#define MT8167_PIN_36_MRG_CLK__FUNC_DPI_D4 (MTK_PIN_NO(36) | 2) +#define MT8167_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) | 3) +#define MT8167_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) | 4) +#define MT8167_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) | 5) +#define MT8167_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) | 6) +#define MT8167_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) | 7) + +#define MT8167_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8167_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) | 1) +#define MT8167_PIN_37_MRG_SYNC__FUNC_DPI_D3 (MTK_PIN_NO(37) | 2) +#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) | 3) +#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) | 4) +#define MT8167_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) | 5) +#define MT8167_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) | 6) +#define MT8167_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) | 7) + +#define MT8167_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8167_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) | 1) +#define MT8167_PIN_38_MRG_DI__FUNC_DPI_D1 (MTK_PIN_NO(38) | 2) +#define MT8167_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) | 3) +#define MT8167_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) | 4) +#define MT8167_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) | 5) +#define MT8167_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) | 6) +#define MT8167_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) | 7) + +#define MT8167_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8167_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) | 1) +#define MT8167_PIN_39_MRG_DO__FUNC_DPI_D2 (MTK_PIN_NO(39) | 2) +#define MT8167_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) | 3) +#define MT8167_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) | 4) +#define MT8167_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) | 5) +#define MT8167_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) | 6) +#define MT8167_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) | 7) + +#define MT8167_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8167_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) | 1) +#define MT8167_PIN_40_KPROW0__FUNC_IMG_TEST_CK (MTK_PIN_NO(40) | 4) +#define MT8167_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) | 7) + +#define MT8167_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8167_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) | 1) +#define MT8167_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) | 2) +#define MT8167_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 3) +#define MT8167_PIN_41_KPROW1__FUNC_MFG_TEST_CK (MTK_PIN_NO(41) | 4) +#define MT8167_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) | 7) + +#define MT8167_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8167_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) | 1) +#define MT8167_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) | 7) + +#define MT8167_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8167_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) | 1) +#define MT8167_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) | 2) +#define MT8167_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) | 3) +#define MT8167_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) | 4) +#define MT8167_PIN_43_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(43) | 5) +#define MT8167_PIN_43_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(43) | 6) +#define MT8167_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) | 7) + +#define MT8167_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8167_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) | 1) +#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) | 2) +#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) | 3) +#define MT8167_PIN_44_JTMS__FUNC_GPUDFD_TMS_XI (MTK_PIN_NO(44) | 4) +#define MT8167_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) | 5) +#define MT8167_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) | 6) + +#define MT8167_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8167_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) | 1) +#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) | 2) +#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) | 3) +#define MT8167_PIN_45_JTCK__FUNC_GPUDFD_TCK_XI (MTK_PIN_NO(45) | 4) +#define MT8167_PIN_45_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(45) | 5) +#define MT8167_PIN_45_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(45) | 6) + +#define MT8167_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8167_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) | 1) +#define MT8167_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) | 2) +#define MT8167_PIN_46_JTDI__FUNC_GPUDFD_TDI_XI (MTK_PIN_NO(46) | 4) +#define MT8167_PIN_46_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(46) | 5) +#define MT8167_PIN_46_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(46) | 6) + +#define MT8167_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8167_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) | 1) +#define MT8167_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) | 2) +#define MT8167_PIN_47_JTDO__FUNC_GPUDFD_TDO (MTK_PIN_NO(47) | 4) +#define MT8167_PIN_47_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(47) | 5) +#define MT8167_PIN_47_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(47) | 6) + +#define MT8167_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8167_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) | 1) +#define MT8167_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) | 3) +#define MT8167_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) | 4) +#define MT8167_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) | 7) + +#define MT8167_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8167_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) | 1) +#define MT8167_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) | 3) +#define MT8167_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) | 4) +#define MT8167_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) | 7) + +#define MT8167_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) | 1) +#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) | 2) +#define MT8167_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) | 3) +#define MT8167_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 4) +#define MT8167_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) | 7) + +#define MT8167_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) | 1) +#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) | 2) +#define MT8167_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) | 3) +#define MT8167_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) | 4) +#define MT8167_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) | 7) + +#define MT8167_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8167_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) | 1) + +#define MT8167_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8167_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) | 1) + +#define MT8167_PIN_54_DISP_PWM__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8167_PIN_54_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(54) | 1) +#define MT8167_PIN_54_DISP_PWM__FUNC_PWM_B (MTK_PIN_NO(54) | 2) +#define MT8167_PIN_54_DISP_PWM__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) | 7) + +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) | 1) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) | 2) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) | 3) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) | 4) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) | 5) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) | 6) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) | 7) + +#define MT8167_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) | 1) +#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) | 3) +#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) | 4) +#define MT8167_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) | 5) +#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) | 6) +#define MT8167_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) | 7) + +#define MT8167_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8167_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) | 1) +#define MT8167_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) | 2) +#define MT8167_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 3) +#define MT8167_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) | 4) +#define MT8167_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) | 5) +#define MT8167_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) | 6) +#define MT8167_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) | 7) + +#define MT8167_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8167_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) | 1) + +#define MT8167_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8167_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) | 1) + +#define MT8167_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8167_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) | 1) +#define MT8167_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) | 2) + +#define MT8167_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8167_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) | 1) +#define MT8167_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) | 2) + +#define MT8167_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8167_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) | 1) +#define MT8167_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) | 2) + +#define MT8167_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8167_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) | 1) +#define MT8167_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) | 2) + +#define MT8167_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8167_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) | 1) +#define MT8167_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) | 2) +#define MT8167_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) | 7) + +#define MT8167_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8167_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) | 1) +#define MT8167_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) | 2) +#define MT8167_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) | 7) + +#define MT8167_PIN_66_LCM_RST__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT8167_PIN_66_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(66) | 1) +#define MT8167_PIN_66_LCM_RST__FUNC_I2S0_MCK (MTK_PIN_NO(66) | 3) +#define MT8167_PIN_66_LCM_RST__FUNC_DBG_MON_B_3 (MTK_PIN_NO(66) | 7) + +#define MT8167_PIN_67_DSI_TE__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT8167_PIN_67_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(67) | 1) +#define MT8167_PIN_67_DSI_TE__FUNC_I2S_8CH_MCK (MTK_PIN_NO(67) | 3) +#define MT8167_PIN_67_DSI_TE__FUNC_DBG_MON_B_14 (MTK_PIN_NO(67) | 7) + +#define MT8167_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) | 1) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) | 2) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) | 3) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) | 5) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) | 6) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) | 7) + +#define MT8167_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_DPI_D21 (MTK_PIN_NO(69) | 4) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7) + +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) | 1) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) | 2) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DPI_D22 (MTK_PIN_NO(70) | 4) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) | 5) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) | 6) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) | 7) + +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) | 1) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) | 2) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) | 3) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 4) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) | 5) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) | 6) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) | 7) + +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) | 1) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) | 2) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) | 3) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(72) | 4) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) | 5) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) | 6) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7) + +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) | 1) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) | 2) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) | 3) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) | 4) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) | 5) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) | 6) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7) + +#define MT8167_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) | 0) +#define MT8167_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) | 1) + +#define MT8167_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) | 0) +#define MT8167_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) | 1) + +#define MT8167_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) | 0) +#define MT8167_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) | 1) + +#define MT8167_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) | 0) +#define MT8167_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) | 1) + +#define MT8167_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) | 0) +#define MT8167_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) | 1) + +#define MT8167_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) | 0) +#define MT8167_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) | 1) + +#define MT8167_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) | 0) +#define MT8167_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) | 1) + +#define MT8167_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) | 0) +#define MT8167_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) | 1) + +#define MT8167_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) | 0) +#define MT8167_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) | 1) + +#define MT8167_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) | 0) +#define MT8167_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) | 1) + +#define MT8167_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) | 0) +#define MT8167_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) | 1) + +#define MT8167_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) | 0) +#define MT8167_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) | 1) + +#define MT8167_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) | 0) +#define MT8167_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) | 1) + +#define MT8167_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) | 0) +#define MT8167_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) | 1) + +#define MT8167_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) | 0) +#define MT8167_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) | 1) + +#define MT8167_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) | 0) +#define MT8167_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) | 1) + +#define MT8167_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) | 0) +#define MT8167_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) | 1) +#define MT8167_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) | 2) + +#define MT8167_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) | 0) +#define MT8167_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) | 1) +#define MT8167_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) | 2) + +#define MT8167_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) +#define MT8167_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) | 1) +#define MT8167_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) | 2) + +#define MT8167_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) | 0) +#define MT8167_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) | 1) +#define MT8167_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) | 2) + +#define MT8167_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) | 0) +#define MT8167_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) | 1) +#define MT8167_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) | 2) + +#define MT8167_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) | 0) +#define MT8167_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) | 1) +#define MT8167_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) | 2) + +#define MT8167_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) | 0) +#define MT8167_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) | 1) +#define MT8167_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) | 2) +#define MT8167_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) | 3) + +#define MT8167_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) | 0) +#define MT8167_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) | 1) +#define MT8167_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) | 2) +#define MT8167_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) | 3) + +#define MT8167_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) | 0) +#define MT8167_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) | 1) +#define MT8167_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) | 2) + +#define MT8167_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) | 0) +#define MT8167_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) | 1) +#define MT8167_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) | 2) + +#define MT8167_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT8167_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) | 1) +#define MT8167_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) | 2) +#define MT8167_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) | 3) +#define MT8167_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) | 5) +#define MT8167_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) | 7) + +#define MT8167_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT8167_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) | 1) +#define MT8167_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) | 2) +#define MT8167_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) | 3) +#define MT8167_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) | 4) +#define MT8167_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) | 5) +#define MT8167_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) | 7) + +#define MT8167_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT8167_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) | 1) +#define MT8167_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) | 3) +#define MT8167_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) | 5) +#define MT8167_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) | 7) + +#define MT8167_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT8167_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) | 1) +#define MT8167_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) | 2) +#define MT8167_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) | 3) +#define MT8167_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) | 5) +#define MT8167_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) | 7) + +#define MT8167_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT8167_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) | 1) +#define MT8167_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) | 4) +#define MT8167_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) | 7) + +#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) | 1) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_UDI_NTRST_XI (MTK_PIN_NO(105) | 2) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_DFD_NTRST_XI (MTK_PIN_NO(105) | 3) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) | 4) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPUEJ_NTRST_XI (MTK_PIN_NO(105) | 5) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) | 7) + +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) | 1) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_UDI_TMS_XI (MTK_PIN_NO(106) | 2) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DFD_TMS_XI (MTK_PIN_NO(106) | 3) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) | 4) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPUEJ_TMS_XI (MTK_PIN_NO(106) | 5) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) | 7) + +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) | 1) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_UDI_TCK_XI (MTK_PIN_NO(107) | 2) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DFD_TCK_XI (MTK_PIN_NO(107) | 3) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) | 4) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPUEJ_TCK_XI (MTK_PIN_NO(107) | 5) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) | 7) + +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) | 1) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_UDI_TDI_XI (MTK_PIN_NO(108) | 2) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DFD_TDI_XI (MTK_PIN_NO(108) | 3) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) | 4) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPUEJ_TDI_XI (MTK_PIN_NO(108) | 5) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) | 7) + +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) | 1) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_UDI_TDO (MTK_PIN_NO(109) | 2) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DFD_TDO (MTK_PIN_NO(109) | 3) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) | 4) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPUEJ_TDO (MTK_PIN_NO(109) | 5) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) | 7) + +#define MT8167_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT8167_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) | 1) +#define MT8167_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) | 4) + +#define MT8167_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT8167_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) | 1) +#define MT8167_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) | 4) + +#define MT8167_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT8167_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) | 1) +#define MT8167_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) | 4) + +#define MT8167_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT8167_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) | 1) +#define MT8167_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) | 4) + +#define MT8167_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT8167_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) | 1) +#define MT8167_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) | 4) + +#define MT8167_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT8167_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) | 1) +#define MT8167_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) | 4) + +#define MT8167_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT8167_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) | 1) +#define MT8167_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) | 4) + +#define MT8167_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8167_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1) +#define MT8167_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) | 4) + +#define MT8167_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8167_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) | 1) +#define MT8167_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) | 4) + +#define MT8167_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8167_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) | 1) +#define MT8167_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) | 4) + +#define MT8167_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8167_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) | 1) +#define MT8167_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) | 4) +#define MT8167_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) | 5) + +#define MT8167_PIN_121_CEC__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT8167_PIN_121_CEC__FUNC_CEC (MTK_PIN_NO(121) | 1) + +#define MT8167_PIN_122_HTPLG__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT8167_PIN_122_HTPLG__FUNC_HTPLG (MTK_PIN_NO(122) | 1) + +#define MT8167_PIN_123_HDMISCK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT8167_PIN_123_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(123) | 1) + +#define MT8167_PIN_124_HDMISD__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT8167_PIN_124_HDMISD__FUNC_HDMISD (MTK_PIN_NO(124) | 1) + +#endif /* __DTS_MT8167_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi new file mode 100644 index 000000000000..1c5639ead622 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2020 BayLibre, SAS. + * Author: Fabien Parent + */ + +#include +#include + +#include "mt8167-pinfunc.h" + +#include "mt8516.dtsi" + +/ { + compatible = "mediatek,mt8167"; + + soc { + topckgen: topckgen@10000000 { + compatible = "mediatek,mt8167-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt8167-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: apmixedsys@10018000 { + compatible = "mediatek,mt8167-apmixedsys", "syscon"; + reg = <0 0x10018000 0 0x710>; + #clock-cells = <1>; + }; + + imgsys: syscon@15000000 { + compatible = "mediatek,mt8167-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8167-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8167-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; +}; -- cgit v1.2.3 From 7f1e3823ba03a60dd61731ed752f08790806e74d Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 27 Oct 2020 20:48:15 +0100 Subject: arm64: dts: mediatek: add MT8167 pumpkin board dts The pumpkin board is made by Gossamer Engineering and is using a MediaTek SoC. The board currently comes in two available version: MT8516 SoC and MT8167 SoC. The board provides the following IOs: eMMC, NAND, SD card, USB type-A, Ethernet, Wi-Fi, Bluetooth, Audio (jack out, 2 PDM port, 1 analog in), serial over USB, HDMI, DSI, CSI, and an expansion header. The board can be powered by battery and/or via a USB Type-C port and is using a PMIC MT6392. The eMMC and NAND are sharing pins and cannot be used together. This commit is adding the basic boot support for the Pumpkin MT8167 board. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201027194816.1227654-3-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 66eeba60acac..db9dcbf5f245 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts new file mode 100644 index 000000000000..774a2f3fb4b2 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 BayLibre, SAS. + * Author: Fabien Parent + */ + +/dts-v1/; + +#include "mt8167.dtsi" +#include "pumpkin-common.dtsi" + +/ { + model = "Pumpkin MT8167"; + compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; -- cgit v1.2.3 From 48489980e27e091c9e871a48157ceda2db855974 Mon Sep 17 00:00:00 2001 From: Seiya Wang Date: Fri, 30 Oct 2020 17:22:07 +0800 Subject: arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile Add basic chip support for Mediatek MT8192 Signed-off-by: Seiya Wang Link: https://lore.kernel.org/r/20201030092207.26488-2-seiya.wang@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 29 ++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 512 ++++++++++++++++++++++++++++ 3 files changed, 542 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8192.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index db9dcbf5f245..18f7b46c4095 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -14,4 +14,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts new file mode 100644 index 000000000000..0205837fa698 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Seiya Wang + */ +/dts-v1/; +#include "mt8192.dtsi" + +/ { + model = "MediaTek MT8192 evaluation board"; + compatible = "mediatek,mt8192-evb", "mediatek,mt8192"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi new file mode 100644 index 000000000000..e12e024de122 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -0,0 +1,512 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Seiya Wang + */ + +/dts-v1/; +#include +#include +#include + +/ { + compatible = "mediatek,mt8192"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clk26m: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <1701000000>; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <530>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <1701000000>; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <530>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <1701000000>; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <530>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <1701000000>; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <530>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2171000000>; + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2171000000>; + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <2171000000>; + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <2171000000>; + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l3_0: l3-cache { + compatible = "cache"; + }; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <13000000>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8192-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", + "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8192-timer", + "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>; + clock-names = "clk13m"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8192-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8192-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11018000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11019000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11019000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi6: spi@1101d000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1101d000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi7: spi@1101e000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1101e000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + i2c3: i2c3@11cb0000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11cb0000 0 0x1000>, + <0 0x10217300 0 0x80>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c7@11d00000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x10217600 0 0x180>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c8@11d01000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d01000 0 0x1000>, + <0 0x10217780 0 0x180>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c9@11d02000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d02000 0 0x1000>, + <0 0x10217900 0 0x180>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c1@11d20000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d20000 0 0x1000>, + <0 0x10217100 0 0x80>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c2@11d21000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d21000 0 0x1000>, + <0 0x10217180 0 0x180>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c4@11d22000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d22000 0 0x1000>, + <0 0x10217380 0 0x180>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c5@11e00000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11e00000 0 0x1000>, + <0 0x10217500 0 0x80>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c0@11f00000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11f00000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c6@11f01000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11f01000 0 0x1000>, + <0 0x10217580 0 0x80>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; -- cgit v1.2.3 From 8b6562644df9de4e01387635f4d8bf3852d7ad92 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 30 Oct 2020 12:36:09 +0100 Subject: arm64: dts: mediatek: Add mt8173 power domain controller Add power domain controller node for SoC mt8173. Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-4-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 164 ++++++++++++++++++++++--------- 1 file changed, 115 insertions(+), 49 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 5e046f9d48ce..7fa870e4386a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -450,16 +450,82 @@ }; }; - scpsys: power-controller@10006000 { - compatible = "mediatek,mt8173-scpsys"; - #power-domain-cells = <1>; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - clocks = <&clk26m>, - <&topckgen CLK_TOP_MM_SEL>, - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "mfg", "mm", "venc", "venc_lt"; - infracfg = <&infracfg>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8173-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8173_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_VENC { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_VENC_SEL>; + clock-names = "mm", "venc"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_MM { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + power-domain@MT8173_POWER_DOMAIN_VENC_LT { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "mm", "venclt"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_AUDIO { + reg = ; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_USB { + reg = ; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { + reg = ; + clocks = <&clk26m>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8173_POWER_DOMAIN_MFG_2D { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8173_POWER_DOMAIN_MFG { + reg = ; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + }; }; watchdog: watchdog@10007000 { @@ -792,7 +858,7 @@ compatible = "mediatek,mt8173-afe-pcm"; reg = <0 0x11220000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; + power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>; clocks = <&infracfg CLK_INFRA_AUDIO>, <&topckgen CLK_TOP_AUDIO_SEL>, <&topckgen CLK_TOP_AUD_INTBUS_SEL>, @@ -868,7 +934,7 @@ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>, <&u2port1 PHY_TYPE_USB2>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; + power-domains = <&spm MT8173_POWER_DOMAIN_USB>; clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; clock-names = "sys_ck", "ref_ck"; mediatek,syscon-wakeup = <&pericfg 0x400 1>; @@ -882,7 +948,7 @@ reg = <0 0x11270000 0 0x1000>; reg-names = "mac"; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; + power-domains = <&spm MT8173_POWER_DOMAIN_USB>; clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; clock-names = "sys_ck", "ref_ck"; status = "disabled"; @@ -925,7 +991,7 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; assigned-clock-rates = <400000000>; #clock-cells = <1>; @@ -940,7 +1006,7 @@ reg = <0 0x14001000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_RDMA0>, <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_RDMA0>; mediatek,larb = <&larb0>; mediatek,vpu = <&vpu>; @@ -951,7 +1017,7 @@ reg = <0 0x14002000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_RDMA1>, <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_RDMA1>; mediatek,larb = <&larb4>; }; @@ -960,28 +1026,28 @@ compatible = "mediatek,mt8173-mdp-rsz"; reg = <0 0x14003000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_RSZ0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; }; mdp_rsz1: rsz@14004000 { compatible = "mediatek,mt8173-mdp-rsz"; reg = <0 0x14004000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_RSZ1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; }; mdp_rsz2: rsz@14005000 { compatible = "mediatek,mt8173-mdp-rsz"; reg = <0 0x14005000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_RSZ2>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; }; mdp_wdma0: wdma@14006000 { compatible = "mediatek,mt8173-mdp-wdma"; reg = <0 0x14006000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_WDMA>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_WDMA>; mediatek,larb = <&larb0>; }; @@ -990,7 +1056,7 @@ compatible = "mediatek,mt8173-mdp-wrot"; reg = <0 0x14007000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_WROT0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_WROT0>; mediatek,larb = <&larb0>; }; @@ -999,7 +1065,7 @@ compatible = "mediatek,mt8173-mdp-wrot"; reg = <0 0x14008000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_WROT1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_WROT1>; mediatek,larb = <&larb4>; }; @@ -1008,7 +1074,7 @@ compatible = "mediatek,mt8173-disp-ovl"; reg = <0 0x1400c000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; mediatek,larb = <&larb0>; @@ -1019,7 +1085,7 @@ compatible = "mediatek,mt8173-disp-ovl"; reg = <0 0x1400d000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OVL1>; iommus = <&iommu M4U_PORT_DISP_OVL1>; mediatek,larb = <&larb4>; @@ -1030,7 +1096,7 @@ compatible = "mediatek,mt8173-disp-rdma"; reg = <0 0x1400e000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,larb = <&larb0>; @@ -1041,7 +1107,7 @@ compatible = "mediatek,mt8173-disp-rdma"; reg = <0 0x1400f000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,larb = <&larb4>; @@ -1052,7 +1118,7 @@ compatible = "mediatek,mt8173-disp-rdma"; reg = <0 0x14010000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_RDMA2>; iommus = <&iommu M4U_PORT_DISP_RDMA2>; mediatek,larb = <&larb4>; @@ -1063,7 +1129,7 @@ compatible = "mediatek,mt8173-disp-wdma"; reg = <0 0x14011000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_WDMA0>; iommus = <&iommu M4U_PORT_DISP_WDMA0>; mediatek,larb = <&larb0>; @@ -1074,7 +1140,7 @@ compatible = "mediatek,mt8173-disp-wdma"; reg = <0 0x14012000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_WDMA1>; iommus = <&iommu M4U_PORT_DISP_WDMA1>; mediatek,larb = <&larb4>; @@ -1085,7 +1151,7 @@ compatible = "mediatek,mt8173-disp-color"; reg = <0 0x14013000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; }; @@ -1094,7 +1160,7 @@ compatible = "mediatek,mt8173-disp-color"; reg = <0 0x14014000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_COLOR1>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; }; @@ -1103,7 +1169,7 @@ compatible = "mediatek,mt8173-disp-aal"; reg = <0 0x14015000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_AAL>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; }; @@ -1112,7 +1178,7 @@ compatible = "mediatek,mt8173-disp-gamma"; reg = <0 0x14016000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_GAMMA>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; }; @@ -1120,21 +1186,21 @@ merge@14017000 { compatible = "mediatek,mt8173-disp-merge"; reg = <0 0x14017000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_MERGE>; }; split0: split@14018000 { compatible = "mediatek,mt8173-disp-split"; reg = <0 0x14018000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_SPLIT0>; }; split1: split@14019000 { compatible = "mediatek,mt8173-disp-split"; reg = <0 0x14019000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_SPLIT1>; }; @@ -1142,7 +1208,7 @@ compatible = "mediatek,mt8173-disp-ufoe"; reg = <0 0x1401a000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_UFOE>; }; @@ -1150,7 +1216,7 @@ compatible = "mediatek,mt8173-dsi"; reg = <0 0x1401b000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DSI0_ENGINE>, <&mmsys CLK_MM_DSI0_DIGITAL>, <&mipi_tx0>; @@ -1164,7 +1230,7 @@ compatible = "mediatek,mt8173-dsi"; reg = <0 0x1401c000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DSI1_ENGINE>, <&mmsys CLK_MM_DSI1_DIGITAL>, <&mipi_tx1>; @@ -1178,7 +1244,7 @@ compatible = "mediatek,mt8173-dpi"; reg = <0 0x1401d000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DPI_PIXEL>, <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>; @@ -1218,7 +1284,7 @@ compatible = "mediatek,mt8173-disp-mutex"; reg = <0 0x14020000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_MUTEX_32K>; mediatek,gce-events = , ; @@ -1228,7 +1294,7 @@ compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x14021000 0 0x1000>; mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_SMI_LARB0>, <&mmsys CLK_MM_SMI_LARB0>; clock-names = "apb", "smi"; @@ -1237,7 +1303,7 @@ smi_common: smi@14022000 { compatible = "mediatek,mt8173-smi-common"; reg = <0 0x14022000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>; clock-names = "apb", "smi"; @@ -1285,7 +1351,7 @@ compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x14027000 0 0x1000>; mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_SMI_LARB4>, <&mmsys CLK_MM_SMI_LARB4>; clock-names = "apb", "smi"; @@ -1301,7 +1367,7 @@ compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x15001000 0 0x1000>; mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; + power-domains = <&spm MT8173_POWER_DOMAIN_ISP>; clocks = <&imgsys CLK_IMG_LARB2_SMI>, <&imgsys CLK_IMG_LARB2_SMI>; clock-names = "apb", "smi"; @@ -1338,7 +1404,7 @@ <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; mediatek,vpu = <&vpu>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; + power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, <&topckgen CLK_TOP_UNIVPLL_D2>, <&topckgen CLK_TOP_CCI400_SEL>, @@ -1370,7 +1436,7 @@ compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x16010000 0 0x1000>; mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; + power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>; clock-names = "apb", "smi"; @@ -1386,7 +1452,7 @@ compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x18001000 0 0x1000>; mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; clocks = <&vencsys CLK_VENC_CKE1>, <&vencsys CLK_VENC_CKE0>; clock-names = "apb", "smi"; @@ -1443,7 +1509,7 @@ <&vencsys CLK_VENC_CKE3>; clock-names = "jpgdec-smi", "jpgdec"; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; mediatek,larb = <&larb3>; iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, <&iommu M4U_PORT_JPGDEC_BSDMA>; @@ -1459,7 +1525,7 @@ compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x19001000 0 0x1000>; mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; clocks = <&vencltsys CLK_VENCLT_CKE1>, <&vencltsys CLK_VENCLT_CKE0>; clock-names = "apb", "smi"; -- cgit v1.2.3 From ddebdbad8149af123574b87596927437339318f7 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 30 Oct 2020 12:36:18 +0100 Subject: arm64: dts: mediatek: Add smi_common node for MT8183 The SMI (Smart Multimedia Interface) Common is a bridge between the m4u (Multimedia Memory Management Unit) and the Multimedia HW. This block is needed to support different multimedia features, like display, video decode, and camera. Also is needed to control the power domains of such HW blocks. Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-13-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 08a914d3a643..360a638d6b87 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -765,6 +765,16 @@ #clock-cells = <1>; }; + smi_common: smi@14019000 { + compatible = "mediatek,mt8183-smi-common", "syscon"; + reg = <0 0x14019000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_GALS_COMM0>, + <&mmsys CLK_MM_GALS_COMM1>; + clock-names = "apb", "smi", "gals0", "gals1"; + }; + imgsys: syscon@15020000 { compatible = "mediatek,mt8183-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>; -- cgit v1.2.3 From 37fb78b9aeb75d79f0bdfbbbdcb85ebb68ae1476 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 30 Oct 2020 12:36:19 +0100 Subject: arm64: dts: mediatek: Add mt8183 power domains controller Add power domains controller node for SoC mt8183 Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-14-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 162 +++++++++++++++++++++++++++++++ 1 file changed, 162 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 360a638d6b87..1ef39c5cc9fa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include "mt8183-pinfunc.h" @@ -316,6 +317,167 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8183-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + power-domain@MT8183_POWER_DOMAIN_AUDIO { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; + clock-names = "audio", "audio1", "audio2"; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_CONN { + reg = ; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_MFG>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8183_POWER_DOMAIN_MFG { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_MFG_2D { + reg = ; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8183_POWER_DOMAIN_DISP { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_MM>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB1>, + <&mmsys CLK_MM_GALS_COMM0>, + <&mmsys CLK_MM_GALS_COMM1>, + <&mmsys CLK_MM_GALS_CCU2MM>, + <&mmsys CLK_MM_GALS_IPU12MM>, + <&mmsys CLK_MM_GALS_IMG2MM>, + <&mmsys CLK_MM_GALS_CAM2MM>, + <&mmsys CLK_MM_GALS_IPU2MM>; + clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", + "mm-4", "mm-5", "mm-6", "mm-7", + "mm-8", "mm-9"; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8183_POWER_DOMAIN_CAM { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_CAM>, + <&camsys CLK_CAM_LARB6>, + <&camsys CLK_CAM_LARB3>, + <&camsys CLK_CAM_SENINF>, + <&camsys CLK_CAM_CAMSV0>, + <&camsys CLK_CAM_CAMSV1>, + <&camsys CLK_CAM_CAMSV2>, + <&camsys CLK_CAM_CCU>; + clock-names = "cam", "cam-0", "cam-1", + "cam-2", "cam-3", "cam-4", + "cam-5", "cam-6"; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_IMG>, + <&imgsys CLK_IMG_LARB5>, + <&imgsys CLK_IMG_LARB2>; + clock-names = "isp", "isp-0", "isp-1"; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_VDEC { + reg = ; + mediatek,smi = <&smi_common>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_VENC { + reg = ; + mediatek,smi = <&smi_common>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_VPU_TOP { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, + <&topckgen CLK_TOP_MUX_DSP>, + <&ipu_conn CLK_IPU_CONN_IPU>, + <&ipu_conn CLK_IPU_CONN_AHB>, + <&ipu_conn CLK_IPU_CONN_AXI>, + <&ipu_conn CLK_IPU_CONN_ISP>, + <&ipu_conn CLK_IPU_CONN_CAM_ADL>, + <&ipu_conn CLK_IPU_CONN_IMG_ADL>; + clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", + "vpu-2", "vpu-3", "vpu-4", "vpu-5"; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_DSP1>; + clock-names = "vpu2"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_DSP2>; + clock-names = "vpu3"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8183-wdt"; reg = <0 0x10007000 0 0x100>; -- cgit v1.2.3 From f15722c0fef05a62d64ca1b1fc682f6f7396c108 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Tue, 24 Nov 2020 12:12:54 +0800 Subject: arm64: dts: mt8183: Add pwm and backlight node Add pwm to mt8183 and backlight to mt8183-kukui. Signed-off-by: Hsin-Yi Wang Tested-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201124041253.4181273-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 28 ++++++++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 10 +++++++++ 2 files changed, 38 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 85f7c33ba446..bf2ad1294dd3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -19,6 +19,17 @@ stdout-path = "serial0:115200n8"; }; + backlight_lcd0: backlight_lcd0 { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 500000>; + power-supply = <&bl_pp5000>; + enable-gpios = <&pio 176 0>; + brightness-levels = <0 1023>; + num-interpolated-steps = <1023>; + default-brightness-level = <576>; + status = "okay"; + }; + memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0 0x80000000>; @@ -536,6 +547,17 @@ }; }; + pwm0_pin_default: pwm0_pin_default { + pins1 { + pinmux = ; + output-high; + bias-pull-up; + }; + pins2 { + pinmux = ; + }; + }; + scp_pins: scp { pins_scp_uart { pinmux = , @@ -670,6 +692,12 @@ }; }; +&pwm0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin_default>; +}; + &scp { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1ef39c5cc9fa..2a8832537027 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -641,6 +641,16 @@ status = "disabled"; }; + pwm0: pwm@1100e000 { + compatible = "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, + <&infracfg CLK_INFRA_DISP_PWM>; + clock-names = "main", "mm"; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8183-i2c"; reg = <0 0x1100f000 0 0x1000>, -- cgit v1.2.3 From 88ec840270e62e18dac4bb678fb0823077378b8d Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Fri, 27 Nov 2020 11:49:28 +0100 Subject: arm64: dts: mt8183: Add dsi node Add dsi and mipitx nodes to the MT8183. Signed-off-by: Jitao Shi Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201127104930.1981497-2-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 2a8832537027..548026d0e977 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -892,10 +892,27 @@ status = "disabled"; }; + mipi_tx0: mipi-dphy@11e50000 { + compatible = "mediatek,mt8183-mipi-tx"; + reg = <0 0x11e50000 0 0x1000>; + clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; + clock-names = "ref_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "mipi_tx0_pll"; + nvmem-cells = <&mipi_tx_calibration>; + nvmem-cell-names = "calibration-data"; + }; + efuse: efuse@11f10000 { compatible = "mediatek,mt8183-efuse", "mediatek,efuse"; reg = <0 0x11f10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + mipi_tx_calibration: calib@190 { + reg = <0x190 0xc>; + }; }; u3phy: usb-phy@11f40000 { @@ -937,6 +954,20 @@ #clock-cells = <1>; }; + dsi0: dsi@14014000 { + compatible = "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + mediatek,syscon-dsi = <&mmsys 0x140>; + clocks = <&mmsys CLK_MM_DSI0_MM>, + <&mmsys CLK_MM_DSI0_IF>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + }; + smi_common: smi@14019000 { compatible = "mediatek,mt8183-smi-common", "syscon"; reg = <0 0x14019000 0 0x1000>; -- cgit v1.2.3 From c6080916310b6d47bb7d75a5647a346ae7c4b56f Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 27 Nov 2020 11:49:29 +0100 Subject: arm64: dts: mt8183: Add iommu and larb nodes Add iommu and larb nodes to the MT8183. Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201127104930.1981497-3-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79 ++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 548026d0e977..dfe80cb15c46 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -521,6 +522,15 @@ clock-names = "clk13m"; }; + iommu: iommu@10205000 { + compatible = "mediatek,mt8183-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 + &larb4 &larb5 &larb6>; + #iommu-cells = <1>; + }; + gce: mailbox@10238000 { compatible = "mediatek,mt8183-gce"; reg = <0 0x10238000 0 0x4000>; @@ -968,6 +978,16 @@ phy-names = "dphy"; }; + larb0: larb@14017000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x14017000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clock-names = "apb", "smi"; + }; + smi_common: smi@14019000 { compatible = "mediatek,mt8183-smi-common", "syscon"; reg = <0 0x14019000 0 0x1000>; @@ -984,18 +1004,57 @@ #clock-cells = <1>; }; + larb5: larb@15021000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x15021000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, + <&mmsys CLK_MM_GALS_IMG2MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; + }; + + larb2: larb@1502f000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x1502f000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, + <&mmsys CLK_MM_GALS_IPU2MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; + }; + vdecsys: syscon@16000000 { compatible = "mediatek,mt8183-vdecsys", "syscon"; reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; + larb1: larb@16010000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; + }; + vencsys: syscon@17000000 { compatible = "mediatek,mt8183-vencsys", "syscon"; reg = <0 0x17000000 0 0x1000>; #clock-cells = <1>; }; + larb4: larb@17010000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC_LARB>, + <&vencsys CLK_VENC_LARB>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; + }; + ipu_conn: syscon@19000000 { compatible = "mediatek,mt8183-ipu_conn", "syscon"; reg = <0 0x19000000 0 0x1000>; @@ -1025,5 +1084,25 @@ reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + + larb6: larb@1a001000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x1a001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, + <&mmsys CLK_MM_GALS_CAM2MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; + }; + + larb3: larb@1a002000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x1a002000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, + <&mmsys CLK_MM_GALS_IPU12MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; + }; }; }; -- cgit v1.2.3 From 91f9c963ce79fcc34577fc008d54f633c3e11d42 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 27 Nov 2020 11:49:30 +0100 Subject: arm64: dts: mt8183: Add display nodes for MT8183 Add display subsystem device nodes to allow video output. Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201127104930.1981497-4-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 114 +++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index dfe80cb15c46..5b782a4769e7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -33,6 +34,11 @@ i2c9 = &i2c9; i2c10 = &i2c10; i2c11 = &i2c11; + ovl0 = &ovl0; + ovl-2l0 = &ovl_2l0; + ovl-2l1 = &ovl_2l1; + rdma0 = &rdma0; + rdma1 = &rdma1; }; cpus { @@ -964,6 +970,107 @@ #clock-cells = <1>; }; + ovl0: ovl@14008000 { + compatible = "mediatek,mt8183-disp-ovl"; + reg = <0 0x14008000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + }; + + ovl_2l0: ovl@14009000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; + mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + }; + + ovl_2l1: ovl@1400a000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; + iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; + mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + }; + + rdma0: rdma@1400b000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,larb = <&larb0>; + mediatek,rdma_fifo_size = <5120>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + }; + + rdma1: rdma@1400c000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb0>; + mediatek,rdma_fifo_size = <2048>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + }; + + color0: color@1400e000 { + compatible = "mediatek,mt8183-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + }; + + ccorr0: ccorr@1400f000 { + compatible = "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + }; + + aal0: aal@14010000 { + compatible = "mediatek,mt8183-disp-aal", + "mediatek,mt8173-disp-aal"; + reg = <0 0x14010000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + }; + + gamma0: gamma@14011000 { + compatible = "mediatek,mt8183-disp-gamma", + "mediatek,mt8173-disp-gamma"; + reg = <0 0x14011000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + }; + + dither0: dither@14012000 { + compatible = "mediatek,mt8183-disp-dither"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + }; + dsi0: dsi@14014000 { compatible = "mediatek,mt8183-dsi"; reg = <0 0x14014000 0 0x1000>; @@ -978,6 +1085,13 @@ phy-names = "dphy"; }; + mutex: mutex@14016000 { + compatible = "mediatek,mt8183-disp-mutex"; + reg = <0 0x14016000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + }; + larb0: larb@14017000 { compatible = "mediatek,mt8183-smi-larb"; reg = <0 0x14017000 0 0x1000>; -- cgit v1.2.3 From b6633d778675a58fba1d7f795169da212a76231d Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 20 Nov 2020 09:35:32 +0200 Subject: arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM The J7200 SOM have additional io expander which is used to control several SOM level muxes to make sure that the correct signals are routed to the correct pin on the SOM <-> CPB connectors. Signed-off-by: Peter Ujfalusi Signed-off-by: Nishanth Menon Reviewed-by: Vignesh Raghavendra Reviewed-by: Grygorii Strashko Link: https://lore.kernel.org/r/20201120073533.24486-2-peter.ujfalusi@ti.com --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 11 --------- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 26 ++++++++++++++++++++++ 2 files changed, 26 insertions(+), 11 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 96fa26365248..1a8dd23eda33 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -43,13 +43,6 @@ }; &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ - >; - }; - main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ @@ -146,10 +139,6 @@ }; &main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - exp1: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index fbd17d38f6b6..7b5e9aa0324e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -48,6 +48,15 @@ }; }; +&main_pmx0 { + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ + J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ + >; + }; +}; + &hbmc { /* OSPI and HBMC are muxed inside FSS, Bootloader will enable * appropriate node based on board detection @@ -131,3 +140,20 @@ &mailbox0_cluster11 { status = "disabled"; }; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + exp_som: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", + "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", + "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL", + "GPIO_LIN_EN", "CAN_STB"; + }; +}; -- cgit v1.2.3 From 2eefbf5f862ed98a043917fa54c7a79a56ec08f6 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 20 Nov 2020 09:35:33 +0200 Subject: arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io expander on main_i2c1 J7200 main_i2c1 is connected to the i2c bus on the CPB marked as main_i2c3 The i2c1 devices on the CPB are _not_ connected to the SoC, they are not usable with the J7200 SOM. Correct the expander name from exp4 to exp3 and at the same time add the line names as well. Signed-off-by: Peter Ujfalusi Signed-off-by: Nishanth Menon Reviewed-by: Vignesh Raghavendra Reviewed-by: Grygorii Strashko Link: https://lore.kernel.org/r/20201120073533.24486-3-peter.ujfalusi@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 1a8dd23eda33..331b388e1d1b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -154,16 +154,26 @@ }; }; +/* + * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be + * swapped on the CPB. + * + * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. + * The i2c1 of the CPB (as it is labeled) is not connected to j7200. + */ &main_i2c1 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; - exp4: gpio@20 { + exp3: gpio@20 { compatible = "ti,tca6408"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; + gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", + "UB926_LOCK", "UB926_PWR_SW_CNTRL", + "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; }; }; -- cgit v1.2.3 From 3f0716710ae93e467cd313855c1aa96dd40321d2 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 16 Oct 2020 22:40:17 +0200 Subject: dts64: mt7622: enable all pwm for bananapi r64 mt7622 only supports 6 pwm-channels so drop pwm7 third pwm (pwm2) is inverted and connected to fan-socket Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20201016204019.2606-2-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 9a11e5c60c26..ca8d5c7a1346 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -412,10 +412,15 @@ }; }; - pwm7_pins: pwm1-2-pins { + pwm_pins: pwm-pins { mux { function = "pwm"; - groups = "pwm_ch7_2"; + groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */ + "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */ + "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */ + "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */ + "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */ + "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */ }; }; @@ -535,7 +540,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pins>; + pinctrl-0 = <&pwm_pins>; status = "okay"; }; -- cgit v1.2.3 From 5833bc6c7319dd59441562d853b8e435e3bc8ac2 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 16 Oct 2020 22:40:18 +0200 Subject: dts64: mt7622: disable spi1 and uart2 because pins are used by pwm MDI_TP_P0 (gpio51) is used by pwm1 and uart2 (uart1 on gpio-header) MDI_RP_P4 (gpio67) is used by pwm4 and spi1 Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20201016204019.2606-3-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index ca8d5c7a1346..2f77dc40b9b8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -568,7 +568,6 @@ &spi1 { pinctrl-names = "default"; pinctrl-0 = <&spic1_pins>; - status = "okay"; }; &ssusb { @@ -590,7 +589,6 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; - status = "okay"; }; &watchdog { -- cgit v1.2.3 From 15ffd94a904bafcce6dd4babf8f26bd8fe965bff Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Sat, 28 Nov 2020 02:31:28 +0530 Subject: arm64: dts: ti: k3: squelch warning about lack of #interrupt-cells There are couple of places where INTA interrupt controller lacks #interrupt-cells property. This leads to warnings of the type: arch/arm64/boot/dts/ti/k3-j721e-main.dtsi:147.51-156.5: Warning (interrupt_provider): /bus@100000/main-navss/interrupt-controller@33d00000: Missing #interrupt-cells in interrupt provider when building TI device-tree files with W=2 warning level. Fix these. Signed-off-by: Sekhar Nori Signed-off-by: Nishanth Menon Reviewed-by: Grygorii Strashko Link: https://lore.kernel.org/r/20201127210128.9151-1-nsekhar@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 116818912ba2..12591a854020 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -472,6 +472,7 @@ interrupt-controller; interrupt-parent = <&intr_main_navss>; msi-controller; + #interrupt-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <179>; ti,interrupt-ranges = <0 0 256>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 19e602afdb05..4e189b34a99e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -148,6 +148,7 @@ interrupt-controller; interrupt-parent = <&main_navss_intr>; msi-controller; + #interrupt-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <209>; ti,interrupt-ranges = <0 0 256>; -- cgit v1.2.3 From 5c44c564e4491758124050643f00c6bad9bfbea8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 27 Nov 2020 23:00:44 +0530 Subject: arm64: dts: qcom: qrb5165-rb5: Add support for MCP2518FD Add support for onboard MCP2518FD SPI CAN transceiver attached to SPI0 of RB5. Tested-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20201127173044.55144-1-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index d9f52703ba2a..ce22d4fa383e 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -25,6 +25,13 @@ stdout-path = "serial0:115200n8"; }; + /* Fixed crystal oscillator dedicated to MCP2518FD */ + clk40M: can_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + dc12v: dc12v-regulator { compatible = "regulator-fixed"; regulator-name = "DC12V"; @@ -493,6 +500,16 @@ /* CAN */ &spi0 { status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + clocks = <&clk40M>; + interrupts-extended = <&tlmm 15 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + vdd-supply = <&vdc_5v>; + xceiver-supply = <&vdc_5v>; + }; }; &tlmm { -- cgit v1.2.3 From 8077f593d77cf53b0e0ee467b2de2f9e781ab437 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Tue, 8 Sep 2020 09:30:50 +0200 Subject: arm64: dts: marvell: espressobin: Simplify v7 ethernet port labeling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that the switch ports have a label in the .dtsi, simplify the whole "switch0" block for the v7 dts files. Signed-off-by: Andre Heider Reviewed-by: Pali Rohár Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- .../dts/marvell/armada-3720-espressobin-v7-emmc.dts | 18 +++++------------- .../boot/dts/marvell/armada-3720-espressobin-v7.dts | 18 +++++------------- 2 files changed, 10 insertions(+), 26 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts index 215d2f702623..61d49d6a2a2a 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts @@ -28,20 +28,12 @@ }; }; -&switch0 { - ports { - switch0port1: port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy0>; - }; +&switch0port1 { + label = "lan1"; +}; - switch0port3: port@3 { - reg = <3>; - label = "wan"; - phy-handle = <&switch0phy2>; - }; - }; +&switch0port3 { + label = "wan"; }; /* U11 */ diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts index b6f4af8ebafb..44dbe9a21cc7 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts @@ -27,18 +27,10 @@ }; }; -&switch0 { - ports { - switch0port1: port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy0>; - }; +&switch0port1 { + label = "lan1"; +}; - switch0port3: port@3 { - reg = <3>; - label = "wan"; - phy-handle = <&switch0phy2>; - }; - }; +&switch0port3 { + label = "wan"; }; -- cgit v1.2.3 From d77998497783cab316acde46add4ee4cc70fb76f Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Tue, 22 Sep 2020 06:31:41 +0200 Subject: arm64: dts: marvell: espressobin: Get rid of duplicate serial aliases MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The included armada-37xx.dtsi already defines these two aliases. Signed-off-by: Andre Heider Reviewed-by: Pali Rohár Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index 0775c16e0ec8..3169a820558f 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -17,8 +17,6 @@ ethernet1 = &switch0port1; ethernet2 = &switch0port2; ethernet3 = &switch0port3; - serial0 = &uart0; - serial1 = &uart1; }; chosen { -- cgit v1.2.3 From f9559f029ebe05a87e9689f4aa444e19cc7426e4 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 25 Sep 2020 10:50:43 +0200 Subject: arm64: dts: marvell: espressobin: De-duplicate eMMC definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit eMMC definitions in files armada-3720-espressobin-emmc.dts and armada-3720-espressobin-v7-emmc.dts is same. So move it into common armada-3720-espressobin.dtsi file with status "disabled". This change simplifies eMMC variants of DTS files for Espressobin. Signed-off-by: Pali Rohár Reviewed-by: Andre Heider Tested-by: Andre Heider Signed-off-by: Gregory CLEMENT --- .../dts/marvell/armada-3720-espressobin-emmc.dts | 18 ---------------- .../marvell/armada-3720-espressobin-v7-emmc.dts | 18 ---------------- .../boot/dts/marvell/armada-3720-espressobin.dtsi | 24 ++++++++++++++++++++++ 3 files changed, 24 insertions(+), 36 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts index ec72a11ed80f..5c4d8f379704 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts @@ -21,24 +21,6 @@ "marvell,armada3720", "marvell,armada3710"; }; -/* U11 */ &sdhci0 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,xenon-emmc; - marvell,xenon-tun-count = <9>; - marvell,pad-type = "fixed-1-8v"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - mmccard: mmccard@0 { - compatible = "mmc-card"; - reg = <0>; - }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts index 61d49d6a2a2a..e225dce64b9e 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts @@ -36,24 +36,6 @@ label = "wan"; }; -/* U11 */ &sdhci0 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,xenon-emmc; - marvell,xenon-tun-count = <9>; - marvell,pad-type = "fixed-1-8v"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - mmccard: mmccard@0 { - compatible = "mmc-card"; - reg = <0>; - }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index 3169a820558f..8a1c678bea5f 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -58,6 +58,30 @@ phy-names = "sata-phy"; }; +/* U11 */ +&sdhci0 { + /* Main DTS file for Espressobin is without eMMC */ + status = "disabled"; + + non-removable; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + marvell,xenon-emmc; + marvell,xenon-tun-count = <9>; + marvell,pad-type = "fixed-1-8v"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins>; + + #address-cells = <1>; + #size-cells = <0>; + mmccard: mmccard@0 { + compatible = "mmc-card"; + reg = <0>; + }; +}; + /* J1 */ &sdhci1 { wp-inverted; -- cgit v1.2.3 From 6d96e11b777129d709096744e125bd866ff8b5a1 Mon Sep 17 00:00:00 2001 From: Luka Kovacic Date: Sun, 25 Oct 2020 02:13:51 +0100 Subject: arm64: dts: marvell: Add a device tree for the IEI Puzzle-M801 board Add initial support for the IEI Puzzle-M801 1U Rackmount Network Appliance board. The board is based on the quad-core Marvell Armada 8040 SoC and supports up to 16 GB of DDR4 2400 MHz ECC RAM. It has a PCIe x16 slot (x2 lanes only) and an M.2 type B slot. Main system hardware: 2x USB 3.0 4x Gigabit Ethernet 2x SFP+ 1x SATA 3.0 1x M.2 type B 1x RJ45 UART 1x SPI flash 1x IEI WT61P803 PUZZLE Microcontroller 1x EPSON RX8010 RTC (used instead of the integrated Marvell RTC controller) 6x SFP+ LED 1x HDD LED All of the hardware listed above is supported and tested in this port. Signed-off-by: Luka Kovacic Acked-by: Andrew Lunn Cc: Luka Perkov Cc: Robert Marko Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-8040-puzzle-m801.dts | 523 +++++++++++++++++++++ 2 files changed, 524 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 3e5f2e7a040c..e413c3261792 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-puzzle-m801.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts new file mode 100644 index 000000000000..dac85fa748de --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts @@ -0,0 +1,523 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * Copyright (C) 2020 Sartura Ltd. + * + * Device Tree file for IEI Puzzle-M801 + */ + +#include "armada-8040.dtsi" + +#include +#include + +/ { + model = "IEI-Puzzle-M801"; + compatible = "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + aliases { + ethernet0 = &cp0_eth0; + ethernet1 = &cp1_eth0; + ethernet2 = &cp0_eth1; + ethernet3 = &cp0_eth2; + ethernet4 = &cp1_eth1; + ethernet5 = &cp1_eth2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + /* Regulator labels correspond with schematics */ + v_3_3: regulator-3-3v { + compatible = "regulator-fixed"; + regulator-name = "v_3_3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + status = "okay"; + }; + + v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_xhci_vbus_pins>; + regulator-name = "v_5v0_usb3_hst_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "okay"; + }; + + v_vddo_h: regulator-1-8v { + compatible = "regulator-fixed"; + regulator-name = "v_vddo_h"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + status = "okay"; + }; + + sfp_cp0_eth0: sfp-cp0-eth0 { + compatible = "sff,sfp"; + i2c-bus = <&sfpplus0_i2c>; + los-gpio = <&sfpplus_gpio 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&sfpplus_gpio 10 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&sfpplus_gpio 9 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&sfpplus_gpio 8 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + + sfp_cp1_eth0: sfp-cp1-eth0 { + compatible = "sff,sfp"; + i2c-bus = <&sfpplus1_i2c>; + los-gpio = <&sfpplus_gpio 3 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&sfpplus_gpio 2 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&sfpplus_gpio 1 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&sfpplus_gpio 0 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + pinctrl-0 = <&cp0_sfpplus_led_pins &cp1_sfpplus_led_pins>; + pinctrl-names = "default"; + + led-0 { + /* SFP+ port 2: Activity */ + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + gpios = <&cp1_gpio1 6 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* SFP+ port 1: Activity */ + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&cp1_gpio1 14 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* SFP+ port 2: 10 Gbps indicator */ + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&cp1_gpio1 7 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* SFP+ port 2: 1 Gbps indicator */ + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&cp1_gpio1 8 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* SFP+ port 1: 10 Gbps indicator */ + function = LED_FUNCTION_LAN; + function-enumerator = <4>; + gpios = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>; + }; + + led-5 { + /* SFP+ port 1: 1 Gbps indicator */ + function = LED_FUNCTION_LAN; + function-enumerator = <5>; + gpios = <&cp1_gpio1 31 GPIO_ACTIVE_LOW>; + }; + + led-6 { + function = LED_FUNCTION_DISK; + linux,default-trigger = "disk-activity"; + gpios = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; + }; + + }; +}; + +&ap_sdhci0 { + bus-width = <8>; + /* + * Not stable in HS modes - phy needs "more calibration", so add + * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. + */ + marvell,xenon-phy-slow-mode; + no-1-8-v; + no-sd; + no-sdio; + non-removable; + status = "okay"; + vqmmc-supply = <&v_vddo_h>; +}; + +&ap_thermal_cpu1 { + trips { + cpu_active: cpu-active { + temperature = <44000>; + hysteresis = <2000>; + type = "active"; + }; + }; + cooling-maps { + fan-map { + trip = <&cpu_active>; + cooling-device = <&chassis_fan_group0 64 THERMAL_NO_LIMIT>, + <&chassis_fan_group1 64 THERMAL_NO_LIMIT>; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + rtc@32 { + compatible = "epson,rx8010"; + reg = <0x32>; + }; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <20000000>; + partition@u-boot { + label = "u-boot"; + reg = <0x00000000 0x001f0000>; + }; + partition@u-boot-env { + label = "u-boot-env"; + reg = <0x001f0000 0x00010000>; + }; + partition@ubi1 { + label = "ubi1"; + reg = <0x00200000 0x03f00000>; + }; + partition@ubi2 { + label = "ubi2"; + reg = <0x04100000 0x03f00000>; + }; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + /* IEI WT61P803 PUZZLE MCU Controller */ + mcu { + compatible = "iei,wt61p803-puzzle"; + current-speed = <115200>; + enable-beep; + + leds { + compatible = "iei,wt61p803-puzzle-leds"; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_POWER; + color = ; + }; + }; + + hwmon { + compatible = "iei,wt61p803-puzzle-hwmon"; + #address-cells = <1>; + #size-cells = <0>; + + chassis_fan_group0:fan-group@0 { + #cooling-cells = <2>; + reg = <0x00>; + cooling-levels = <64 102 170 230 250>; + }; + + chassis_fan_group1:fan-group@1 { + #cooling-cells = <2>; + reg = <0x01>; + cooling-levels = <64 102 170 230 250>; + }; + }; + }; +}; + +&cp0_rtc { + status = "disabled"; +}; + +&cp0_i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c0_pins>; + status = "okay"; + + sfpplus_gpio: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@54 { + compatible = "atmel,24c04"; + reg = <0x54>; + }; +}; + +&cp0_i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c1_pins>; + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + sfpplus0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + sfpplus1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; +}; + +&cp0_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_uart1_pins>; + status = "okay"; +}; + +&cp0_mdio { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + ge_phy2: ethernet-phy@0 { + reg = <0>; + }; + + ge_phy3: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cp0_pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_pcie_pins>; + num-lanes = <1>; + num-viewport = <8>; + reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; + ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; + phys = <&cp0_comphy0 0>; + phy-names = "cp0-pcie0-x1-phy"; + status = "okay"; +}; + +&cp0_pinctrl { + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins = "mpp32", "mpp34"; + marvell,function = "ge"; + }; + cp0_i2c1_pins: i2c1-pins { + marvell,pins = "mpp35", "mpp36"; + marvell,function = "i2c1"; + }; + cp0_i2c0_pins: i2c0-pins { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "i2c0"; + }; + cp0_uart1_pins: uart1-pins { + marvell,pins = "mpp40", "mpp41"; + marvell,function = "uart1"; + }; + cp0_xhci_vbus_pins: xhci0-vbus-pins { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + cp0_pcie_pins: pcie-pins { + marvell,pins = "mpp52"; + marvell,function = "gpio"; + }; + cp0_sdhci_pins: sdhci-pins { + marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", + "mpp60", "mpp61"; + marvell,function = "sdio"; + }; + cp0_sfpplus_led_pins: sfpplus-led-pins { + marvell,pins = "mpp54"; + marvell,function = "gpio"; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth0 { + status = "okay"; + phy-mode = "10gbase-r"; + phys = <&cp0_comphy4 0>; + local-mac-address = [ae 00 00 00 ff 00]; + sfp = <&sfp_cp0_eth0>; + managed = "in-band-status"; +}; + +&cp0_eth1 { + status = "okay"; + phy = <&ge_phy2>; + phy-mode = "sgmii"; + local-mac-address = [ae 00 00 00 ff 01]; + phys = <&cp0_comphy3 1>; +}; + +&cp0_eth2 { + status = "okay"; + phy-mode = "sgmii"; + phys = <&cp0_comphy1 2>; + local-mac-address = [ae 00 00 00 ff 02]; + phy = <&ge_phy3>; +}; + +&cp0_sata0 { + status = "okay"; + + sata-port@0 { + phys = <&cp0_comphy2 0>; + phy-names = "cp0-sata0-0-phy"; + }; + + sata-port@1 { + phys = <&cp0_comphy5 1>; + phy-names = "cp0-sata0-1-phy"; + }; +}; + +&cp0_sdhci0 { + broken-cd; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_sdhci_pins>; + status = "okay"; + vqmmc-supply = <&v_3_3>; +}; + +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_usb3_1 { + status = "okay"; +}; + +&cp1_i2c0 { + clock-frequency = <100000>; + status = "disabled"; +}; + +&cp1_i2c1 { + clock-frequency = <100000>; + status = "disabled"; +}; + +&cp1_rtc { + status = "disabled"; +}; + +&cp1_ethernet { + status = "okay"; +}; + +&cp1_eth0 { + status = "okay"; + phy-mode = "10gbase-r"; + phys = <&cp1_comphy4 0>; + local-mac-address = [ae 00 00 00 ff 03]; + sfp = <&sfp_cp1_eth0>; + managed = "in-band-status"; +}; + +&cp1_eth1 { + status = "okay"; + phy = <&ge_phy4>; + phy-mode = "sgmii"; + local-mac-address = [ae 00 00 00 ff 04]; + phys = <&cp1_comphy3 1>; +}; + +&cp1_eth2 { + status = "okay"; + phy-mode = "sgmii"; + local-mac-address = [ae 00 00 00 ff 05]; + phys = <&cp1_comphy5 2>; + phy = <&ge_phy5>; +}; + +&cp1_pinctrl { + cp1_sfpplus_led_pins: sfpplus-led-pins { + marvell,pins = "mpp6", "mpp7", "mpp8", "mpp10", "mpp14", "mpp31"; + marvell,function = "gpio"; + }; +}; + +&cp1_uart0 { + status = "disabled"; +}; + +&cp1_comphy2 { + cp1_usbh0_con: connector { + compatible = "usb-a-connector"; + phy-supply = <&v_5v0_usb3_hst_vbus>; + }; +}; + +&cp1_usb3_0 { + phys = <&cp1_comphy2 0>; + phy-names = "cp1-usb3h0-comphy"; + status = "okay"; +}; + +&cp1_mdio { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + ge_phy4: ethernet-phy@1 { + reg = <1>; + }; + ge_phy5: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cp1_pcie0 { + num-lanes = <2>; + phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>; + phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy"; + status = "okay"; +}; -- cgit v1.2.3 From c1e9911fcc54afb2ccfe8bab213ec6679c455675 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Tue, 6 Oct 2020 14:44:55 +0200 Subject: arm64: dts: marvell: espressobin: Add support for LED2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LED2 is connected to MPP1_2 pin. It is working only on V7 boards. V5 boards have hw bug which cause that LED2 is non-working. So enable LED2 only for Espressobin V7 boards. Note that LED1 is connected to LED_WLAN# pin on miniPCIe card and LED3 to power supply. Therefore on Espressobin board only LED2 can be controlled directly from the host. LED1 is possible to control via WiFi card inserted in miniPCIe slot if driver for particular card supports it. Signed-off-by: Pali Rohár Tested-by: Gérald Kerma Signed-off-by: Gregory CLEMENT --- .../boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts | 4 ++++ arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts | 4 ++++ arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 13 +++++++++++++ 3 files changed, 21 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts index e225dce64b9e..58b94db5f652 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts @@ -39,3 +39,7 @@ &sdhci0 { status = "okay"; }; + +&led2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts index 44dbe9a21cc7..b22ae550a45b 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts @@ -34,3 +34,7 @@ &switch0port3 { label = "wan"; }; + +&led2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index 8a1c678bea5f..daffe136c523 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -41,6 +41,19 @@ 3300000 0x0>; enable-active-high; }; + + led2: gpio-led2 { + /* led2 is working only on v7 board */ + status = "disabled"; + + compatible = "gpio-leds"; + + led2 { + label = "led2"; + gpios = <&gpionb 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; }; /* J9 */ -- cgit v1.2.3 From 3404fe15a60fe790799d6e1dd5de51997f338cc6 Mon Sep 17 00:00:00 2001 From: Vladimir Vid Date: Mon, 26 Oct 2020 19:44:42 +0100 Subject: arm64: dts: marvell: add DT for ESPRESSObin-Ultra This adds support for ESPRESSObin-Ultra from Globalscale. Specifications are similar to the base ESPRESSObin board, with main difference being being WAN port with PoE capability and 2 additional ethernet ports. Full specifications: 1x Marvell 64 bit Dual Core ARM A53 Armada 3700 SOC clocked up to 1.2Ghz 1x Topaz 6341 Networking Switch 1GB DDR4 8GB eMMC 1x WAN with 30W POE 4x Gb LAN 1x RTC Clock and battery 1x DC Jack 1x USB 3.0 Type A 1x USB 2.0 Type A 1x SIM NanoSIM card Slot 1x Power Button 4x LED 1x Reset button 1x microUSB for UART 1x M.2 2280 slot for memory 1x 2x2 802.11ac Wi-Fi 1x MiniPCIE slot for Wi-Fi (PCIe interface) Signed-off-by: Vladimir Vid Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../dts/marvell/armada-3720-espressobin-ultra.dts | 165 +++++++++++++++++++++ 2 files changed, 166 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index e413c3261792..34efe0fb6f37 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-emmc.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-ultra.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7-emmc.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts new file mode 100644 index 000000000000..c5eb3604dd5b --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for ESPRESSObin-Ultra board. + * Copyright (C) 2019 Globalscale technologies, Inc. + * + * Jason Hung + */ + +/dts-v1/; + +#include "armada-3720-espressobin.dtsi" + +/ { + model = "Globalscale Marvell ESPRESSOBin Ultra Board"; + compatible = "globalscale,espressobin-ultra", "marvell,armada3720", + "marvell,armada3710"; + + aliases { + /* ethernet1 is WAN port */ + ethernet1 = &switch0port5; + ethernet2 = &switch0port1; + ethernet3 = &switch0port2; + ethernet4 = &switch0port3; + ethernet5 = &switch0port4; + }; + + reg_usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpionb 19 GPIO_ACTIVE_HIGH>; + }; + + usb3_phy: usb3-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_usb3_vbus>; + }; + + gpio-leds { + pinctrl-names = "default"; + compatible = "gpio-leds"; + /* No assigned functions to the LEDs by default */ + led1 { + label = "ebin-ultra:blue:led1"; + gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; + }; + led2 { + label = "ebin-ultra:green:led2"; + gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; + }; + led3 { + label = "ebin-ultra:red:led3"; + gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; + }; + led4 { + label = "ebin-ultra:yellow:led4"; + gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&sdhci1 { + status = "disabled"; +}; + +&spi0 { + flash@0 { + spi-max-frequency = <108000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "firmware"; + reg = <0x0 0x3e0000>; + }; + partition@3e0000 { + label = "hw-info"; + reg = <0x3e0000 0x10000>; + read-only; + }; + partition@3f0000 { + label = "u-boot-env"; + reg = <0x3f0000 0x10000>; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <100000>; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&usb3 { + usb-phy = <&usb3_phy>; + status = "disabled"; +}; + +&mdio { + extphy: ethernet-phy@1 { + reg = <1>; + }; +}; + +&switch0 { + reg = <3>; + + ports { + switch0port1: port@1 { + reg = <1>; + label = "lan0"; + phy-handle = <&switch0phy0>; + }; + + switch0port2: port@2 { + reg = <2>; + label = "lan1"; + phy-handle = <&switch0phy1>; + }; + + switch0port3: port@3 { + reg = <3>; + label = "lan2"; + phy-handle = <&switch0phy2>; + }; + + switch0port4: port@4 { + reg = <4>; + label = "lan3"; + phy-handle = <&switch0phy3>; + }; + + switch0port5: port@5 { + reg = <5>; + label = "wan"; + phy-handle = <&extphy>; + phy-mode = "sgmii"; + }; + }; + + mdio { + switch0phy3: switch0phy3@14 { + reg = <0x14>; + }; + }; +}; -- cgit v1.2.3 From 53e950d597e3578da84238b86424bfcc9e101d87 Mon Sep 17 00:00:00 2001 From: Sven Auhagen Date: Mon, 9 Nov 2020 18:39:48 +0100 Subject: arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts There are two SATA ports per CP110. Each of them has a dedicated interrupt. Describe the real hardware by adding two SATA ports to the CP110 SATA node. Reviewed-by: Hans de Goede Signed-off-by: Sven Auhagen Signed-off-by: Thomas Petazzoni Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 9dcf16beabf5..ec27294f097b 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -300,11 +300,9 @@ }; CP11X_LABEL(sata0): sata@540000 { - compatible = "marvell,armada-8k-ahci", - "generic-ahci"; + compatible = "marvell,armada-8k-ahci"; reg = <0x540000 0x30000>; dma-coherent; - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&CP11X_LABEL(clk) 1 15>, <&CP11X_LABEL(clk) 1 16>; #address-cells = <1>; @@ -312,10 +310,12 @@ status = "disabled"; sata-port@0 { + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; reg = <0>; }; sata-port@1 { + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; reg = <1>; }; }; -- cgit v1.2.3 From 3aa669a994c9110a2dc7e08a5c0958a9ea5eb17c Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Sat, 14 Nov 2020 21:42:53 +0100 Subject: arm64: dts: armada-3720-turris-mox: update ethernet-phy handle name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use property name `phy-handle` instead of the deprecated `phy` to connect eth2 to the PHY. Signed-off-by: Marek Behún Fixes: 7109d817db2e ("arm64: dts: marvell: add DTS for Turris Mox") Cc: Gregory CLEMENT Cc: Andrew Lunn Cc: Rob Herring Cc: devicetree@vger.kernel.org Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index f3a678e0fd99..bf76ebe46379 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -146,7 +146,7 @@ pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; phy-mode = "rgmii-id"; - phy = <&phy1>; + phy-handle = <&phy1>; status = "okay"; }; -- cgit v1.2.3 From 4076a007bd0f6171434bdb119a0b8797749b0502 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 26 Nov 2020 15:33:34 +0800 Subject: arm64: dts: rockchip: Set dr_mode to "host" for OTG on rk3328-roc-cc The board has a standard USB A female port connected to the USB OTG controller's data pins. Set dr_mode in the OTG controller node to indicate this usage, instead of having the implementation guess. Fixes: 2171f4fdac06 ("arm64: dts: rockchip: add roc-rk3328-cc board") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201126073336.30794-2-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts index b70ffb1c6a63..b76282e704de 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -334,6 +334,7 @@ }; &usb20_otg { + dr_mode = "host"; status = "okay"; }; -- cgit v1.2.3 From 65f0b420dea7e70d70cd6ef0f12f9ff81ab90d23 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 26 Nov 2020 15:33:35 +0800 Subject: arm64: dts: rockchip: Enable HDMI audio on rk3328-roc-cc The RK3328-ROC-CC already has HDMI display output enabled. Now that audio for the HDMI controller is supported, it can be enabled as well. Enable the simple-audio-card, and the I2S interface the audio is fed from. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201126073336.30794-3-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts index b76282e704de..697fce709031 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -161,6 +161,10 @@ status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -270,6 +274,10 @@ }; }; +&i2s0 { + status = "okay"; +}; + &io_domains { status = "okay"; -- cgit v1.2.3 From 5df4d4d16ce4c6e6a5cb9d4b684b187f28258219 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 26 Nov 2020 15:33:36 +0800 Subject: arm64: dts: rockchip: Enable analog audio on rk3328-roc-cc Now that driver support for the RK3328's audio codec, and the plumbing is defined at the SoC level, we can enable analog audio at the board level. Enable analog audio by enabling the codec and the I2S interface connected and the simple-audio-card that binds them together. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201126073336.30794-4-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts index 697fce709031..19959bfba451 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -104,6 +104,14 @@ }; }; +&analog_sound { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_arm>; }; @@ -278,6 +286,10 @@ status = "okay"; }; +&i2s1 { + status = "okay"; +}; + &io_domains { status = "okay"; -- cgit v1.2.3 From 9a9f642784074d09efe9337e64b959f76c9f6913 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 16 Nov 2020 14:23:11 +0100 Subject: arm64: dts: rockchip: rename sdhci nodename to mmc on rk3399 A test with the command below gives for example this error: /arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: sdhci@fe330000: $nodename:0: 'sdhci@fe330000' does not match '^mmc(@.*)?$' Fix it by renaming sdhci to mmc. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/ mmc/arasan,sdhci.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20201116132311.8318-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index ada724b12f01..1aa52ec938a1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -328,7 +328,7 @@ status = "disabled"; }; - sdhci: sdhci@fe330000 { + sdhci: mmc@fe330000 { compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = ; -- cgit v1.2.3 From 4548ea027c900f1e0f07a292b8e10dc3d2725f44 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 9 Nov 2020 23:40:09 +0530 Subject: arm64: dts: rockchip: Enable USB Host, OTG on px30-enagicam Engicam EDIMM2.2 and C.Touch 2.0 Kits support USB Host and OTG ports. Add support to enable USB on these kits while mounting px30-core SOM. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-2-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/px30-engicam-common.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi index bd5bde989e8d..fbbdbb0a40af 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -33,7 +33,31 @@ status = "okay"; }; +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + &uart2 { pinctrl-0 = <&uart2m1_xfer>; status = "okay"; }; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; -- cgit v1.2.3 From 87761edeb2cd90b8251f269eb52c4b48152aace8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 9 Nov 2020 23:40:10 +0530 Subject: arm64: dts: rockchip: Enable LVDS panel on px30-engicam-edimm2.2 Engicam PX30.Core EDIMM2.2 developement Kit has on board 10" LVDS panel from yes-optoelectronics. This patch adds panel enablement nodes on respective dts(i) files. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-3-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/px30-engicam-common.dtsi | 4 ++ .../boot/dts/rockchip/px30-engicam-edimm2.2.dtsi | 59 ++++++++++++++++++++++ .../boot/dts/rockchip/px30-engicam-px30-core.dtsi | 5 ++ 3 files changed, 68 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi index fbbdbb0a40af..8fdd7ff2fdf9 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -25,6 +25,10 @@ status = "okay"; }; +&pwm0 { + status = "okay"; +}; + &sdmmc { cap-sd-highspeed; card-detect-delay = <800>; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi index cb00988953e9..449b8eb6454e 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi @@ -5,3 +5,62 @@ */ #include "px30-engicam-common.dtsi" + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + }; + + panel { + compatible = "yes-optoelectronics,ytc700tlag-05-201c"; + backlight = <&backlight>; + data-mapping = "vesa-24"; + power-supply = <&vcc3v3_lcd>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +/* LVDS_B(secondary) */ +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi index db22f776c68f..cdacd3483600 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi @@ -192,6 +192,11 @@ }; }; + vcc3v3_lcd: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + vcc5v0_host: SWITCH_REG2 { regulator-name = "vcc5v0_host"; regulator-always-on; -- cgit v1.2.3 From 0e418423be1c824b2cda37fd00528f62231cd219 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 9 Nov 2020 23:40:12 +0530 Subject: arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. Add support for it. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-5-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../px30-engicam-px30-core-ctouch2-of10.dts | 77 ++++++++++++++++++++++ 2 files changed, 78 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 5a53979b7057..1ab55a124a87 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts new file mode 100644 index 000000000000..47aa30505a42 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-ctouch2.dtsi" +#include "px30-engicam-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame"; + compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core", + "rockchip,px30"; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + panel { + compatible = "ampire,am-1280800n3tzqw-t00h"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd>; + data-mapping = "vesa-24"; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; -- cgit v1.2.3 From 93a4e7d12468b0ab46796f3ed8dc5838dc7f63bc Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Mon, 9 Nov 2020 23:40:13 +0530 Subject: arm64: dts: rockchip: Add WiFi support on px30-engicam Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected on the SDIO bus. The SDIO power sequnce is connacted with exteernal 32KHz oscillator and it require 3V3 regulator input. This patch adds WiFi enablement nodes for these respective boards. Signed-off-by: Michael Trimarchi Signed-off-by: Suniel Mahesh Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-6-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/px30-engicam-common.dtsi | 45 ++++++++++++++++++++++ .../boot/dts/rockchip/px30-engicam-ctouch2.dtsi | 12 ++++++ .../rockchip/px30-engicam-px30-core-edimm2.2.dts | 12 ++++++ 3 files changed, 69 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi index 8fdd7ff2fdf9..0e1a93ec3234 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -14,6 +14,51 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&xin32k>; + clock-names = "ext_clock"; + post-power-on-delay-ms = <80>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + }; + + vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_rf_aux_mod"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; }; &gmac { diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi index 58425b1e559f..d5708779c285 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi @@ -6,3 +6,15 @@ */ #include "px30-engicam-common.dtsi" + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio_pwrseq { + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts index e54d1e480daa..913444548b59 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts @@ -19,3 +19,15 @@ stdout-path = "serial2:115200n8"; }; }; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio_pwrseq { + reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; +}; -- cgit v1.2.3 From 1cc1e851d15b4ebd4c6c5f741cfdb58b988a4445 Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Mon, 9 Nov 2020 23:40:14 +0530 Subject: arm64: dts: rockchip: Add BT support on px30-engicam Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected on the UART bus. UART bus on the design routed via USB to UART CP20x bridge. This bridge powered from 3V3 regualtor gpio. This patch adds BT enablement nodes for these respective boards. Signed-off-by: Michael Trimarchi Signed-off-by: Suniel Mahesh Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-7-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi | 10 ++++++++++ .../boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts | 10 ++++++++++ 3 files changed, 32 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi index 0e1a93ec3234..08b0b9fbcbc9 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -24,6 +24,18 @@ pinctrl-0 = <&wifi_enable_h>; }; + vcc3v3_btreg: vcc3v3-btreg { + compatible = "regulator-gpio"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable_h>; + regulator-name = "btreg-gpio-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + states = <3300000 0x0>; + }; + vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { compatible = "regulator-fixed"; regulator-name = "vcc3v3_rf_aux_mod"; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi index d5708779c285..bf10a3d29fca 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi @@ -8,6 +8,12 @@ #include "px30-engicam-common.dtsi" &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -18,3 +24,7 @@ &sdio_pwrseq { reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; }; + +&vcc3v3_btreg { + enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts index 913444548b59..d759478e1c84 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts @@ -21,6 +21,12 @@ }; &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; @@ -31,3 +37,7 @@ &sdio_pwrseq { reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; }; + +&vcc3v3_btreg { + enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; +}; -- cgit v1.2.3 From cbc4a395dcc730be9114ef077a67e07b32a029a4 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 5 Oct 2020 15:35:13 +0200 Subject: arm64: dts: marvell: espressobin: Update link to V7 schematic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Up-to-date version of V7 schematic is on new URL linked from official tech-spec webpage http://espressobin.net/tech-spec/ Signed-off-by: Pali Rohár Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts | 2 +- arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts index 58b94db5f652..75401eab4d42 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts @@ -8,7 +8,7 @@ * */ /* - * Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200 + * Schematic available at http://espressobin.net/wp-content/uploads/2020/05/ESPRESSObin_V7-0_Schematic.pdf */ /dts-v1/; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts index b22ae550a45b..48a7f50fb427 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts @@ -8,7 +8,7 @@ * */ /* - * Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200 + * Schematic available at http://espressobin.net/wp-content/uploads/2020/05/ESPRESSObin_V7-0_Schematic.pdf */ /dts-v1/; -- cgit v1.2.3 From 09ff4e90e041485f7562d9baec340a9824af4f45 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Sun, 29 Nov 2020 23:22:22 +0530 Subject: arm64: dts: ti: k3-j721e-main: Add output tap delay values Add output tap delay values as given in the latest Data Manual[1], SPRSP36E, revised December 2019. [1] https://www.ti.com/lit/gpn/tda4vm Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20201129175223.21751-2-nsekhar@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 4e189b34a99e..556bc317b866 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1080,7 +1080,11 @@ bus-width = <8>; mmc-hs400-1_8v; mmc-ddr-1_8v; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0xf>; + ti,otap-del-sel-mmc-hs = <0xf>; + ti,otap-del-sel-ddr52 = <0x5>; + ti,otap-del-sel-hs200 = <0x6>; + ti,otap-del-sel-hs400 = <0x0>; ti,trm-icp = <0x8>; ti,strobe-sel = <0x77>; dma-coherent; @@ -1095,7 +1099,12 @@ clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0xc>; ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; @@ -1111,7 +1120,12 @@ clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0xc>; ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; -- cgit v1.2.3 From cd48ce86a4d0c1ffec86aa46a26da993c9af5f53 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Sun, 29 Nov 2020 23:22:23 +0530 Subject: arm64: dts: ti: k3-j721e-common-proc-board: Add support for SD card UHS modes Add support for UHS modes for the SD card connected at sdhci1. This involves adding regulators for voltage switching and power cycling the SD card and removing the no-1-8-v property. Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20201129175223.21751-3-nsekhar@ti.com --- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 33 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 -- 2 files changed, 33 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 5754892f8501..60764366e22b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -67,6 +67,31 @@ regulator-boot-on; }; + vdd_mmc1: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv_alt: gpio-regulator-TLV71033 { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; + regulator-name = "tlv71033"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + sound0: sound@0 { compatible = "ti,j721e-cpb-audio"; model = "j721e-cpb"; @@ -106,6 +131,12 @@ >; }; + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ + >; + }; + main_usbss0_pins_default: main-usbss0-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ @@ -295,6 +326,8 @@ &main_sdhci1 { /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 556bc317b866..b32df591c766 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1108,7 +1108,6 @@ ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; - no-1-8-v; }; main_sdhci2: sdhci@4f98000 { @@ -1129,7 +1128,6 @@ ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; - no-1-8-v; }; usbss0: cdns-usb@4104000 { -- cgit v1.2.3 From 29952fea5e85083374d19cb0a33206962e087d5b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2020 23:48:14 +0530 Subject: ARM: dts: rockchip: Add SDIO0 node for VMARC SOM Rockchip RK3288 and RK3399Pro based VMARC SOM has sdio0 for connecting WiFi/BT devices as a pluggable card via M.2 E-Key. Add associated sdio0 nodes, properties. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201023181814.220974-2-jagan@amarulasolutions.com [moved the unrelated rtc addition to a separate patch] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 17 +++++++++++++++++ .../arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi | 21 +++++++++++++++++++++ .../boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 16 ++++++++++++++++ 3 files changed, 54 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi index da80bfd5f2d5..0ae2bd150e37 100644 --- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi +++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi @@ -258,6 +258,7 @@ gpio1830-supply = <&vcc_18>; gpio30-supply = <&vcc_io>; sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_wl>; status = "okay"; }; @@ -283,6 +284,12 @@ }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_bus4: sdmmc-bus4 { rockchip,pins = @@ -314,6 +321,16 @@ }; }; +&sdio_pwrseq { + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */ +}; + &usbphy { status = "okay"; }; diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi index 26b53eac4706..da1d548b7330 100644 --- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi @@ -15,6 +15,14 @@ #clock-cells = <0>; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -78,6 +86,19 @@ status = "okay"; }; +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index 5d087be04af8..7257494d2831 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -353,6 +353,12 @@ }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vbus_host { usb1_en_oc: usb1-en-oc { rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; @@ -371,6 +377,16 @@ pmu1830-supply = <&vcc_1v8>; }; +&sdio_pwrseq { + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; +}; + &sdhci { bus-width = <8>; mmc-hs400-1_8v; -- cgit v1.2.3 From e56ed188c83053a505041e1a8ad4fba0f3b39089 Mon Sep 17 00:00:00 2001 From: Alexis Ballier Date: Thu, 22 Oct 2020 13:35:32 +0200 Subject: arm64: dts: rockchip: Properly define the type C connector on rk3399-orangepi Tested: - USB3 Gigabit adapter - USB2 mass storage The wiring is the same as the pinebook pro according to the schematics, thus this patch is heavily based on its dts. Signed-off-by: Alexis Ballier Cc: devicetree@vger.kernel.org Cc: Heiko Stuebner Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: linux-kernel@vger.kernel.org Link: https://lore.kernel.org/r/20201022113532.18470-1-aballier@gentoo.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts | 62 +++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts index 6163ae8063a7..ad7c4d00888f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts @@ -7,6 +7,7 @@ #include "dt-bindings/pwm/pwm.h" #include "dt-bindings/input/input.h" +#include "dt-bindings/usb/pd.h" #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -531,6 +532,43 @@ pinctrl-names = "default"; pinctrl-0 = <&chg_cc_int_l>; vbus-supply = <&vbus_typec>; + + typec_con: connector { + compatible = "usb-c-connector"; + data-role = "host"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + typec_hs: endpoint { + remote-endpoint = <&u2phy0_typec_hs>; + }; + }; + port@1 { + reg = <1>; + typec_ss: endpoint { + remote-endpoint = <&tcphy0_typec_ss>; + }; + }; + port@2 { + reg = <2>; + typec_dp: endpoint { + remote-endpoint = <&tcphy0_typec_dp>; + }; + }; + }; + }; }; }; @@ -717,6 +755,22 @@ status = "okay"; }; +&tcphy0_dp { + port { + tcphy0_typec_dp: endpoint { + remote-endpoint = <&typec_dp>; + }; + }; +}; + +&tcphy0_usb3 { + port { + tcphy0_typec_ss: endpoint { + remote-endpoint = <&typec_ss>; + }; + }; +}; + &tcphy1 { status = "okay"; }; @@ -739,6 +793,12 @@ phy-supply = <&vcc5v0_host>; status = "okay"; }; + + port { + u2phy0_typec_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; }; &u2phy1 { @@ -799,7 +859,7 @@ &usbdrd_dwc3_0 { status = "okay"; - dr_mode = "otg"; + dr_mode = "host"; }; &usbdrd3_1 { -- cgit v1.2.3 From 60a9d6ab2fdd5cac6366eb27de2469c7abee5696 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 31 Oct 2020 07:31:14 -0500 Subject: arm64: dts: imx8mm-beacon-som: Fix whitespace issue The pinmux subnodes are indented too much. This patch does nothing more than remove an extra tab. There are no functional changes. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-beacon-som.dtsi | 296 ++++++++++----------- 1 file changed, 148 insertions(+), 148 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index c74e006ad0e8..6b53830ddf74 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -284,166 +284,166 @@ }; &iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; - pinctrl_flexspi: flexspigrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 - MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 - MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 - MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + >; + }; - pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 - >; - }; + pinctrl_usdhc1_gpio: usdhc1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - >; - }; + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - >; - }; + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 + >; + }; - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 - >; - }; + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; }; -- cgit v1.2.3 From 87f7ba165168ee0bff0baf6ded6d4dfa5bba1217 Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Mon, 2 Nov 2020 11:29:41 +0530 Subject: arm64: dts: lx2160a: add device tree for lx2162aqds board Add device tree support for LX2162AQDS board. LX2162A has same die as of LX2160A with different packaging. Signed-off-by: Ioana Ciornei Signed-off-by: Kuldeep Singh Signed-off-by: Meenakshi Aggarwal Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 334 ++++++++++++++++++++++ 2 files changed, 335 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index e43254f1294d..876bf484bbe6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts new file mode 100644 index 000000000000..91786848bd30 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2162AQDS +// +// Copyright 2020 NXP + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" + +/ { + model = "NXP Layerscape LX2162AQDS"; + compatible = "fsl,lx2162a-qds", "fsl,lx2160a"; + + aliases { + crypto = &crypto; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sb_3v3: regulator-sb3v3 { + compatible = "regulator-fixed"; + regulator-name = "LTM4619-3.3VSB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + mdio-mux-1 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 0>; + mdio-parent-bus = <&emdio1>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + eee-broken-1000t; + }; + }; + + mdio@8 { /* On-board RTL8211F PHY #2 RGMII2 */ + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x2>; + eee-broken-1000t; + }; + }; + + mdio@18 { /* Slot #1 */ + reg = <0x18>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@19 { /* Slot #2 */ + reg = <0x19>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1a { /* Slot #3 */ + reg = <0x1a>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1b { /* Slot #4 */ + reg = <0x1b>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1c { /* Slot #5 */ + reg = <0x1c>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1d { /* Slot #6 */ + reg = <0x1d>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1e { /* Slot #7 */ + reg = <0x1e>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1f { /* Slot #8 */ + reg = <0x1f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 1>; + mdio-parent-bus = <&emdio2>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* Slot #1 (secondary EMI) */ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1 { /* Slot #2 (secondary EMI) */ + reg = <0x01>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@2 { /* Slot #3 (secondary EMI) */ + reg = <0x02>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@3 { /* Slot #4 (secondary EMI) */ + reg = <0x03>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@4 { /* Slot #5 (secondary EMI) */ + reg = <0x04>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@5 { /* Slot #6 (secondary EMI) */ + reg = <0x05>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@6 { /* Slot #7 (secondary EMI) */ + reg = <0x06>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@7 { /* Slot #8 (secondary EMI) */ + reg = <0x07>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +&dpmac17 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac18 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; + +&dspi0 { + status = "okay"; + + dflash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&dspi1 { + status = "okay"; + + dflash1: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&dspi2 { + status = "okay"; + + dflash2: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&fspi { + status = "okay"; + + mt35xu512aba0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + m25p,fast-read; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; + }; +}; + +&i2c0 { + status = "okay"; + + fpga@66 { + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", + "simple-mfd"; + reg = <0x66>; + + mux: mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ + <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + power-monitor@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <500>; + }; + + power-monitor@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + vcc-supply = <&sb_3v3>; + }; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; + }; + }; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; -- cgit v1.2.3 From bbe75af7b092f2d15a146328c107a3ebb5d1e25f Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:47 +0200 Subject: arm64: dts: ls1088a: add external MDIO device nodes Add the external MDIO device nodes found in the WRIOP global memory region. This is needed for management of external PHYs. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index b2c5189e59fa..42563c9c9e04 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -672,6 +672,24 @@ fsl,extts-fifo; }; + emdio1: mdio@8b96000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b96000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + emdio2: mdio@8b97000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b97000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cluster1_core0_watchdog: wdt@c000000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; -- cgit v1.2.3 From 73f034cc45e9bd554003919873066a2acbe0cf22 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:48 +0200 Subject: arm64: dts: ls1088ardb: add QSGMII PHY nodes Annotate the external MDIO1 node and describe the 8 QSGMII PHYs found on the LS1088ARDB board and add phy-handles for DPMACs 3-10 to its associated PHY. Also, add the internal PCS MDIO nodes for the internal MDIO buses found on the LS1088A SoC along with their internal PCS PHY and link the corresponding DPMAC to the PCS through the pcs-handle. Also, rename the dpmac@x nodes to ethernet@x in order to be compliant with the naming convention used by ethernet controllers. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 100 ++++++++++++++++++++++ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 70 ++++++++++++--- 2 files changed, 160 insertions(+), 10 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 5633e59febc3..e28443ba2633 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -17,6 +17,98 @@ compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; }; +&dpmac3 { + phy-handle = <&mdio1_phy5>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_0>; +}; + +&dpmac4 { + phy-handle = <&mdio1_phy6>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_1>; +}; + +&dpmac5 { + phy-handle = <&mdio1_phy7>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_2>; +}; + +&dpmac6 { + phy-handle = <&mdio1_phy8>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_3>; +}; + +&dpmac7 { + phy-handle = <&mdio1_phy1>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs7_0>; +}; + +&dpmac8 { + phy-handle = <&mdio1_phy2>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs7_1>; +}; + +&dpmac9 { + phy-handle = <&mdio1_phy3>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs7_2>; +}; + +&dpmac10 { + phy-handle = <&mdio1_phy4>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs7_3>; +}; + +&emdio1 { + status = "okay"; + + mdio1_phy5: ethernet-phy@c { + reg = <0xc>; + }; + + mdio1_phy6: ethernet-phy@d { + reg = <0xd>; + }; + + mdio1_phy7: ethernet-phy@e { + reg = <0xe>; + }; + + mdio1_phy8: ethernet-phy@f { + reg = <0xf>; + }; + + mdio1_phy1: ethernet-phy@1c { + reg = <0x1c>; + }; + + mdio1_phy2: ethernet-phy@1d { + reg = <0x1d>; + }; + + mdio1_phy3: ethernet-phy@1e { + reg = <0x1e>; + }; + + mdio1_phy4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; + &i2c0 { status = "okay"; @@ -87,6 +179,14 @@ status = "okay"; }; +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio7 { + status = "okay"; +}; + &qspi { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 42563c9c9e04..80ed64cdb73e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -690,6 +690,56 @@ status = "disabled"; }; + pcs_mdio3: mdio@8c0f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs3_0: ethernet-phy@0 { + reg = <0>; + }; + + pcs3_1: ethernet-phy@1 { + reg = <1>; + }; + + pcs3_2: ethernet-phy@2 { + reg = <2>; + }; + + pcs3_3: ethernet-phy@3 { + reg = <3>; + }; + }; + + pcs_mdio7: mdio@8c1f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs7_0: ethernet-phy@0 { + reg = <0>; + }; + + pcs7_1: ethernet-phy@1 { + reg = <1>; + }; + + pcs7_2: ethernet-phy@2 { + reg = <2>; + }; + + pcs7_3: ethernet-phy@3 { + reg = <3>; + }; + }; + cluster1_core0_watchdog: wdt@c000000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; @@ -767,52 +817,52 @@ #address-cells = <1>; #size-cells = <0>; - dpmac1: dpmac@1 { + dpmac1: ethernet@1 { compatible = "fsl,qoriq-mc-dpmac"; reg = <1>; }; - dpmac2: dpmac@2 { + dpmac2: ethernet@2 { compatible = "fsl,qoriq-mc-dpmac"; reg = <2>; }; - dpmac3: dpmac@3 { + dpmac3: ethernet@3 { compatible = "fsl,qoriq-mc-dpmac"; reg = <3>; }; - dpmac4: dpmac@4 { + dpmac4: ethernet@4 { compatible = "fsl,qoriq-mc-dpmac"; reg = <4>; }; - dpmac5: dpmac@5 { + dpmac5: ethernet@5 { compatible = "fsl,qoriq-mc-dpmac"; reg = <5>; }; - dpmac6: dpmac@6 { + dpmac6: ethernet@6 { compatible = "fsl,qoriq-mc-dpmac"; reg = <6>; }; - dpmac7: dpmac@7 { + dpmac7: ethernet@7 { compatible = "fsl,qoriq-mc-dpmac"; reg = <7>; }; - dpmac8: dpmac@8 { + dpmac8: ethernet@8 { compatible = "fsl,qoriq-mc-dpmac"; reg = <8>; }; - dpmac9: dpmac@9 { + dpmac9: ethernet@9 { compatible = "fsl,qoriq-mc-dpmac"; reg = <9>; }; - dpmac10: dpmac@a { + dpmac10: ethernet@a { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xa>; }; -- cgit v1.2.3 From 379b4f764563c094c00aa547c1ff8f4aeda72e23 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:49 +0200 Subject: arm64: dts: ls1088ardb: add necessary DTS nodes for DPMAC2 Annotate the external MDIO2 node and describe the 10GBASER PHY found on the LS1088ARDB board and add a phy-handle for DPMAC2 to link it. Also, add the internal PCS MDIO node for the internal MDIO buses found on the LS1088A SoC along with its internal PCS PHY and link the corresponding DPMAC to the PCS through the pcs-handle. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 19 +++++++++++++++++++ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 13 +++++++++++++ 2 files changed, 32 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index e28443ba2633..528ec72d0b83 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -17,6 +17,12 @@ compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; }; +&dpmac2 { + phy-handle = <&mdio2_aquantia_phy>; + phy-connection-type = "10gbase-r"; + pcs-handle = <&pcs2>; +}; + &dpmac3 { phy-handle = <&mdio1_phy5>; phy-connection-type = "qsgmii"; @@ -109,6 +115,15 @@ }; }; +&emdio2 { + status = "okay"; + + mdio2_aquantia_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; + &i2c0 { status = "okay"; @@ -179,6 +194,10 @@ status = "okay"; }; +&pcs_mdio2 { + status = "okay"; +}; + &pcs_mdio3 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 80ed64cdb73e..9c9c323cc3cd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -690,6 +690,19 @@ status = "disabled"; }; + pcs_mdio2: mdio@8c0b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs2: ethernet-phy@0 { + reg = <0>; + }; + }; + pcs_mdio3: mdio@8c0f000 { compatible = "fsl,fman-memac-mdio"; reg = <0x0 0x8c0f000 0x0 0x1000>; -- cgit v1.2.3 From 0420dde30a90534d7272847aea3f55845b3af22c Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:50 +0200 Subject: arm64: dts: ls208xa: add the external MDIO nodes Add the external MDIO device nodes found in the WRIOP global memory region. This is needed for management of external PHYs. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 4d3f72d126e7..ba0877d1e261 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -458,6 +458,24 @@ fsl,extts-fifo; }; + emdio1: mdio@8b96000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b96000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + emdio2: mdio@8b97000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b97000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ -- cgit v1.2.3 From 173fb0a3f9fb3ce416d2cb78476e0406a6db7490 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:51 +0200 Subject: arm64: dts: ls2088ardb: add PHY nodes for the CS4340 PHYs Annotate the EMDIO1 node and describe the 4 10GBASER PHYs found on the LS2088ARDB board. Also, add phy-handles for DPMACs 1-4 to their associated PHY. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts index f6b4d75a258b..a4b0dcab6e8e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts @@ -22,3 +22,47 @@ stdout-path = "serial1:115200n8"; }; }; + +&dpmac1 { + phy-handle = <&mdio1_phy1>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac2 { + phy-handle = <&mdio1_phy2>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac3 { + phy-handle = <&mdio1_phy3>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac4 { + phy-handle = <&mdio1_phy4>; + phy-connection-type = "10gbase-r"; +}; + +&emdio1 { + status = "okay"; + + mdio1_phy1: ethernet-phy@10 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x10>; + }; + + mdio1_phy2: ethernet-phy@11 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x11>; + }; + + mdio1_phy3: ethernet-phy@12 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x12>; + }; + + mdio1_phy4: ethernet-phy@13 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x13>; + }; +}; -- cgit v1.2.3 From dd2ab5c8b81e23847db5477033fc14f9b8783db2 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:52 +0200 Subject: arm64: dts: ls2088ardb: add PHY nodes for the AQR405 PHYs Annotate the EMDIO2 node and describe the other 4 10GBASER PHYs found on the LS2088ARDB board. Also, add phy-handles for DPMACs 5-8 to their associated PHY. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts index a4b0dcab6e8e..854f604049ca 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts @@ -43,6 +43,26 @@ phy-connection-type = "10gbase-r"; }; +&dpmac5 { + phy-handle = <&mdio2_phy1>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac6 { + phy-handle = <&mdio2_phy2>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac7 { + phy-handle = <&mdio2_phy3>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac8 { + phy-handle = <&mdio2_phy4>; + phy-connection-type = "10gbase-r"; +}; + &emdio1 { status = "okay"; @@ -66,3 +86,27 @@ reg = <0x13>; }; }; + +&emdio2 { + status = "okay"; + + mdio2_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + mdio2_phy2: ethernet-phy@1 { + compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + mdio2_phy3: ethernet-phy@2 { + compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + + mdio2_phy4: ethernet-phy@3 { + compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + }; +}; -- cgit v1.2.3 From 2e7c4c3c2fe7da00bd4061b32307dad4eeb9b39e Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:53 +0200 Subject: arm64: dts: ls208xa: add PCS MDIO and PCS PHY nodes Add PCS MDIO nodes for the internal MDIO buses on the LS208x SoCs, along with their internal PCS PHYs which will be used when the DPMAC object is in TYPE_PHY mode. Also, rename the dpmac@x nodes to ethernet@x in order to be compliant with the naming convention used by ethernet controllers. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 32 +++ arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 256 ++++++++++++++++++++-- 2 files changed, 272 insertions(+), 16 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts index 854f604049ca..60563917be44 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts @@ -110,3 +110,35 @@ reg = <0x3>; }; }; + +&pcs_mdio1 { + status = "okay"; +}; + +&pcs_mdio2 { + status = "okay"; +}; + +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio4 { + status = "okay"; +}; + +&pcs_mdio5 { + status = "okay"; +}; + +&pcs_mdio6 { + status = "okay"; +}; + +&pcs_mdio7 { + status = "okay"; +}; + +&pcs_mdio8 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index ba0877d1e261..02ad16b1bfe3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -476,6 +476,214 @@ status = "disabled"; }; + pcs_mdio1: mdio@8c07000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c07000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs1: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio2: mdio@8c0b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs2: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio3: mdio@8c0f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs3: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio4: mdio@8c13000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c13000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs4: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio5: mdio@8c17000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c17000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs5: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio6: mdio@8c1b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs6: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio7: mdio@8c1f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs7: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio8: mdio@8c23000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c23000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs8: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio9: mdio@8c27000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c27000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs9: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio10: mdio@8c2b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c2b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs10: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio11: mdio@8c2f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c2f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs11: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio12: mdio@8c33000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c33000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs12: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio13: mdio@8c37000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c37000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs13: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio14: mdio@8c3b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c3b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs14: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio15: mdio@8c3f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c3f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs15: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio16: mdio@8c43000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c43000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs16: ethernet-phy@0 { + reg = <0>; + }; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ @@ -500,84 +708,100 @@ #address-cells = <1>; #size-cells = <0>; - dpmac1: dpmac@1 { + dpmac1: ethernet@1 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x1>; + pcs-handle = <&pcs1>; }; - dpmac2: dpmac@2 { + dpmac2: ethernet@2 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x2>; + pcs-handle = <&pcs2>; }; - dpmac3: dpmac@3 { + dpmac3: ethernet@3 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x3>; + pcs-handle = <&pcs3>; }; - dpmac4: dpmac@4 { + dpmac4: ethernet@4 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x4>; + pcs-handle = <&pcs4>; }; - dpmac5: dpmac@5 { + dpmac5: ethernet@5 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x5>; + pcs-handle = <&pcs5>; }; - dpmac6: dpmac@6 { + dpmac6: ethernet@6 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x6>; + pcs-handle = <&pcs6>; }; - dpmac7: dpmac@7 { + dpmac7: ethernet@7 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x7>; + pcs-handle = <&pcs7>; }; - dpmac8: dpmac@8 { + dpmac8: ethernet@8 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x8>; + pcs-handle = <&pcs8>; }; - dpmac9: dpmac@9 { + dpmac9: ethernet@9 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x9>; + pcs-handle = <&pcs9>; }; - dpmac10: dpmac@a { + dpmac10: ethernet@a { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xa>; + pcs-handle = <&pcs10>; }; - dpmac11: dpmac@b { + dpmac11: ethernet@b { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xb>; + pcs-handle = <&pcs11>; }; - dpmac12: dpmac@c { + dpmac12: ethernet@c { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xc>; + pcs-handle = <&pcs12>; }; - dpmac13: dpmac@d { + dpmac13: ethernet@d { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xd>; + pcs-handle = <&pcs13>; }; - dpmac14: dpmac@e { + dpmac14: ethernet@e { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xe>; + pcs-handle = <&pcs14>; }; - dpmac15: dpmac@f { + dpmac15: ethernet@f { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xf>; + pcs-handle = <&pcs15>; }; - dpmac16: dpmac@10 { + dpmac16: ethernet@10 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x10>; + pcs-handle = <&pcs16>; }; }; }; -- cgit v1.2.3 From f94cfe322f3c9f15e8b0fd0e75bb3acdf5927b84 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:54 +0200 Subject: arm64: dts: lx2160a: add PCS MDIO and PCS PHY nodes Add PCS MDIO nodes for the internal MDIO buses on the LX2160A, along with their internal PCS PHYs, which will be used when the DPMAC is in TYPE_PHY mode. Also, rename the dpmac@x nodes to ethernet@x in order to be compliant with the naming convention used by ethernet controllers. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 288 +++++++++++++++++++++++-- 1 file changed, 270 insertions(+), 18 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 83072da6f6c6..197397777c83 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1305,6 +1305,240 @@ status = "disabled"; }; + pcs_mdio1: mdio@8c07000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c07000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs1: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio2: mdio@8c0b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs2: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio3: mdio@8c0f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs3: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio4: mdio@8c13000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c13000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs4: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio5: mdio@8c17000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c17000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs5: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio6: mdio@8c1b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs6: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio7: mdio@8c1f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs7: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio8: mdio@8c23000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c23000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs8: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio9: mdio@8c27000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c27000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs9: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio10: mdio@8c2b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c2b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs10: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio11: mdio@8c2f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c2f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs11: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio12: mdio@8c33000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c33000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs12: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio13: mdio@8c37000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c37000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs13: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio14: mdio@8c3b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c3b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs14: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio15: mdio@8c3f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c3f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs15: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio16: mdio@8c43000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c43000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs16: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio17: mdio@8c47000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c47000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs17: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio18: mdio@8c4b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c4b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs18: ethernet-phy@0 { + reg = <0>; + }; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, @@ -1330,94 +1564,112 @@ #address-cells = <1>; #size-cells = <0>; - dpmac1: dpmac@1 { + dpmac1: ethernet@1 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x1>; + pcs-handle = <&pcs1>; }; - dpmac2: dpmac@2 { + dpmac2: ethernet@2 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x2>; + pcs-handle = <&pcs2>; }; - dpmac3: dpmac@3 { + dpmac3: ethernet@3 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x3>; + pcs-handle = <&pcs3>; }; - dpmac4: dpmac@4 { + dpmac4: ethernet@4 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x4>; + pcs-handle = <&pcs4>; }; - dpmac5: dpmac@5 { + dpmac5: ethernet@5 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x5>; + pcs-handle = <&pcs5>; }; - dpmac6: dpmac@6 { + dpmac6: ethernet@6 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x6>; + pcs-handle = <&pcs6>; }; - dpmac7: dpmac@7 { + dpmac7: ethernet@7 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x7>; + pcs-handle = <&pcs7>; }; - dpmac8: dpmac@8 { + dpmac8: ethernet@8 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x8>; + pcs-handle = <&pcs8>; }; - dpmac9: dpmac@9 { + dpmac9: ethernet@9 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x9>; + pcs-handle = <&pcs9>; }; - dpmac10: dpmac@a { + dpmac10: ethernet@a { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xa>; + pcs-handle = <&pcs10>; }; - dpmac11: dpmac@b { + dpmac11: ethernet@b { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xb>; + pcs-handle = <&pcs11>; }; - dpmac12: dpmac@c { + dpmac12: ethernet@c { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xc>; + pcs-handle = <&pcs12>; }; - dpmac13: dpmac@d { + dpmac13: ethernet@d { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xd>; + pcs-handle = <&pcs13>; }; - dpmac14: dpmac@e { + dpmac14: ethernet@e { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xe>; + pcs-handle = <&pcs14>; }; - dpmac15: dpmac@f { + dpmac15: ethernet@f { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xf>; + pcs-handle = <&pcs15>; }; - dpmac16: dpmac@10 { + dpmac16: ethernet@10 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x10>; + pcs-handle = <&pcs16>; }; - dpmac17: dpmac@11 { + dpmac17: ethernet@11 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x11>; + pcs-handle = <&pcs17>; }; - dpmac18: dpmac@12 { + dpmac18: ethernet@12 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x12>; + pcs-handle = <&pcs18>; }; }; }; -- cgit v1.2.3 From f0f3531f3a540b7d6effa451873b0fefd073e182 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:55 +0200 Subject: arm64: dts: lx2160ardb: add nodes for the AQR107 PHYs Annotate the EMDIO1 node and describe the 2 AQR107 PHYs found on the LX2160ARDB board. Also, add the necessary phy-handles for DPMACs 3 and 4 to their associated PHY. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 54fe8cd3a711..7723ad5efd37 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -35,6 +35,18 @@ status = "okay"; }; +&dpmac3 { + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; + managed = "in-band-status"; +}; + +&dpmac4 { + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; + managed = "in-band-status"; +}; + &dpmac17 { phy-handle = <&rgmii_phy1>; phy-connection-type = "rgmii-id"; @@ -61,6 +73,18 @@ reg = <0x2>; eee-broken-1000t; }; + + aquantia_phy1: ethernet-phy@4 { + /* AQR107 PHY */ + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x4>; + }; + + aquantia_phy2: ethernet-phy@5 { + /* AQR107 PHY */ + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x5>; + }; }; &esdhc0 { @@ -156,6 +180,14 @@ }; }; +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio4 { + status = "okay"; +}; + &sata0 { status = "okay"; }; -- cgit v1.2.3 From b6abb31375ededd7d87d5a9b117ee77ca9817fc1 Mon Sep 17 00:00:00 2001 From: Xiaowei Bao Date: Mon, 2 Nov 2020 13:44:17 +0800 Subject: arm64: dts: layerscape: Add PCIe EP node for ls1088a Add PCIe EP node for ls1088a to support EP mode. Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang Reviewed-by: Andrew Murray Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 ++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 9c9c323cc3cd..cfd341ee48bf 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -517,6 +517,17 @@ status = "disabled"; }; + pcie_ep1: pcie-ep@3400000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x20 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <24>; + num-ob-windows = <256>; + max-functions = /bits/ 8 <2>; + status = "disabled"; + }; + pcie2: pcie@3500000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ @@ -543,6 +554,16 @@ status = "disabled"; }; + pcie_ep2: pcie-ep@3500000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000 + 0x28 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + pcie3: pcie@3600000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ @@ -569,6 +590,16 @@ status = "disabled"; }; + pcie_ep3: pcie-ep@3600000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x00100000 + 0x30 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; -- cgit v1.2.3 From 71fa01d3a909446ca70c3b751f5a1124b2552329 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 2 Nov 2020 10:11:16 +0800 Subject: arm64: dts: imx8mq: Configure clock rate for audio plls Configure clock rate for audio plls. audio pll1 is used as parent clock for clocks that is multiple of 8kHz. audio pll2 is used as parent clock for clocks that is multiple of 11kHz. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 5e0e7d0f1bc4..49cc79246288 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -606,11 +606,25 @@ "clk_ext3", "clk_ext4"; assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, <&clk IMX8MQ_CLK_A53_CORE>, - <&clk IMX8MQ_CLK_NOC>; + <&clk IMX8MQ_CLK_NOC>, + <&clk IMX8MQ_CLK_AUDIO_AHB>, + <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, + <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, + <&clk IMX8MQ_AUDIO_PLL1>, + <&clk IMX8MQ_AUDIO_PLL2>; assigned-clock-rates = <0>, <0>, - <800000000>; + <800000000>, + <0>, + <0>, + <0>, + <786432000>, + <722534400>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_ARM_PLL_OUT>; + <&clk IMX8MQ_ARM_PLL_OUT>, + <0>, + <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_AUDIO_PLL1>, + <&clk IMX8MQ_AUDIO_PLL2>; }; src: reset-controller@30390000 { -- cgit v1.2.3 From 08a1a2e205e3a5159a9dcc2c0019e6f9c1e04f90 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 2 Nov 2020 10:11:17 +0800 Subject: arm64: dts: imx8mq-evk: Add spdif sound card support There are two spdif IP on imx8mq, spdif1 is for normal spdif device, spdif2 is for HDMI ARC interface. Enable these spdif sound card in this patch. Signed-off-by: Shengjiu Wang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 38 ++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 48 ++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 2418cca00bc5..e4250812586b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -87,6 +87,21 @@ clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; }; }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif2>; + spdif-in; + }; }; &A53_0 { @@ -336,6 +351,22 @@ status = "okay"; }; +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&spdif2 { + assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -467,6 +498,13 @@ >; }; + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 49cc79246288..a841a023e8e0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -793,6 +793,30 @@ ranges = <0x30800000 0x30800000 0x400000>, <0x08000000 0x08000000 0x10000000>; + spdif1: spdif@30810000 { + compatible = "fsl,imx35-spdif"; + reg = <0x30810000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ + <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ + <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MQ_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + ecspi1: spi@30820000 { #address-cells = <1>; #size-cells = <0>; @@ -862,6 +886,30 @@ status = "disabled"; }; + spdif2: spdif@308a0000 { + compatible = "fsl,imx35-spdif"; + reg = <0x308a0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ + <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ + <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MQ_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + sai2: sai@308b0000 { #sound-dai-cells = <0>; compatible = "fsl,imx8mq-sai"; -- cgit v1.2.3 From 3a7d56b3cdc90cbc1d854e0dbde4f2de83bbe6d7 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Mon, 2 Nov 2020 10:16:34 +0800 Subject: arm64: dts: imx8mp-evk: add CAN support Add CAN device node and pinctrl on i.MX8MP evk board. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 62 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 30 ++++++++++++++ 2 files changed, 92 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 908b92bb4dcd..b10dce8767a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -33,6 +33,28 @@ <0x1 0x00000000 0 0xc0000000>; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -45,6 +67,20 @@ }; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "disabled";/* can2 pin conflict with pdm */ +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; @@ -144,6 +180,32 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ + >; + }; + pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 479312293036..ecccfbb4f5ad 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -552,6 +552,36 @@ status = "disabled"; }; + flexcan1: can@308c0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308c0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN1_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&gpr 0x10 4>; + status = "disabled"; + }; + + flexcan2: can@308d0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308d0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN2_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&gpr 0x10 5>; + status = "disabled"; + }; + crypto: crypto@30900000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; -- cgit v1.2.3 From 4d583263f4c9e6aded6f56f4963fa53f747c83c5 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Mon, 2 Nov 2020 10:25:25 +0800 Subject: arm64: dts: imx8mq-evk: add linux,autosuspend-period property for IR Add linux,autosuspend-period property for IR, details please refer to: commit ff1c9223b7b8 ("media: rc: gpio-ir-recv: add QoS support for cpuidle system") Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index e4250812586b..85b045253a0e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -57,6 +57,7 @@ gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ir>; + linux,autosuspend-period = <125>; }; wm8524: audio-codec { -- cgit v1.2.3 From 56e08dc3a62d27531fea16a92797573525ddf3f0 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Mon, 2 Nov 2020 10:25:26 +0800 Subject: arm64: dts: imx8mm-evk: add IR support Add IR support on i.MX8MM EVK board. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 469d5703250b..8c5aa2d8f4a0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -41,6 +41,14 @@ enable-active-high; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir>; + linux,autosuspend-period = <125>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; @@ -363,6 +371,12 @@ >; }; + pinctrl_ir: irgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + pinctrl_gpio_wlf: gpiowlfgrp { fsl,pins = < MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 -- cgit v1.2.3 From 29939851a633cd2be1a6e78e3349169a017d0f73 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Mon, 2 Nov 2020 10:25:27 +0800 Subject: arm64: dts: imx8mn-evk: add IR support Add IR support on i.MX8MN EVK board. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index fda890589a09..76d042a4cf09 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -38,6 +38,14 @@ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir>; + linux,autosuspend-period = <125>; + }; }; &fec1 { @@ -202,6 +210,12 @@ >; }; + pinctrl_ir: irgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 -- cgit v1.2.3 From bd5840df916dc57929af727ff99b63a93be096c6 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Sun, 8 Nov 2020 12:16:15 -0700 Subject: arm64: dts: imx: Fix imx8mm-kontron-n801x-s.dtb target While running 'make dtbs_install', the following error occurs: make[3]: *** No rule to make target 'rootfs/freescale/imx8mm-kontron-n801x-s.dts', needed by '__dtbs_install'. It should be .dtb, not .dts. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Nathan Chancellor Reviewed-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 876bf484bbe6..6f0777ee6cd6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -32,7 +32,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dts +dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb -- cgit v1.2.3 From d0570a575aa83116bd0f6a99c4de548af773d950 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 8 Nov 2020 19:51:05 +0100 Subject: arm64: dts: ls1028a: fix ENETC PTP clock input On the LS1028A the ENETC reference clock is connected to 4th HWA output, see Figure 7 "Clock subsystem block diagram". The PHC may run with a wrong frequency. ptp_qoriq_auto_config() will read the clock speed of the clock given in the device tree. It is likely that, on the reference board this wasn't noticed because both clocks have the same frequency. But this must not be always the case. Fix it. Fixes: 49401003e260 ("arm64: dts: fsl: ls1028a: add ENETC 1588 timer node") Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index ac17752ab3ec..ae5769cf4e95 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -952,7 +952,7 @@ ethernet@0,4 { compatible = "fsl,enetc-ptp"; reg = <0x000400 0 0 0 0>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen 2 3>; little-endian; fsl,extts-fifo; }; -- cgit v1.2.3 From 588b17eda1356e06efa4b888d0af02c80a2788f6 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 8 Nov 2020 19:51:06 +0100 Subject: arm64: dts: ls1028a: fix FlexSPI clock input On the LS1028A the FlexSPI clock is connected to the first HWA output, see Figure 7 "Clock subsystem block diagram". Fixes: c77fae5ba09a ("arm64: dts: ls1028a: Add FlexSPI support") Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index ae5769cf4e95..f166c6689452 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -309,7 +309,7 @@ <0x0 0x20000000 0x0 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; interrupts = ; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen 2 0>, <&clockgen 2 0>; clock-names = "fspi_en", "fspi"; status = "disabled"; }; -- cgit v1.2.3 From f90931aeefe3f3edd2556806bbe59df3a5a9790d Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 15 Nov 2020 23:53:14 +0100 Subject: arm64: dts: ls1028a: add optee node Add the optee node which can either be enabled by a specific board or by the bootloader. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index f166c6689452..7cb603497d65 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -90,6 +90,14 @@ clocks = <&osc_27m>; }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; + reboot { compatible ="syscon-reboot"; regmap = <&rst>; -- cgit v1.2.3 From 91ab1c12285c9999afe56c09aa296d8b96862976 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 15 Nov 2020 23:54:35 +0100 Subject: arm64: dts: freescale: sl28: combine SPI MTD partitions The upstream port, doesn't really follow the vendor partitioning. The bootloader partition has one U-Boot FIT image containing all needed bits and pieces. Even today the bootloader is already larger than the current "bootloader" partition. Thus, fold all the partitions into one and keep the environment one. The latter is still valid. We keep the failsafe partitions because the first half of the SPI flash is preinstalled by the vendor and immutable. Fixes: 815364d0424e ("arm64: dts: freescale: add Kontron sl28 support") Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index 17a2f5dacc3f..6b1ec50d6a65 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -158,20 +158,10 @@ }; partition@210000 { - reg = <0x210000 0x0f0000>; + reg = <0x210000 0x1d0000>; label = "bootloader"; }; - partition@300000 { - reg = <0x300000 0x040000>; - label = "DP firmware"; - }; - - partition@340000 { - reg = <0x340000 0x0a0000>; - label = "trusted firmware"; - }; - partition@3e0000 { reg = <0x3e0000 0x020000>; label = "bootloader environment"; -- cgit v1.2.3 From 64d81113931b3f73ce2f5783c1032892c5046f93 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Tue, 17 Nov 2020 11:43:04 +0800 Subject: arm64: dts: freescale: update calibration table for TMU module Update the calibration table to make the temperature more accurate. Three platforms have been updated: ls1012a, ls1043a and ls1046a. Signed-off-by: Yuantian Tang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 63 +++++++++++---------- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 78 ++++++++++++++------------ arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 72 +++++++++++++----------- 3 files changed, 112 insertions(+), 101 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index a168e06ac50a..626b709d1fb9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -291,43 +291,46 @@ compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = <0 33 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = <0x00000000 0x00000026 - 0x00000001 0x0000002d + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>; + fsl,tmu-calibration = <0x00000000 0x00000025 + 0x00000001 0x0000002c 0x00000002 0x00000032 0x00000003 0x00000039 0x00000004 0x0000003f 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 - - 0x00010000 0x00000025 - 0x00010001 0x0000002c + 0x00000006 0x0000004c + 0x00000007 0x00000053 + 0x00000008 0x00000059 + 0x00000009 0x0000005f + 0x0000000a 0x00000066 + 0x0000000b 0x0000006c + + 0x00010000 0x00000026 + 0x00010001 0x0000002d 0x00010002 0x00000035 0x00010003 0x0000003d 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 - - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d - - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; + 0x00010005 0x0000004d + 0x00010006 0x00000055 + 0x00010007 0x0000005d + 0x00010008 0x00000065 + 0x00010009 0x0000006d + + 0x00020000 0x00000026 + 0x00020001 0x00000030 + 0x00020002 0x0000003a + 0x00020003 0x00000044 + 0x00020004 0x0000004e + 0x00020005 0x00000059 + 0x00020006 0x00000063 + + 0x00030000 0x00000014 + 0x00030001 0x00000021 + 0x00030002 0x0000002e + 0x00030003 0x0000003a + 0x00030004 0x00000047 + 0x00030005 0x00000053 + 0x00030006 0x00000060>; big-endian; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index d5d219311161..bbae4b353d3f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -403,43 +403,47 @@ compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = <0 33 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 - - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 - - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d - - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; + fsl,tmu-calibration = <0x00000000 0x00000023 + 0x00000001 0x0000002a + 0x00000002 0x00000031 + 0x00000003 0x00000037 + 0x00000004 0x0000003e + 0x00000005 0x00000044 + 0x00000006 0x0000004b + 0x00000007 0x00000051 + 0x00000008 0x00000058 + 0x00000009 0x0000005e + 0x0000000a 0x00000065 + 0x0000000b 0x0000006b + + 0x00010000 0x00000023 + 0x00010001 0x0000002b + 0x00010002 0x00000033 + 0x00010003 0x0000003b + 0x00010004 0x00000043 + 0x00010005 0x0000004b + 0x00010006 0x00000054 + 0x00010007 0x0000005c + 0x00010008 0x00000064 + 0x00010009 0x0000006c + + 0x00020000 0x00000021 + 0x00020001 0x0000002c + 0x00020002 0x00000036 + 0x00020003 0x00000040 + 0x00020004 0x0000004b + 0x00020005 0x00000055 + 0x00020006 0x0000005f + + 0x00030000 0x00000013 + 0x00030001 0x0000001d + 0x00030002 0x00000028 + 0x00030003 0x00000032 + 0x00030004 0x0000003d + 0x00030005 0x00000047 + 0x00030006 0x00000052 + 0x00030007 0x0000005c>; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 1fa39bacff4b..025e1f587662 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -400,45 +400,49 @@ compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = <0 33 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; fsl,tmu-calibration = /* Calibration data group 1 */ - <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 + <0x00000000 0x00000023 + 0x00000001 0x00000029 + 0x00000002 0x0000002f + 0x00000003 0x00000036 + 0x00000004 0x0000003c + 0x00000005 0x00000042 + 0x00000006 0x00000049 + 0x00000007 0x0000004f + 0x00000008 0x00000055 + 0x00000009 0x0000005c + 0x0000000a 0x00000062 + 0x0000000b 0x00000068 /* Calibration data group 2 */ - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 + 0x00010000 0x00000022 + 0x00010001 0x0000002a + 0x00010002 0x00000032 + 0x00010003 0x0000003a + 0x00010004 0x00000042 + 0x00010005 0x0000004a + 0x00010006 0x00000052 + 0x00010007 0x0000005a + 0x00010008 0x00000062 + 0x00010009 0x0000006a /* Calibration data group 3 */ - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d + 0x00020000 0x00000021 + 0x00020001 0x0000002b + 0x00020002 0x00000035 + 0x00020003 0x0000003e + 0x00020004 0x00000048 + 0x00020005 0x00000052 + 0x00020006 0x0000005c /* Calibration data group 4 */ - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; + 0x00030000 0x00000011 + 0x00030001 0x0000001a + 0x00030002 0x00000024 + 0x00030003 0x0000002e + 0x00030004 0x00000038 + 0x00030005 0x00000042 + 0x00030006 0x0000004c + 0x00030007 0x00000056>; big-endian; #thermal-sensor-cells = <1>; }; -- cgit v1.2.3 From 83afd0b3e0279107ff06945bad4b63a1fbe83224 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Wed, 11 Nov 2020 12:15:45 +0300 Subject: arm64: dts: marvell: cp11x: Harmonize xHCI DT nodes name In accordance with the Generic xHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-xhci"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index ec27294f097b..994a2fce449a 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -275,7 +275,7 @@ }; }; - CP11X_LABEL(usb3_0): usb3@500000 { + CP11X_LABEL(usb3_0): usb@500000 { compatible = "marvell,armada-8k-xhci", "generic-xhci"; reg = <0x500000 0x4000>; @@ -287,7 +287,7 @@ status = "disabled"; }; - CP11X_LABEL(usb3_1): usb3@510000 { + CP11X_LABEL(usb3_1): usb@510000 { compatible = "marvell,armada-8k-xhci", "generic-xhci"; reg = <0x510000 0x4000>; -- cgit v1.2.3 From da57203dc7fd556fbb3f0ec7d7d7c0b0e893b386 Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Tue, 10 Nov 2020 16:38:31 +0100 Subject: arm64: dts: mcbin-singleshot: add heartbeat LED With board revision 1.3, SolidRun moved the power LED to the middle of the board. In old place of power LED a GPIO controllable heartbeat LED was added. This commit only touches Single Shot variant, since only this variant is all revision 1.3. Reported-by: Alexandra Alth Signed-off-by: Tomasz Maciej Nowak Signed-off-by: Gregory CLEMENT --- .../dts/marvell/armada-8040-mcbin-singleshot.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts index 2e6832d02a59..411d20064271 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts @@ -5,6 +5,8 @@ * Device Tree file for MACCHIATOBin Armada 8040 community board platform */ +#include + #include "armada-8040-mcbin.dtsi" / { @@ -12,6 +14,19 @@ compatible = "marvell,armada8040-mcbin-singleshot", "marvell,armada8040-mcbin", "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&cp0_led18_pins>; + pinctrl-names = "default"; + + led18 { + gpios = <&cp0_gpio2 1 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + }; + }; }; &cp0_eth0 { @@ -27,3 +42,10 @@ managed = "in-band-status"; sfp = <&sfp_eth1>; }; + +&cp0_pinctrl { + cp0_led18_pins: led18-pins { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; +}; -- cgit v1.2.3 From f43cadef2df260101497a6aace05e24201f00202 Mon Sep 17 00:00:00 2001 From: Tomasz Nowicki Date: Thu, 5 Nov 2020 12:26:02 +0100 Subject: arm64: dts: marvell: keep SMMU disabled by default for Armada 7040 and 8040 FW has to configure devices' StreamIDs so that SMMU is able to lookup context and do proper translation later on. For Armada 7040 & 8040 and publicly available FW, most of the devices are configured properly, but some like ap_sdhci0, PCIe, NIC still remain unassigned which results in SMMU faults about unmatched StreamID (assuming ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=y). Since there is dependency on custom FW let SMMU be disabled by default. People who still willing to use SMMU need to enable manually and use ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=n (or via kernel command line) with extra caution. Fixes: 83a3545d9c37 ("arm64: dts: marvell: add SMMU support") Cc: # 5.9+ Signed-off-by: Tomasz Nowicki Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-7040.dtsi | 4 ---- arch/arm64/boot/dts/marvell/armada-8040.dtsi | 4 ---- 2 files changed, 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi index 7a3198cd7a07..2f440711d21d 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi @@ -15,10 +15,6 @@ "marvell,armada-ap806"; }; -&smmu { - status = "okay"; -}; - &cp0_pcie0 { iommu-map = <0x0 &smmu 0x480 0x20>, diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi index 79e8ce59baa8..22c2d6ebf381 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi @@ -15,10 +15,6 @@ "marvell,armada-ap806"; }; -&smmu { - status = "okay"; -}; - &cp0_pcie0 { iommu-map = <0x0 &smmu 0x480 0x20>, -- cgit v1.2.3 From a2081c09d7410c3e55d902a09602b833dc96c58a Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 16 Nov 2020 13:33:03 +0100 Subject: arm64: dts: armada-3720-turris-mox: add 3W power capability to SFP cage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add maximum-power-milliwatt = 3000 to SFP node of Turris MOX. Signed-off-by: Marek Behún Fixes: 7109d817db2e ("arm64: dts: marvell: add DTS for Turris Mox") Cc: Gregory CLEMENT Cc: Andrew Lunn Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index bf76ebe46379..f5ec3b644769 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -102,6 +102,7 @@ mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; /* enabled by U-Boot if SFP module is present */ status = "disabled"; -- cgit v1.2.3 From 97a0115cd96a173369ef30eee2290184921b3f24 Mon Sep 17 00:00:00 2001 From: Shunqian Zheng Date: Tue, 20 Oct 2020 16:38:49 -0300 Subject: arm64: dts: rockchip: add isp0 node for rk3399 RK3399 has two ISPs, but only isp0 was tested. Add isp0 node in rk3399 dtsi Verified with: make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/media/rockchip-isp1.yaml Signed-off-by: Shunqian Zheng Signed-off-by: Jacob Chen Signed-off-by: Helen Koike Link: https://lore.kernel.org/r/20201020193850.1460644-9-helen.koike@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 1aa52ec938a1..248de7b5d724 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1723,6 +1723,32 @@ status = "disabled"; }; + isp0: isp0@ff910000 { + compatible = "rockchip,rk3399-cif-isp"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_ISP0>, + <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0_WRAPPER>; + clock-names = "isp", "aclk", "hclk"; + iommus = <&isp0_mmu>; + phys = <&mipi_dphy_rx0>; + phy-names = "dphy"; + power-domains = <&power RK3399_PD_ISP0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + isp0_mmu: iommu@ff914000 { compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; -- cgit v1.2.3 From ef098edc9c245dd1c150001e22c78e6a3ffd7ff8 Mon Sep 17 00:00:00 2001 From: Eddie Cai Date: Tue, 20 Oct 2020 16:38:50 -0300 Subject: arm64: dts: rockchip: add isp and sensors for Scarlet Enable ISP and camera sensor ov2685 and ov5695 for Scarlet Chromebook Verified with: make ARCH=arm64 dtbs_check Signed-off-by: Shunqian Zheng Signed-off-by: Eddie Cai Signed-off-by: Tomasz Figa Signed-off-by: Helen Koike Reviewed-by: Tomasz Figa Link: https://lore.kernel.org/r/20201020193850.1460644-10-helen.koike@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index 60cd1c18cd4e..beee5fbb3443 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -296,6 +296,52 @@ camera: &i2c7 { /* 24M mclk is shared between world and user cameras */ pinctrl-0 = <&i2c7_xfer &test_clkout1>; + + /* Rear-facing camera */ + wcam: camera@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&wcam_rst>; + + clocks = <&cru SCLK_TESTCLKOUT1>; + clock-names = "xvclk"; + + avdd-supply = <&pp2800_cam>; + dvdd-supply = <&pp1250_cam>; + dovdd-supply = <&pp1800_s0>; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + + port { + wcam_out: endpoint { + remote-endpoint = <&mipi_in_wcam>; + data-lanes = <1 2>; + }; + }; + }; + + /* Front-facing camera */ + ucam: camera@3c { + compatible = "ovti,ov2685"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&ucam_rst>; + + clocks = <&cru SCLK_TESTCLKOUT1>; + clock-names = "xvclk"; + + avdd-supply = <&pp2800_cam>; + dovdd-supply = <&pp1800_s0>; + dvdd-supply = <&pp1800_s0>; + reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1>; + }; + }; + }; }; &cdn_dp { @@ -353,10 +399,38 @@ camera: &i2c7 { gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ }; +&isp0 { + status = "okay"; + + ports { + port@0 { + mipi_in_wcam: endpoint@0 { + reg = <0>; + remote-endpoint = <&wcam_out>; + data-lanes = <1 2>; + }; + + mipi_in_ucam: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out>; + data-lanes = <1>; + }; + }; + }; +}; + +&isp0_mmu { + status = "okay"; +}; + &max98357a { sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; }; +&mipi_dphy_rx0 { + status = "okay"; +}; + &mipi_dsi { status = "okay"; clock-master; -- cgit v1.2.3 From 3e482859f1ef73244849ea56e08933b2a8d21882 Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Thu, 19 Nov 2020 10:52:32 -0500 Subject: dts: qcom: sdm845: Add dt entries to support crypto engine. Add crypto engine (CE) and CE BAM related nodes and definitions to "sdm845.dtsi". Signed-off-by: Thara Gopinath Link: https://lore.kernel.org/r/20201119155233.3974286-6-thara.gopinath@linaro.org [bjorn: Replaced RPMH_CE_CLK constant, for now] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 256a698745ac..de542862748d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2140,6 +2140,36 @@ }; }; + cryptobam: dma@1dc4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = ; + clocks = <&rpmhcc 15>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely = <1>; + iommus = <&apps_smmu 0x704 0x1>, + <&apps_smmu 0x706 0x1>, + <&apps_smmu 0x714 0x1>, + <&apps_smmu 0x716 0x1>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,crypto-v5.4"; + reg = <0 0x01dfa000 0 0x6000>; + clocks = <&gcc GCC_CE1_AHB_CLK>, + <&gcc GCC_CE1_AHB_CLK>, + <&rpmhcc 15>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 6>, <&cryptobam 7>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x704 0x1>, + <&apps_smmu 0x706 0x1>, + <&apps_smmu 0x714 0x1>, + <&apps_smmu 0x716 0x1>; + }; + ipa: ipa@1e40000 { compatible = "qcom,sdm845-ipa"; -- cgit v1.2.3 From 683227e5a34e4ca40bb13bca47952b48516ea87d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 24 Nov 2020 12:44:14 -0600 Subject: arm64: dts: qcom: c630: Re-enable apps_smmu Re-enable the apps_smmu now that the arm-smmu driver supports stream mapping handoff from firmware. Tested-by: Steev Klimaszewski Acked-by: Shawn Guo Link: https://lore.kernel.org/r/20201124184414.380796-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index d03ca3190746..f5b98845fa90 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -232,11 +232,6 @@ }; }; -&apps_smmu { - /* TODO: Figure out how to survive booting with this enabled */ - status = "disabled"; -}; - &cdsp_pas { firmware-name = "qcom/LENOVO/81JL/qccdsp850.mbn"; status = "okay"; -- cgit v1.2.3 From 71b83b74cca3f6b583b7c343896be3922ea80466 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 25 Nov 2020 00:08:38 -0600 Subject: arm64: dts: qcom: c630: Expose LID events The LID state can be read from GPIO 124 and the "tablet mode" from GPIO 95, expose these to the system using gpio-keys and mark the falling edge of the LID state as a wakeup-source - to wake the system from suspend. Tested-by: Steev Klimaszewski Acked-by: Shawn Guo Link: https://lore.kernel.org/r/20201125060838.165576-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index f5b98845fa90..3850e74ed653 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -8,6 +8,8 @@ /dts-v1/; #include +#include +#include #include #include #include @@ -21,6 +23,27 @@ aliases { hsuart0 = &uart6; }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&lid_pin_active>, <&mode_pin_active>; + + lid { + gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + + mode { + gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + linux,code = ; + }; + }; }; &adsp_pas { @@ -456,6 +479,22 @@ bias-pull-down; drive-strength = <2>; }; + + lid_pin_active: lid-pin { + pins = "gpio124"; + function = "gpio"; + + input-enable; + bias-disable; + }; + + mode_pin_active: mode-pin { + pins = "gpio95"; + function = "gpio"; + + input-enable; + bias-disable; + }; }; &uart6 { -- cgit v1.2.3 From 05b801afb7d7eb569bfe5bdf9c192e2a5306473a Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 5 Nov 2020 15:52:11 +0200 Subject: arm64: dts: sdm845: Add interconnect properties for QUP Add the interconnects DT property to describe the ports for GENI QUPs on the sdm845 platform. Signed-off-by: Georgi Djakov Link: https://lore.kernel.org/r/20201105135211.7160-3-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 160 +++++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index de542862748d..bcf888381f14 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1124,6 +1124,8 @@ #address-cells = <2>; #size-cells = <2>; ranges; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core"; status = "disabled"; i2c0: i2c@880000 { @@ -1138,6 +1140,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1151,6 +1157,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1164,6 +1173,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1179,6 +1191,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1192,6 +1208,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1205,6 +1224,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1220,6 +1242,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1233,6 +1259,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1246,6 +1275,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1261,6 +1293,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1274,6 +1310,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1287,6 +1326,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1302,6 +1344,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1315,6 +1361,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1328,6 +1377,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1343,6 +1395,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1356,6 +1412,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1369,6 +1428,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1384,6 +1446,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1397,6 +1463,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1410,6 +1479,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1438,6 +1510,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1451,6 +1526,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; @@ -1465,6 +1543,8 @@ #address-cells = <2>; #size-cells = <2>; ranges; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core"; status = "disabled"; i2c8: i2c@a80000 { @@ -1479,6 +1559,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1492,6 +1576,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1505,6 +1592,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1520,6 +1610,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1533,6 +1627,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1546,6 +1643,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1561,6 +1661,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1574,6 +1678,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1587,6 +1694,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1602,6 +1712,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1615,6 +1729,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1628,6 +1745,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1643,6 +1763,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1656,6 +1780,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1669,6 +1796,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1684,6 +1814,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1697,6 +1831,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1710,6 +1847,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1725,6 +1865,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1738,6 +1882,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1751,6 +1898,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1767,6 +1917,10 @@ power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; }; spi15: spi@a9c000 { @@ -1779,6 +1933,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1792,6 +1949,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; -- cgit v1.2.3 From 74ab8ccfb8f3133acf8b2a2a7bcfba9c1710960d Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 30 Nov 2020 16:31:45 +0530 Subject: arm64: dts: ipq6018: Add the QPIC peripheral nodes Add the QPIC BAM and QPIC NAND controller support and enable the same in board DTS file. Co-developed-by: Anusha Canchi Ramachandra Rao Signed-off-by: Anusha Canchi Ramachandra Rao Signed-off-by: Kathiravan T Link: https://lore.kernel.org/r/1606734105-12414-2-git-send-email-kathirav@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 16 +++++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 41 ++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index e8eaa958c199..99cefe88f6f2 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -62,3 +62,19 @@ bias-pull-down; }; }; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index a94dac76bf3f..a366a05128c2 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -231,6 +231,17 @@ drive-strength = <8>; bias-pull-down; }; + + qpic_pins: qpic-pins { + pins = "gpio1", "gpio3", "gpio4", + "gpio5", "gpio6", "gpio7", + "gpio8", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", + "gpio15", "gpio17"; + function = "qpic_pad"; + drive-strength = <8>; + bias-disable; + }; }; gcc: gcc@1800000 { @@ -332,6 +343,36 @@ status = "disabled"; }; + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x07984000 0x0 0x1a000>; + interrupts = ; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "iface_clk", "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + qpic_nand: nand@79b0000 { + compatible = "qcom,ipq6018-nand"; + reg = <0x0 0x079b0000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + pinctrl-0 = <&qpic_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; -- cgit v1.2.3 From 96ddfbf46a35d75cd496efbd23d714271c0c0d46 Mon Sep 17 00:00:00 2001 From: Ajit Pandey Date: Fri, 18 Sep 2020 23:03:46 +0530 Subject: arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driver Add the I2S controller node to sc7180 dtsi. Add pinmux for primary and secondary I2S. Reviewed-by: Srinivas Kandagatla Signed-off-by: Ajit Pandey Signed-off-by: Cheng-Yi Chiang Signed-off-by: V Sujith Kumar Reddy Signed-off-by: Srinivasa Rao Mandadapu Link: https://lore.kernel.org/r/1600450426-14063-1-git-send-email-srivasam@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 69 ++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index c7c701e32b9a..22b832fc62e3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1854,6 +1854,45 @@ }; }; + sec_mi2s_active: sec-mi2s-active { + pinmux { + pins = "gpio49", "gpio50", "gpio51"; + function = "mi2s_1"; + }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_active: pri-mi2s-active { + pinmux { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "mi2s_0"; + }; + + pinconf { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_mclk_active: pri-mi2s-mclk-active { + pinmux { + pins = "gpio57"; + function = "lpass_ext"; + }; + + pinconf { + pins = "gpio57"; + drive-strength = <8>; + bias-pull-up; + }; + }; + sdc1_on: sdc1-on { pinconf-clk { pins = "sdc1_clk"; @@ -3515,6 +3554,36 @@ #power-domain-cells = <1>; }; + lpass_cpu: lpass@62f00000 { + compatible = "qcom,sc7180-lpass-cpu"; + + reg = <0 0x62f00000 0 0x29000>; + reg-names = "lpass-lpaif"; + + iommus = <&apps_smmu 0x1020 0>; + + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, + <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, + <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, + <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, + <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, + <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; + + clock-names = "pcnoc-sway-clk", "audio-core", + "mclk0", "pcnoc-mport-clk", + "mi2s-bit-clk0", "mi2s-bit-clk1"; + + + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + interrupts = ; + interrupt-names = "lpass-irq-lpaif"; + }; + lpass_hm: clock-controller@63000000 { compatible = "qcom,sc7180-lpasshm"; reg = <0 0x63000000 0 0x28>; -- cgit v1.2.3 From 11d0e4f281565ef757479764ce7fd8d35eeb01b0 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 30 Nov 2020 10:59:24 -0600 Subject: arm64: dts: qcom: c630: Polish i2c-hid devices The numbering of the i2c busses differs from ACPI and a number of typos was made in the original patch. Further more the irq flags for the various resources was not correct and i2c3 only has one of the two client devices active in any one device. Also label the various devices, for easier comparison with the ACPI tables. Tested-by: Steev Klimaszewski Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Link: https://lore.kernel.org/r/20201130165924.319708-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 31 +++++++++++++--------- 1 file changed, 18 insertions(+), 13 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 3850e74ed653..f8a371078a08 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -282,23 +282,28 @@ status = "okay"; clock-frequency = <400000>; - hid@15 { + tsel: hid@15 { compatible = "hid-over-i2c"; reg = <0x15>; hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>; + interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_hid_active>; }; - hid@2c { + tsc2: hid@2c { compatible = "hid-over-i2c"; reg = <0x2c>; hid-descr-addr = <0x20>; - interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>; + interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&i2c2_hid_active>; + pinctrl-0 = <&i2c3_hid_active>; + + status = "disabled"; }; }; @@ -306,15 +311,15 @@ status = "okay"; clock-frequency = <400000>; - hid@10 { + tsc1: hid@10 { compatible = "hid-over-i2c"; reg = <0x10>; hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&tlmm 125 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hid_active>; + pinctrl-0 = <&i2c5_hid_active>; }; }; @@ -322,7 +327,7 @@ status = "okay"; clock-frequency = <400000>; - hid@5c { + ecsh: hid@5c { compatible = "hid-over-i2c"; reg = <0x5c>; hid-descr-addr = <0x1>; @@ -330,7 +335,7 @@ interrupts-extended = <&tlmm 92 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&i2c12_hid_active>; + pinctrl-0 = <&i2c11_hid_active>; }; }; @@ -444,7 +449,7 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - i2c2_hid_active: i2c2-hid-active { + i2c3_hid_active: i2c2-hid-active { pins = <37>; function = "gpio"; @@ -453,7 +458,7 @@ drive-strength = <2>; }; - i2c6_hid_active: i2c6-hid-active { + i2c5_hid_active: i2c5-hid-active { pins = <125>; function = "gpio"; @@ -462,7 +467,7 @@ drive-strength = <2>; }; - i2c12_hid_active: i2c12-hid-active { + i2c11_hid_active: i2c11-hid-active { pins = <92>; function = "gpio"; -- cgit v1.2.3 From f55d373f7953909160cb4c1398f62123cdbe7650 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 30 Nov 2020 11:00:28 -0600 Subject: arm64: dts: qcom: c630: Fix pinctrl pins properties The "pins" property takes an array of pin _names_, not pin numbers. Fix this. Tested-by: Steev Klimaszewski Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Link: https://lore.kernel.org/r/20201130170028.319798-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index f8a371078a08..44fc5aaaf1c6 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -450,7 +450,7 @@ gpio-reserved-ranges = <0 4>, <81 4>; i2c3_hid_active: i2c2-hid-active { - pins = <37>; + pins = "gpio37"; function = "gpio"; input-enable; @@ -459,7 +459,7 @@ }; i2c5_hid_active: i2c5-hid-active { - pins = <125>; + pins = "gpio125"; function = "gpio"; input-enable; @@ -468,7 +468,7 @@ }; i2c11_hid_active: i2c11-hid-active { - pins = <92>; + pins = "gpio92"; function = "gpio"; input-enable; @@ -477,7 +477,7 @@ }; wcd_intr_default: wcd_intr_default { - pins = <54>; + pins = "gpio54"; function = "gpio"; input-enable; -- cgit v1.2.3 From 956e9c85f47bfe874d58d96c85471f2e2ebae626 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 27 Nov 2020 21:42:31 -0600 Subject: arm64: dts: qcom: c630: Define eDP bridge and panel The Lenovo Yoga C630 drives the Boe NV133FHM-N61 eDP display from DSI using a TI SN65DSI86 bridge chip on I2C 10. Define the bridge and eDP panel and enable the display blocks. Tested-by: Steev Klimaszewski Acked-by: Shawn Guo Link: https://lore.kernel.org/r/20201128034231.89750-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 100 +++++++++++++++++++++ 1 file changed, 100 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 44fc5aaaf1c6..13fdd02cffe6 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -44,6 +44,26 @@ linux,code = ; }; }; + + panel { + compatible = "boe,nv133fhm-n61"; + no-hpd; + + ports { + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; + + sn65dsi86_refclk: sn65dsi86-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + + clock-frequency = <19200000>; + }; }; &adsp_pas { @@ -260,6 +280,25 @@ status = "okay"; }; +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l26a_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&sn65dsi86_in_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l1a_0p875>; +}; + &gcc { protected-clocks = , , @@ -323,6 +362,45 @@ }; }; +&i2c10 { + status = "okay"; + clock-frequency = <400000>; + + sn65dsi86: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&sn65dsi86_pin_active>; + + enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&vreg_l14a_1p88>; + vccio-supply = <&vreg_l14a_1p88>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in_a: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + }; +}; + &i2c11 { status = "okay"; clock-frequency = <400000>; @@ -339,10 +417,26 @@ }; }; +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &mss_pil { firmware-name = "qcom/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/LENOVO/81JL/qcdsp2850.mbn"; }; +&qup_i2c10_default { + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; +}; + &qup_i2c12_default { drive-strength = <2>; bias-disable; @@ -449,6 +543,12 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; + sn65dsi86_pin_active: sn65dsi86-enable { + pins = "gpio96"; + drive-strength = <2>; + bias-disable; + }; + i2c3_hid_active: i2c2-hid-active { pins = "gpio37"; function = "gpio"; -- cgit v1.2.3 From 287eb2be4037c3d8d96b5d9490fa0e695e4553b9 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 16 Nov 2020 06:41:47 +0000 Subject: arm64: dts: meson: enable rtc node on Khadas VIM1/VIM2 boards Enable the rtc node on VIM1/VIM2 boards so users can simply attach a power cell and use the on-board RTC without modifying the device-tree. Cold boot with no cell attached is gracefully handled: VIM2:~ # dmesg | grep rtc [ 7.716150] rtc-hym8563 1-0051: no valid clock/calendar values available [ 7.716957] rtc-hym8563 1-0051: registered as rtc0 [ 7.729850] rtc-hym8563 1-0051: no valid clock/calendar values available [ 7.729877] rtc-hym8563 1-0051: hctosys: unable to read the hardware clock [ 8.126768] rtc-hym8563 1-0051: no valid clock/calendar values available Warm boot (and any boot with cell attached) recalls stored values resulting in consistently faster (re)boot times: VIM2:~ # dmesg | grep rtc [ 7.441671] rtc-hym8563 1-0051: registered as rtc0 [ 7.442663] rtc-hym8563 1-0051: setting system clock to 2020-11-16T05:49:59 UTC (1605505799) Suggested-by: Artem Lapkin Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201116064147.12062-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 3 +-- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 8bcdffdf55d0..638a5992d760 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -97,8 +97,7 @@ pinctrl-names = "default"; rtc: rtc@51 { - /* has to be enabled manually when a battery is connected: */ - status = "disabled"; + status = "okay"; compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index bff8ec2c1c70..da000c10b945 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -228,8 +228,7 @@ pinctrl-names = "default"; rtc: rtc@51 { - /* has to be enabled manually when a battery is connected: */ - status = "disabled"; + status = "okay"; compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; -- cgit v1.2.3 From 78a6dcb52736da4d54e0b42788a4c5f13da9a8e1 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 20 Nov 2020 16:21:30 +0100 Subject: arm64: dts: meson-axg: add PWRC node This adds the power controller PWRC node and the corresponding ethernet power domain. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201120152131.3918814-2-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 42 ++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 724ee179b316..fed9e6edbfa9 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { compatible = "amlogic,meson-axg"; @@ -229,6 +230,7 @@ tx-fifo-depth = <2048>; resets = <&reset RESET_ETHERNET>; reset-names = "stmmaceth"; + power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>; status = "disabled"; }; @@ -1159,6 +1161,46 @@ clocks = <&xtal>; clock-names = "xtal"; }; + + pwrc: power-controller { + compatible = "amlogic,meson-axg-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&sysctrl_AO>; + resets = <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_VCBUS>, + <&reset RESET_VENCL>, + <&reset RESET_VID_LOCK>; + reset-names = "viu", "venc", "vcbus", + "vencl", "vid_lock"; + clocks = <&clkc CLKID_VPU>, + <&clkc CLKID_VAPB>; + clock-names = "vpu", "vapb"; + /* + * VPU clocking is provided by two identical clock paths + * VPU_0 and VPU_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + * Same for VAPB but with a final gate after the glitch free mux. + */ + assigned-clocks = <&clkc CLKID_VPU_0_SEL>, + <&clkc CLKID_VPU_0>, + <&clkc CLKID_VPU>, /* Glitch free mux */ + <&clkc CLKID_VAPB_0_SEL>, + <&clkc CLKID_VAPB_0>, + <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>, + <0>, /* Do Nothing */ + <&clkc CLKID_VPU_0>, + <&clkc CLKID_FCLK_DIV4>, + <0>, /* Do Nothing */ + <&clkc CLKID_VAPB_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <250000000>, + <0>, /* Do Nothing */ + <0>, /* Do Nothing */ + <250000000>, + <0>; /* Do Nothing */ + }; }; }; -- cgit v1.2.3 From 3d3f1dfa0897bd14eebc3e79b38ae90a2eac67c5 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 20 Nov 2020 16:21:31 +0100 Subject: arm64: dts: meson-axg: add MIPI DSI PHY nodes This adds the nodes for : - MIPI DSI+PCIe analog phy - MIPI D-PHY Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201120152131.3918814-3-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index fed9e6edbfa9..f22481c4054f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1201,6 +1201,12 @@ <250000000>, <0>; /* Do Nothing */ }; + + mipi_pcie_analog_dphy: phy { + compatible = "amlogic,axg-mipi-pcie-analog-phy"; + #phy-cells = <0>; + status = "disabled"; + }; }; }; @@ -1213,6 +1219,19 @@ #mbox-cells = <1>; }; + mipi_dphy: phy@ff640000 { + compatible = "amlogic,axg-mipi-dphy"; + reg = <0x0 0xff640000 0x0 0x100>; + clocks = <&clkc CLKID_MIPI_DSI_PHY>; + clock-names = "pclk"; + resets = <&reset RESET_MIPI_PHY>; + reset-names = "phy"; + phys = <&mipi_pcie_analog_dphy>; + phy-names = "analog"; + #phy-cells = <0>; + status = "disabled"; + }; + audio: bus@ff642000 { compatible = "simple-bus"; reg = <0x0 0xff642000 0x0 0x2000>; -- cgit v1.2.3 From 5b3a9c20926e78f9d226b1853386dee6d22df9c3 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 20 Nov 2020 16:32:28 +0100 Subject: arm64: dts: meson-axg: add PCIe nodes This adds the nodes for the : - AXG PCIe PHY, using the shared analog PCIe/MIPI DSI PHY - 2x AXG PCIe controllers Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201120153229.3920123-4-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 61 ++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index f22481c4054f..bd8c4ac128a8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -172,6 +172,58 @@ #size-cells = <2>; ranges; + pcieA: pcie@f9800000 { + compatible = "amlogic,axg-pcie", "snps,dw-pcie"; + reg = <0x0 0xf9800000 0x0 0x400000>, + <0x0 0xff646000 0x0 0x2000>, + <0x0 0xf9f00000 0x0 0x100000>; + reg-names = "elbi", "cfg", "config"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>; + + clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>; + clock-names = "general", "pclk", "port"; + resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; + reset-names = "port", "apb"; + num-lanes = <1>; + phys = <&pcie_phy>; + phy-names = "pcie"; + status = "disabled"; + }; + + pcieB: pcie@fa000000 { + compatible = "amlogic,axg-pcie", "snps,dw-pcie"; + reg = <0x0 0xfa000000 0x0 0x400000>, + <0x0 0xff648000 0x0 0x2000>, + <0x0 0xfa400000 0x0 0x100000>; + reg-names = "elbi", "cfg", "config"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>; + + clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>; + clock-names = "general", "pclk", "port"; + resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>; + reset-names = "port", "apb"; + num-lanes = <1>; + phys = <&pcie_phy>; + phy-names = "pcie"; + status = "disabled"; + }; + usb: usb@ffe09080 { compatible = "amlogic,meson-axg-usb-ctrl"; reg = <0x0 0xffe09080 0x0 0x20>; @@ -234,6 +286,15 @@ status = "disabled"; }; + pcie_phy: phy@ff644000 { + compatible = "amlogic,axg-pcie-phy"; + reg = <0x0 0xff644000 0x0 0x1c>; + resets = <&reset RESET_PCIE_PHY>; + phys = <&mipi_pcie_analog_dphy>; + phy-names = "analog"; + #phy-cells = <0>; + }; + pdm: audio-controller@ff632000 { compatible = "amlogic,axg-pdm"; reg = <0x0 0xff632000 0x0 0x34>; -- cgit v1.2.3 From 9715b01da6cfb361b2a09fe2ad94287d6fa72261 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 20 Nov 2020 16:32:29 +0100 Subject: arm64: dts: meson-axg-s400: enable PCIe M.2 Key E slots Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201120153229.3920123-5-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 7740f97c240f..359589d1dfa9 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -441,6 +441,16 @@ status = "okay"; }; +&pcieA { + reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcieB { + reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + &pwm_ab { status = "okay"; pinctrl-0 = <&pwm_a_x20_pins>; -- cgit v1.2.3 From 4592bfe9d9f3359ae9db4620a405441530207733 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 24 Nov 2020 12:17:40 +0000 Subject: arm64: dts: meson: Add capacity-dmips-mhz attributes to GXM GXM (S912) is a big-little design with CPUs 0-3 clocked at 1.5GHz and CPUs 4-7 at 1.0GHz. Adding capacity-dmips-mhz attributes allows the scheduler to factor the different clock speeds into capacity calculations and prefer the higher-clocked cluster to improve overall performance. This was inspired by the similar change for G12B [0] boards. The diference here is that all cores are A53's so the same dmips-mhz value is used. VIM2:~ # cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq 1512000 1512000 1512000 1512000 1000000 1000000 1000000 1000000 before: VIM2:~ # cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 1024 1024 1024 1024 1024 1024 after: VIM2:~ # cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 1024 1024 677 677 677 677 The after value matches my table-napkin calculation: (1000000 / 1512000 = 0.661) * 1024 = 677 [0] https://github.com/torvalds/linux/commit/6eeaf4d2452ec8b1ece58776812140734fc2e088 Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201124121740.25704-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi index fe4145112295..411cc312fc62 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi @@ -42,11 +42,28 @@ }; }; + cpu0: cpu@0 { + capacity-dmips-mhz = <1024>; + }; + + cpu1: cpu@1 { + capacity-dmips-mhz = <1024>; + }; + + cpu2: cpu@2 { + capacity-dmips-mhz = <1024>; + }; + + cpu3: cpu@3 { + capacity-dmips-mhz = <1024>; + }; + cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x100>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -57,6 +74,7 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x101>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -67,6 +85,7 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x102>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -77,6 +96,7 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x103>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; -- cgit v1.2.3 From a6077652cb6595b1d668af41a3978dd965d57b9e Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 24 Nov 2020 14:53:38 +0000 Subject: arm64: dts: meson: add rtc aliases to meson-khadas-vim3.dtsi Tweak the node name to make it aliasable, then add aliases for the on-board RTC chip and meson-vrtc timer so they probe as rtc0 and rtc1 respectively. before: VIM3:~ # dmesg | grep rtc [ 3.622530] meson-vrtc ff8000a8.rtc: registered as rtc0 [ 3.622574] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:03 UTC (3) [ 3.646936] rtc-hym8563 0-0051: no valid clock/calendar values available [ 3.647125] rtc-hym8563 0-0051: registered as rtc1 [ 3.852382] rtc-hym8563 0-0051: no valid clock/calendar values available after: VIM3:~ # dmesg | grep rtc [ 3.583735] meson-vrtc ff8000a8.rtc: registered as rtc1 [ 3.633888] rtc-hym8563 0-0051: no valid clock/calendar values available [ 3.634120] rtc-hym8563 0-0051: registered as rtc0 [ 3.635250] rtc-hym8563 0-0051: no valid clock/calendar values available [ 3.635267] rtc-hym8563 0-0051: hctosys: unable to read the hardware clock [ 3.852632] rtc-hym8563 0-0051: no valid clock/calendar values available Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201124145338.17137-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 7b46555ac55a..87bd8c9516f2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -13,6 +13,8 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac; + rtc0 = &rtc; + rtc1 = &vrtc; }; chosen { @@ -330,7 +332,7 @@ #gpio-cells = <2>; }; - rtc@51 { + rtc: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; -- cgit v1.2.3 From b6c605e00ce8910d7ec3d9a54725d78b14db49b9 Mon Sep 17 00:00:00 2001 From: Artem Lapkin Date: Wed, 25 Nov 2020 02:40:01 +0000 Subject: arm64: dts: meson: fix spi-max-frequency on Khadas VIM2 The max frequency for the w25q32 (VIM v1.2) and w25q128 (VIM v1.4) spifc chip should be 104Mhz not 30MHz. Fixes: b8b74dda3908 ("ARM64: dts: meson-gxm: Add support for Khadas VIM2") Signed-off-by: Artem Lapkin Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201125024001.19036-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index da000c10b945..c5ee55caae0a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -340,7 +340,7 @@ #size-cells = <1>; compatible = "winbond,w25q16", "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <3000000>; + spi-max-frequency = <104000000>; }; }; -- cgit v1.2.3 From 6714f28178889da983d020fd9cf3bf7ae1a8c49d Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 25 Nov 2020 05:29:14 +0000 Subject: arm64: dts: meson: update the Khadas VIM3/3L LED bindings Update the VIM3/3L common dtsi to use the new function/color bindings. Suggested-by: Artem Lapkin Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201125052914.4092-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 87bd8c9516f2..8f8656262ae7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include @@ -42,14 +43,16 @@ leds { compatible = "gpio-leds"; - led-white { - label = "vim3:white:sys"; + white { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - led-red { - label = "vim3:red"; + red { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>; }; }; -- cgit v1.2.3 From 2493a9a515cf2bfa958d1d68beab507a1c7f5962 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 26 Nov 2020 05:04:40 +0000 Subject: arm64: dts: meson: add KHAMSIN IR remote node to SML5442TW Set the IR keymap to the KHAMSIN remote shipped with the SML5442TW. Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201126050440.6273-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts index 0b95e9ecbef0..ad6d72254150 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts @@ -63,6 +63,10 @@ pinctrl-names = "default"; }; +&ir { + linux,rc-map-name = "rc-khamsin"; +}; + /* This is connected to the Bluetooth module: */ &uart_A { status = "okay"; -- cgit v1.2.3 From b6a1c8a1eaa73b1e2ae251399308e9445d74cef7 Mon Sep 17 00:00:00 2001 From: Dongjin Kim Date: Mon, 30 Nov 2020 15:03:20 +0900 Subject: arm64: dts: meson-sm1: fix typo in opp table The freqency 1512000000 should be 1500000000. Signed-off-by: Dongjin Kim Fixes: 3d9e76483049 ("arm64: dts: meson-sm1-sei610: enable DVFS") Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201130060320.GA30098@anyang-linuxfactory-or-kr --- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 71317f5aada1..c309517abae3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -130,7 +130,7 @@ opp-microvolt = <790000>; }; - opp-1512000000 { + opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <800000>; }; -- cgit v1.2.3 From 2e6cde96873253fd9eb0f20afd8ffd18278cff75 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 19 Nov 2020 18:38:21 +0200 Subject: arm64: dts: ls1028a: make the eMMC and SD card controllers use fixed indices As the boot order in the kernel continues to change, sometimes it may happen that the eSDHC controller mmc@2150000 (the one for eMMC) gets probed before the one at mmc@2140000 (for external SD cards). The effect is that the eMMC controller gets the /dev/mmcblk0 name, and the SD card gets /dev/mmcblk1. Since the introduction of this SoC, that has never happened in practice, even though it was never guaranteed in theory. Setting "root=/dev/mmcblk0p2" in /proc/cmdline has always caused the kernel to use the second partition from the SD card as the rootfs. The NXP development boards are typically shipped with either - LSDK, which uses "root=UUID=", or - OpenIL, which uses "root=/dev/mmcblkNp2" So for OpenIL, let's preserve that old behavior by adding some aliases which create naming consistency (for LSDK it doesn't matter): - the SD card controller uses /dev/mmcblk0 - the eMMC controller uses /dev/mmcblk1 For the Kontron SL28 boards, Michael Walle says that they are shipped with "root=UUID=" already, so the probing order doesn't matter, but it is more natural to him for /dev/mmcblk0 to be the eMMC, so let's do it the other way around there. The aliases are parsed by mmc_alloc_host() in drivers/mmc/core/host.c. Cc: Ashish Kumar Cc: Yangbo Lu Cc: Michael Walle Signed-off-by: Vladimir Oltean Acked-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 2 ++ arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 2 ++ arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 2 ++ 3 files changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index 6b1ec50d6a65..3123e4173c62 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -23,6 +23,8 @@ serial2 = &lpuart1; spi0 = &fspi; spi1 = &dspi2; + mmc0 = &esdhc1; + mmc1 = &esdhc; }; buttons0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 13cdc958ba3e..c0786b713791 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -23,6 +23,8 @@ gpio2 = &gpio3; serial0 = &duart0; serial1 = &duart1; + mmc0 = &esdhc; + mmc1 = &esdhc1; }; chosen { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 1efb61cff454..c1d1ba459307 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -19,6 +19,8 @@ crypto = &crypto; serial0 = &duart0; serial1 = &duart1; + mmc0 = &esdhc; + mmc1 = &esdhc1; }; chosen { -- cgit v1.2.3 From 970406eaef3a5304cc1513d8a4aae23e183f7ba8 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 7 Nov 2020 05:58:05 -0600 Subject: arm64: dts: imx8mn: Enable Asynchronous Sample Rate Converter The driver exists for the Enhanced Asynchronous Sample Rate Converter (EASRC) Controller, but there isn't a device tree entry for it. On the vendor kernel, they put this on a spba-bus for SDMA support. Add the node for the spba-bus with the easrc node inside. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index d5cb8abb13e8..412e4a7773ef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -253,6 +253,34 @@ #size-cells = <1>; ranges; + spba: bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + + easrc: easrc@300c0000 { + compatible = "fsl,imx8mn-easrc"; + reg = <0x300c0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + firmware-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-format = <2>; + status = "disabled"; + }; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; -- cgit v1.2.3 From 9e9860069725f81a97571f565a1e93a4734b6dd7 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 7 Nov 2020 05:58:06 -0600 Subject: arm64: dts: imx8mn: Add SAI nodes The i.MX8M Nano has several SAI nodes available to it. Enable them. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 72 +++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 412e4a7773ef..bc80b0201408 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -260,6 +260,78 @@ reg = <0x30000000 0x100000>; ranges; + sai2: sai@30020000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30020000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI2_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI2_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@30030000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30030000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai5: sai@30050000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30050000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI5_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI5_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + status = "disabled"; + }; + + sai6: sai@30060000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30060000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI6_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI6_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai7: sai@300b0000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x300b0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI7_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI7_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + easrc: easrc@300c0000 { compatible = "fsl,imx8mn-easrc"; reg = <0x300c0000 0x10000>; -- cgit v1.2.3 From cca69ef6eba514e04717dec49a1dac2a7db221ec Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 7 Nov 2020 05:58:07 -0600 Subject: arm64: dts: imx8mn: Add support for micfil The i.MX8M Nano has supports the MICFIL digital interface. It's a 16-bit audio signal from a PDM microphone bitstream. The driver is already in the kernel, but the node is missing. Add the micfil node. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index bc80b0201408..2087fe84c7cf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -318,6 +318,25 @@ status = "disabled"; }; + micfil: audio-controller@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x30080000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8MN_CLK_PDM_IPG>, + <&clk IMX8MN_CLK_PDM_ROOT>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>, + <&clk IMX8MN_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; + sai7: sai@300b0000 { compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>; -- cgit v1.2.3 From b9cf7d3b6592561e2a9f123a989f7dd5708a61d3 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 7 Nov 2020 05:58:08 -0600 Subject: arm64: dts: imx8mn: Add node for SPDIF The i.MX8M Nano can support SPDIF which is compatible to the IP used on the i.MX35. Add the node. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 2087fe84c7cf..31ca1f3bfece 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -337,6 +337,30 @@ status = "disabled"; }; + spdif1: spdif@30090000 { + compatible = "fsl,imx35-spdif"; + reg = <0x30090000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ + <&clk IMX8MN_CLK_24M>, /* rxtx0 */ + <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MN_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + sai7: sai@300b0000 { compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>; -- cgit v1.2.3 From 6b5cd77371e5e34769284bfb058ff332ae278cc5 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 26 Nov 2020 04:45:34 -0600 Subject: arm64: dts: imx8mm-beacon-som: Configure RTC aliases On the i.MX8MM Beacon SOM, there is an RTC chip which is fed power from the baseboard during power off. The SNVS RTC integrated into the SoC is not fed power. Depending on the order the modules are loaded, this can be a problem if the external RTC isn't rtc0. Make the alias for rtc0 point to the external RTC all the time and rtc1 point to the SVNS in order to correctly hold date/time over a power-cycle. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 6b53830ddf74..8380fd4047d4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -4,6 +4,11 @@ */ / { + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -218,7 +223,7 @@ reg = <0x50>; }; - rtc@51 { + rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; }; -- cgit v1.2.3 From 0b84862688951ad5f6ad8990dd9a44e1363c4a2b Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 26 Nov 2020 04:45:35 -0600 Subject: arm64: dts: imx8mm-beacon-som: Assign PMIC clock The PMIC throws an errors because the clock isn't assigned to it. Fix this by assigning the clocks info. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 8380fd4047d4..c14add99bfa4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -110,6 +110,10 @@ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + regulators { buck1_reg: BUCK1 { regulator-name = "buck1"; -- cgit v1.2.3 From 94dad6bed3c86c00050bf7c2b2ad6b630facae31 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 4 Dec 2020 14:48:05 +0800 Subject: arm64: dts: rockchip: Fix UART pull-ups on rk3328 For UARTs, the local pull-ups should be on the RX pin, not the TX pin. UARTs transmit active-low, so a disconnected RX pin should be pulled high instead of left floating to prevent noise being interpreted as transmissions. This gets rid of bogus sysrq events when the UART console is not connected. Fixes: 52e02d377a72 ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201204064805.6480-1-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index bbdb19a3e85d..db0d5c8e5f96 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -1237,8 +1237,8 @@ uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, - <1 RK_PB0 1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, + <1 RK_PB0 1 &pcfg_pull_up>; }; uart0_cts: uart0-cts { @@ -1256,8 +1256,8 @@ uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, - <3 RK_PA6 4 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, + <3 RK_PA6 4 &pcfg_pull_up>; }; uart1_cts: uart1-cts { @@ -1275,15 +1275,15 @@ uart2-0 { uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, - <1 RK_PA1 2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, + <1 RK_PA1 2 &pcfg_pull_up>; }; }; uart2-1 { uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, - <2 RK_PA1 1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, + <2 RK_PA1 1 &pcfg_pull_up>; }; }; -- cgit v1.2.3 From 328c6112787bf7562dbea638840366cd197868d6 Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Tue, 1 Dec 2020 16:41:30 +0100 Subject: arm64: dts: rockchip: fix supplies on rk3399-rock-pi-4 Based on the board schematics at https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf on page 18: vcc_lan is not controllable by software, it is just an analog LC filter. Because of this, it can not be turned off-in-suspend. and on page 17: vcc_cam and vcc_mipi are not voltage regulators, they are just switches. So, the voltage range is not applicable. This silences an error message about not being able to adjust the voltage. Signed-off-by: Vicente Bergas Link: https://lore.kernel.org/r/20201201154132.1286-2-vicencb@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 678a336010bf..06df2397bbb4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -111,10 +111,6 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; }; vdd_log: vdd-log { @@ -362,8 +358,6 @@ regulator-name = "vcc_cam"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; regulator-state-mem { regulator-off-in-suspend; }; @@ -373,8 +367,6 @@ regulator-name = "vcc_mipi"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; regulator-state-mem { regulator-off-in-suspend; }; -- cgit v1.2.3 From eff57d38b546b3a50588e447a41ff3571a407c9f Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Tue, 1 Dec 2020 16:41:31 +0100 Subject: arm64: dts: rockchip: fix I2S conflict on rk3399-rock-pi-4 Based on the board schematics at https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf on page 14: Only two channels of I2S are connected and the extra I2S pins are in conflict with other functions like USB power. Signed-off-by: Vicente Bergas Link: https://lore.kernel.org/r/20201201154132.1286-3-vicencb@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 06df2397bbb4..63b029a543c1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -432,8 +432,9 @@ }; &i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; + pinctrl-0 = <&i2s0_2ch_bus>; + rockchip,capture-channels = <2>; + rockchip,playback-channels = <2>; status = "okay"; }; -- cgit v1.2.3 From e12f67fe83446432ef16704c22ec23bd1dbcd094 Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Tue, 1 Dec 2020 16:41:32 +0100 Subject: arm64: dts: rockchip: use USB host by default on rk3399-rock-pi-4 Based on the board schematics at https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf on page 19 there is an USB Type-A receptacle being used as an USB-OTG port. But the Type-A connector is not valid for OTG operation, for this reason there is a switch to select host or device role. This is non-compliant and error prone because switching is manual. So, use host mode as it corresponds for a Type-A receptacle. Signed-off-by: Vicente Bergas Link: https://lore.kernel.org/r/20201201154132.1286-4-vicencb@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 63b029a543c1..fb7599f07af4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -673,7 +673,7 @@ &usbdrd_dwc3_0 { status = "okay"; - dr_mode = "otg"; + dr_mode = "host"; }; &usbdrd3_1 { -- cgit v1.2.3 From b03455ae3c8a7e7999f9cc43ad87c63b44a89344 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 2 Dec 2020 18:44:17 +0100 Subject: arm64: dts: meson-axg: add GE2D node This adds the node for the GE2D accelerator unit. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201202174417.3778306-5-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index bd8c4ac128a8..ba1c6dfdc4b6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1727,6 +1727,15 @@ }; }; + ge2d: ge2d@ff940000 { + compatible = "amlogic,axg-ge2d"; + reg = <0x0 0xff940000 0x0 0x10000>; + interrupts = ; + clocks = <&clkc CLKID_VAPB>; + resets = <&reset RESET_GE2D>; + reset-names = "core"; + }; + gic: interrupt-controller@ffc01000 { compatible = "arm,gic-400"; reg = <0x0 0xffc01000 0 0x1000>, -- cgit v1.2.3 From ec78dc8964bbc68d76d0e9b132379bc3f22c72a6 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:17 +0000 Subject: arm64: dts: meson: add audio playback to a95x Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-2-christianshewitt@gmail.com --- .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts index 67d901ed2fa3..b5b11cb9f393 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts @@ -10,6 +10,7 @@ #include "meson-gxbb.dtsi" #include #include +#include / { compatible = "nexbox,a95x", "amlogic,meson-gxbb"; @@ -139,6 +140,45 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXBB-NEXBOX-A95X"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cvbs_vdac_port { -- cgit v1.2.3 From 4e0649f4957436cbce20ffc26239fdbe19638444 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:18 +0000 Subject: arm64: dts: meson: add audio playback to khadas-vim Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-3-christianshewitt@gmail.com --- .../dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 638a5992d760..7aa08f74c49b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -8,6 +8,7 @@ #include #include "meson-gxl-s905x-p212.dtsi" +#include / { compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl"; @@ -63,6 +64,45 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXL-KHADAS-VIM1"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cec_AO { -- cgit v1.2.3 From 0157e1a63c7685dfeee4e7cfd22635ebf104f64f Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:19 +0000 Subject: arm64: dts: meson: add audio playback to khadas-vim2 Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-4-christianshewitt@gmail.com --- .../boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index c5ee55caae0a..0250c98dbe9e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -10,6 +10,7 @@ #include #include "meson-gxm.dtsi" +#include / { compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm"; @@ -145,6 +146,45 @@ clock-frequency = <32768>; pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXM-KHADAS-VIM2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cec_AO { -- cgit v1.2.3 From 6a74f78c34e7503e35da724cdc555f26ea8d1cd1 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:20 +0000 Subject: arm64: dts: meson: add audio playback to nanopi-k2 Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-5-christianshewitt@gmail.com --- .../boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index 7be3e354093b..8e5df00b06a2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -7,6 +7,7 @@ #include "meson-gxbb.dtsi" #include +#include / { compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb"; @@ -130,6 +131,45 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXBB-NANOPI-K2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cec_AO { -- cgit v1.2.3 From ba414bc5484873bb157e63ba8684d59e27feaeb2 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:21 +0000 Subject: arm64: dts: meson: add audio playback to odroid-c2 Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-6-christianshewitt@gmail.com --- .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 70fcfb7b0683..9d8c919c6e19 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -9,6 +9,7 @@ #include "meson-gxbb.dtsi" #include +#include / { compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; @@ -172,6 +173,45 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXBB-ODROID-C2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cec_AO { -- cgit v1.2.3 From e0d9e6eead35be9842aae14f424f2d2ab0be0678 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:22 +0000 Subject: arm64: dts: meson: add audio playback to wetek-hub Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-7-christianshewitt@gmail.com --- .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts index 83b985bb015e..0c1570153842 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts @@ -7,10 +7,50 @@ /dts-v1/; #include "meson-gxbb-wetek.dtsi" +#include / { compatible = "wetek,hub", "amlogic,meson-gxbb"; model = "WeTek Hub"; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXBB-WETEK-HUB"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &ir { -- cgit v1.2.3 From 5e3ee48ea072a6fd2c46c552d013e047dc54d1c6 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:23 +0000 Subject: arm64: dts: meson: add audio playback to wetek-play2 Add initial support limited to HDMI i2s and SPDIF (LPCM). Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-8-christianshewitt@gmail.com --- .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts index 2ab8a3d10079..f2562c7de67c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts @@ -8,11 +8,19 @@ #include "meson-gxbb-wetek.dtsi" #include +#include / { compatible = "wetek,play2", "amlogic,meson-gxbb"; model = "WeTek Play 2"; + spdif_dit: audio-codec-0 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; + leds { led-wifi { label = "wetek-play:wifi-status"; @@ -39,6 +47,59 @@ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXBB-WETEK-PLAY2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-3 { + sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; + + codec-0 { + sound-dai = <&spdif_dit>; + }; + }; + + dai-link-4 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; + pinctrl-0 = <&spdif_out_y_pins>; + pinctrl-names = "default"; }; &i2c_A { -- cgit v1.2.3 From c993c4e84369acf5686a6f345ebb0efb0107f73e Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:16:05 +0000 Subject: arm64: dts: meson: minor fixups for Khadas VIM/VIM2 dts Reorder the VIM/VIM2 includes/bindings to follow the format of other dts in the Amlogic tree and remove a stray empty line in the VIM2 dts. Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203061605.9603-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 3 +-- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 4 +--- 2 files changed, 2 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 7aa08f74c49b..6fe589cd2ba2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -5,9 +5,8 @@ /dts-v1/; -#include - #include "meson-gxl-s905x-p212.dtsi" +#include #include / { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 0250c98dbe9e..955a63aaa5ed 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -7,9 +7,8 @@ /dts-v1/; -#include - #include "meson-gxm.dtsi" +#include #include / { @@ -194,7 +193,6 @@ hdmi-phandle = <&hdmi_tx>; }; - &cpu_cooling_maps { map0 { cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>; -- cgit v1.2.3 From 1c7412530d5d0e0a0b27f1642f5c13c8b9f36f05 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 7 Dec 2020 18:57:59 +0100 Subject: arm64: dts: meson: g12b: odroid-n2: fix PHY deassert timing requirements According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY registers. This fixes an issue where the Ethernet link doesn't come up when using ip link set down/up: [ 29.360965] meson8b-dwmac ff3f0000.ethernet eth0: Link is Down [ 34.569012] meson8b-dwmac ff3f0000.ethernet eth0: PHY [0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=31) [ 34.676732] meson8b-dwmac ff3f0000.ethernet: Failed to reset the dma [ 34.678874] meson8b-dwmac ff3f0000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed [ 34.687850] meson8b-dwmac ff3f0000.ethernet eth0: stmmac_open: Hw setup failed Fixes: 658e4129bb81 ("arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY reset line") Reviewed-by: Martin Blumenstingl Signed-off-by: Stefan Agner Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/df3f5c4fc6e43c55429fd3662a636036a21eed49.1607363522.git.stefan@agner.ch --- arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi index 6982632ae646..39a09661c5f6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi @@ -413,7 +413,7 @@ max-speed = <1000>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; interrupt-parent = <&gpio_intc>; -- cgit v1.2.3 From c183c406c4321002fe85b345b51bc1a3a04b6d33 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 7 Dec 2020 18:58:00 +0100 Subject: arm64: dts: meson: fix PHY deassert timing requirements According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY registers. This fixes an issue seen on ODROID-C2 where the Ethernet link doesn't come up when using ip link set down/up: [ 6630.714855] meson8b-dwmac c9410000.ethernet eth0: Link is Down [ 6630.785775] meson8b-dwmac c9410000.ethernet eth0: PHY [stmmac-0:00] driver [RTL8211F Gigabit Ethernet] (irq=36) [ 6630.893071] meson8b-dwmac c9410000.ethernet: Failed to reset the dma [ 6630.893800] meson8b-dwmac c9410000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed [ 6630.902835] meson8b-dwmac c9410000.ethernet eth0: stmmac_open: Hw setup failed Fixes: f29cabf240ed ("arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings") Reviewed-by: Martin Blumenstingl Signed-off-by: Stefan Agner Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/4a322c198b86e4c8b3dda015560a683babea4d63.1607363522.git.stefan@agner.ch --- arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index 8e5df00b06a2..089e0636ba8a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -205,7 +205,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 9d8c919c6e19..c04ef57f7b3b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -240,7 +240,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index 222ee8069cfa..9b0b81f191f1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -126,7 +126,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index ad812854a107..a350fee1264d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -147,7 +147,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts index b08c4537f260..b2ab05c22090 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts @@ -82,7 +82,7 @@ /* External PHY reset is shared with internal PHY Led signal */ reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 955a63aaa5ed..bf9877d33427 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -232,7 +232,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts index 83eca3af44ce..dfa7a37a1281 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts @@ -112,7 +112,7 @@ max-speed = <1000>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts index ea45ae0c71b7..8edbfe040805 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts @@ -64,7 +64,7 @@ /* External PHY reset is shared with internal PHY Led signal */ reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts index c89c9f846fb1..dde7cfe12cff 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts @@ -114,7 +114,7 @@ max-speed = <1000>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; }; }; -- cgit v1.2.3 From 3d07c3b3a886fefd583c1b485b5e4e3c4e2da493 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 7 Dec 2020 18:58:02 +0100 Subject: arm64: dts: meson: g12a: x96-max: fix PHY deassert timing requirements According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY registers. On similar boards with the same PHY this fixes an issue where Ethernet link would not come up when using ip link set down/up. Fixes: ed5e8f689154 ("arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY reset line") Reviewed-by: Martin Blumenstingl Signed-off-by: Stefan Agner Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/12506964ca5d5f936579a280ad0a7e7f9a0a2d4c.1607363522.git.stefan@agner.ch --- arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index 1b07c8c06eac..463a72d6bb7c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -340,7 +340,7 @@ eee-broken-1000t; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; interrupt-parent = <&gpio_intc>; -- cgit v1.2.3 From 9e454e37dc7c0ee9e108d70b983e7a71332aedff Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 7 Dec 2020 18:58:03 +0100 Subject: arm64: dts: meson: g12b: w400: fix PHY deassert timing requirements According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY egisters. On similar boards with the same PHY this fixes an issue where Ethernet link would not come up when using ip link set down/up. Fixes: 2cd2310fca4c ("arm64: dts: meson-g12b-ugoos-am6: add initial device-tree") Reviewed-by: Martin Blumenstingl Signed-off-by: Stefan Agner Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/46298e66572784c44f873f1b71cc4ab3d8fc5aa6.1607363522.git.stefan@agner.ch --- arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi index 2802ddbb83ac..feb088504740 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi @@ -264,7 +264,7 @@ max-speed = <1000>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; interrupt-parent = <&gpio_intc>; -- cgit v1.2.3 From 7704b100719cf0fead976a1bc839c60ee552d045 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 1 Dec 2020 06:21:35 +0000 Subject: arm64: dts: meson: add i2c3/rtc nodes and vrtc alias to GT-King/GT-King-Pro The GT-King and GT-King-Pro boxes have an RTC chip and power cell, so enable it. GTKING:~ # dmesg | grep rtc [ 5.237245] meson-vrtc ff8000a8.rtc: registered as rtc1 [ 5.261869] rtc-hym8563 0-0051: registered as rtc0 [ 5.265016] rtc-hym8563 0-0051: setting system clock to 2020-11-30T09:16:54 UTC (1606727814) Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201201062135.18241-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts | 18 ++++++++++++++++++ 2 files changed, 35 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts index f0c56a16af3d..0e5c500fb78f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts @@ -14,6 +14,11 @@ compatible = "azw,gtking", "amlogic,g12b"; model = "Beelink GT-King Pro"; + aliases { + rtc0 = &rtc; + rtc1 = &vrtc; + }; + gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -112,6 +117,18 @@ status = "okay"; }; +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + wakeup-source; + }; +}; + &tdmif_b { status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts index eeb7bc5539ef..10b87eb97b14 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts @@ -14,6 +14,11 @@ compatible = "azw,gtking", "amlogic,g12b"; model = "Beelink GT-King"; + aliases { + rtc0 = &rtc; + rtc1 = &vrtc; + }; + spdif_dit: audio-codec-1 { #sound-dai-cells = <0>; compatible = "linux,spdif-dit"; @@ -122,6 +127,19 @@ status = "okay"; }; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + wakeup-source; + }; +}; + &spdifout { pinctrl-0 = <&spdif_out_h_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From 5ef399aa5c5f9c4c2ac9208d1f00e935f13012ce Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Tue, 6 Oct 2020 22:03:16 +0200 Subject: arm64: dts: sparx5: Add reset support This adds reset support to the Sparx5 SoC DT. Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20201006200316.2261245-4-lars.povlsen@microchip.com --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 3cb01c39c3c8..1def30e6b728 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -135,6 +135,11 @@ }; }; + reset@611010008 { + compatible = "microchip,sparx5-chip-reset"; + reg = <0x6 0x11010008 0x4>; + }; + uart0: serial@600100000 { pinctrl-0 = <&uart_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From 7e1f91cbfa0d330fad61c621389373cff81898fd Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Fri, 13 Nov 2020 15:51:51 +0100 Subject: arm64: dts: sparx5: Add SGPIO devices This adds SGPIO devices for the Sparx5 SoC and configures it for the applicable reference boards. Signed-off-by: Lars Povlsen Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20201113145151.68900-4-lars.povlsen@microchip.com --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 91 ++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 5 + .../boot/dts/microchip/sparx5_pcb134_board.dtsi | 258 +++++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb135_board.dtsi | 55 +++++ 4 files changed, 409 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 1def30e6b728..d64621d1213b 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -231,6 +231,22 @@ function = "si2"; }; + sgpio0_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sg0"; + }; + + sgpio1_pins: sgpio1-pins { + pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13"; + function = "sg1"; + }; + + sgpio2_pins: sgpio2-pins { + pins = "GPIO_30", "GPIO_31", "GPIO_32", + "GPIO_33"; + function = "sg2"; + }; + uart_pins: uart-pins { pins = "GPIO_10", "GPIO_11"; function = "uart"; @@ -261,6 +277,81 @@ }; }; + sgpio0: gpio@61101036c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio0_pins>; + pinctrl-names = "default"; + reg = <0x6 0x1101036c 0x100>; + sgpio_in0: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + sgpio_out0: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + }; + + sgpio1: gpio@611010484 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio1_pins>; + pinctrl-names = "default"; + reg = <0x6 0x11010484 0x100>; + sgpio_in1: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + sgpio_out1: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + }; + + sgpio2: gpio@61101059c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio2_pins>; + pinctrl-names = "default"; + reg = <0x6 0x1101059c 0x100>; + sgpio_in2: gpio@0 { + reg = <0>; + compatible = "microchip,sparx5-sgpio-bank"; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + sgpio_out2: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + }; + i2c0: i2c@600101000 { compatible = "snps,designware-i2c"; status = "disabled"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 6b2da7c7520c..9baa085d7861 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -69,6 +69,11 @@ }; }; +&sgpio0 { + status = "okay"; + microchip,sgpio-port-ranges = <0 23>; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index f37b478d6534..f0c915160990 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -36,6 +36,264 @@ gpios = <&gpio 37 GPIO_ACTIVE_LOW>; priority = <200>; }; + + leds { + compatible = "gpio-leds"; + led@0 { + label = "twr0:green"; + gpios = <&sgpio_out0 8 0 GPIO_ACTIVE_LOW>; + }; + led@1 { + label = "twr0:yellow"; + gpios = <&sgpio_out0 8 1 GPIO_ACTIVE_LOW>; + }; + led@2 { + label = "twr1:green"; + gpios = <&sgpio_out0 9 0 GPIO_ACTIVE_LOW>; + }; + led@3 { + label = "twr1:yellow"; + gpios = <&sgpio_out0 9 1 GPIO_ACTIVE_LOW>; + }; + led@4 { + label = "twr2:green"; + gpios = <&sgpio_out0 10 0 GPIO_ACTIVE_LOW>; + }; + led@5 { + label = "twr2:yellow"; + gpios = <&sgpio_out0 10 1 GPIO_ACTIVE_LOW>; + }; + led@6 { + label = "twr3:green"; + gpios = <&sgpio_out0 11 0 GPIO_ACTIVE_LOW>; + }; + led@7 { + label = "twr3:yellow"; + gpios = <&sgpio_out0 11 1 GPIO_ACTIVE_LOW>; + }; + led@8 { + label = "eth12:green"; + gpios = <&sgpio_out0 12 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@9 { + label = "eth12:yellow"; + gpios = <&sgpio_out0 12 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@10 { + label = "eth13:green"; + gpios = <&sgpio_out0 13 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@11 { + label = "eth13:yellow"; + gpios = <&sgpio_out0 13 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@12 { + label = "eth14:green"; + gpios = <&sgpio_out0 14 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@13 { + label = "eth14:yellow"; + gpios = <&sgpio_out0 14 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@14 { + label = "eth15:green"; + gpios = <&sgpio_out0 15 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@15 { + label = "eth15:yellow"; + gpios = <&sgpio_out0 15 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@16 { + label = "eth48:green"; + gpios = <&sgpio_out1 16 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@17 { + label = "eth48:yellow"; + gpios = <&sgpio_out1 16 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@18 { + label = "eth49:green"; + gpios = <&sgpio_out1 17 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@19 { + label = "eth49:yellow"; + gpios = <&sgpio_out1 17 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@20 { + label = "eth50:green"; + gpios = <&sgpio_out1 18 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@21 { + label = "eth50:yellow"; + gpios = <&sgpio_out1 18 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@22 { + label = "eth51:green"; + gpios = <&sgpio_out1 19 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@23 { + label = "eth51:yellow"; + gpios = <&sgpio_out1 19 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@24 { + label = "eth52:green"; + gpios = <&sgpio_out1 20 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@25 { + label = "eth52:yellow"; + gpios = <&sgpio_out1 20 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@26 { + label = "eth53:green"; + gpios = <&sgpio_out1 21 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@27 { + label = "eth53:yellow"; + gpios = <&sgpio_out1 21 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@28 { + label = "eth54:green"; + gpios = <&sgpio_out1 22 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@29 { + label = "eth54:yellow"; + gpios = <&sgpio_out1 22 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@30 { + label = "eth55:green"; + gpios = <&sgpio_out1 23 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@31 { + label = "eth55:yellow"; + gpios = <&sgpio_out1 23 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@32 { + label = "eth56:green"; + gpios = <&sgpio_out1 24 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@33 { + label = "eth56:yellow"; + gpios = <&sgpio_out1 24 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@34 { + label = "eth57:green"; + gpios = <&sgpio_out1 25 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@35 { + label = "eth57:yellow"; + gpios = <&sgpio_out1 25 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@36 { + label = "eth58:green"; + gpios = <&sgpio_out1 26 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@37 { + label = "eth58:yellow"; + gpios = <&sgpio_out1 26 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@38 { + label = "eth59:green"; + gpios = <&sgpio_out1 27 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@39 { + label = "eth59:yellow"; + gpios = <&sgpio_out1 27 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@40 { + label = "eth60:green"; + gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@41 { + label = "eth60:yellow"; + gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@42 { + label = "eth61:green"; + gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@43 { + label = "eth61:yellow"; + gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@44 { + label = "eth62:green"; + gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@45 { + label = "eth62:yellow"; + gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@46 { + label = "eth63:green"; + gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@47 { + label = "eth63:yellow"; + gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&sgpio0 { + status = "okay"; + microchip,sgpio-port-ranges = <8 15>; + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + +&sgpio1 { + status = "okay"; + microchip,sgpio-port-ranges = <24 31>; + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; }; &spi0 { diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index b02b8c8ce44d..e28c6dd16377 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -20,6 +20,50 @@ gpios = <&gpio 37 GPIO_ACTIVE_LOW>; priority = <200>; }; + + leds { + compatible = "gpio-leds"; + led@0 { + label = "eth60:yellow"; + gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@1 { + label = "eth60:green"; + gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@2 { + label = "eth61:yellow"; + gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@3 { + label = "eth61:green"; + gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@4 { + label = "eth62:yellow"; + gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@5 { + label = "eth62:green"; + gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@6 { + label = "eth63:yellow"; + gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@7 { + label = "eth63:green"; + gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; }; &gpio { @@ -83,6 +127,17 @@ }; }; +&sgpio1 { + status = "okay"; + microchip,sgpio-port-ranges = <24 31>; + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + &axi { i2c0_imux: i2c0-imux@0 { compatible = "i2c-mux-pinctrl"; -- cgit v1.2.3