From 9781aa8adbc13b9960b5a3a7353efc57eeb3697d Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 12 Jun 2013 09:59:59 +0100 Subject: ARM: l2x0: use -st dsb option for ordering writel_relaxed with unlock writel_relaxed and spin_unlock are both store operations, so we only need to enforce store ordering in the dsb. Signed-off-by: Will Deacon --- arch/arm/mm/cache-l2x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mm/cache-l2x0.c') diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index d70e0aba0c9d..0c3fc276bd30 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -290,7 +290,7 @@ static void l2x0_disable(void) raw_spin_lock_irqsave(&l2x0_lock, flags); __l2x0_flush_all(); writel_relaxed(0, l2x0_base + L2X0_CTRL); - dsb(); + dsb(st); raw_spin_unlock_irqrestore(&l2x0_lock, flags); } -- cgit v1.2.3 From c477b8db45aa4c4976be22c807bf43d31fecf17d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Aug 2013 13:04:32 +0100 Subject: ARM: 7820/1: mm: cache-l2x0: Print the cache size in kB Currently we have the following output from cache-l2x0: l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x32070000, Cache size: 1048576 B Using kB for the cache size can improve readability a bit: l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x32070000, Cache size: 1024 kB While at it use pr_info. Signed-off-by: Fabio Estevam Signed-off-by: Russell King --- arch/arm/mm/cache-l2x0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/mm/cache-l2x0.c') diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index d70e0aba0c9d..ad4e8825f91e 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -417,9 +417,9 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) outer_cache.disable = l2x0_disable; } - printk(KERN_INFO "%s cache controller enabled\n", type); - printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", - ways, cache_id, aux, l2x0_size); + pr_info("%s cache controller enabled\n", type); + pr_info("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d kB\n", + ways, cache_id, aux, l2x0_size >> 10); } #ifdef CONFIG_OF -- cgit v1.2.3 From 505caa66fe8551c2c8421395c2e56a5bb02520ff Mon Sep 17 00:00:00 2001 From: Christian Daudt Date: Mon, 19 Aug 2013 23:00:45 +0100 Subject: ARM: 7821/1: DT: binding fixup to align with vendor-prefixes.txt [ this is a follow-up to this discussion: http://archive.arm.linux.org.uk/lurker/message/20130730.230827.a1ceb12a.en.html ] This patchset renames all uses of "bcm," name bindings to "brcm," as they were done prior to knowing that brcm had already been standardized as Broadcom vendor prefix (in Documentation/devicetree/bindings/vendor-prefixes.txt). This will not cause any churn on devices because none of these bindings have made it into production yet. Acked-by: Stephen Warren Signed-off-by: Christian Daudt Signed-off-by: Russell King --- Documentation/devicetree/bindings/arm/l2cc.txt | 4 +++- arch/arm/mm/cache-l2x0.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm/mm/cache-l2x0.c') diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index 69ddf9fad2dc..c0c7626fd0ff 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -16,9 +16,11 @@ Required properties: performs the same operation). "marvell,"aurora-outer-cache: Marvell Controller designed to be compatible with the ARM one with outer cache mode. - "bcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an + "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an offset needs to be added to the address before passing down to the L2 cache controller + "bcm,bcm11351-a2-pl310-cache": DEPRECATED by + "brcm,bcm11351-a2-pl310-cache" - cache-unified : Specifies the cache is a unified cache. - cache-level : Should be set to 2 for a level 2 cache. - reg : Physical base address and size of cache controller's memory mapped diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index ad4e8825f91e..f6a4bb2d2551 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -929,7 +929,9 @@ static const struct of_device_id l2x0_ids[] __initconst = { .data = (void *)&aurora_no_outer_data}, { .compatible = "marvell,aurora-outer-cache", .data = (void *)&aurora_with_outer_data}, - { .compatible = "bcm,bcm11351-a2-pl310-cache", + { .compatible = "brcm,bcm11351-a2-pl310-cache", + .data = (void *)&bcm_l2x0_data}, + { .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */ .data = (void *)&bcm_l2x0_data}, {} }; -- cgit v1.2.3