From 71b9114d2c13a648fbe6523dd859e611c316ad90 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 2 Sep 2019 17:47:55 +0200 Subject: ARM: s3c: move into a common directory s3c24xx and s3c64xx have a lot in common, but are split across three separate directories, which makes the interaction of the header files more complicated than necessary. Move all three directories into a new mach-s3c, with a minimal set of changes to each file. Signed-off-by: Arnd Bergmann [krzk: Rebase, add s3c24xx and s3c64xx suffix to several files, add SPDX headers to new files, remove plat-samsung from MAINTAINERS] Co-developed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski https://lore.kernel.org/r/20200806182059.2431-39-krzk@kernel.org --- arch/arm/mach-s3c/init.c | 173 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 173 insertions(+) create mode 100644 arch/arm/mach-s3c/init.c (limited to 'arch/arm/mach-s3c/init.c') diff --git a/arch/arm/mach-s3c/init.c b/arch/arm/mach-s3c/init.c new file mode 100644 index 000000000000..e9acf02ef3c3 --- /dev/null +++ b/arch/arm/mach-s3c/init.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2008 Simtec Electronics +// Ben Dooks +// http://armlinux.simtec.co.uk/ +// +// S3C series CPU initialisation + +/* + * NOTE: Code in this file is not used on S3C64xx when booting with + * Device Tree support. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +static struct cpu_table *cpu; + +static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode, + struct cpu_table *tab, + unsigned int count) +{ + for (; count != 0; count--, tab++) { + if ((idcode & tab->idmask) == (tab->idcode & tab->idmask)) + return tab; + } + + return NULL; +} + +void __init s3c_init_cpu(unsigned long idcode, + struct cpu_table *cputab, unsigned int cputab_size) +{ + cpu = s3c_lookup_cpu(idcode, cputab, cputab_size); + + if (cpu == NULL) { + printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); + panic("Unknown S3C24XX CPU"); + } + + printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); + + if (cpu->init == NULL) { + printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); + panic("Unsupported Samsung CPU"); + } + + if (cpu->map_io) + cpu->map_io(); +} + +/* s3c24xx_init_clocks + * + * Initialise the clock subsystem and associated information from the + * given master crystal value. + * + * xtal = 0 -> use default PLL crystal value (normally 12MHz) + * != 0 -> PLL crystal value in Hz +*/ + +void __init s3c24xx_init_clocks(int xtal) +{ + if (xtal == 0) + xtal = 12*1000*1000; + + if (cpu == NULL) + panic("s3c24xx_init_clocks: no cpu setup?\n"); + + if (cpu->init_clocks == NULL) + panic("s3c24xx_init_clocks: cpu has no clock init\n"); + else + (cpu->init_clocks)(xtal); +} + +/* uart management */ +#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS) +static int nr_uarts __initdata = 0; + +#ifdef CONFIG_SERIAL_SAMSUNG_UARTS +static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS]; +#endif + +/* s3c24xx_init_uartdevs + * + * copy the specified platform data and configuration into our central + * set of devices, before the data is thrown away after the init process. + * + * This also fills in the array passed to the serial driver for the + * early initialisation of the console. +*/ + +void __init s3c24xx_init_uartdevs(char *name, + struct s3c24xx_uart_resources *res, + struct s3c2410_uartcfg *cfg, int no) +{ +#ifdef CONFIG_SERIAL_SAMSUNG_UARTS + struct platform_device *platdev; + struct s3c2410_uartcfg *cfgptr = uart_cfgs; + struct s3c24xx_uart_resources *resp; + int uart; + + memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no); + + for (uart = 0; uart < no; uart++, cfg++, cfgptr++) { + platdev = s3c24xx_uart_src[cfgptr->hwport]; + + resp = res + cfgptr->hwport; + + s3c24xx_uart_devs[uart] = platdev; + + platdev->name = name; + platdev->resource = resp->resources; + platdev->num_resources = resp->nr_resources; + + platdev->dev.platform_data = cfgptr; + } + + nr_uarts = no; +#endif +} + +void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + if (cpu == NULL) + return; + + if (cpu->init_uarts == NULL && IS_ENABLED(CONFIG_SAMSUNG_ATAGS)) { + printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); + } else + (cpu->init_uarts)(cfg, no); +} +#endif + +static int __init s3c_arch_init(void) +{ + int ret; + + /* init is only needed for ATAGS based platforms */ + if (!IS_ENABLED(CONFIG_ATAGS) || + (!soc_is_s3c24xx() && !soc_is_s3c64xx())) + return 0; + + // do the correct init for cpu + + if (cpu == NULL) { + /* Not needed when booting with device tree. */ + if (of_have_populated_dt()) + return 0; + panic("s3c_arch_init: NULL cpu\n"); + } + + ret = (cpu->init)(); + if (ret != 0) + return ret; +#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS) + ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); +#endif + return ret; +} + +arch_initcall(s3c_arch_init); -- cgit v1.2.3 From c6ff132d4224022ffaa461ec771ec27c5319369c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 2 Sep 2019 18:37:30 +0200 Subject: ARM: s3c: make headers local if possible A lot of header files are only used internally now, so they can be moved to mach-s3c, out of the visibility of drivers. Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20200806182059.2431-40-krzk@kernel.org [krzk: Rebase and fixup leds-s3c24xx driver] Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-s3c/adc-core.h | 24 + arch/arm/mach-s3c/adc.c | 2 +- arch/arm/mach-s3c/bast-ide.c | 2 +- arch/arm/mach-s3c/bast-irq.c | 2 +- arch/arm/mach-s3c/common-smdk-s3c24xx.c | 10 +- arch/arm/mach-s3c/cpu.c | 4 +- arch/arm/mach-s3c/cpu.h | 128 +++++ arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c | 4 +- arch/arm/mach-s3c/cpuidle-s3c64xx.c | 4 +- arch/arm/mach-s3c/crag6410.h | 2 +- arch/arm/mach-s3c/dev-audio-s3c64xx.c | 8 +- arch/arm/mach-s3c/dev-backlight-s3c64xx.c | 4 +- arch/arm/mach-s3c/dev-uart-s3c64xx.c | 4 +- arch/arm/mach-s3c/dev-uart.c | 2 +- arch/arm/mach-s3c/devs.c | 22 +- arch/arm/mach-s3c/devs.h | 96 ++++ arch/arm/mach-s3c/dma-s3c24xx.h | 51 ++ arch/arm/mach-s3c/dma-s3c64xx.h | 57 ++ arch/arm/mach-s3c/dma.h | 9 + arch/arm/mach-s3c/fb.h | 31 ++ arch/arm/mach-s3c/gpio-cfg-helpers.h | 159 ++++++ arch/arm/mach-s3c/gpio-cfg.h | 178 ++++++ arch/arm/mach-s3c/gpio-core.h | 142 +++++ arch/arm/mach-s3c/gpio-samsung-s3c24xx.h | 103 ++++ arch/arm/mach-s3c/gpio-samsung-s3c64xx.h | 94 ++++ arch/arm/mach-s3c/gpio-samsung.c | 18 +- arch/arm/mach-s3c/gpio-samsung.h | 9 + arch/arm/mach-s3c/gta02.h | 2 +- arch/arm/mach-s3c/h1940-bluetooth.c | 6 +- arch/arm/mach-s3c/hardware-s3c24xx.h | 14 + arch/arm/mach-s3c/iic-core.h | 38 ++ arch/arm/mach-s3c/include/mach/dma-s3c24xx.h | 51 -- arch/arm/mach-s3c/include/mach/dma-s3c64xx.h | 57 -- arch/arm/mach-s3c/include/mach/dma.h | 9 - .../mach-s3c/include/mach/gpio-samsung-s3c24xx.h | 103 ---- .../mach-s3c/include/mach/gpio-samsung-s3c64xx.h | 94 ---- arch/arm/mach-s3c/include/mach/gpio-samsung.h | 9 - arch/arm/mach-s3c/include/mach/hardware-s3c24xx.h | 14 - arch/arm/mach-s3c/include/mach/io-s3c24xx.h | 2 +- arch/arm/mach-s3c/include/mach/map-base.h | 42 ++ arch/arm/mach-s3c/include/mach/map-s3c24xx.h | 159 ------ arch/arm/mach-s3c/include/mach/map-s3c64xx.h | 122 ----- arch/arm/mach-s3c/include/mach/map.h | 9 - arch/arm/mach-s3c/include/mach/pm-core-s3c24xx.h | 96 ---- arch/arm/mach-s3c/include/mach/pm-core-s3c64xx.h | 84 --- arch/arm/mach-s3c/include/mach/pm-core.h | 9 - .../arm/mach-s3c/include/mach/regs-clock-s3c24xx.h | 146 ----- .../arm/mach-s3c/include/mach/regs-clock-s3c64xx.h | 34 -- arch/arm/mach-s3c/include/mach/regs-clock.h | 9 - arch/arm/mach-s3c/include/mach/regs-gpio-s3c24xx.h | 608 --------------------- arch/arm/mach-s3c/include/mach/regs-gpio-s3c64xx.h | 188 ------- arch/arm/mach-s3c/include/mach/regs-gpio.h | 9 - arch/arm/mach-s3c/include/mach/regs-irq-s3c24xx.h | 51 -- arch/arm/mach-s3c/include/mach/regs-irq-s3c64xx.h | 15 - arch/arm/mach-s3c/include/mach/regs-irq.h | 9 - .../arm/mach-s3c/include/mach/regs-s3c2443-clock.h | 238 -------- arch/arm/mach-s3c/include/mach/rtc-core-s3c24xx.h | 23 - arch/arm/mach-s3c/include/mach/s3c2412.h | 25 - arch/arm/mach-s3c/include/plat/adc-core.h | 24 - arch/arm/mach-s3c/include/plat/cpu.h | 128 ----- arch/arm/mach-s3c/include/plat/devs.h | 96 ---- arch/arm/mach-s3c/include/plat/fb.h | 31 -- arch/arm/mach-s3c/include/plat/gpio-cfg-helpers.h | 159 ------ arch/arm/mach-s3c/include/plat/gpio-cfg.h | 178 ------ arch/arm/mach-s3c/include/plat/gpio-core.h | 142 ----- arch/arm/mach-s3c/include/plat/iic-core.h | 38 -- arch/arm/mach-s3c/include/plat/keypad.h | 27 - arch/arm/mach-s3c/include/plat/map-base.h | 42 -- arch/arm/mach-s3c/include/plat/map-s3c.h | 70 --- arch/arm/mach-s3c/include/plat/map-s5p.h | 20 - arch/arm/mach-s3c/include/plat/pm-common.h | 40 -- arch/arm/mach-s3c/include/plat/pm.h | 109 ---- arch/arm/mach-s3c/include/plat/pwm-core.h | 19 - arch/arm/mach-s3c/include/plat/regs-adc.h | 64 --- arch/arm/mach-s3c/include/plat/regs-irqtype.h | 17 - arch/arm/mach-s3c/include/plat/sdhci.h | 162 ------ arch/arm/mach-s3c/include/plat/usb-phy.h | 13 - arch/arm/mach-s3c/include/plat/wakeup-mask.h | 39 -- arch/arm/mach-s3c/init.c | 4 +- arch/arm/mach-s3c/iotiming-s3c2410.c | 4 +- arch/arm/mach-s3c/iotiming-s3c2412.c | 4 +- arch/arm/mach-s3c/irq-pm-s3c24xx.c | 16 +- arch/arm/mach-s3c/irq-pm-s3c64xx.c | 8 +- arch/arm/mach-s3c/irq-s3c24xx-fiq.S | 4 +- arch/arm/mach-s3c/irq-s3c24xx.c | 10 +- arch/arm/mach-s3c/keypad.h | 27 + arch/arm/mach-s3c/mach-amlm5900.c | 10 +- arch/arm/mach-s3c/mach-anubis.c | 8 +- arch/arm/mach-s3c/mach-anw6410.c | 12 +- arch/arm/mach-s3c/mach-at2440evb.c | 8 +- arch/arm/mach-s3c/mach-bast.c | 10 +- arch/arm/mach-s3c/mach-crag6410-module.c | 2 +- arch/arm/mach-s3c/mach-crag6410.c | 20 +- arch/arm/mach-s3c/mach-gta02.c | 16 +- arch/arm/mach-s3c/mach-h1940.c | 20 +- arch/arm/mach-s3c/mach-hmt.c | 10 +- arch/arm/mach-s3c/mach-jive.c | 14 +- arch/arm/mach-s3c/mach-mini2440.c | 10 +- arch/arm/mach-s3c/mach-mini6410.c | 14 +- arch/arm/mach-s3c/mach-n30.c | 13 +- arch/arm/mach-s3c/mach-ncp.c | 8 +- arch/arm/mach-s3c/mach-nexcoder.c | 10 +- arch/arm/mach-s3c/mach-osiris-dvs.c | 2 +- arch/arm/mach-s3c/mach-osiris.c | 10 +- arch/arm/mach-s3c/mach-otom.c | 9 +- arch/arm/mach-s3c/mach-qt2410.c | 10 +- arch/arm/mach-s3c/mach-real6410.c | 12 +- arch/arm/mach-s3c/mach-rx1950.c | 16 +- arch/arm/mach-s3c/mach-rx3715.c | 12 +- arch/arm/mach-s3c/mach-s3c2416-dt.c | 6 +- arch/arm/mach-s3c/mach-s3c64xx-dt.c | 4 +- arch/arm/mach-s3c/mach-smartq.c | 14 +- arch/arm/mach-s3c/mach-smartq5.c | 16 +- arch/arm/mach-s3c/mach-smartq7.c | 16 +- arch/arm/mach-s3c/mach-smdk2410.c | 8 +- arch/arm/mach-s3c/mach-smdk2413.c | 12 +- arch/arm/mach-s3c/mach-smdk2416.c | 18 +- arch/arm/mach-s3c/mach-smdk2440.c | 10 +- arch/arm/mach-s3c/mach-smdk2443.c | 6 +- arch/arm/mach-s3c/mach-smdk6400.c | 8 +- arch/arm/mach-s3c/mach-smdk6410.c | 16 +- arch/arm/mach-s3c/mach-tct_hammer.c | 4 +- arch/arm/mach-s3c/mach-vr1000.c | 10 +- arch/arm/mach-s3c/mach-vstms.c | 10 +- arch/arm/mach-s3c/map-s3c.h | 70 +++ arch/arm/mach-s3c/map-s3c24xx.h | 159 ++++++ arch/arm/mach-s3c/map-s3c64xx.h | 122 +++++ arch/arm/mach-s3c/map-s5p.h | 20 + arch/arm/mach-s3c/map.h | 9 + arch/arm/mach-s3c/pl080.c | 4 +- arch/arm/mach-s3c/platformdata.c | 4 +- arch/arm/mach-s3c/pm-common.c | 2 +- arch/arm/mach-s3c/pm-common.h | 40 ++ arch/arm/mach-s3c/pm-core-s3c24xx.h | 96 ++++ arch/arm/mach-s3c/pm-core-s3c64xx.h | 84 +++ arch/arm/mach-s3c/pm-core.h | 9 + arch/arm/mach-s3c/pm-gpio.c | 6 +- arch/arm/mach-s3c/pm-h1940.S | 4 +- arch/arm/mach-s3c/pm-s3c2410.c | 10 +- arch/arm/mach-s3c/pm-s3c2412.c | 8 +- arch/arm/mach-s3c/pm-s3c2416.c | 6 +- arch/arm/mach-s3c/pm-s3c24xx.c | 12 +- arch/arm/mach-s3c/pm-s3c64xx.c | 16 +- arch/arm/mach-s3c/pm.c | 12 +- arch/arm/mach-s3c/pm.h | 109 ++++ arch/arm/mach-s3c/pwm-core.h | 19 + arch/arm/mach-s3c/regs-adc.h | 64 +++ arch/arm/mach-s3c/regs-clock-s3c24xx.h | 146 +++++ arch/arm/mach-s3c/regs-clock-s3c64xx.h | 34 ++ arch/arm/mach-s3c/regs-clock.h | 9 + arch/arm/mach-s3c/regs-gpio-s3c24xx.h | 608 +++++++++++++++++++++ arch/arm/mach-s3c/regs-gpio-s3c64xx.h | 188 +++++++ arch/arm/mach-s3c/regs-gpio.h | 9 + arch/arm/mach-s3c/regs-irq-s3c24xx.h | 51 ++ arch/arm/mach-s3c/regs-irq-s3c64xx.h | 15 + arch/arm/mach-s3c/regs-irq.h | 9 + arch/arm/mach-s3c/regs-irqtype.h | 17 + arch/arm/mach-s3c/regs-mem-s3c24xx.h | 2 +- arch/arm/mach-s3c/regs-s3c2443-clock.h | 238 ++++++++ arch/arm/mach-s3c/rtc-core-s3c24xx.h | 23 + arch/arm/mach-s3c/s3c2410.c | 18 +- arch/arm/mach-s3c/s3c2412.c | 12 +- arch/arm/mach-s3c/s3c2412.h | 25 + arch/arm/mach-s3c/s3c2416.c | 26 +- arch/arm/mach-s3c/s3c2440.c | 14 +- arch/arm/mach-s3c/s3c2442.c | 14 +- arch/arm/mach-s3c/s3c2443.c | 20 +- arch/arm/mach-s3c/s3c244x.c | 12 +- arch/arm/mach-s3c/s3c24xx.c | 16 +- arch/arm/mach-s3c/s3c6400.c | 10 +- arch/arm/mach-s3c/s3c6410.c | 12 +- arch/arm/mach-s3c/s3c64xx.c | 21 +- arch/arm/mach-s3c/sdhci.h | 162 ++++++ arch/arm/mach-s3c/setup-fb-24bpp-s3c64xx.c | 6 +- arch/arm/mach-s3c/setup-i2c-s3c24xx.c | 7 +- arch/arm/mach-s3c/setup-i2c0-s3c64xx.c | 4 +- arch/arm/mach-s3c/setup-i2c1-s3c64xx.c | 4 +- arch/arm/mach-s3c/setup-ide-s3c64xx.c | 9 +- arch/arm/mach-s3c/setup-keypad-s3c64xx.c | 6 +- arch/arm/mach-s3c/setup-sdhci-gpio-s3c24xx.c | 8 +- arch/arm/mach-s3c/setup-sdhci-gpio-s3c64xx.c | 6 +- arch/arm/mach-s3c/setup-spi-s3c24xx.c | 6 +- arch/arm/mach-s3c/setup-spi-s3c64xx.c | 4 +- arch/arm/mach-s3c/setup-ts-s3c24xx.c | 4 +- arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c | 6 +- arch/arm/mach-s3c/simtec-audio.c | 8 +- arch/arm/mach-s3c/simtec-nor.c | 2 +- arch/arm/mach-s3c/simtec-pm.c | 6 +- arch/arm/mach-s3c/simtec-usb.c | 4 +- arch/arm/mach-s3c/sleep-s3c2410.S | 6 +- arch/arm/mach-s3c/sleep-s3c2412.S | 4 +- arch/arm/mach-s3c/sleep-s3c24xx.S | 6 +- arch/arm/mach-s3c/sleep-s3c64xx.S | 4 +- arch/arm/mach-s3c/usb-phy.h | 13 + arch/arm/mach-s3c/wakeup-mask.c | 4 +- arch/arm/mach-s3c/wakeup-mask.h | 39 ++ drivers/leds/leds-s3c24xx.c | 2 - 197 files changed, 4057 insertions(+), 4060 deletions(-) create mode 100644 arch/arm/mach-s3c/adc-core.h create mode 100644 arch/arm/mach-s3c/cpu.h create mode 100644 arch/arm/mach-s3c/devs.h create mode 100644 arch/arm/mach-s3c/dma-s3c24xx.h create mode 100644 arch/arm/mach-s3c/dma-s3c64xx.h create mode 100644 arch/arm/mach-s3c/dma.h create mode 100644 arch/arm/mach-s3c/fb.h create mode 100644 arch/arm/mach-s3c/gpio-cfg-helpers.h create mode 100644 arch/arm/mach-s3c/gpio-cfg.h create mode 100644 arch/arm/mach-s3c/gpio-core.h create mode 100644 arch/arm/mach-s3c/gpio-samsung-s3c24xx.h create mode 100644 arch/arm/mach-s3c/gpio-samsung-s3c64xx.h create mode 100644 arch/arm/mach-s3c/gpio-samsung.h create mode 100644 arch/arm/mach-s3c/hardware-s3c24xx.h create mode 100644 arch/arm/mach-s3c/iic-core.h delete mode 100644 arch/arm/mach-s3c/include/mach/dma-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/dma-s3c64xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/dma.h delete mode 100644 arch/arm/mach-s3c/include/mach/gpio-samsung-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/gpio-samsung-s3c64xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/gpio-samsung.h delete mode 100644 arch/arm/mach-s3c/include/mach/hardware-s3c24xx.h create mode 100644 arch/arm/mach-s3c/include/mach/map-base.h delete mode 100644 arch/arm/mach-s3c/include/mach/map-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/map-s3c64xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/map.h delete mode 100644 arch/arm/mach-s3c/include/mach/pm-core-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/pm-core-s3c64xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/pm-core.h delete mode 100644 arch/arm/mach-s3c/include/mach/regs-clock-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/regs-clock-s3c64xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/regs-clock.h delete mode 100644 arch/arm/mach-s3c/include/mach/regs-gpio-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/regs-gpio-s3c64xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/regs-gpio.h delete mode 100644 arch/arm/mach-s3c/include/mach/regs-irq-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/regs-irq-s3c64xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/regs-irq.h delete mode 100644 arch/arm/mach-s3c/include/mach/regs-s3c2443-clock.h delete mode 100644 arch/arm/mach-s3c/include/mach/rtc-core-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/s3c2412.h delete mode 100644 arch/arm/mach-s3c/include/plat/adc-core.h delete mode 100644 arch/arm/mach-s3c/include/plat/cpu.h delete mode 100644 arch/arm/mach-s3c/include/plat/devs.h delete mode 100644 arch/arm/mach-s3c/include/plat/fb.h delete mode 100644 arch/arm/mach-s3c/include/plat/gpio-cfg-helpers.h delete mode 100644 arch/arm/mach-s3c/include/plat/gpio-cfg.h delete mode 100644 arch/arm/mach-s3c/include/plat/gpio-core.h delete mode 100644 arch/arm/mach-s3c/include/plat/iic-core.h delete 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arch/arm/mach-s3c/map.h create mode 100644 arch/arm/mach-s3c/pm-common.h create mode 100644 arch/arm/mach-s3c/pm-core-s3c24xx.h create mode 100644 arch/arm/mach-s3c/pm-core-s3c64xx.h create mode 100644 arch/arm/mach-s3c/pm-core.h create mode 100644 arch/arm/mach-s3c/pm.h create mode 100644 arch/arm/mach-s3c/pwm-core.h create mode 100644 arch/arm/mach-s3c/regs-adc.h create mode 100644 arch/arm/mach-s3c/regs-clock-s3c24xx.h create mode 100644 arch/arm/mach-s3c/regs-clock-s3c64xx.h create mode 100644 arch/arm/mach-s3c/regs-clock.h create mode 100644 arch/arm/mach-s3c/regs-gpio-s3c24xx.h create mode 100644 arch/arm/mach-s3c/regs-gpio-s3c64xx.h create mode 100644 arch/arm/mach-s3c/regs-gpio.h create mode 100644 arch/arm/mach-s3c/regs-irq-s3c24xx.h create mode 100644 arch/arm/mach-s3c/regs-irq-s3c64xx.h create mode 100644 arch/arm/mach-s3c/regs-irq.h create mode 100644 arch/arm/mach-s3c/regs-irqtype.h create mode 100644 arch/arm/mach-s3c/regs-s3c2443-clock.h create mode 100644 arch/arm/mach-s3c/rtc-core-s3c24xx.h create mode 100644 arch/arm/mach-s3c/s3c2412.h create mode 100644 arch/arm/mach-s3c/sdhci.h create mode 100644 arch/arm/mach-s3c/usb-phy.h create mode 100644 arch/arm/mach-s3c/wakeup-mask.h (limited to 'arch/arm/mach-s3c/init.c') diff --git a/arch/arm/mach-s3c/adc-core.h b/arch/arm/mach-s3c/adc-core.h new file mode 100644 index 000000000000..039f6862b6a7 --- /dev/null +++ b/arch/arm/mach-s3c/adc-core.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Samsung ADC Controller core functions + */ + +#ifndef __ASM_PLAT_ADC_CORE_H +#define __ASM_PLAT_ADC_CORE_H __FILE__ + +/* These functions are only for use with the core support code, such as + * the cpu specific initialisation code + */ + +/* re-define device name depending on support. */ +static inline void s3c_adc_setname(char *name) +{ +#if defined(CONFIG_SAMSUNG_DEV_ADC) || defined(CONFIG_PLAT_S3C24XX) + s3c_device_adc.name = name; +#endif +} + +#endif /* __ASM_PLAT_ADC_CORE_H */ diff --git a/arch/arm/mach-s3c/adc.c b/arch/arm/mach-s3c/adc.c index e35e04417cce..0232520d3c13 100644 --- a/arch/arm/mach-s3c/adc.c +++ b/arch/arm/mach-s3c/adc.c @@ -19,7 +19,7 @@ #include #include -#include +#include "regs-adc.h" #include /* This driver is designed to control the usage of the ADC block between diff --git a/arch/arm/mach-s3c/bast-ide.c b/arch/arm/mach-s3c/bast-ide.c index ee6fbb407640..da64db1811d8 100644 --- a/arch/arm/mach-s3c/bast-ide.c +++ b/arch/arm/mach-s3c/bast-ide.c @@ -19,7 +19,7 @@ #include #include -#include +#include "map.h" #include #include "bast.h" diff --git a/arch/arm/mach-s3c/bast-irq.c b/arch/arm/mach-s3c/bast-irq.c index 141a35d58dd7..d299f124e6dc 100644 --- a/arch/arm/mach-s3c/bast-irq.c +++ b/arch/arm/mach-s3c/bast-irq.c @@ -15,7 +15,7 @@ #include #include -#include +#include "regs-irq.h" #include #include "bast.h" diff --git a/arch/arm/mach-s3c/common-smdk-s3c24xx.c b/arch/arm/mach-s3c/common-smdk-s3c24xx.c index e3281dc3af13..353bc22ce448 100644 --- a/arch/arm/mach-s3c/common-smdk-s3c24xx.c +++ b/arch/arm/mach-s3c/common-smdk-s3c24xx.c @@ -31,14 +31,14 @@ #include #include -#include -#include +#include "regs-gpio.h" +#include "gpio-samsung.h" #include #include -#include -#include -#include +#include "gpio-cfg.h" +#include "devs.h" +#include "pm.h" #include "common-smdk-s3c24xx.h" diff --git a/arch/arm/mach-s3c/cpu.c b/arch/arm/mach-s3c/cpu.c index 8acba21bbf4b..6e9772555f0d 100644 --- a/arch/arm/mach-s3c/cpu.c +++ b/arch/arm/mach-s3c/cpu.c @@ -10,8 +10,8 @@ #include #include -#include -#include +#include +#include "cpu.h" unsigned long samsung_cpu_id; diff --git a/arch/arm/mach-s3c/cpu.h b/arch/arm/mach-s3c/cpu.h new file mode 100644 index 000000000000..20ff98d05c53 --- /dev/null +++ b/arch/arm/mach-s3c/cpu.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Copyright (c) 2004-2005 Simtec Electronics + * Ben Dooks + * + * Header file for Samsung CPU support + */ + +/* todo - fix when rmk changes iodescs to use `void __iomem *` */ + +#ifndef __SAMSUNG_PLAT_CPU_H +#define __SAMSUNG_PLAT_CPU_H + +extern unsigned long samsung_cpu_id; + +#define S3C2410_CPU_ID 0x32410000 +#define S3C2410_CPU_MASK 0xFFFFFFFF + +#define S3C24XX_CPU_ID 0x32400000 +#define S3C24XX_CPU_MASK 0xFFF00000 + +#define S3C2412_CPU_ID 0x32412000 +#define S3C2412_CPU_MASK 0xFFFFF000 + +#define S3C6400_CPU_ID 0x36400000 +#define S3C6410_CPU_ID 0x36410000 +#define S3C64XX_CPU_MASK 0xFFFFF000 + +#define S5PV210_CPU_ID 0x43110000 +#define S5PV210_CPU_MASK 0xFFFFF000 + +#define IS_SAMSUNG_CPU(name, id, mask) \ +static inline int is_samsung_##name(void) \ +{ \ + return ((samsung_cpu_id & mask) == (id & mask)); \ +} + +IS_SAMSUNG_CPU(s3c2410, S3C2410_CPU_ID, S3C2410_CPU_MASK) +IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK) +IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK) +IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) +IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK) + +#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ + defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ + defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \ + defined(CONFIG_CPU_S3C2443) +# define soc_is_s3c24xx() is_samsung_s3c24xx() +# define soc_is_s3c2410() is_samsung_s3c2410() +#else +# define soc_is_s3c24xx() 0 +# define soc_is_s3c2410() 0 +#endif + +#if defined(CONFIG_CPU_S3C2412) +# define soc_is_s3c2412() is_samsung_s3c2412() +#else +# define soc_is_s3c2412() 0 +#endif + +#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) +# define soc_is_s3c6400() is_samsung_s3c6400() +# define soc_is_s3c6410() is_samsung_s3c6410() +# define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410()) +#else +# define soc_is_s3c6400() 0 +# define soc_is_s3c6410() 0 +# define soc_is_s3c64xx() 0 +#endif + +#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } + +#ifndef KHZ +#define KHZ (1000) +#endif + +#ifndef MHZ +#define MHZ (1000*1000) +#endif + +#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000) + +/* forward declaration */ +struct s3c24xx_uart_resources; +struct platform_device; +struct s3c2410_uartcfg; +struct map_desc; + +/* per-cpu initialisation function table. */ + +struct cpu_table { + unsigned long idcode; + unsigned long idmask; + void (*map_io)(void); + void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); + void (*init_clocks)(int xtal); + int (*init)(void); + const char *name; +}; + +extern void s3c_init_cpu(unsigned long idcode, + struct cpu_table *cpus, unsigned int cputab_size); + +/* core initialisation functions */ + +extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); + +extern void s3c64xx_init_cpu(void); + +extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +extern void s3c24xx_init_clocks(int xtal); + +extern void s3c24xx_init_uartdevs(char *name, + struct s3c24xx_uart_resources *res, + struct s3c2410_uartcfg *cfg, int no); + +extern struct syscore_ops s3c2410_pm_syscore_ops; +extern struct syscore_ops s3c2412_pm_syscore_ops; +extern struct syscore_ops s3c2416_pm_syscore_ops; +extern struct syscore_ops s3c244x_pm_syscore_ops; + +extern struct bus_type s3c6410_subsys; + +#endif diff --git a/arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c b/arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c index 17b70d635236..c1784d8facdf 100644 --- a/arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c +++ b/arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c @@ -12,8 +12,8 @@ #include #include -#include -#include +#include "map.h" +#include "regs-clock.h" #include diff --git a/arch/arm/mach-s3c/cpuidle-s3c64xx.c b/arch/arm/mach-s3c/cpuidle-s3c64xx.c index a629f4d2fa3b..b1c5f43d4922 100644 --- a/arch/arm/mach-s3c/cpuidle-s3c64xx.c +++ b/arch/arm/mach-s3c/cpuidle-s3c64xx.c @@ -13,8 +13,8 @@ #include -#include -#include +#include "cpu.h" +#include "map.h" #include "regs-sys-s3c64xx.h" #include "regs-syscon-power-s3c64xx.h" diff --git a/arch/arm/mach-s3c/crag6410.h b/arch/arm/mach-s3c/crag6410.h index 00d9aa114aa7..f39ea2ca7a75 100644 --- a/arch/arm/mach-s3c/crag6410.h +++ b/arch/arm/mach-s3c/crag6410.h @@ -8,7 +8,7 @@ #ifndef MACH_CRAG6410_H #define MACH_CRAG6410_H -#include +#include "gpio-samsung.h" #define GLENFARCLAS_PMIC_IRQ_BASE IRQ_BOARD_START #define BANFF_PMIC_IRQ_BASE (IRQ_BOARD_START + 64) diff --git a/arch/arm/mach-s3c/dev-audio-s3c64xx.c b/arch/arm/mach-s3c/dev-audio-s3c64xx.c index 1d3124db6afc..fc2f077afd24 100644 --- a/arch/arm/mach-s3c/dev-audio-s3c64xx.c +++ b/arch/arm/mach-s3c/dev-audio-s3c64xx.c @@ -11,12 +11,12 @@ #include #include -#include +#include "map.h" -#include +#include "devs.h" #include -#include -#include +#include "gpio-cfg.h" +#include "gpio-samsung.h" static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev) { diff --git a/arch/arm/mach-s3c/dev-backlight-s3c64xx.c b/arch/arm/mach-s3c/dev-backlight-s3c64xx.c index 53bf14f5467f..65488b61e50c 100644 --- a/arch/arm/mach-s3c/dev-backlight-s3c64xx.c +++ b/arch/arm/mach-s3c/dev-backlight-s3c64xx.c @@ -11,8 +11,8 @@ #include #include -#include -#include +#include "devs.h" +#include "gpio-cfg.h" #include "backlight-s3c64xx.h" diff --git a/arch/arm/mach-s3c/dev-uart-s3c64xx.c b/arch/arm/mach-s3c/dev-uart-s3c64xx.c index 021a2b7926fa..8288e8d6c092 100644 --- a/arch/arm/mach-s3c/dev-uart-s3c64xx.c +++ b/arch/arm/mach-s3c/dev-uart-s3c64xx.c @@ -15,10 +15,10 @@ #include #include -#include +#include "map.h" #include -#include +#include "devs.h" /* Serial port registrations */ diff --git a/arch/arm/mach-s3c/dev-uart.c b/arch/arm/mach-s3c/dev-uart.c index 7476a5dbae77..3d1f7f2fd7c7 100644 --- a/arch/arm/mach-s3c/dev-uart.c +++ b/arch/arm/mach-s3c/dev-uart.c @@ -10,7 +10,7 @@ #include #include -#include +#include "devs.h" /* uart devices */ diff --git a/arch/arm/mach-s3c/devs.c b/arch/arm/mach-s3c/devs.c index e23204132b27..06dec64848f9 100644 --- a/arch/arm/mach-s3c/devs.c +++ b/arch/arm/mach-s3c/devs.c @@ -39,31 +39,31 @@ #include #include -#include -#include +#include "map.h" +#include "gpio-samsung.h" +#include "gpio-cfg.h" #ifdef CONFIG_PLAT_S3C24XX -#include +#include "regs-s3c2443-clock.h" #endif /* CONFIG_PLAT_S3C24XX */ -#include -#include -#include +#include "cpu.h" +#include "devs.h" #include #include -#include +#include "fb.h" #include #include #include -#include +#include "keypad.h" #include #include -#include -#include +#include "pwm-core.h" +#include "sdhci.h" #include #include #include -#include +#include "usb-phy.h" #include #include diff --git a/arch/arm/mach-s3c/devs.h b/arch/arm/mach-s3c/devs.h new file mode 100644 index 000000000000..02b0c5750572 --- /dev/null +++ b/arch/arm/mach-s3c/devs.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Copyright (c) 2004 Simtec Electronics + * Ben Dooks + * + * Header file for s3c2410 standard platform devices + */ + +#ifndef __PLAT_DEVS_H +#define __PLAT_DEVS_H __FILE__ + +#include + +struct s3c24xx_uart_resources { + struct resource *resources; + unsigned long nr_resources; +}; + +extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; +extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; + +extern struct platform_device *s3c24xx_uart_devs[]; +extern struct platform_device *s3c24xx_uart_src[]; + +extern struct platform_device s3c64xx_device_ac97; +extern struct platform_device s3c64xx_device_iis0; +extern struct platform_device s3c64xx_device_iis1; +extern struct platform_device s3c64xx_device_iisv4; +extern struct platform_device s3c64xx_device_onenand1; +extern struct platform_device s3c64xx_device_pcm0; +extern struct platform_device s3c64xx_device_pcm1; +extern struct platform_device s3c64xx_device_spi0; +extern struct platform_device s3c64xx_device_spi1; +extern struct platform_device s3c64xx_device_spi2; + +extern struct platform_device s3c_device_adc; +extern struct platform_device s3c_device_cfcon; +extern struct platform_device s3c_device_fb; +extern struct platform_device s3c_device_hwmon; +extern struct platform_device s3c_device_hsmmc0; +extern struct platform_device s3c_device_hsmmc1; +extern struct platform_device s3c_device_hsmmc2; +extern struct platform_device s3c_device_hsmmc3; +extern struct platform_device s3c_device_i2c0; +extern struct platform_device s3c_device_i2c1; +extern struct platform_device s3c_device_i2c2; +extern struct platform_device s3c_device_i2c3; +extern struct platform_device s3c_device_i2c4; +extern struct platform_device s3c_device_i2c5; +extern struct platform_device s3c_device_i2c6; +extern struct platform_device s3c_device_i2c7; +extern struct platform_device s3c_device_iis; +extern struct platform_device s3c_device_lcd; +extern struct platform_device s3c_device_nand; +extern struct platform_device s3c_device_ohci; +extern struct platform_device s3c_device_onenand; +extern struct platform_device s3c_device_rtc; +extern struct platform_device s3c_device_sdi; +extern struct platform_device s3c_device_spi0; +extern struct platform_device s3c_device_spi1; +extern struct platform_device s3c_device_ts; +extern struct platform_device s3c_device_timer[]; +extern struct platform_device s3c_device_usbgadget; +extern struct platform_device s3c_device_usb_hsotg; +extern struct platform_device s3c_device_usb_hsudc; +extern struct platform_device s3c_device_wdt; + +extern struct platform_device samsung_asoc_idma; +extern struct platform_device samsung_device_keypad; +extern struct platform_device samsung_device_pwm; + +/* s3c2440 specific devices */ + +#ifdef CONFIG_CPU_S3C2440 + +extern struct platform_device s3c_device_camif; +extern struct platform_device s3c_device_ac97; + +#endif + +/** + * s3c_set_platdata() - helper for setting platform data + * @pd: The default platform data for this device. + * @pdsize: The size of the platform data. + * @pdev: Pointer to the device to fill in. + * + * This helper replaces a number of calls that copy and then set the + * platform data of the device. + */ +extern void *s3c_set_platdata(void *pd, size_t pdsize, + struct platform_device *pdev); + +#endif /* __PLAT_DEVS_H */ diff --git a/arch/arm/mach-s3c/dma-s3c24xx.h b/arch/arm/mach-s3c/dma-s3c24xx.h new file mode 100644 index 000000000000..25fc9c258fc1 --- /dev/null +++ b/arch/arm/mach-s3c/dma-s3c24xx.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2003-2006 Simtec Electronics + * Ben Dooks + * + * Samsung S3C24XX DMA support + */ + +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H __FILE__ + +#include + +/* We use `virtual` dma channels to hide the fact we have only a limited + * number of DMA channels, and not of all of them (dependent on the device) + * can be attached to any DMA source. We therefore let the DMA core handle + * the allocation of hardware channels to clients. +*/ + +enum dma_ch { + DMACH_XD0 = 0, + DMACH_XD1, + DMACH_SDI, + DMACH_SPI0, + DMACH_SPI1, + DMACH_UART0, + DMACH_UART1, + DMACH_UART2, + DMACH_TIMER, + DMACH_I2S_IN, + DMACH_I2S_OUT, + DMACH_PCM_IN, + DMACH_PCM_OUT, + DMACH_MIC_IN, + DMACH_USB_EP1, + DMACH_USB_EP2, + DMACH_USB_EP3, + DMACH_USB_EP4, + DMACH_UART0_SRC2, /* s3c2412 second uart sources */ + DMACH_UART1_SRC2, + DMACH_UART2_SRC2, + DMACH_UART3, /* s3c2443 has extra uart */ + DMACH_UART3_SRC2, + DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */ + DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */ + DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */ + DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */ + DMACH_MAX, /* the end entry */ +}; + +#endif /* __ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-s3c/dma-s3c64xx.h b/arch/arm/mach-s3c/dma-s3c64xx.h new file mode 100644 index 000000000000..40ca8de21096 --- /dev/null +++ b/arch/arm/mach-s3c/dma-s3c64xx.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* linux/arch/arm/mach-s3c6400/include/mach/dma.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * S3C6400 - DMA support + */ + +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H __FILE__ + +#define S3C64XX_DMA_CHAN(name) ((unsigned long)(name)) + +/* DMA0/SDMA0 */ +#define DMACH_UART0 "uart0_tx" +#define DMACH_UART0_SRC2 "uart0_rx" +#define DMACH_UART1 "uart1_tx" +#define DMACH_UART1_SRC2 "uart1_rx" +#define DMACH_UART2 "uart2_tx" +#define DMACH_UART2_SRC2 "uart2_rx" +#define DMACH_UART3 "uart3_tx" +#define DMACH_UART3_SRC2 "uart3_rx" +#define DMACH_PCM0_TX "pcm0_tx" +#define DMACH_PCM0_RX "pcm0_rx" +#define DMACH_I2S0_OUT "i2s0_tx" +#define DMACH_I2S0_IN "i2s0_rx" +#define DMACH_SPI0_TX S3C64XX_DMA_CHAN("spi0_tx") +#define DMACH_SPI0_RX S3C64XX_DMA_CHAN("spi0_rx") +#define DMACH_HSI_I2SV40_TX "i2s2_tx" +#define DMACH_HSI_I2SV40_RX "i2s2_rx" + +/* DMA1/SDMA1 */ +#define DMACH_PCM1_TX "pcm1_tx" +#define DMACH_PCM1_RX "pcm1_rx" +#define DMACH_I2S1_OUT "i2s1_tx" +#define DMACH_I2S1_IN "i2s1_rx" +#define DMACH_SPI1_TX S3C64XX_DMA_CHAN("spi1_tx") +#define DMACH_SPI1_RX S3C64XX_DMA_CHAN("spi1_rx") +#define DMACH_AC97_PCMOUT "ac97_out" +#define DMACH_AC97_PCMIN "ac97_in" +#define DMACH_AC97_MICIN "ac97_mic" +#define DMACH_PWM "pwm" +#define DMACH_IRDA "irda" +#define DMACH_EXTERNAL "external" +#define DMACH_SECURITY_RX "sec_rx" +#define DMACH_SECURITY_TX "sec_tx" + +enum dma_ch { + DMACH_MAX = 32 +}; + +#include + +#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c/dma.h b/arch/arm/mach-s3c/dma.h new file mode 100644 index 000000000000..59a4578c5f00 --- /dev/null +++ b/arch/arm/mach-s3c/dma.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "dma-s3c24xx.h" +#endif + +#ifdef CONFIG_ARCH_S3C64XX +#include "dma-s3c64xx.h" +#endif diff --git a/arch/arm/mach-s3c/fb.h b/arch/arm/mach-s3c/fb.h new file mode 100644 index 000000000000..615d381ae32e --- /dev/null +++ b/arch/arm/mach-s3c/fb.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C - FB platform data definitions + */ + +#ifndef __PLAT_S3C_FB_H +#define __PLAT_S3C_FB_H __FILE__ + +#include + +/** + * s3c_fb_set_platdata() - Setup the FB device with platform data. + * @pd: The platform data to set. The data is copied from the passed structure + * so the machine data can mark the data __initdata so that any unused + * machines will end up dumping their data at runtime. + */ +extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); + +/** + * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD + * + * Initialise the GPIO for an 24bpp LCD display on the RGB interface. + */ +extern void s3c64xx_fb_gpio_setup_24bpp(void); + +#endif /* __PLAT_S3C_FB_H */ diff --git a/arch/arm/mach-s3c/gpio-cfg-helpers.h b/arch/arm/mach-s3c/gpio-cfg-helpers.h new file mode 100644 index 000000000000..db0c56f5ca15 --- /dev/null +++ b/arch/arm/mach-s3c/gpio-cfg-helpers.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * Samsung Platform - GPIO pin configuration helper definitions + */ + +/* This is meant for core cpu support, machine or other driver files + * should not be including this header. + */ + +#ifndef __PLAT_GPIO_CFG_HELPERS_H +#define __PLAT_GPIO_CFG_HELPERS_H __FILE__ + +/* As a note, all gpio configuration functions are entered exclusively, either + * with the relevant lock held or the system prevented from doing anything else + * by disabling interrupts. +*/ + +static inline int samsung_gpio_do_setcfg(struct samsung_gpio_chip *chip, + unsigned int off, unsigned int config) +{ + return (chip->config->set_config)(chip, off, config); +} + +static inline unsigned samsung_gpio_do_getcfg(struct samsung_gpio_chip *chip, + unsigned int off) +{ + return (chip->config->get_config)(chip, off); +} + +static inline int samsung_gpio_do_setpull(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull) +{ + return (chip->config->set_pull)(chip, off, pull); +} + +static inline samsung_gpio_pull_t samsung_gpio_do_getpull(struct samsung_gpio_chip *chip, + unsigned int off) +{ + return chip->config->get_pull(chip, off); +} + +/* Pull-{up,down} resistor controls. + * + * S3C2410,S3C2440 = Pull-UP, + * S3C2412,S3C2413 = Pull-Down + * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef] + * S3C2443 = Pull-Both [not same as S3C6400] + */ + +/** + * s3c24xx_gpio_setpull_1up() - Pull configuration for choice of up or none. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @param: pull: The pull mode being requested. + * + * This is a helper function for the case where we have GPIOs with one + * bit configuring the presence of a pull-up resistor. + */ +extern int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull); + +/** + * s3c24xx_gpio_setpull_1down() - Pull configuration for choice of down or none + * @chip: The gpio chip that is being configured + * @off: The offset for the GPIO being configured + * @param: pull: The pull mode being requested + * + * This is a helper function for the case where we have GPIOs with one + * bit configuring the presence of a pull-down resistor. + */ +extern int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull); + +/** + * samsung_gpio_setpull_upown() - Pull configuration for choice of up, + * down or none + * + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @param: pull: The pull mode being requested. + * + * This is a helper function for the case where we have GPIOs with two + * bits configuring the presence of a pull resistor, in the following + * order: + * 00 = No pull resistor connected + * 01 = Pull-up resistor connected + * 10 = Pull-down resistor connected + */ +extern int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull); + +/** + * samsung_gpio_getpull_updown() - Get configuration for choice of up, + * down or none + * + * @chip: The gpio chip that the GPIO pin belongs to + * @off: The offset to the pin to get the configuration of. + * + * This helper function reads the state of the pull-{up,down} resistor + * for the given GPIO in the same case as samsung_gpio_setpull_upown. +*/ +extern samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip, + unsigned int off); + +/** + * s3c24xx_gpio_getpull_1up() - Get configuration for choice of up or none + * @chip: The gpio chip that the GPIO pin belongs to + * @off: The offset to the pin to get the configuration of. + * + * This helper function reads the state of the pull-up resistor for the + * given GPIO in the same case as s3c24xx_gpio_setpull_1up. +*/ +extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip, + unsigned int off); + +/** + * s3c24xx_gpio_getpull_1down() - Get configuration for choice of down or none + * @chip: The gpio chip that the GPIO pin belongs to + * @off: The offset to the pin to get the configuration of. + * + * This helper function reads the state of the pull-down resistor for the + * given GPIO in the same case as s3c24xx_gpio_setpull_1down. +*/ +extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip, + unsigned int off); + +/** + * s3c2443_gpio_setpull() - Pull configuration for s3c2443. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @param: pull: The pull mode being requested. + * + * This is a helper function for the case where we have GPIOs with two + * bits configuring the presence of a pull resistor, in the following + * order: + * 00 = Pull-up resistor connected + * 10 = Pull-down resistor connected + * x1 = No pull up resistor + */ +extern int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull); + +/** + * s3c2443_gpio_getpull() - Get configuration for s3c2443 pull resistors + * @chip: The gpio chip that the GPIO pin belongs to. + * @off: The offset to the pin to get the configuration of. + * + * This helper function reads the state of the pull-{up,down} resistor for the + * given GPIO in the same case as samsung_gpio_setpull_upown. +*/ +extern samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip, + unsigned int off); + +#endif /* __PLAT_GPIO_CFG_HELPERS_H */ diff --git a/arch/arm/mach-s3c/gpio-cfg.h b/arch/arm/mach-s3c/gpio-cfg.h new file mode 100644 index 000000000000..469c220e092b --- /dev/null +++ b/arch/arm/mach-s3c/gpio-cfg.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C Platform - GPIO pin configuration + */ + +/* This file contains the necessary definitions to get the basic gpio + * pin configuration done such as setting a pin to input or output or + * changing the pull-{up,down} configurations. + */ + +/* Note, this interface is being added to the s3c64xx arch first and will + * be added to the s3c24xx systems later. + */ + +#ifndef __PLAT_GPIO_CFG_H +#define __PLAT_GPIO_CFG_H __FILE__ + +#include + +typedef unsigned int __bitwise samsung_gpio_pull_t; + +/* forward declaration if gpio-core.h hasn't been included */ +struct samsung_gpio_chip; + +/** + * struct samsung_gpio_cfg GPIO configuration + * @cfg_eint: Configuration setting when used for external interrupt source + * @get_pull: Read the current pull configuration for the GPIO + * @set_pull: Set the current pull configuration for the GPIO + * @set_config: Set the current configuration for the GPIO + * @get_config: Read the current configuration for the GPIO + * + * Each chip can have more than one type of GPIO bank available and some + * have different capabilites even when they have the same control register + * layouts. Provide an point to vector control routine and provide any + * per-bank configuration information that other systems such as the + * external interrupt code will need. + * + * @sa samsung_gpio_cfgpin + * @sa s3c_gpio_getcfg + * @sa s3c_gpio_setpull + * @sa s3c_gpio_getpull + */ +struct samsung_gpio_cfg { + unsigned int cfg_eint; + + samsung_gpio_pull_t (*get_pull)(struct samsung_gpio_chip *chip, unsigned offs); + int (*set_pull)(struct samsung_gpio_chip *chip, unsigned offs, + samsung_gpio_pull_t pull); + + unsigned (*get_config)(struct samsung_gpio_chip *chip, unsigned offs); + int (*set_config)(struct samsung_gpio_chip *chip, unsigned offs, + unsigned config); +}; + +#define S3C_GPIO_SPECIAL_MARK (0xfffffff0) +#define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x)) + +/* Defines for generic pin configurations */ +#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0)) +#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1)) +#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x)) + +#define samsung_gpio_is_cfg_special(_cfg) \ + (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK) + +/** + * s3c_gpio_cfgpin() - Change the GPIO function of a pin. + * @pin pin The pin number to configure. + * @to to The configuration for the pin's function. + * + * Configure which function is actually connected to the external + * pin, such as an gpio input, output or some form of special function + * connected to an internal peripheral block. + * + * The @to parameter can be one of the generic S3C_GPIO_INPUT, S3C_GPIO_OUTPUT + * or S3C_GPIO_SFN() to indicate one of the possible values that the helper + * will then generate the correct bit mask and shift for the configuration. + * + * If a bank of GPIOs all needs to be set to special-function 2, then + * the following code will work: + * + * for (gpio = start; gpio < end; gpio++) + * s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + * + * The @to parameter can also be a specific value already shifted to the + * correct position in the control register, although these are discouraged + * in newer kernels and are only being kept for compatibility. + */ +extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to); + +/** + * s3c_gpio_getcfg - Read the current function for a GPIO pin + * @pin: The pin to read the configuration value for. + * + * Read the configuration state of the given @pin, returning a value that + * could be passed back to s3c_gpio_cfgpin(). + * + * @sa s3c_gpio_cfgpin + */ +extern unsigned s3c_gpio_getcfg(unsigned int pin); + +/** + * s3c_gpio_cfgpin_range() - Change the GPIO function for configuring pin range + * @start: The pin number to start at + * @nr: The number of pins to configure from @start. + * @cfg: The configuration for the pin's function + * + * Call s3c_gpio_cfgpin() for the @nr pins starting at @start. + * + * @sa s3c_gpio_cfgpin. + */ +extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, + unsigned int cfg); + +/* Define values for the pull-{up,down} available for each gpio pin. + * + * These values control the state of the weak pull-{up,down} resistors + * available on most pins on the S3C series. Not all chips support both + * up or down settings, and it may be dependent on the chip that is being + * used to whether the particular mode is available. + */ +#define S3C_GPIO_PULL_NONE ((__force samsung_gpio_pull_t)0x00) +#define S3C_GPIO_PULL_DOWN ((__force samsung_gpio_pull_t)0x01) +#define S3C_GPIO_PULL_UP ((__force samsung_gpio_pull_t)0x02) + +/** + * s3c_gpio_setpull() - set the state of a gpio pin pull resistor + * @pin: The pin number to configure the pull resistor. + * @pull: The configuration for the pull resistor. + * + * This function sets the state of the pull-{up,down} resistor for the + * specified pin. It will return 0 if successful, or a negative error + * code if the pin cannot support the requested pull setting. + * + * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP. +*/ +extern int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull); + +/** + * s3c_gpio_getpull() - get the pull resistor state of a gpio pin + * @pin: The pin number to get the settings for + * + * Read the pull resistor value for the specified pin. +*/ +extern samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin); + +/* configure `all` aspects of an gpio */ + +/** + * s3c_gpio_cfgall_range() - configure range of gpio functtion and pull. + * @start: The gpio number to start at. + * @nr: The number of gpio to configure from @start. + * @cfg: The configuration to use + * @pull: The pull setting to use. + * + * Run s3c_gpio_cfgpin() and s3c_gpio_setpull() over the gpio range starting + * @gpio and running for @size. + * + * @sa s3c_gpio_cfgpin + * @sa s3c_gpio_setpull + * @sa s3c_gpio_cfgpin_range + */ +extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, + unsigned int cfg, samsung_gpio_pull_t pull); + +static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size, + unsigned int cfg) +{ + return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE); +} + +#endif /* __PLAT_GPIO_CFG_H */ diff --git a/arch/arm/mach-s3c/gpio-core.h b/arch/arm/mach-s3c/gpio-core.h new file mode 100644 index 000000000000..b361c8c0d669 --- /dev/null +++ b/arch/arm/mach-s3c/gpio-core.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C Platform - GPIO core + */ + +#ifndef __PLAT_SAMSUNG_GPIO_CORE_H +#define __PLAT_SAMSUNG_GPIO_CORE_H + +/* Bring in machine-local definitions, especially S3C_GPIO_END */ +#include "gpio-samsung.h" +#include + +#define GPIOCON_OFF (0x00) +#define GPIODAT_OFF (0x04) + +#define con_4bit_shift(__off) ((__off) * 4) + +/* Define the core gpiolib support functions that the s3c platforms may + * need to extend or change depending on the hardware and the s3c chip + * selected at build or found at run time. + * + * These definitions are not intended for driver inclusion, there is + * nothing here that should not live outside the platform and core + * specific code. +*/ + +struct samsung_gpio_chip; + +/** + * struct samsung_gpio_pm - power management (suspend/resume) information + * @save: Routine to save the state of the GPIO block + * @resume: Routine to resume the GPIO block. + */ +struct samsung_gpio_pm { + void (*save)(struct samsung_gpio_chip *chip); + void (*resume)(struct samsung_gpio_chip *chip); +}; + +struct samsung_gpio_cfg; + +/** + * struct samsung_gpio_chip - wrapper for specific implementation of gpio + * @chip: The chip structure to be exported via gpiolib. + * @base: The base pointer to the gpio configuration registers. + * @group: The group register number for gpio interrupt support. + * @irq_base: The base irq number. + * @config: special function and pull-resistor control information. + * @lock: Lock for exclusive access to this gpio bank. + * @pm_save: Save information for suspend/resume support. + * @bitmap_gpio_int: Bitmap for representing GPIO interrupt or not. + * + * This wrapper provides the necessary information for the Samsung + * specific gpios being registered with gpiolib. + * + * The lock protects each gpio bank from multiple access of the shared + * configuration registers, or from reading of data whilst another thread + * is writing to the register set. + * + * Each chip has its own lock to avoid any contention between different + * CPU cores trying to get one lock for different GPIO banks, where each + * bank of GPIO has its own register space and configuration registers. + */ +struct samsung_gpio_chip { + struct gpio_chip chip; + struct samsung_gpio_cfg *config; + struct samsung_gpio_pm *pm; + void __iomem *base; + int irq_base; + int group; + spinlock_t lock; +#ifdef CONFIG_PM + u32 pm_save[4]; +#endif + u32 bitmap_gpio_int; +}; + +static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc) +{ + return container_of(gpc, struct samsung_gpio_chip, chip); +} + +/** + * samsung_gpiolib_to_irq - convert gpio pin to irq number + * @chip: The gpio chip that the pin belongs to. + * @offset: The offset of the pin in the chip. + * + * This helper returns the irq number calculated from the chip->irq_base and + * the provided offset. + */ +extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset); + +/* exported for core SoC support to change */ +extern struct samsung_gpio_cfg s3c24xx_gpiocfg_default; + +#ifdef CONFIG_S3C_GPIO_TRACK +extern struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END]; + +static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int chip) +{ + return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; +} +#else +/* machine specific code should provide samsung_gpiolib_getchip */ + +extern struct samsung_gpio_chip s3c24xx_gpios[]; + +static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin) +{ + struct samsung_gpio_chip *chip; + + if (pin > S3C_GPIO_END) + return NULL; + + chip = &s3c24xx_gpios[pin/32]; + return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL; +} + +static inline void s3c_gpiolib_track(struct samsung_gpio_chip *chip) { } +#endif + +#ifdef CONFIG_PM +extern struct samsung_gpio_pm samsung_gpio_pm_1bit; +extern struct samsung_gpio_pm samsung_gpio_pm_2bit; +extern struct samsung_gpio_pm samsung_gpio_pm_4bit; +#define __gpio_pm(x) x +#else +#define samsung_gpio_pm_1bit NULL +#define samsung_gpio_pm_2bit NULL +#define samsung_gpio_pm_4bit NULL +#define __gpio_pm(x) NULL + +#endif /* CONFIG_PM */ + +/* locking wrappers to deal with multiple access to the same gpio bank */ +#define samsung_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) +#define samsung_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) + +#endif /* __PLAT_SAMSUNG_GPIO_CORE_H */ diff --git a/arch/arm/mach-s3c/gpio-samsung-s3c24xx.h b/arch/arm/mach-s3c/gpio-samsung-s3c24xx.h new file mode 100644 index 000000000000..c29fdc95f883 --- /dev/null +++ b/arch/arm/mach-s3c/gpio-samsung-s3c24xx.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C2410 - GPIO lib support + */ + +/* some boards require extra gpio capacity to support external + * devices that need GPIO. + */ + +#ifndef GPIO_SAMSUNG_S3C24XX_H +#define GPIO_SAMSUNG_S3C24XX_H + +#include "map.h" + +/* + * GPIO sizes for various SoCs: + * + * 2410 2412 2440 2443 2416 + * 2442 + * ---- ---- ---- ---- ---- + * A 23 22 25 16 27 + * B 11 11 11 11 11 + * C 16 16 16 16 16 + * D 16 16 16 16 16 + * E 16 16 16 16 16 + * F 8 8 8 8 8 + * G 16 16 16 16 8 + * H 11 11 11 15 15 + * J -- -- 13 16 -- + * K -- -- -- -- 16 + * L -- -- -- 15 14 + * M -- -- -- 2 2 + */ + +/* GPIO bank sizes */ + +#define S3C2410_GPIO_A_NR (32) +#define S3C2410_GPIO_B_NR (32) +#define S3C2410_GPIO_C_NR (32) +#define S3C2410_GPIO_D_NR (32) +#define S3C2410_GPIO_E_NR (32) +#define S3C2410_GPIO_F_NR (32) +#define S3C2410_GPIO_G_NR (32) +#define S3C2410_GPIO_H_NR (32) +#define S3C2410_GPIO_J_NR (32) /* technically 16. */ +#define S3C2410_GPIO_K_NR (32) /* technically 16. */ +#define S3C2410_GPIO_L_NR (32) /* technically 15. */ +#define S3C2410_GPIO_M_NR (32) /* technically 2. */ + +#if CONFIG_S3C_GPIO_SPACE != 0 +#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment +#endif + +#define S3C2410_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0) + +#ifndef __ASSEMBLY__ + +enum s3c_gpio_number { + S3C2410_GPIO_A_START = 0, + S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A), + S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B), + S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C), + S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D), + S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), + S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), + S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), + S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H), + S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J), + S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K), + S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L), +}; + +#endif /* __ASSEMBLY__ */ + +/* S3C2410 GPIO number definitions. */ + +#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr)) +#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr)) +#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr)) +#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr)) +#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr)) +#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) +#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) +#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) +#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr)) +#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr)) +#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) +#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) + +#ifdef CONFIG_CPU_S3C244X +#define S3C_GPIO_END (S3C2410_GPJ(0) + 32) +#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) +#define S3C_GPIO_END (S3C2410_GPM(0) + 32) +#else +#define S3C_GPIO_END (S3C2410_GPH(0) + 32) +#endif + +#endif /* GPIO_SAMSUNG_S3C24XX_H */ diff --git a/arch/arm/mach-s3c/gpio-samsung-s3c64xx.h b/arch/arm/mach-s3c/gpio-samsung-s3c64xx.h new file mode 100644 index 000000000000..8ed144a0d474 --- /dev/null +++ b/arch/arm/mach-s3c/gpio-samsung-s3c64xx.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C6400 - GPIO lib support + */ + +#ifndef GPIO_SAMSUNG_S3C64XX_H +#define GPIO_SAMSUNG_S3C64XX_H + +#ifdef CONFIG_GPIO_SAMSUNG + +/* GPIO bank sizes */ +#define S3C64XX_GPIO_A_NR (8) +#define S3C64XX_GPIO_B_NR (7) +#define S3C64XX_GPIO_C_NR (8) +#define S3C64XX_GPIO_D_NR (5) +#define S3C64XX_GPIO_E_NR (5) +#define S3C64XX_GPIO_F_NR (16) +#define S3C64XX_GPIO_G_NR (7) +#define S3C64XX_GPIO_H_NR (10) +#define S3C64XX_GPIO_I_NR (16) +#define S3C64XX_GPIO_J_NR (12) +#define S3C64XX_GPIO_K_NR (16) +#define S3C64XX_GPIO_L_NR (15) +#define S3C64XX_GPIO_M_NR (6) +#define S3C64XX_GPIO_N_NR (16) +#define S3C64XX_GPIO_O_NR (16) +#define S3C64XX_GPIO_P_NR (15) +#define S3C64XX_GPIO_Q_NR (9) + +/* GPIO bank numbes */ + +/* CONFIG_S3C_GPIO_SPACE allows the user to select extra + * space for debugging purposes so that any accidental + * change from one gpio bank to another can be caught. +*/ + +#define S3C64XX_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) + +enum s3c_gpio_number { + S3C64XX_GPIO_A_START = 0, + S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A), + S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B), + S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C), + S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D), + S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E), + S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F), + S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G), + S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H), + S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I), + S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J), + S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K), + S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L), + S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M), + S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N), + S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O), + S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P), +}; + +/* S3C64XX GPIO number definitions. */ + +#define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr)) +#define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr)) +#define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr)) +#define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr)) +#define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr)) +#define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr)) +#define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr)) +#define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr)) +#define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr)) +#define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr)) +#define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr)) +#define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr)) +#define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr)) +#define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr)) +#define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr)) +#define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr)) +#define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr)) + +/* the end of the S3C64XX specific gpios */ +#define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) +#define S3C_GPIO_END S3C64XX_GPIO_END + +/* define the number of gpios we need to the one after the GPQ() range */ +#define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) + +#endif /* GPIO_SAMSUNG */ +#endif /* GPIO_SAMSUNG_S3C64XX_H */ + diff --git a/arch/arm/mach-s3c/gpio-samsung.c b/arch/arm/mach-s3c/gpio-samsung.c index 8955fd675265..76ef415789f2 100644 --- a/arch/arm/mach-s3c/gpio-samsung.c +++ b/arch/arm/mach-s3c/gpio-samsung.c @@ -27,15 +27,15 @@ #include #include -#include -#include -#include - -#include -#include -#include -#include -#include +#include "map.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" + +#include "cpu.h" +#include "gpio-core.h" +#include "gpio-cfg.h" +#include "gpio-cfg-helpers.h" +#include "pm.h" int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, unsigned int off, samsung_gpio_pull_t pull) diff --git a/arch/arm/mach-s3c/gpio-samsung.h b/arch/arm/mach-s3c/gpio-samsung.h new file mode 100644 index 000000000000..02f6f4a96862 --- /dev/null +++ b/arch/arm/mach-s3c/gpio-samsung.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "gpio-samsung-s3c24xx.h" +#endif + +#ifdef CONFIG_ARCH_S3C64XX +#include "gpio-samsung-s3c64xx.h" +#endif diff --git a/arch/arm/mach-s3c/gta02.h b/arch/arm/mach-s3c/gta02.h index d5610ba829a4..043ae382bfc5 100644 --- a/arch/arm/mach-s3c/gta02.h +++ b/arch/arm/mach-s3c/gta02.h @@ -6,7 +6,7 @@ #ifndef __MACH_S3C24XX_GTA02_H #define __MACH_S3C24XX_GTA02_H __FILE__ -#include +#include "regs-gpio.h" #define GTA02_GPIO_AUX_LED S3C2410_GPB(2) #define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9) diff --git a/arch/arm/mach-s3c/h1940-bluetooth.c b/arch/arm/mach-s3c/h1940-bluetooth.c index 8533e7521b50..59edcf8a620d 100644 --- a/arch/arm/mach-s3c/h1940-bluetooth.c +++ b/arch/arm/mach-s3c/h1940-bluetooth.c @@ -13,9 +13,9 @@ #include #include -#include -#include -#include +#include "gpio-cfg.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" #include "h1940.h" diff --git a/arch/arm/mach-s3c/hardware-s3c24xx.h b/arch/arm/mach-s3c/hardware-s3c24xx.h new file mode 100644 index 000000000000..33b37467d05f --- /dev/null +++ b/arch/arm/mach-s3c/hardware-s3c24xx.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2003 Simtec Electronics + * Ben Dooks + * + * S3C2410 - hardware + */ + +#ifndef __ASM_ARCH_HARDWARE_S3C24XX_H +#define __ASM_ARCH_HARDWARE_S3C24XX_H + +extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); + +#endif /* __ASM_ARCH_HARDWARE_S3C24XX_H */ diff --git a/arch/arm/mach-s3c/iic-core.h b/arch/arm/mach-s3c/iic-core.h new file mode 100644 index 000000000000..c5cfd5af3874 --- /dev/null +++ b/arch/arm/mach-s3c/iic-core.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks + * + * S3C - I2C Controller core functions + */ + +#ifndef __ASM_ARCH_IIC_CORE_H +#define __ASM_ARCH_IIC_CORE_H __FILE__ + +/* These functions are only for use with the core support code, such as + * the cpu specific initialisation code + */ + +/* re-define device name depending on support. */ +static inline void s3c_i2c0_setname(char *name) +{ + /* currently this device is always compiled in */ + s3c_device_i2c0.name = name; +} + +static inline void s3c_i2c1_setname(char *name) +{ +#ifdef CONFIG_S3C_DEV_I2C1 + s3c_device_i2c1.name = name; +#endif +} + +static inline void s3c_i2c2_setname(char *name) +{ +#ifdef CONFIG_S3C_DEV_I2C2 + s3c_device_i2c2.name = name; +#endif +} + +#endif /* __ASM_ARCH_IIC_H */ diff --git a/arch/arm/mach-s3c/include/mach/dma-s3c24xx.h b/arch/arm/mach-s3c/include/mach/dma-s3c24xx.h deleted file mode 100644 index 25fc9c258fc1..000000000000 --- a/arch/arm/mach-s3c/include/mach/dma-s3c24xx.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2003-2006 Simtec Electronics - * Ben Dooks - * - * Samsung S3C24XX DMA support - */ - -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H __FILE__ - -#include - -/* We use `virtual` dma channels to hide the fact we have only a limited - * number of DMA channels, and not of all of them (dependent on the device) - * can be attached to any DMA source. We therefore let the DMA core handle - * the allocation of hardware channels to clients. -*/ - -enum dma_ch { - DMACH_XD0 = 0, - DMACH_XD1, - DMACH_SDI, - DMACH_SPI0, - DMACH_SPI1, - DMACH_UART0, - DMACH_UART1, - DMACH_UART2, - DMACH_TIMER, - DMACH_I2S_IN, - DMACH_I2S_OUT, - DMACH_PCM_IN, - DMACH_PCM_OUT, - DMACH_MIC_IN, - DMACH_USB_EP1, - DMACH_USB_EP2, - DMACH_USB_EP3, - DMACH_USB_EP4, - DMACH_UART0_SRC2, /* s3c2412 second uart sources */ - DMACH_UART1_SRC2, - DMACH_UART2_SRC2, - DMACH_UART3, /* s3c2443 has extra uart */ - DMACH_UART3_SRC2, - DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */ - DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */ - DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */ - DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */ - DMACH_MAX, /* the end entry */ -}; - -#endif /* __ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-s3c/include/mach/dma-s3c64xx.h b/arch/arm/mach-s3c/include/mach/dma-s3c64xx.h deleted file mode 100644 index 40ca8de21096..000000000000 --- a/arch/arm/mach-s3c/include/mach/dma-s3c64xx.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* linux/arch/arm/mach-s3c6400/include/mach/dma.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C6400 - DMA support - */ - -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H __FILE__ - -#define S3C64XX_DMA_CHAN(name) ((unsigned long)(name)) - -/* DMA0/SDMA0 */ -#define DMACH_UART0 "uart0_tx" -#define DMACH_UART0_SRC2 "uart0_rx" -#define DMACH_UART1 "uart1_tx" -#define DMACH_UART1_SRC2 "uart1_rx" -#define DMACH_UART2 "uart2_tx" -#define DMACH_UART2_SRC2 "uart2_rx" -#define DMACH_UART3 "uart3_tx" -#define DMACH_UART3_SRC2 "uart3_rx" -#define DMACH_PCM0_TX "pcm0_tx" -#define DMACH_PCM0_RX "pcm0_rx" -#define DMACH_I2S0_OUT "i2s0_tx" -#define DMACH_I2S0_IN "i2s0_rx" -#define DMACH_SPI0_TX S3C64XX_DMA_CHAN("spi0_tx") -#define DMACH_SPI0_RX S3C64XX_DMA_CHAN("spi0_rx") -#define DMACH_HSI_I2SV40_TX "i2s2_tx" -#define DMACH_HSI_I2SV40_RX "i2s2_rx" - -/* DMA1/SDMA1 */ -#define DMACH_PCM1_TX "pcm1_tx" -#define DMACH_PCM1_RX "pcm1_rx" -#define DMACH_I2S1_OUT "i2s1_tx" -#define DMACH_I2S1_IN "i2s1_rx" -#define DMACH_SPI1_TX S3C64XX_DMA_CHAN("spi1_tx") -#define DMACH_SPI1_RX S3C64XX_DMA_CHAN("spi1_rx") -#define DMACH_AC97_PCMOUT "ac97_out" -#define DMACH_AC97_PCMIN "ac97_in" -#define DMACH_AC97_MICIN "ac97_mic" -#define DMACH_PWM "pwm" -#define DMACH_IRDA "irda" -#define DMACH_EXTERNAL "external" -#define DMACH_SECURITY_RX "sec_rx" -#define DMACH_SECURITY_TX "sec_tx" - -enum dma_ch { - DMACH_MAX = 32 -}; - -#include - -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c/include/mach/dma.h b/arch/arm/mach-s3c/include/mach/dma.h deleted file mode 100644 index 59a4578c5f00..000000000000 --- a/arch/arm/mach-s3c/include/mach/dma.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifdef CONFIG_ARCH_S3C24XX -#include "dma-s3c24xx.h" -#endif - -#ifdef CONFIG_ARCH_S3C64XX -#include "dma-s3c64xx.h" -#endif diff --git a/arch/arm/mach-s3c/include/mach/gpio-samsung-s3c24xx.h b/arch/arm/mach-s3c/include/mach/gpio-samsung-s3c24xx.h deleted file mode 100644 index f8a114891f16..000000000000 --- a/arch/arm/mach-s3c/include/mach/gpio-samsung-s3c24xx.h +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C2410 - GPIO lib support - */ - -/* some boards require extra gpio capacity to support external - * devices that need GPIO. - */ - -#ifndef GPIO_SAMSUNG_S3C24XX_H -#define GPIO_SAMSUNG_S3C24XX_H - -#include - -/* - * GPIO sizes for various SoCs: - * - * 2410 2412 2440 2443 2416 - * 2442 - * ---- ---- ---- ---- ---- - * A 23 22 25 16 27 - * B 11 11 11 11 11 - * C 16 16 16 16 16 - * D 16 16 16 16 16 - * E 16 16 16 16 16 - * F 8 8 8 8 8 - * G 16 16 16 16 8 - * H 11 11 11 15 15 - * J -- -- 13 16 -- - * K -- -- -- -- 16 - * L -- -- -- 15 14 - * M -- -- -- 2 2 - */ - -/* GPIO bank sizes */ - -#define S3C2410_GPIO_A_NR (32) -#define S3C2410_GPIO_B_NR (32) -#define S3C2410_GPIO_C_NR (32) -#define S3C2410_GPIO_D_NR (32) -#define S3C2410_GPIO_E_NR (32) -#define S3C2410_GPIO_F_NR (32) -#define S3C2410_GPIO_G_NR (32) -#define S3C2410_GPIO_H_NR (32) -#define S3C2410_GPIO_J_NR (32) /* technically 16. */ -#define S3C2410_GPIO_K_NR (32) /* technically 16. */ -#define S3C2410_GPIO_L_NR (32) /* technically 15. */ -#define S3C2410_GPIO_M_NR (32) /* technically 2. */ - -#if CONFIG_S3C_GPIO_SPACE != 0 -#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment -#endif - -#define S3C2410_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0) - -#ifndef __ASSEMBLY__ - -enum s3c_gpio_number { - S3C2410_GPIO_A_START = 0, - S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A), - S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B), - S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C), - S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D), - S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), - S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), - S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), - S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H), - S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J), - S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K), - S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L), -}; - -#endif /* __ASSEMBLY__ */ - -/* S3C2410 GPIO number definitions. */ - -#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr)) -#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr)) -#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr)) -#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr)) -#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr)) -#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) -#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) -#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) -#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr)) -#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr)) -#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) -#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) - -#ifdef CONFIG_CPU_S3C244X -#define S3C_GPIO_END (S3C2410_GPJ(0) + 32) -#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) -#define S3C_GPIO_END (S3C2410_GPM(0) + 32) -#else -#define S3C_GPIO_END (S3C2410_GPH(0) + 32) -#endif - -#endif /* GPIO_SAMSUNG_S3C24XX_H */ diff --git a/arch/arm/mach-s3c/include/mach/gpio-samsung-s3c64xx.h b/arch/arm/mach-s3c/include/mach/gpio-samsung-s3c64xx.h deleted file mode 100644 index 8ed144a0d474..000000000000 --- a/arch/arm/mach-s3c/include/mach/gpio-samsung-s3c64xx.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C6400 - GPIO lib support - */ - -#ifndef GPIO_SAMSUNG_S3C64XX_H -#define GPIO_SAMSUNG_S3C64XX_H - -#ifdef CONFIG_GPIO_SAMSUNG - -/* GPIO bank sizes */ -#define S3C64XX_GPIO_A_NR (8) -#define S3C64XX_GPIO_B_NR (7) -#define S3C64XX_GPIO_C_NR (8) -#define S3C64XX_GPIO_D_NR (5) -#define S3C64XX_GPIO_E_NR (5) -#define S3C64XX_GPIO_F_NR (16) -#define S3C64XX_GPIO_G_NR (7) -#define S3C64XX_GPIO_H_NR (10) -#define S3C64XX_GPIO_I_NR (16) -#define S3C64XX_GPIO_J_NR (12) -#define S3C64XX_GPIO_K_NR (16) -#define S3C64XX_GPIO_L_NR (15) -#define S3C64XX_GPIO_M_NR (6) -#define S3C64XX_GPIO_N_NR (16) -#define S3C64XX_GPIO_O_NR (16) -#define S3C64XX_GPIO_P_NR (15) -#define S3C64XX_GPIO_Q_NR (9) - -/* GPIO bank numbes */ - -/* CONFIG_S3C_GPIO_SPACE allows the user to select extra - * space for debugging purposes so that any accidental - * change from one gpio bank to another can be caught. -*/ - -#define S3C64XX_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) - -enum s3c_gpio_number { - S3C64XX_GPIO_A_START = 0, - S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A), - S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B), - S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C), - S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D), - S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E), - S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F), - S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G), - S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H), - S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I), - S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J), - S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K), - S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L), - S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M), - S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N), - S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O), - S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P), -}; - -/* S3C64XX GPIO number definitions. */ - -#define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr)) -#define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr)) -#define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr)) -#define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr)) -#define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr)) -#define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr)) -#define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr)) -#define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr)) -#define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr)) -#define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr)) -#define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr)) -#define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr)) -#define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr)) -#define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr)) -#define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr)) -#define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr)) -#define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr)) - -/* the end of the S3C64XX specific gpios */ -#define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) -#define S3C_GPIO_END S3C64XX_GPIO_END - -/* define the number of gpios we need to the one after the GPQ() range */ -#define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) - -#endif /* GPIO_SAMSUNG */ -#endif /* GPIO_SAMSUNG_S3C64XX_H */ - diff --git a/arch/arm/mach-s3c/include/mach/gpio-samsung.h b/arch/arm/mach-s3c/include/mach/gpio-samsung.h deleted file mode 100644 index 02f6f4a96862..000000000000 --- a/arch/arm/mach-s3c/include/mach/gpio-samsung.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifdef CONFIG_ARCH_S3C24XX -#include "gpio-samsung-s3c24xx.h" -#endif - -#ifdef CONFIG_ARCH_S3C64XX -#include "gpio-samsung-s3c64xx.h" -#endif diff --git a/arch/arm/mach-s3c/include/mach/hardware-s3c24xx.h b/arch/arm/mach-s3c/include/mach/hardware-s3c24xx.h deleted file mode 100644 index 33b37467d05f..000000000000 --- a/arch/arm/mach-s3c/include/mach/hardware-s3c24xx.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003 Simtec Electronics - * Ben Dooks - * - * S3C2410 - hardware - */ - -#ifndef __ASM_ARCH_HARDWARE_S3C24XX_H -#define __ASM_ARCH_HARDWARE_S3C24XX_H - -extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); - -#endif /* __ASM_ARCH_HARDWARE_S3C24XX_H */ diff --git a/arch/arm/mach-s3c/include/mach/io-s3c24xx.h b/arch/arm/mach-s3c/include/mach/io-s3c24xx.h index 9b78b0a3d486..738b775d3336 100644 --- a/arch/arm/mach-s3c/include/mach/io-s3c24xx.h +++ b/arch/arm/mach-s3c/include/mach/io-s3c24xx.h @@ -10,7 +10,7 @@ #ifndef __ASM_ARM_ARCH_IO_S3C24XX_H #define __ASM_ARM_ARCH_IO_S3C24XX_H -#include +#include /* * ISA style IO, for each machine to sort out mappings for, diff --git a/arch/arm/mach-s3c/include/mach/map-base.h b/arch/arm/mach-s3c/include/mach/map-base.h new file mode 100644 index 000000000000..34b39ded0e2e --- /dev/null +++ b/arch/arm/mach-s3c/include/mach/map-base.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2003, 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C - Memory map definitions (virtual addresses) + */ + +#ifndef __ASM_PLAT_MAP_H +#define __ASM_PLAT_MAP_H __FILE__ + +/* Fit all our registers in at 0xF6000000 upwards, trying to use as + * little of the VA space as possible so vmalloc and friends have a + * better chance of getting memory. + * + * we try to ensure stuff like the IRQ registers are available for + * an single MOVS instruction (ie, only 8 bits of set data) + */ + +#define S3C_ADDR_BASE 0xF6000000 + +#ifndef __ASSEMBLY__ +#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) +#else +#define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) +#endif + +#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ +#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ +#define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ +#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ +#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ +#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ + +/* This is used for the CPU specific mappings that may be needed, so that + * they do not need to directly used S3C_ADDR() and thus make it easier to + * modify the space for mapping. + */ +#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x)) + +#endif /* __ASM_PLAT_MAP_H */ diff --git a/arch/arm/mach-s3c/include/mach/map-s3c24xx.h b/arch/arm/mach-s3c/include/mach/map-s3c24xx.h deleted file mode 100644 index a20c9fd0d855..000000000000 --- a/arch/arm/mach-s3c/include/mach/map-s3c24xx.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003 Simtec Electronics - * Ben Dooks - * - * S3C2410 - Memory map definitions - */ - -#ifndef __ASM_ARCH_MAP_H -#define __ASM_ARCH_MAP_H - -#include -#include - -/* - * interrupt controller is the first thing we put in, to make - * the assembly code for the irq detection easier - */ -#define S3C2410_PA_IRQ (0x4A000000) -#define S3C24XX_SZ_IRQ SZ_1M - -/* memory controller registers */ -#define S3C2410_PA_MEMCTRL (0x48000000) -#define S3C24XX_SZ_MEMCTRL SZ_1M - -/* Timers */ -#define S3C2410_PA_TIMER (0x51000000) -#define S3C24XX_SZ_TIMER SZ_1M - -/* Clock and Power management */ -#define S3C24XX_SZ_CLKPWR SZ_1M - -/* USB Device port */ -#define S3C2410_PA_USBDEV (0x52000000) -#define S3C24XX_SZ_USBDEV SZ_1M - -/* Watchdog */ -#define S3C2410_PA_WATCHDOG (0x53000000) -#define S3C24XX_SZ_WATCHDOG SZ_1M - -/* Standard size definitions for peripheral blocks. */ - -#define S3C24XX_SZ_UART SZ_1M -#define S3C24XX_SZ_IIS SZ_1M -#define S3C24XX_SZ_ADC SZ_1M -#define S3C24XX_SZ_SPI SZ_1M -#define S3C24XX_SZ_SDI SZ_1M -#define S3C24XX_SZ_NAND SZ_1M -#define S3C24XX_SZ_GPIO SZ_1M - -/* USB host controller */ -#define S3C2410_PA_USBHOST (0x49000000) - -/* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */ -#define S3C2416_PA_HSUDC (0x49800000) -#define S3C2416_SZ_HSUDC (SZ_4K) - -/* DMA controller */ -#define S3C2410_PA_DMA (0x4B000000) -#define S3C24XX_SZ_DMA SZ_1M - -/* Clock and Power management */ -#define S3C2410_PA_CLKPWR (0x4C000000) - -/* LCD controller */ -#define S3C2410_PA_LCD (0x4D000000) -#define S3C24XX_SZ_LCD SZ_1M - -/* NAND flash controller */ -#define S3C2410_PA_NAND (0x4E000000) - -/* IIC hardware controller */ -#define S3C2410_PA_IIC (0x54000000) - -/* IIS controller */ -#define S3C2410_PA_IIS (0x55000000) - -/* RTC */ -#define S3C2410_PA_RTC (0x57000000) -#define S3C24XX_SZ_RTC SZ_1M - -/* ADC */ -#define S3C2410_PA_ADC (0x58000000) - -/* SPI */ -#define S3C2410_PA_SPI (0x59000000) -#define S3C2443_PA_SPI0 (0x52000000) -#define S3C2443_PA_SPI1 S3C2410_PA_SPI -#define S3C2410_SPI1 (0x20) -#define S3C2412_SPI1 (0x100) - -/* SDI */ -#define S3C2410_PA_SDI (0x5A000000) - -/* CAMIF */ -#define S3C2440_PA_CAMIF (0x4F000000) -#define S3C2440_SZ_CAMIF SZ_1M - -/* AC97 */ - -#define S3C2440_PA_AC97 (0x5B000000) -#define S3C2440_SZ_AC97 SZ_1M - -/* S3C2443/S3C2416 High-speed SD/MMC */ -#define S3C2443_PA_HSMMC (0x4A800000) -#define S3C2416_PA_HSMMC0 (0x4AC00000) - -#define S3C2443_PA_FB (0x4C800000) - -/* S3C2412 memory and IO controls */ -#define S3C2412_PA_SSMC (0x4F000000) - -#define S3C2412_PA_EBI (0x48800000) - -/* physical addresses of all the chip-select areas */ - -#define S3C2410_CS0 (0x00000000) -#define S3C2410_CS1 (0x08000000) -#define S3C2410_CS2 (0x10000000) -#define S3C2410_CS3 (0x18000000) -#define S3C2410_CS4 (0x20000000) -#define S3C2410_CS5 (0x28000000) -#define S3C2410_CS6 (0x30000000) -#define S3C2410_CS7 (0x38000000) - -#define S3C2410_SDRAM_PA (S3C2410_CS6) - -/* Use a single interface for common resources between S3C24XX cpus */ - -#define S3C24XX_PA_IRQ S3C2410_PA_IRQ -#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL -#define S3C24XX_PA_DMA S3C2410_PA_DMA -#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR -#define S3C24XX_PA_LCD S3C2410_PA_LCD -#define S3C24XX_PA_TIMER S3C2410_PA_TIMER -#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV -#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG -#define S3C24XX_PA_IIS S3C2410_PA_IIS -#define S3C24XX_PA_RTC S3C2410_PA_RTC -#define S3C24XX_PA_ADC S3C2410_PA_ADC -#define S3C24XX_PA_SPI S3C2410_PA_SPI -#define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1) -#define S3C24XX_PA_SDI S3C2410_PA_SDI -#define S3C24XX_PA_NAND S3C2410_PA_NAND - -#define S3C_PA_FB S3C2443_PA_FB -#define S3C_PA_IIC S3C2410_PA_IIC -#define S3C_PA_USBHOST S3C2410_PA_USBHOST -#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0 -#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC -#define S3C_PA_WDT S3C2410_PA_WATCHDOG -#define S3C_PA_NAND S3C24XX_PA_NAND - -#define S3C_PA_SPI0 S3C2443_PA_SPI0 -#define S3C_PA_SPI1 S3C2443_PA_SPI1 - -#define SAMSUNG_PA_TIMER S3C2410_PA_TIMER - -#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s3c/include/mach/map-s3c64xx.h b/arch/arm/mach-s3c/include/mach/map-s3c64xx.h deleted file mode 100644 index 9372a535b7ba..000000000000 --- a/arch/arm/mach-s3c/include/mach/map-s3c64xx.h +++ /dev/null @@ -1,122 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C64XX - Memory map definitions - */ - -#ifndef __ASM_ARCH_MAP_H -#define __ASM_ARCH_MAP_H __FILE__ - -#include -#include - -/* - * Post-mux Chip Select Regions Xm0CSn_ - * These may be used by SROM, NAND or CF depending on settings - */ - -#define S3C64XX_PA_XM0CSN0 (0x10000000) -#define S3C64XX_PA_XM0CSN1 (0x18000000) -#define S3C64XX_PA_XM0CSN2 (0x20000000) -#define S3C64XX_PA_XM0CSN3 (0x28000000) -#define S3C64XX_PA_XM0CSN4 (0x30000000) -#define S3C64XX_PA_XM0CSN5 (0x38000000) - -/* HSMMC units */ -#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000)) -#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0) -#define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1) -#define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2) - -#define S3C_PA_UART (0x7F005000) -#define S3C_PA_UART0 (S3C_PA_UART + 0x00) -#define S3C_PA_UART1 (S3C_PA_UART + 0x400) -#define S3C_PA_UART2 (S3C_PA_UART + 0x800) -#define S3C_PA_UART3 (S3C_PA_UART + 0xC00) -#define S3C_UART_OFFSET (0x400) - -/* See notes on UART VA mapping in debug-macro.S */ -#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET)) - -#define S3C_VA_UART0 S3C_VA_UARTx(0) -#define S3C_VA_UART1 S3C_VA_UARTx(1) -#define S3C_VA_UART2 S3C_VA_UARTx(2) -#define S3C_VA_UART3 S3C_VA_UARTx(3) - -#define S3C64XX_PA_SROM (0x70000000) - -#define S3C64XX_PA_ONENAND0 (0x70100000) -#define S3C64XX_PA_ONENAND0_BUF (0x20000000) -#define S3C64XX_SZ_ONENAND0_BUF (SZ_64M) - -/* NAND and OneNAND1 controllers occupy the same register region - (depending on SoC POP version) */ -#define S3C64XX_PA_ONENAND1 (0x70200000) -#define S3C64XX_PA_ONENAND1_BUF (0x28000000) -#define S3C64XX_SZ_ONENAND1_BUF (SZ_64M) - -#define S3C64XX_PA_NAND (0x70200000) -#define S3C64XX_PA_FB (0x77100000) -#define S3C64XX_PA_USB_HSOTG (0x7C000000) -#define S3C64XX_PA_WATCHDOG (0x7E004000) -#define S3C64XX_PA_RTC (0x7E005000) -#define S3C64XX_PA_KEYPAD (0x7E00A000) -#define S3C64XX_PA_ADC (0x7E00B000) -#define S3C64XX_PA_SYSCON (0x7E00F000) -#define S3C64XX_PA_AC97 (0x7F001000) -#define S3C64XX_PA_IIS0 (0x7F002000) -#define S3C64XX_PA_IIS1 (0x7F003000) -#define S3C64XX_PA_TIMER (0x7F006000) -#define S3C64XX_PA_IIC0 (0x7F004000) -#define S3C64XX_PA_SPI0 (0x7F00B000) -#define S3C64XX_PA_SPI1 (0x7F00C000) -#define S3C64XX_PA_PCM0 (0x7F009000) -#define S3C64XX_PA_PCM1 (0x7F00A000) -#define S3C64XX_PA_IISV4 (0x7F00D000) -#define S3C64XX_PA_IIC1 (0x7F00F000) - -#define S3C64XX_PA_GPIO (0x7F008000) -#define S3C64XX_SZ_GPIO SZ_4K - -#define S3C64XX_PA_SDRAM (0x50000000) - -#define S3C64XX_PA_CFCON (0x70300000) - -#define S3C64XX_PA_VIC0 (0x71200000) -#define S3C64XX_PA_VIC1 (0x71300000) - -#define S3C64XX_PA_MODEM (0x74108000) - -#define S3C64XX_PA_USBHOST (0x74300000) - -#define S3C64XX_PA_USB_HSPHY (0x7C100000) - -/* compatibility defines. */ -#define S3C_PA_TIMER S3C64XX_PA_TIMER -#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0 -#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1 -#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2 -#define S3C_PA_IIC S3C64XX_PA_IIC0 -#define S3C_PA_IIC1 S3C64XX_PA_IIC1 -#define S3C_PA_NAND S3C64XX_PA_NAND -#define S3C_PA_ONENAND S3C64XX_PA_ONENAND0 -#define S3C_PA_ONENAND_BUF S3C64XX_PA_ONENAND0_BUF -#define S3C_SZ_ONENAND_BUF S3C64XX_SZ_ONENAND0_BUF -#define S3C_PA_FB S3C64XX_PA_FB -#define S3C_PA_USBHOST S3C64XX_PA_USBHOST -#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG -#define S3C_PA_RTC S3C64XX_PA_RTC -#define S3C_PA_WDT S3C64XX_PA_WATCHDOG -#define S3C_PA_SPI0 S3C64XX_PA_SPI0 -#define S3C_PA_SPI1 S3C64XX_PA_SPI1 - -#define SAMSUNG_PA_ADC S3C64XX_PA_ADC -#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON -#define SAMSUNG_PA_KEYPAD S3C64XX_PA_KEYPAD -#define SAMSUNG_PA_TIMER S3C64XX_PA_TIMER - -#endif /* __ASM_ARCH_6400_MAP_H */ diff --git a/arch/arm/mach-s3c/include/mach/map.h b/arch/arm/mach-s3c/include/mach/map.h deleted file mode 100644 index 7cfb517d4886..000000000000 --- a/arch/arm/mach-s3c/include/mach/map.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifdef CONFIG_ARCH_S3C24XX -#include "map-s3c24xx.h" -#endif - -#ifdef CONFIG_ARCH_S3C64XX -#include "map-s3c64xx.h" -#endif diff --git a/arch/arm/mach-s3c/include/mach/pm-core-s3c24xx.h b/arch/arm/mach-s3c/include/mach/pm-core-s3c24xx.h deleted file mode 100644 index bcb7978a4e85..000000000000 --- a/arch/arm/mach-s3c/include/mach/pm-core-s3c24xx.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c - */ - -#include -#include - -#include "regs-clock.h" -#include "regs-irq-s3c24xx.h" -#include - -static inline void s3c_pm_debug_init_uart(void) -{ -#ifdef CONFIG_SAMSUNG_PM_DEBUG - unsigned long tmp = __raw_readl(S3C2410_CLKCON); - - /* re-start uart clocks */ - tmp |= S3C2410_CLKCON_UART0; - tmp |= S3C2410_CLKCON_UART1; - tmp |= S3C2410_CLKCON_UART2; - - __raw_writel(tmp, S3C2410_CLKCON); - udelay(10); -#endif -} - -static inline void s3c_pm_arch_prepare_irqs(void) -{ - __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); - __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); - - /* ack any outstanding external interrupts before we go to sleep */ - - __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); - __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); - __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); - -} - -static inline void s3c_pm_arch_stop_clocks(void) -{ - __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ -} - -/* s3c2410_pm_show_resume_irqs - * - * print any IRQs asserted at resume time (ie, we woke from) -*/ -static inline void s3c_pm_show_resume_irqs(int start, unsigned long which, - unsigned long mask) -{ - int i; - - which &= ~mask; - - for (i = 0; i <= 31; i++) { - if (which & (1L< - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c - */ - -#ifndef __MACH_S3C64XX_PM_CORE_H -#define __MACH_S3C64XX_PM_CORE_H __FILE__ - -#include -#include - -#include -#include -#include - -static inline void s3c_pm_debug_init_uart(void) -{ -#ifdef CONFIG_SAMSUNG_PM_DEBUG - u32 tmp = __raw_readl(S3C_PCLK_GATE); - - /* As a note, since the S3C64XX UARTs generally have multiple - * clock sources, we simply enable PCLK at the moment and hope - * that the resume settings for the UART are suitable for the - * use with PCLK. - */ - - tmp |= S3C_CLKCON_PCLK_UART0; - tmp |= S3C_CLKCON_PCLK_UART1; - tmp |= S3C_CLKCON_PCLK_UART2; - tmp |= S3C_CLKCON_PCLK_UART3; - - __raw_writel(tmp, S3C_PCLK_GATE); - udelay(10); -#endif -} - -static inline void s3c_pm_arch_prepare_irqs(void) -{ - /* VIC should have already been taken care of */ - - /* clear any pending EINT0 interrupts */ - __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); -} - -static inline void s3c_pm_arch_stop_clocks(void) -{ -} - -static inline void s3c_pm_arch_show_resume_irqs(void) -{ -} - -/* make these defines, we currently do not have any need to change - * the IRQ wake controls depending on the CPU we are running on */ -#ifdef CONFIG_PM_SLEEP -#define s3c_irqwake_eintallow ((1 << 28) - 1) -#define s3c_irqwake_intallow (~0) -#else -#define s3c_irqwake_eintallow 0 -#define s3c_irqwake_intallow 0 -#endif - -static inline void s3c_pm_restored_gpios(void) -{ - /* ensure sleep mode has been cleared from the system */ - - __raw_writel(0, S3C64XX_SLPEN); -} - -static inline void samsung_pm_saved_gpios(void) -{ - /* turn on the sleep mode and keep it there, as it seems that during - * suspend the xCON registers get re-set and thus you can end up with - * problems between going to sleep and resuming. - */ - - __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN); -} -#endif /* __MACH_S3C64XX_PM_CORE_H */ diff --git a/arch/arm/mach-s3c/include/mach/pm-core.h b/arch/arm/mach-s3c/include/mach/pm-core.h deleted file mode 100644 index b0e1d277f599..000000000000 --- a/arch/arm/mach-s3c/include/mach/pm-core.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifdef CONFIG_ARCH_S3C24XX -#include "pm-core-s3c24xx.h" -#endif - -#ifdef CONFIG_ARCH_S3C64XX -#include "pm-core-s3c64xx.h" -#endif diff --git a/arch/arm/mach-s3c/include/mach/regs-clock-s3c24xx.h b/arch/arm/mach-s3c/include/mach/regs-clock-s3c24xx.h deleted file mode 100644 index da4e7b3aeba6..000000000000 --- a/arch/arm/mach-s3c/include/mach/regs-clock-s3c24xx.h +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003-2006 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * - * S3C2410 clock register definitions - */ - -#ifndef __ASM_ARM_REGS_CLOCK -#define __ASM_ARM_REGS_CLOCK - -#include - -#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) - -#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s))) - -#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00) -#define S3C2410_MPLLCON S3C2410_CLKREG(0x04) -#define S3C2410_UPLLCON S3C2410_CLKREG(0x08) -#define S3C2410_CLKCON S3C2410_CLKREG(0x0C) -#define S3C2410_CLKSLOW S3C2410_CLKREG(0x10) -#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14) - -#define S3C2410_CLKCON_IDLE (1<<2) -#define S3C2410_CLKCON_POWER (1<<3) -#define S3C2410_CLKCON_NAND (1<<4) -#define S3C2410_CLKCON_LCDC (1<<5) -#define S3C2410_CLKCON_USBH (1<<6) -#define S3C2410_CLKCON_USBD (1<<7) -#define S3C2410_CLKCON_PWMT (1<<8) -#define S3C2410_CLKCON_SDI (1<<9) -#define S3C2410_CLKCON_UART0 (1<<10) -#define S3C2410_CLKCON_UART1 (1<<11) -#define S3C2410_CLKCON_UART2 (1<<12) -#define S3C2410_CLKCON_GPIO (1<<13) -#define S3C2410_CLKCON_RTC (1<<14) -#define S3C2410_CLKCON_ADC (1<<15) -#define S3C2410_CLKCON_IIC (1<<16) -#define S3C2410_CLKCON_IIS (1<<17) -#define S3C2410_CLKCON_SPI (1<<18) - -#define S3C2410_CLKDIVN_PDIVN (1<<0) -#define S3C2410_CLKDIVN_HDIVN (1<<1) - -#define S3C2410_CLKSLOW_UCLK_OFF (1<<7) -#define S3C2410_CLKSLOW_MPLL_OFF (1<<5) -#define S3C2410_CLKSLOW_SLOW (1<<4) -#define S3C2410_CLKSLOW_SLOWVAL(x) (x) -#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) - -#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) - -/* extra registers */ -#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) - -#define S3C2440_CLKCON_CAMERA (1<<19) -#define S3C2440_CLKCON_AC97 (1<<20) - -#define S3C2440_CLKDIVN_PDIVN (1<<0) -#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1) -#define S3C2440_CLKDIVN_HDIVN_1 (0<<1) -#define S3C2440_CLKDIVN_HDIVN_2 (1<<1) -#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1) -#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1) -#define S3C2440_CLKDIVN_UCLK (1<<3) - -#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0) -#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4) -#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) -#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) -#define S3C2440_CAMDIVN_DVSEN (1<<12) - -#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5) - -#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */ - -#if defined(CONFIG_CPU_S3C2412) - -#define S3C2412_OSCSET S3C2410_CLKREG(0x18) -#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C) - -#define S3C2412_PLLCON_OFF (1<<20) - -#define S3C2412_CLKDIVN_PDIVN (1<<2) -#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0) -#define S3C2412_CLKDIVN_ARMDIVN (1<<3) -#define S3C2412_CLKDIVN_DVSEN (1<<4) -#define S3C2412_CLKDIVN_HALFHCLK (1<<5) -#define S3C2412_CLKDIVN_USB48DIV (1<<6) -#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8) -#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8) -#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12) -#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12) -#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16) -#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16) - -#define S3C2412_CLKCON_WDT (1<<28) -#define S3C2412_CLKCON_SPI (1<<27) -#define S3C2412_CLKCON_IIS (1<<26) -#define S3C2412_CLKCON_IIC (1<<25) -#define S3C2412_CLKCON_ADC (1<<24) -#define S3C2412_CLKCON_RTC (1<<23) -#define S3C2412_CLKCON_GPIO (1<<22) -#define S3C2412_CLKCON_UART2 (1<<21) -#define S3C2412_CLKCON_UART1 (1<<20) -#define S3C2412_CLKCON_UART0 (1<<19) -#define S3C2412_CLKCON_SDI (1<<18) -#define S3C2412_CLKCON_PWMT (1<<17) -#define S3C2412_CLKCON_USBD (1<<16) -#define S3C2412_CLKCON_CAMCLK (1<<15) -#define S3C2412_CLKCON_UARTCLK (1<<14) -/* missing 13 */ -#define S3C2412_CLKCON_USB_HOST48 (1<<12) -#define S3C2412_CLKCON_USB_DEV48 (1<<11) -#define S3C2412_CLKCON_HCLKdiv2 (1<<10) -#define S3C2412_CLKCON_HCLKx2 (1<<9) -#define S3C2412_CLKCON_SDRAM (1<<8) -/* missing 7 */ -#define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH -#define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC -#define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND -#define S3C2412_CLKCON_DMA3 (1<<3) -#define S3C2412_CLKCON_DMA2 (1<<2) -#define S3C2412_CLKCON_DMA1 (1<<1) -#define S3C2412_CLKCON_DMA0 (1<<0) - -/* clock sourec controls */ - -#define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0) -#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0) -#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3) -#define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4) -#define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5) -#define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8) -#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) -#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) -#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) -#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12) -#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14) - -#endif /* CONFIG_CPU_S3C2412 */ - -#define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28) - -#endif /* __ASM_ARM_REGS_CLOCK */ diff --git a/arch/arm/mach-s3c/include/mach/regs-clock-s3c64xx.h b/arch/arm/mach-s3c/include/mach/regs-clock-s3c64xx.h deleted file mode 100644 index 35a68767b318..000000000000 --- a/arch/arm/mach-s3c/include/mach/regs-clock-s3c64xx.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX clock register definitions - */ - -#ifndef __PLAT_REGS_CLOCK_H -#define __PLAT_REGS_CLOCK_H __FILE__ - -/* - * FIXME: Remove remaining definitions - */ - -#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) - -#define S3C_PCLK_GATE S3C_CLKREG(0x34) -#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) -#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) - -/* PCLK GATE Registers */ -#define S3C_CLKCON_PCLK_UART3 (1<<4) -#define S3C_CLKCON_PCLK_UART2 (1<<3) -#define S3C_CLKCON_PCLK_UART1 (1<<2) -#define S3C_CLKCON_PCLK_UART0 (1<<1) - -/* MEM_SYS_CFG */ -#define MEM_SYS_CFG_INDEP_CF 0x4000 -#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 - -#endif /* _PLAT_REGS_CLOCK_H */ diff --git a/arch/arm/mach-s3c/include/mach/regs-clock.h b/arch/arm/mach-s3c/include/mach/regs-clock.h deleted file mode 100644 index 7df31f203d28..000000000000 --- a/arch/arm/mach-s3c/include/mach/regs-clock.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifdef CONFIG_ARCH_S3C24XX -#include "regs-clock-s3c24xx.h" -#endif - -#ifdef CONFIG_ARCH_S3C64XX -#include "regs-clock-s3c64xx.h" -#endif diff --git a/arch/arm/mach-s3c/include/mach/regs-gpio-s3c24xx.h b/arch/arm/mach-s3c/include/mach/regs-gpio-s3c24xx.h deleted file mode 100644 index 51827d5577b6..000000000000 --- a/arch/arm/mach-s3c/include/mach/regs-gpio-s3c24xx.h +++ /dev/null @@ -1,608 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003-2004 Simtec Electronics - * http://www.simtec.co.uk/products/SWLINUX/ - * - * S3C2410 GPIO register definitions - */ - - -#ifndef __ASM_ARCH_REGS_GPIO_H -#define __ASM_ARCH_REGS_GPIO_H - -#include - -#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) - -/* general configuration options */ - -#define S3C2410_GPIO_LEAVE (0xFFFFFFFF) -#define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */ -#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) -#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ -#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */ -#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ - -/* register address for the GPIO registers. - * S3C24XX_GPIOREG2 is for the second set of registers in the - * GPIO which move between s3c2410 and s3c2412 type systems */ - -#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) -#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2) - - -/* configure GPIO ports A..G */ - -/* port A - S3C2410: 22bits, zero in bit X makes pin X output - * 1 makes port special function, this is default -*/ -#define S3C2410_GPACON S3C2410_GPIOREG(0x00) -#define S3C2410_GPADAT S3C2410_GPIOREG(0x04) - -#define S3C2410_GPA0_ADDR0 (1<<0) -#define S3C2410_GPA1_ADDR16 (1<<1) -#define S3C2410_GPA2_ADDR17 (1<<2) -#define S3C2410_GPA3_ADDR18 (1<<3) -#define S3C2410_GPA4_ADDR19 (1<<4) -#define S3C2410_GPA5_ADDR20 (1<<5) -#define S3C2410_GPA6_ADDR21 (1<<6) -#define S3C2410_GPA7_ADDR22 (1<<7) -#define S3C2410_GPA8_ADDR23 (1<<8) -#define S3C2410_GPA9_ADDR24 (1<<9) -#define S3C2410_GPA10_ADDR25 (1<<10) -#define S3C2410_GPA11_ADDR26 (1<<11) -#define S3C2410_GPA12_nGCS1 (1<<12) -#define S3C2410_GPA13_nGCS2 (1<<13) -#define S3C2410_GPA14_nGCS3 (1<<14) -#define S3C2410_GPA15_nGCS4 (1<<15) -#define S3C2410_GPA16_nGCS5 (1<<16) -#define S3C2410_GPA17_CLE (1<<17) -#define S3C2410_GPA18_ALE (1<<18) -#define S3C2410_GPA19_nFWE (1<<19) -#define S3C2410_GPA20_nFRE (1<<20) -#define S3C2410_GPA21_nRSTOUT (1<<21) -#define S3C2410_GPA22_nFCE (1<<22) - -/* 0x08 and 0x0c are reserved on S3C2410 */ - -/* S3C2410: - * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. - * 00 = input, 01 = output, 10=special function, 11=reserved - - * bit 0,1 = pin 0, 2,3= pin 1... - * - * CPBUP = pull up resistor control, 1=disabled, 0=enabled -*/ - -#define S3C2410_GPBCON S3C2410_GPIOREG(0x10) -#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) -#define S3C2410_GPBUP S3C2410_GPIOREG(0x18) - -/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ - -#define S3C2410_GPB0_TOUT0 (0x02 << 0) - -#define S3C2410_GPB1_TOUT1 (0x02 << 2) - -#define S3C2410_GPB2_TOUT2 (0x02 << 4) - -#define S3C2410_GPB3_TOUT3 (0x02 << 6) - -#define S3C2410_GPB4_TCLK0 (0x02 << 8) -#define S3C2410_GPB4_MASK (0x03 << 8) - -#define S3C2410_GPB5_nXBACK (0x02 << 10) -#define S3C2443_GPB5_XBACK (0x03 << 10) - -#define S3C2410_GPB6_nXBREQ (0x02 << 12) -#define S3C2443_GPB6_XBREQ (0x03 << 12) - -#define S3C2410_GPB7_nXDACK1 (0x02 << 14) -#define S3C2443_GPB7_XDACK1 (0x03 << 14) - -#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) - -#define S3C2410_GPB9_nXDACK0 (0x02 << 18) -#define S3C2443_GPB9_XDACK0 (0x03 << 18) - -#define S3C2410_GPB10_nXDRE0 (0x02 << 20) -#define S3C2443_GPB10_XDREQ0 (0x03 << 20) - -#define S3C2410_GPB_PUPDIS(x) (1<<(x)) - -/* Port C consits of 16 GPIO/Special function - * - * almost identical setup to port b, but the special functions are mostly - * to do with the video system's sync/etc. -*/ - -#define S3C2410_GPCCON S3C2410_GPIOREG(0x20) -#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) -#define S3C2410_GPCUP S3C2410_GPIOREG(0x28) -#define S3C2410_GPC0_LEND (0x02 << 0) -#define S3C2410_GPC1_VCLK (0x02 << 2) -#define S3C2410_GPC2_VLINE (0x02 << 4) -#define S3C2410_GPC3_VFRAME (0x02 << 6) -#define S3C2410_GPC4_VM (0x02 << 8) -#define S3C2410_GPC5_LCDVF0 (0x02 << 10) -#define S3C2410_GPC6_LCDVF1 (0x02 << 12) -#define S3C2410_GPC7_LCDVF2 (0x02 << 14) -#define S3C2410_GPC8_VD0 (0x02 << 16) -#define S3C2410_GPC9_VD1 (0x02 << 18) -#define S3C2410_GPC10_VD2 (0x02 << 20) -#define S3C2410_GPC11_VD3 (0x02 << 22) -#define S3C2410_GPC12_VD4 (0x02 << 24) -#define S3C2410_GPC13_VD5 (0x02 << 26) -#define S3C2410_GPC14_VD6 (0x02 << 28) -#define S3C2410_GPC15_VD7 (0x02 << 30) -#define S3C2410_GPC_PUPDIS(x) (1<<(x)) - -/* - * S3C2410: Port D consists of 16 GPIO/Special function - * - * almost identical setup to port b, but the special functions are mostly - * to do with the video system's data. - * - * almost identical setup to port c -*/ - -#define S3C2410_GPDCON S3C2410_GPIOREG(0x30) -#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) -#define S3C2410_GPDUP S3C2410_GPIOREG(0x38) - -#define S3C2410_GPD0_VD8 (0x02 << 0) -#define S3C2442_GPD0_nSPICS1 (0x03 << 0) - -#define S3C2410_GPD1_VD9 (0x02 << 2) -#define S3C2442_GPD1_SPICLK1 (0x03 << 2) - -#define S3C2410_GPD2_VD10 (0x02 << 4) - -#define S3C2410_GPD3_VD11 (0x02 << 6) - -#define S3C2410_GPD4_VD12 (0x02 << 8) - -#define S3C2410_GPD5_VD13 (0x02 << 10) - -#define S3C2410_GPD6_VD14 (0x02 << 12) - -#define S3C2410_GPD7_VD15 (0x02 << 14) - -#define S3C2410_GPD8_VD16 (0x02 << 16) -#define S3C2440_GPD8_SPIMISO1 (0x03 << 16) - -#define S3C2410_GPD9_VD17 (0x02 << 18) -#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) - -#define S3C2410_GPD10_VD18 (0x02 << 20) -#define S3C2440_GPD10_SPICLK1 (0x03 << 20) - -#define S3C2410_GPD11_VD19 (0x02 << 22) - -#define S3C2410_GPD12_VD20 (0x02 << 24) - -#define S3C2410_GPD13_VD21 (0x02 << 26) - -#define S3C2410_GPD14_VD22 (0x02 << 28) -#define S3C2410_GPD14_nSS1 (0x03 << 28) - -#define S3C2410_GPD15_VD23 (0x02 << 30) -#define S3C2410_GPD15_nSS0 (0x03 << 30) - -#define S3C2410_GPD_PUPDIS(x) (1<<(x)) - -/* S3C2410: - * Port E consists of 16 GPIO/Special function - * - * again, the same as port B, but dealing with I2S, SDI, and - * more miscellaneous functions - * - * GPIO / interrupt inputs -*/ - -#define S3C2410_GPECON S3C2410_GPIOREG(0x40) -#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) -#define S3C2410_GPEUP S3C2410_GPIOREG(0x48) - -#define S3C2410_GPE0_I2SLRCK (0x02 << 0) -#define S3C2443_GPE0_AC_nRESET (0x03 << 0) -#define S3C2410_GPE0_MASK (0x03 << 0) - -#define S3C2410_GPE1_I2SSCLK (0x02 << 2) -#define S3C2443_GPE1_AC_SYNC (0x03 << 2) -#define S3C2410_GPE1_MASK (0x03 << 2) - -#define S3C2410_GPE2_CDCLK (0x02 << 4) -#define S3C2443_GPE2_AC_BITCLK (0x03 << 4) - -#define S3C2410_GPE3_I2SSDI (0x02 << 6) -#define S3C2443_GPE3_AC_SDI (0x03 << 6) -#define S3C2410_GPE3_nSS0 (0x03 << 6) -#define S3C2410_GPE3_MASK (0x03 << 6) - -#define S3C2410_GPE4_I2SSDO (0x02 << 8) -#define S3C2443_GPE4_AC_SDO (0x03 << 8) -#define S3C2410_GPE4_I2SSDI (0x03 << 8) -#define S3C2410_GPE4_MASK (0x03 << 8) - -#define S3C2410_GPE5_SDCLK (0x02 << 10) -#define S3C2443_GPE5_SD1_CLK (0x02 << 10) -#define S3C2443_GPE5_AC_BITCLK (0x03 << 10) - -#define S3C2410_GPE6_SDCMD (0x02 << 12) -#define S3C2443_GPE6_SD1_CMD (0x02 << 12) -#define S3C2443_GPE6_AC_SDI (0x03 << 12) - -#define S3C2410_GPE7_SDDAT0 (0x02 << 14) -#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) -#define S3C2443_GPE7_AC_SDO (0x03 << 14) - -#define S3C2410_GPE8_SDDAT1 (0x02 << 16) -#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) -#define S3C2443_GPE8_AC_SYNC (0x03 << 16) - -#define S3C2410_GPE9_SDDAT2 (0x02 << 18) -#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) -#define S3C2443_GPE9_AC_nRESET (0x03 << 18) - -#define S3C2410_GPE10_SDDAT3 (0x02 << 20) -#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) - -#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) - -#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) - -#define S3C2410_GPE13_SPICLK0 (0x02 << 26) - -#define S3C2410_GPE14_IICSCL (0x02 << 28) -#define S3C2410_GPE14_MASK (0x03 << 28) - -#define S3C2410_GPE15_IICSDA (0x02 << 30) -#define S3C2410_GPE15_MASK (0x03 << 30) - -#define S3C2440_GPE0_ACSYNC (0x03 << 0) -#define S3C2440_GPE1_ACBITCLK (0x03 << 2) -#define S3C2440_GPE2_ACRESET (0x03 << 4) -#define S3C2440_GPE3_ACIN (0x03 << 6) -#define S3C2440_GPE4_ACOUT (0x03 << 8) - -#define S3C2410_GPE_PUPDIS(x) (1<<(x)) - -/* S3C2410: - * Port F consists of 8 GPIO/Special function - * - * GPIO / interrupt inputs - * - * GPFCON has 2 bits for each of the input pins on port F - * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined - * - * pull up works like all other ports. - * - * GPIO/serial/misc pins -*/ - -#define S3C2410_GPFCON S3C2410_GPIOREG(0x50) -#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) -#define S3C2410_GPFUP S3C2410_GPIOREG(0x58) - -#define S3C2410_GPF0_EINT0 (0x02 << 0) -#define S3C2410_GPF1_EINT1 (0x02 << 2) -#define S3C2410_GPF2_EINT2 (0x02 << 4) -#define S3C2410_GPF3_EINT3 (0x02 << 6) -#define S3C2410_GPF4_EINT4 (0x02 << 8) -#define S3C2410_GPF5_EINT5 (0x02 << 10) -#define S3C2410_GPF6_EINT6 (0x02 << 12) -#define S3C2410_GPF7_EINT7 (0x02 << 14) -#define S3C2410_GPF_PUPDIS(x) (1<<(x)) - -/* S3C2410: - * Port G consists of 8 GPIO/IRQ/Special function - * - * GPGCON has 2 bits for each of the input pins on port G - * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func - * - * pull up works like all other ports. -*/ - -#define S3C2410_GPGCON S3C2410_GPIOREG(0x60) -#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) -#define S3C2410_GPGUP S3C2410_GPIOREG(0x68) - -#define S3C2410_GPG0_EINT8 (0x02 << 0) - -#define S3C2410_GPG1_EINT9 (0x02 << 2) - -#define S3C2410_GPG2_EINT10 (0x02 << 4) -#define S3C2410_GPG2_nSS0 (0x03 << 4) - -#define S3C2410_GPG3_EINT11 (0x02 << 6) -#define S3C2410_GPG3_nSS1 (0x03 << 6) - -#define S3C2410_GPG4_EINT12 (0x02 << 8) -#define S3C2410_GPG4_LCDPWREN (0x03 << 8) -#define S3C2443_GPG4_LCDPWRDN (0x03 << 8) - -#define S3C2410_GPG5_EINT13 (0x02 << 10) -#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ - -#define S3C2410_GPG6_EINT14 (0x02 << 12) -#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) - -#define S3C2410_GPG7_EINT15 (0x02 << 14) -#define S3C2410_GPG7_SPICLK1 (0x03 << 14) - -#define S3C2410_GPG8_EINT16 (0x02 << 16) - -#define S3C2410_GPG9_EINT17 (0x02 << 18) - -#define S3C2410_GPG10_EINT18 (0x02 << 20) - -#define S3C2410_GPG11_EINT19 (0x02 << 22) -#define S3C2410_GPG11_TCLK1 (0x03 << 22) -#define S3C2443_GPG11_CF_nIREQ (0x03 << 22) - -#define S3C2410_GPG12_EINT20 (0x02 << 24) -#define S3C2410_GPG12_XMON (0x03 << 24) -#define S3C2442_GPG12_nSPICS0 (0x03 << 24) -#define S3C2443_GPG12_nINPACK (0x03 << 24) - -#define S3C2410_GPG13_EINT21 (0x02 << 26) -#define S3C2410_GPG13_nXPON (0x03 << 26) -#define S3C2443_GPG13_CF_nREG (0x03 << 26) - -#define S3C2410_GPG14_EINT22 (0x02 << 28) -#define S3C2410_GPG14_YMON (0x03 << 28) -#define S3C2443_GPG14_CF_RESET (0x03 << 28) - -#define S3C2410_GPG15_EINT23 (0x02 << 30) -#define S3C2410_GPG15_nYPON (0x03 << 30) -#define S3C2443_GPG15_CF_PWR (0x03 << 30) - -#define S3C2410_GPG_PUPDIS(x) (1<<(x)) - -/* Port H consists of11 GPIO/serial/Misc pins - * - * GPHCON has 2 bits for each of the input pins on port H - * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func - * - * pull up works like all other ports. -*/ - -#define S3C2410_GPHCON S3C2410_GPIOREG(0x70) -#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) -#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) - -#define S3C2410_GPH0_nCTS0 (0x02 << 0) -#define S3C2416_GPH0_TXD0 (0x02 << 0) - -#define S3C2410_GPH1_nRTS0 (0x02 << 2) -#define S3C2416_GPH1_RXD0 (0x02 << 2) - -#define S3C2410_GPH2_TXD0 (0x02 << 4) -#define S3C2416_GPH2_TXD1 (0x02 << 4) - -#define S3C2410_GPH3_RXD0 (0x02 << 6) -#define S3C2416_GPH3_RXD1 (0x02 << 6) - -#define S3C2410_GPH4_TXD1 (0x02 << 8) -#define S3C2416_GPH4_TXD2 (0x02 << 8) - -#define S3C2410_GPH5_RXD1 (0x02 << 10) -#define S3C2416_GPH5_RXD2 (0x02 << 10) - -#define S3C2410_GPH6_TXD2 (0x02 << 12) -#define S3C2416_GPH6_TXD3 (0x02 << 12) -#define S3C2410_GPH6_nRTS1 (0x03 << 12) -#define S3C2416_GPH6_nRTS2 (0x03 << 12) - -#define S3C2410_GPH7_RXD2 (0x02 << 14) -#define S3C2416_GPH7_RXD3 (0x02 << 14) -#define S3C2410_GPH7_nCTS1 (0x03 << 14) -#define S3C2416_GPH7_nCTS2 (0x03 << 14) - -#define S3C2410_GPH8_UCLK (0x02 << 16) -#define S3C2416_GPH8_nCTS0 (0x02 << 16) - -#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) -#define S3C2442_GPH9_nSPICS0 (0x03 << 18) -#define S3C2416_GPH9_nRTS0 (0x02 << 18) - -#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) -#define S3C2416_GPH10_nCTS1 (0x02 << 20) - -#define S3C2416_GPH11_nRTS1 (0x02 << 22) - -#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24) - -#define S3C2416_GPH13_CLKOUT0 (0x02 << 26) - -#define S3C2416_GPH14_CLKOUT1 (0x02 << 28) - -/* The S3C2412 and S3C2413 move the GPJ register set to after - * GPH, which means all registers after 0x80 are now offset by 0x10 - * for the 2412/2413 from the 2410/2440/2442 -*/ - -/* - * Port J consists of 13 GPIO/Camera pins. GPJCON has 2 bits - * for each of the pins on port J. - * 00 - input, 01 output, 10 - camera - * - * Pull up works like all other ports. - */ - -#define S3C2413_GPJCON S3C2410_GPIOREG(0x80) -#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) -#define S3C2413_GPJUP S3C2410_GPIOREG(0x88) -#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) - -/* S3C2443 and above */ -#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) -#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) -#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8) - -#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0) -#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4) -#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8) - -#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0) -#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4) -#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8) - -#define S3C2443_GPMCON S3C2410_GPIOREG(0x100) -#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104) -#define S3C2443_GPMUP S3C2410_GPIOREG(0x108) - -/* miscellaneous control */ -#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) - -/* see clock.h for dclk definitions */ - -/* pullup control on databus */ -#define S3C2410_MISCCR_SPUCR_HEN (0<<0) -#define S3C2410_MISCCR_SPUCR_HDIS (1<<0) -#define S3C2410_MISCCR_SPUCR_LEN (0<<1) -#define S3C2410_MISCCR_SPUCR_LDIS (1<<1) - -#define S3C2410_MISCCR_USBDEV (0<<3) -#define S3C2410_MISCCR_USBHOST (1<<3) - -#define S3C2410_MISCCR_CLK0_MPLL (0<<4) -#define S3C2410_MISCCR_CLK0_UPLL (1<<4) -#define S3C2410_MISCCR_CLK0_FCLK (2<<4) -#define S3C2410_MISCCR_CLK0_HCLK (3<<4) -#define S3C2410_MISCCR_CLK0_PCLK (4<<4) -#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) -#define S3C2410_MISCCR_CLK0_MASK (7<<4) - -#define S3C2412_MISCCR_CLK0_RTC (2<<4) - -#define S3C2410_MISCCR_CLK1_MPLL (0<<8) -#define S3C2410_MISCCR_CLK1_UPLL (1<<8) -#define S3C2410_MISCCR_CLK1_FCLK (2<<8) -#define S3C2410_MISCCR_CLK1_HCLK (3<<8) -#define S3C2410_MISCCR_CLK1_PCLK (4<<8) -#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) -#define S3C2410_MISCCR_CLK1_MASK (7<<8) - -#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) - -#define S3C2410_MISCCR_USBSUSPND0 (1<<12) -#define S3C2416_MISCCR_SEL_SUSPND (1<<12) -#define S3C2410_MISCCR_USBSUSPND1 (1<<13) - -#define S3C2410_MISCCR_nRSTCON (1<<16) - -#define S3C2410_MISCCR_nEN_SCLK0 (1<<17) -#define S3C2410_MISCCR_nEN_SCLK1 (1<<18) -#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ -#define S3C2410_MISCCR_SDSLEEP (7<<17) - -#define S3C2416_MISCCR_FLT_I2C (1<<24) -#define S3C2416_MISCCR_HSSPI_EN2 (1<<31) - -/* external interrupt control... */ -/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 - * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 - * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 - * - * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 - * - * Samsung datasheet p9-25 -*/ -#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) -#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) -#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) - -#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88) -#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) -#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) - -/* interrupt filtering control for EINT16..EINT23 */ -#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) -#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) -#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) -#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) - -#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94) -#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98) -#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C) -#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0) - -/* values for interrupt filtering */ -#define S3C2410_EINTFLT_PCLK (0x00) -#define S3C2410_EINTFLT_EXTCLK (1<<7) -#define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f) - -/* removed EINTxxxx defs from here, not meant for this */ - -/* GSTATUS have miscellaneous information in them - * - * These move between s3c2410 and s3c2412 style systems. - */ - -#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) -#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0) -#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4) -#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) -#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) - -#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC) -#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0) -#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4) -#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8) -#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC) - -#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC) -#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0) -#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4) -#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8) -#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC) - -#define S3C2410_GSTATUS0_nWAIT (1<<3) -#define S3C2410_GSTATUS0_NCON (1<<2) -#define S3C2410_GSTATUS0_RnB (1<<1) -#define S3C2410_GSTATUS0_nBATTFLT (1<<0) - -#define S3C2410_GSTATUS1_IDMASK (0xffff0000) -#define S3C2410_GSTATUS1_2410 (0x32410000) -#define S3C2410_GSTATUS1_2412 (0x32412001) -#define S3C2410_GSTATUS1_2416 (0x32416003) -#define S3C2410_GSTATUS1_2440 (0x32440000) -#define S3C2410_GSTATUS1_2442 (0x32440aaa) -/* some 2416 CPUs report this value also */ -#define S3C2410_GSTATUS1_2450 (0x32450003) - -#define S3C2410_GSTATUS2_WTRESET (1<<2) -#define S3C2410_GSTATUS2_OFFRESET (1<<1) -#define S3C2410_GSTATUS2_PONRESET (1<<0) - -/* 2412/2413 sleep configuration registers */ - -#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) -#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) -#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) -#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) -#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) -#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) - -/* definitions for each pin bit */ -#define S3C2412_GPIO_SLPCON_LOW ( 0x00 ) -#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 ) -#define S3C2412_GPIO_SLPCON_IN ( 0x02 ) -#define S3C2412_GPIO_SLPCON_PULL ( 0x03 ) - -#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) -#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) -#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) -#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) -#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ -#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) - -#define S3C2412_SLPCON_ALL_LOW (0x0) -#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) -#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) -#define S3C2412_SLPCON_ALL_PULL (0x33333333) - -#endif /* __ASM_ARCH_REGS_GPIO_H */ - diff --git a/arch/arm/mach-s3c/include/mach/regs-gpio-s3c64xx.h b/arch/arm/mach-s3c/include/mach/regs-gpio-s3c64xx.h deleted file mode 100644 index 592a2be3d2aa..000000000000 --- a/arch/arm/mach-s3c/include/mach/regs-gpio-s3c64xx.h +++ /dev/null @@ -1,188 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - GPIO register definitions - */ - -#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H -#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__ - -/* Base addresses for each of the banks */ - -#define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg)) - -#define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000) -#define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020) -#define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040) -#define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060) -#define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080) -#define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0) -#define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0) -#define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0) -#define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100) -#define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120) -#define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800) -#define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810) -#define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820) -#define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830) -#define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140) -#define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160) -#define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180) - -/* SPCON */ - -#define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0) - -#define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30) -#define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30) -#define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30) -#define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30) -#define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30) -#define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30) - -#define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28) -#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28) -#define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28) -#define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28) -#define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28) -#define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28) - -#define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26) -#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26) -#define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26) -#define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26) -#define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26) -#define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26) - -#define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24) -#define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24) -#define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24) -#define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24) -#define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24) -#define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24) - -#define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22) -#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22) -#define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22) -#define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22) -#define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22) -#define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22) - -#define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21) - -#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18) -#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18) -#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18) -#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18) -#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18) -#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18) - -#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16) -#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16) -#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16) -#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16) -#define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16) - -#define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14) -#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14) -#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14) -#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14) -#define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14) - -#define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12) -#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12) -#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12) -#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12) -#define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12) - -#define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8) -#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8) -#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8) -#define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8) -#define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8) - -#define S3C64XX_SPCON_USBH_DMPD (1 << 7) -#define S3C64XX_SPCON_USBH_DPPD (1 << 6) -#define S3C64XX_SPCON_USBH_PUSW2 (1 << 5) -#define S3C64XX_SPCON_USBH_PUSW1 (1 << 4) -#define S3C64XX_SPCON_USBH_SUSPND (1 << 3) - -#define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0) -#define S3C64XX_SPCON_LCD_SEL_SHIFT (0) -#define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0) -#define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0) -#define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0) - - -/* External interrupt registers */ - -#define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200) -#define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204) -#define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208) -#define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C) -#define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210) - -#define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220) -#define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224) -#define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228) -#define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C) -#define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230) - -#define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240) -#define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244) -#define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248) -#define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C) -#define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250) - -#define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260) -#define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264) -#define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268) -#define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C) -#define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270) - -#define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280) -#define S3C64XX_PRIORITY_ARB(x) (1 << (x)) - -#define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284) -#define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288) - -#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) -#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) -#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) -#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) -#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) -#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) - -#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) -#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) - -/* GPIO sleep configuration */ - -#define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880) - -#define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14) -#define S3C64XX_SPCONSLP_CKE1INIT (1 << 5) - -#define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12) -#define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12) -#define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12) -#define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12) - -#define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0) -#define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0) -#define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0) -#define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0) - - -#define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930) - -#define S3C64XX_SLPEN_USE_xSLP (1 << 0) -#define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1) - -#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ - diff --git a/arch/arm/mach-s3c/include/mach/regs-gpio.h b/arch/arm/mach-s3c/include/mach/regs-gpio.h deleted file mode 100644 index 0d41cb76d440..000000000000 --- a/arch/arm/mach-s3c/include/mach/regs-gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifdef CONFIG_ARCH_S3C24XX -#include "regs-gpio-s3c24xx.h" -#endif - -#ifdef CONFIG_ARCH_S3C64XX -#include "regs-gpio-s3c64xx.h" -#endif diff --git a/arch/arm/mach-s3c/include/mach/regs-irq-s3c24xx.h b/arch/arm/mach-s3c/include/mach/regs-irq-s3c24xx.h deleted file mode 100644 index 2921b48c56b2..000000000000 --- a/arch/arm/mach-s3c/include/mach/regs-irq-s3c24xx.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003 Simtec Electronics - * http://www.simtec.co.uk/products/SWLINUX/ - */ - - -#ifndef ___ASM_ARCH_REGS_IRQ_H -#define ___ASM_ARCH_REGS_IRQ_H - -#include - -/* interrupt controller */ - -#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ) -#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO) -#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2) - -#define S3C2410_SRCPND S3C2410_IRQREG(0x000) -#define S3C2410_INTMOD S3C2410_IRQREG(0x004) -#define S3C2410_INTMSK S3C2410_IRQREG(0x008) -#define S3C2410_PRIORITY S3C2410_IRQREG(0x00C) -#define S3C2410_INTPND S3C2410_IRQREG(0x010) -#define S3C2410_INTOFFSET S3C2410_IRQREG(0x014) -#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018) -#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C) - -#define S3C2416_PRIORITY_MODE1 S3C2410_IRQREG(0x030) -#define S3C2416_PRIORITY_UPDATE1 S3C2410_IRQREG(0x034) -#define S3C2416_SRCPND2 S3C2410_IRQREG(0x040) -#define S3C2416_INTMOD2 S3C2410_IRQREG(0x044) -#define S3C2416_INTMSK2 S3C2410_IRQREG(0x048) -#define S3C2416_INTPND2 S3C2410_IRQREG(0x050) -#define S3C2416_INTOFFSET2 S3C2410_IRQREG(0x054) -#define S3C2416_PRIORITY_MODE2 S3C2410_IRQREG(0x070) -#define S3C2416_PRIORITY_UPDATE2 S3C2410_IRQREG(0x074) - -/* mask: 0=enable, 1=disable - * 1 bit EINT, 4=EINT4, 23=EINT23 - * EINT0,1,2,3 are not handled here. -*/ - -#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4) -#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8) -#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4) -#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8) - -#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4) -#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8) - -#endif /* ___ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s3c/include/mach/regs-irq-s3c64xx.h b/arch/arm/mach-s3c/include/mach/regs-irq-s3c64xx.h deleted file mode 100644 index b18c7bcb61c5..000000000000 --- a/arch/arm/mach-s3c/include/mach/regs-irq-s3c64xx.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C64XX - IRQ register definitions - */ - -#ifndef __ASM_ARCH_REGS_IRQ_H -#define __ASM_ARCH_REGS_IRQ_H __FILE__ - - -#endif /* __ASM_ARCH_6400_REGS_IRQ_H */ diff --git a/arch/arm/mach-s3c/include/mach/regs-irq.h b/arch/arm/mach-s3c/include/mach/regs-irq.h deleted file mode 100644 index 57f0dda8dbf5..000000000000 --- a/arch/arm/mach-s3c/include/mach/regs-irq.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifdef CONFIG_ARCH_S3C24XX -#include "regs-irq-s3c24xx.h" -#endif - -#ifdef CONFIG_ARCH_S3C64XX -#include "regs-irq-s3c64xx.h" -#endif diff --git a/arch/arm/mach-s3c/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c/include/mach/regs-s3c2443-clock.h deleted file mode 100644 index fefef7233f4b..000000000000 --- a/arch/arm/mach-s3c/include/mach/regs-s3c2443-clock.h +++ /dev/null @@ -1,238 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2007 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C2443 clock register definitions - */ - -#ifndef __ASM_ARM_REGS_S3C2443_CLOCK -#define __ASM_ARM_REGS_S3C2443_CLOCK - -#include -#include - -#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) - -#define S3C2443_PLLCON_MDIVSHIFT 16 -#define S3C2443_PLLCON_PDIVSHIFT 8 -#define S3C2443_PLLCON_SDIVSHIFT 0 -#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1) -#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1) -#define S3C2443_PLLCON_SDIVMASK (3) - -#define S3C2443_MPLLCON S3C2443_CLKREG(0x10) -#define S3C2443_EPLLCON S3C2443_CLKREG(0x18) -#define S3C2443_CLKSRC S3C2443_CLKREG(0x20) -#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24) -#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28) -#define S3C2443_HCLKCON S3C2443_CLKREG(0x30) -#define S3C2443_PCLKCON S3C2443_CLKREG(0x34) -#define S3C2443_SCLKCON S3C2443_CLKREG(0x38) -#define S3C2443_PWRMODE S3C2443_CLKREG(0x40) -#define S3C2443_SWRST S3C2443_CLKREG(0x44) -#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50) -#define S3C2443_SYSID S3C2443_CLKREG(0x5C) -#define S3C2443_PWRCFG S3C2443_CLKREG(0x60) -#define S3C2443_RSTCON S3C2443_CLKREG(0x64) -#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80) -#define S3C2443_PHYPWR S3C2443_CLKREG(0x84) -#define S3C2443_URSTCON S3C2443_CLKREG(0x88) -#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C) - -#define S3C2443_PLLCON_OFF (1<<24) - -#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7) -#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7) -#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7) -#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7) -#define S3C2443_CLKSRC_EPLLREF_MASK (3<<7) - -#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3) - -#define S3C2443_CLKDIV0_HALF_HCLK (1<<3) -#define S3C2443_CLKDIV0_HALF_PCLK (1<<2) - -#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0) - -#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6) -#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6) - -#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4) -#define S3C2443_CLKDIV0_PREDIV_SHIFT (4) - -#define S3C2416_CLKDIV0_ARMDIV_MASK (7 << 9) -#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9) -#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9) -#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9) -#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9) -#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9) -#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9) -#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9) -#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9) -#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9) -#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9) - -/* S3C2443_CLKDIV1 removed, only used in clock.c code */ - -#define S3C2443_CLKCON_NAND - -#define S3C2443_HCLKCON_DMA0 (1<<0) -#define S3C2443_HCLKCON_DMA1 (1<<1) -#define S3C2443_HCLKCON_DMA2 (1<<2) -#define S3C2443_HCLKCON_DMA3 (1<<3) -#define S3C2443_HCLKCON_DMA4 (1<<4) -#define S3C2443_HCLKCON_DMA5 (1<<5) -#define S3C2443_HCLKCON_CAMIF (1<<8) -#define S3C2443_HCLKCON_LCDC (1<<9) -#define S3C2443_HCLKCON_USBH (1<<11) -#define S3C2443_HCLKCON_USBD (1<<12) -#define S3C2416_HCLKCON_HSMMC0 (1<<15) -#define S3C2443_HCLKCON_HSMMC (1<<16) -#define S3C2443_HCLKCON_CFC (1<<17) -#define S3C2443_HCLKCON_SSMC (1<<18) -#define S3C2443_HCLKCON_DRAMC (1<<19) - -#define S3C2443_PCLKCON_UART0 (1<<0) -#define S3C2443_PCLKCON_UART1 (1<<1) -#define S3C2443_PCLKCON_UART2 (1<<2) -#define S3C2443_PCLKCON_UART3 (1<<3) -#define S3C2443_PCLKCON_IIC (1<<4) -#define S3C2443_PCLKCON_SDI (1<<5) -#define S3C2443_PCLKCON_HSSPI (1<<6) -#define S3C2443_PCLKCON_ADC (1<<7) -#define S3C2443_PCLKCON_AC97 (1<<8) -#define S3C2443_PCLKCON_IIS (1<<9) -#define S3C2443_PCLKCON_PWMT (1<<10) -#define S3C2443_PCLKCON_WDT (1<<11) -#define S3C2443_PCLKCON_RTC (1<<12) -#define S3C2443_PCLKCON_GPIO (1<<13) -#define S3C2443_PCLKCON_SPI0 (1<<14) -#define S3C2443_PCLKCON_SPI1 (1<<15) - -#define S3C2443_SCLKCON_DDRCLK (1<<16) -#define S3C2443_SCLKCON_SSMCCLK (1<<15) -#define S3C2443_SCLKCON_HSSPICLK (1<<14) -#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13) -#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12) -#define S3C2443_SCLKCON_CAMCLK (1<<11) -#define S3C2443_SCLKCON_DISPCLK (1<<10) -#define S3C2443_SCLKCON_I2SCLK (1<<9) -#define S3C2443_SCLKCON_UARTCLK (1<<8) -#define S3C2443_SCLKCON_USBHOST (1<<1) - -#define S3C2443_PWRCFG_SLEEP (1<<15) - -#define S3C2443_PWRCFG_USBPHY (1 << 4) - -#define S3C2443_URSTCON_FUNCRST (1 << 2) -#define S3C2443_URSTCON_PHYRST (1 << 0) - -#define S3C2443_PHYCTRL_CLKSEL (1 << 3) -#define S3C2443_PHYCTRL_EXTCLK (1 << 2) -#define S3C2443_PHYCTRL_PLLSEL (1 << 1) -#define S3C2443_PHYCTRL_DSPORT (1 << 0) - -#define S3C2443_PHYPWR_COMMON_ON (1 << 31) -#define S3C2443_PHYPWR_ANALOG_PD (1 << 4) -#define S3C2443_PHYPWR_PLL_REFCLK (1 << 3) -#define S3C2443_PHYPWR_XO_ON (1 << 2) -#define S3C2443_PHYPWR_PLL_PWRDN (1 << 1) -#define S3C2443_PHYPWR_FSUSPEND (1 << 0) - -#define S3C2443_UCLKCON_DETECT_VBUS (1 << 31) -#define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2) -#define S3C2443_UCLKCON_TCLKEN (1 << 0) - -#include - -static inline unsigned int -s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk) -{ - unsigned int mdiv, pdiv, sdiv; - uint64_t fvco; - - mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; - pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; - sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; - - mdiv &= S3C2443_PLLCON_MDIVMASK; - pdiv &= S3C2443_PLLCON_PDIVMASK; - sdiv &= S3C2443_PLLCON_SDIVMASK; - - fvco = (uint64_t)baseclk * (2 * (mdiv + 8)); - do_div(fvco, pdiv << sdiv); - - return (unsigned int)fvco; -} - -static inline unsigned int -s3c2443_get_epll(unsigned int pllval, unsigned int baseclk) -{ - unsigned int mdiv, pdiv, sdiv; - uint64_t fvco; - - mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; - pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; - sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; - - mdiv &= S3C2443_PLLCON_MDIVMASK; - pdiv &= S3C2443_PLLCON_PDIVMASK; - sdiv &= S3C2443_PLLCON_SDIVMASK; - - fvco = (uint64_t)baseclk * (mdiv + 8); - do_div(fvco, (pdiv + 2) << sdiv); - - return (unsigned int)fvco; -} - -static inline void s3c_hsudc_init_phy(void) -{ - u32 cfg; - - cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY; - writel(cfg, S3C2443_PWRCFG); - - cfg = readl(S3C2443_URSTCON); - cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST); - writel(cfg, S3C2443_URSTCON); - mdelay(1); - - cfg = readl(S3C2443_URSTCON); - cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST); - writel(cfg, S3C2443_URSTCON); - - cfg = readl(S3C2443_PHYCTRL); - cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT); - cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL); - writel(cfg, S3C2443_PHYCTRL); - - cfg = readl(S3C2443_PHYPWR); - cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN | - S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK | - S3C2443_PHYPWR_ANALOG_PD); - cfg |= S3C2443_PHYPWR_COMMON_ON; - writel(cfg, S3C2443_PHYPWR); - - cfg = readl(S3C2443_UCLKCON); - cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN | - S3C2443_UCLKCON_TCLKEN); - writel(cfg, S3C2443_UCLKCON); -} - -static inline void s3c_hsudc_uninit_phy(void) -{ - u32 cfg; - - cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY; - writel(cfg, S3C2443_PWRCFG); - - writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR); - - cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN; - writel(cfg, S3C2443_UCLKCON); -} - -#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */ - diff --git a/arch/arm/mach-s3c/include/mach/rtc-core-s3c24xx.h b/arch/arm/mach-s3c/include/mach/rtc-core-s3c24xx.h deleted file mode 100644 index e7258b2423fc..000000000000 --- a/arch/arm/mach-s3c/include/mach/rtc-core-s3c24xx.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2011 Heiko Stuebner - * - * Samsung RTC Controller core functions - */ - -#ifndef __RTC_CORE_S3C24XX_H -#define __RTC_CORE_S3C24XX_H __FILE__ - -/* These functions are only for use with the core support code, such as - * the cpu specific initialisation code - */ - -extern struct platform_device s3c_device_rtc; - -/* re-define device name depending on support. */ -static inline void s3c_rtc_setname(char *name) -{ - s3c_device_rtc.name = name; -} - -#endif /* __RTC_CORE_S3C24XX_H */ diff --git a/arch/arm/mach-s3c/include/mach/s3c2412.h b/arch/arm/mach-s3c/include/mach/s3c2412.h deleted file mode 100644 index 1ae369c81beb..000000000000 --- a/arch/arm/mach-s3c/include/mach/s3c2412.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - */ - -#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H -#define __ARCH_ARM_MACH_S3C24XX_S3C2412_H __FILE__ - -#include - -#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) - -#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) -#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) - -#define S3C2412_REFRESH S3C2412_MEMREG(0x10) - -#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x4) - -#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x0) - -#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */ diff --git a/arch/arm/mach-s3c/include/plat/adc-core.h b/arch/arm/mach-s3c/include/plat/adc-core.h deleted file mode 100644 index 039f6862b6a7..000000000000 --- a/arch/arm/mach-s3c/include/plat/adc-core.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Samsung ADC Controller core functions - */ - -#ifndef __ASM_PLAT_ADC_CORE_H -#define __ASM_PLAT_ADC_CORE_H __FILE__ - -/* These functions are only for use with the core support code, such as - * the cpu specific initialisation code - */ - -/* re-define device name depending on support. */ -static inline void s3c_adc_setname(char *name) -{ -#if defined(CONFIG_SAMSUNG_DEV_ADC) || defined(CONFIG_PLAT_S3C24XX) - s3c_device_adc.name = name; -#endif -} - -#endif /* __ASM_PLAT_ADC_CORE_H */ diff --git a/arch/arm/mach-s3c/include/plat/cpu.h b/arch/arm/mach-s3c/include/plat/cpu.h deleted file mode 100644 index 20ff98d05c53..000000000000 --- a/arch/arm/mach-s3c/include/plat/cpu.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Copyright (c) 2004-2005 Simtec Electronics - * Ben Dooks - * - * Header file for Samsung CPU support - */ - -/* todo - fix when rmk changes iodescs to use `void __iomem *` */ - -#ifndef __SAMSUNG_PLAT_CPU_H -#define __SAMSUNG_PLAT_CPU_H - -extern unsigned long samsung_cpu_id; - -#define S3C2410_CPU_ID 0x32410000 -#define S3C2410_CPU_MASK 0xFFFFFFFF - -#define S3C24XX_CPU_ID 0x32400000 -#define S3C24XX_CPU_MASK 0xFFF00000 - -#define S3C2412_CPU_ID 0x32412000 -#define S3C2412_CPU_MASK 0xFFFFF000 - -#define S3C6400_CPU_ID 0x36400000 -#define S3C6410_CPU_ID 0x36410000 -#define S3C64XX_CPU_MASK 0xFFFFF000 - -#define S5PV210_CPU_ID 0x43110000 -#define S5PV210_CPU_MASK 0xFFFFF000 - -#define IS_SAMSUNG_CPU(name, id, mask) \ -static inline int is_samsung_##name(void) \ -{ \ - return ((samsung_cpu_id & mask) == (id & mask)); \ -} - -IS_SAMSUNG_CPU(s3c2410, S3C2410_CPU_ID, S3C2410_CPU_MASK) -IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK) -IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK) -IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) -IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK) - -#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ - defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ - defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \ - defined(CONFIG_CPU_S3C2443) -# define soc_is_s3c24xx() is_samsung_s3c24xx() -# define soc_is_s3c2410() is_samsung_s3c2410() -#else -# define soc_is_s3c24xx() 0 -# define soc_is_s3c2410() 0 -#endif - -#if defined(CONFIG_CPU_S3C2412) -# define soc_is_s3c2412() is_samsung_s3c2412() -#else -# define soc_is_s3c2412() 0 -#endif - -#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) -# define soc_is_s3c6400() is_samsung_s3c6400() -# define soc_is_s3c6410() is_samsung_s3c6410() -# define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410()) -#else -# define soc_is_s3c6400() 0 -# define soc_is_s3c6410() 0 -# define soc_is_s3c64xx() 0 -#endif - -#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } - -#ifndef KHZ -#define KHZ (1000) -#endif - -#ifndef MHZ -#define MHZ (1000*1000) -#endif - -#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000) - -/* forward declaration */ -struct s3c24xx_uart_resources; -struct platform_device; -struct s3c2410_uartcfg; -struct map_desc; - -/* per-cpu initialisation function table. */ - -struct cpu_table { - unsigned long idcode; - unsigned long idmask; - void (*map_io)(void); - void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); - void (*init_clocks)(int xtal); - int (*init)(void); - const char *name; -}; - -extern void s3c_init_cpu(unsigned long idcode, - struct cpu_table *cpus, unsigned int cputab_size); - -/* core initialisation functions */ - -extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); - -extern void s3c64xx_init_cpu(void); - -extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); - -extern void s3c24xx_init_clocks(int xtal); - -extern void s3c24xx_init_uartdevs(char *name, - struct s3c24xx_uart_resources *res, - struct s3c2410_uartcfg *cfg, int no); - -extern struct syscore_ops s3c2410_pm_syscore_ops; -extern struct syscore_ops s3c2412_pm_syscore_ops; -extern struct syscore_ops s3c2416_pm_syscore_ops; -extern struct syscore_ops s3c244x_pm_syscore_ops; - -extern struct bus_type s3c6410_subsys; - -#endif diff --git a/arch/arm/mach-s3c/include/plat/devs.h b/arch/arm/mach-s3c/include/plat/devs.h deleted file mode 100644 index 02b0c5750572..000000000000 --- a/arch/arm/mach-s3c/include/plat/devs.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks - * - * Header file for s3c2410 standard platform devices - */ - -#ifndef __PLAT_DEVS_H -#define __PLAT_DEVS_H __FILE__ - -#include - -struct s3c24xx_uart_resources { - struct resource *resources; - unsigned long nr_resources; -}; - -extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; -extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; - -extern struct platform_device *s3c24xx_uart_devs[]; -extern struct platform_device *s3c24xx_uart_src[]; - -extern struct platform_device s3c64xx_device_ac97; -extern struct platform_device s3c64xx_device_iis0; -extern struct platform_device s3c64xx_device_iis1; -extern struct platform_device s3c64xx_device_iisv4; -extern struct platform_device s3c64xx_device_onenand1; -extern struct platform_device s3c64xx_device_pcm0; -extern struct platform_device s3c64xx_device_pcm1; -extern struct platform_device s3c64xx_device_spi0; -extern struct platform_device s3c64xx_device_spi1; -extern struct platform_device s3c64xx_device_spi2; - -extern struct platform_device s3c_device_adc; -extern struct platform_device s3c_device_cfcon; -extern struct platform_device s3c_device_fb; -extern struct platform_device s3c_device_hwmon; -extern struct platform_device s3c_device_hsmmc0; -extern struct platform_device s3c_device_hsmmc1; -extern struct platform_device s3c_device_hsmmc2; -extern struct platform_device s3c_device_hsmmc3; -extern struct platform_device s3c_device_i2c0; -extern struct platform_device s3c_device_i2c1; -extern struct platform_device s3c_device_i2c2; -extern struct platform_device s3c_device_i2c3; -extern struct platform_device s3c_device_i2c4; -extern struct platform_device s3c_device_i2c5; -extern struct platform_device s3c_device_i2c6; -extern struct platform_device s3c_device_i2c7; -extern struct platform_device s3c_device_iis; -extern struct platform_device s3c_device_lcd; -extern struct platform_device s3c_device_nand; -extern struct platform_device s3c_device_ohci; -extern struct platform_device s3c_device_onenand; -extern struct platform_device s3c_device_rtc; -extern struct platform_device s3c_device_sdi; -extern struct platform_device s3c_device_spi0; -extern struct platform_device s3c_device_spi1; -extern struct platform_device s3c_device_ts; -extern struct platform_device s3c_device_timer[]; -extern struct platform_device s3c_device_usbgadget; -extern struct platform_device s3c_device_usb_hsotg; -extern struct platform_device s3c_device_usb_hsudc; -extern struct platform_device s3c_device_wdt; - -extern struct platform_device samsung_asoc_idma; -extern struct platform_device samsung_device_keypad; -extern struct platform_device samsung_device_pwm; - -/* s3c2440 specific devices */ - -#ifdef CONFIG_CPU_S3C2440 - -extern struct platform_device s3c_device_camif; -extern struct platform_device s3c_device_ac97; - -#endif - -/** - * s3c_set_platdata() - helper for setting platform data - * @pd: The default platform data for this device. - * @pdsize: The size of the platform data. - * @pdev: Pointer to the device to fill in. - * - * This helper replaces a number of calls that copy and then set the - * platform data of the device. - */ -extern void *s3c_set_platdata(void *pd, size_t pdsize, - struct platform_device *pdev); - -#endif /* __PLAT_DEVS_H */ diff --git a/arch/arm/mach-s3c/include/plat/fb.h b/arch/arm/mach-s3c/include/plat/fb.h deleted file mode 100644 index 615d381ae32e..000000000000 --- a/arch/arm/mach-s3c/include/plat/fb.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C - FB platform data definitions - */ - -#ifndef __PLAT_S3C_FB_H -#define __PLAT_S3C_FB_H __FILE__ - -#include - -/** - * s3c_fb_set_platdata() - Setup the FB device with platform data. - * @pd: The platform data to set. The data is copied from the passed structure - * so the machine data can mark the data __initdata so that any unused - * machines will end up dumping their data at runtime. - */ -extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); - -/** - * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD - * - * Initialise the GPIO for an 24bpp LCD display on the RGB interface. - */ -extern void s3c64xx_fb_gpio_setup_24bpp(void); - -#endif /* __PLAT_S3C_FB_H */ diff --git a/arch/arm/mach-s3c/include/plat/gpio-cfg-helpers.h b/arch/arm/mach-s3c/include/plat/gpio-cfg-helpers.h deleted file mode 100644 index db0c56f5ca15..000000000000 --- a/arch/arm/mach-s3c/include/plat/gpio-cfg-helpers.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * Samsung Platform - GPIO pin configuration helper definitions - */ - -/* This is meant for core cpu support, machine or other driver files - * should not be including this header. - */ - -#ifndef __PLAT_GPIO_CFG_HELPERS_H -#define __PLAT_GPIO_CFG_HELPERS_H __FILE__ - -/* As a note, all gpio configuration functions are entered exclusively, either - * with the relevant lock held or the system prevented from doing anything else - * by disabling interrupts. -*/ - -static inline int samsung_gpio_do_setcfg(struct samsung_gpio_chip *chip, - unsigned int off, unsigned int config) -{ - return (chip->config->set_config)(chip, off, config); -} - -static inline unsigned samsung_gpio_do_getcfg(struct samsung_gpio_chip *chip, - unsigned int off) -{ - return (chip->config->get_config)(chip, off); -} - -static inline int samsung_gpio_do_setpull(struct samsung_gpio_chip *chip, - unsigned int off, samsung_gpio_pull_t pull) -{ - return (chip->config->set_pull)(chip, off, pull); -} - -static inline samsung_gpio_pull_t samsung_gpio_do_getpull(struct samsung_gpio_chip *chip, - unsigned int off) -{ - return chip->config->get_pull(chip, off); -} - -/* Pull-{up,down} resistor controls. - * - * S3C2410,S3C2440 = Pull-UP, - * S3C2412,S3C2413 = Pull-Down - * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef] - * S3C2443 = Pull-Both [not same as S3C6400] - */ - -/** - * s3c24xx_gpio_setpull_1up() - Pull configuration for choice of up or none. - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * @param: pull: The pull mode being requested. - * - * This is a helper function for the case where we have GPIOs with one - * bit configuring the presence of a pull-up resistor. - */ -extern int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip, - unsigned int off, samsung_gpio_pull_t pull); - -/** - * s3c24xx_gpio_setpull_1down() - Pull configuration for choice of down or none - * @chip: The gpio chip that is being configured - * @off: The offset for the GPIO being configured - * @param: pull: The pull mode being requested - * - * This is a helper function for the case where we have GPIOs with one - * bit configuring the presence of a pull-down resistor. - */ -extern int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip, - unsigned int off, samsung_gpio_pull_t pull); - -/** - * samsung_gpio_setpull_upown() - Pull configuration for choice of up, - * down or none - * - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * @param: pull: The pull mode being requested. - * - * This is a helper function for the case where we have GPIOs with two - * bits configuring the presence of a pull resistor, in the following - * order: - * 00 = No pull resistor connected - * 01 = Pull-up resistor connected - * 10 = Pull-down resistor connected - */ -extern int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, - unsigned int off, samsung_gpio_pull_t pull); - -/** - * samsung_gpio_getpull_updown() - Get configuration for choice of up, - * down or none - * - * @chip: The gpio chip that the GPIO pin belongs to - * @off: The offset to the pin to get the configuration of. - * - * This helper function reads the state of the pull-{up,down} resistor - * for the given GPIO in the same case as samsung_gpio_setpull_upown. -*/ -extern samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip, - unsigned int off); - -/** - * s3c24xx_gpio_getpull_1up() - Get configuration for choice of up or none - * @chip: The gpio chip that the GPIO pin belongs to - * @off: The offset to the pin to get the configuration of. - * - * This helper function reads the state of the pull-up resistor for the - * given GPIO in the same case as s3c24xx_gpio_setpull_1up. -*/ -extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip, - unsigned int off); - -/** - * s3c24xx_gpio_getpull_1down() - Get configuration for choice of down or none - * @chip: The gpio chip that the GPIO pin belongs to - * @off: The offset to the pin to get the configuration of. - * - * This helper function reads the state of the pull-down resistor for the - * given GPIO in the same case as s3c24xx_gpio_setpull_1down. -*/ -extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip, - unsigned int off); - -/** - * s3c2443_gpio_setpull() - Pull configuration for s3c2443. - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * @param: pull: The pull mode being requested. - * - * This is a helper function for the case where we have GPIOs with two - * bits configuring the presence of a pull resistor, in the following - * order: - * 00 = Pull-up resistor connected - * 10 = Pull-down resistor connected - * x1 = No pull up resistor - */ -extern int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip, - unsigned int off, samsung_gpio_pull_t pull); - -/** - * s3c2443_gpio_getpull() - Get configuration for s3c2443 pull resistors - * @chip: The gpio chip that the GPIO pin belongs to. - * @off: The offset to the pin to get the configuration of. - * - * This helper function reads the state of the pull-{up,down} resistor for the - * given GPIO in the same case as samsung_gpio_setpull_upown. -*/ -extern samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip, - unsigned int off); - -#endif /* __PLAT_GPIO_CFG_HELPERS_H */ diff --git a/arch/arm/mach-s3c/include/plat/gpio-cfg.h b/arch/arm/mach-s3c/include/plat/gpio-cfg.h deleted file mode 100644 index 469c220e092b..000000000000 --- a/arch/arm/mach-s3c/include/plat/gpio-cfg.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C Platform - GPIO pin configuration - */ - -/* This file contains the necessary definitions to get the basic gpio - * pin configuration done such as setting a pin to input or output or - * changing the pull-{up,down} configurations. - */ - -/* Note, this interface is being added to the s3c64xx arch first and will - * be added to the s3c24xx systems later. - */ - -#ifndef __PLAT_GPIO_CFG_H -#define __PLAT_GPIO_CFG_H __FILE__ - -#include - -typedef unsigned int __bitwise samsung_gpio_pull_t; - -/* forward declaration if gpio-core.h hasn't been included */ -struct samsung_gpio_chip; - -/** - * struct samsung_gpio_cfg GPIO configuration - * @cfg_eint: Configuration setting when used for external interrupt source - * @get_pull: Read the current pull configuration for the GPIO - * @set_pull: Set the current pull configuration for the GPIO - * @set_config: Set the current configuration for the GPIO - * @get_config: Read the current configuration for the GPIO - * - * Each chip can have more than one type of GPIO bank available and some - * have different capabilites even when they have the same control register - * layouts. Provide an point to vector control routine and provide any - * per-bank configuration information that other systems such as the - * external interrupt code will need. - * - * @sa samsung_gpio_cfgpin - * @sa s3c_gpio_getcfg - * @sa s3c_gpio_setpull - * @sa s3c_gpio_getpull - */ -struct samsung_gpio_cfg { - unsigned int cfg_eint; - - samsung_gpio_pull_t (*get_pull)(struct samsung_gpio_chip *chip, unsigned offs); - int (*set_pull)(struct samsung_gpio_chip *chip, unsigned offs, - samsung_gpio_pull_t pull); - - unsigned (*get_config)(struct samsung_gpio_chip *chip, unsigned offs); - int (*set_config)(struct samsung_gpio_chip *chip, unsigned offs, - unsigned config); -}; - -#define S3C_GPIO_SPECIAL_MARK (0xfffffff0) -#define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x)) - -/* Defines for generic pin configurations */ -#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0)) -#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1)) -#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x)) - -#define samsung_gpio_is_cfg_special(_cfg) \ - (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK) - -/** - * s3c_gpio_cfgpin() - Change the GPIO function of a pin. - * @pin pin The pin number to configure. - * @to to The configuration for the pin's function. - * - * Configure which function is actually connected to the external - * pin, such as an gpio input, output or some form of special function - * connected to an internal peripheral block. - * - * The @to parameter can be one of the generic S3C_GPIO_INPUT, S3C_GPIO_OUTPUT - * or S3C_GPIO_SFN() to indicate one of the possible values that the helper - * will then generate the correct bit mask and shift for the configuration. - * - * If a bank of GPIOs all needs to be set to special-function 2, then - * the following code will work: - * - * for (gpio = start; gpio < end; gpio++) - * s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - * - * The @to parameter can also be a specific value already shifted to the - * correct position in the control register, although these are discouraged - * in newer kernels and are only being kept for compatibility. - */ -extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to); - -/** - * s3c_gpio_getcfg - Read the current function for a GPIO pin - * @pin: The pin to read the configuration value for. - * - * Read the configuration state of the given @pin, returning a value that - * could be passed back to s3c_gpio_cfgpin(). - * - * @sa s3c_gpio_cfgpin - */ -extern unsigned s3c_gpio_getcfg(unsigned int pin); - -/** - * s3c_gpio_cfgpin_range() - Change the GPIO function for configuring pin range - * @start: The pin number to start at - * @nr: The number of pins to configure from @start. - * @cfg: The configuration for the pin's function - * - * Call s3c_gpio_cfgpin() for the @nr pins starting at @start. - * - * @sa s3c_gpio_cfgpin. - */ -extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, - unsigned int cfg); - -/* Define values for the pull-{up,down} available for each gpio pin. - * - * These values control the state of the weak pull-{up,down} resistors - * available on most pins on the S3C series. Not all chips support both - * up or down settings, and it may be dependent on the chip that is being - * used to whether the particular mode is available. - */ -#define S3C_GPIO_PULL_NONE ((__force samsung_gpio_pull_t)0x00) -#define S3C_GPIO_PULL_DOWN ((__force samsung_gpio_pull_t)0x01) -#define S3C_GPIO_PULL_UP ((__force samsung_gpio_pull_t)0x02) - -/** - * s3c_gpio_setpull() - set the state of a gpio pin pull resistor - * @pin: The pin number to configure the pull resistor. - * @pull: The configuration for the pull resistor. - * - * This function sets the state of the pull-{up,down} resistor for the - * specified pin. It will return 0 if successful, or a negative error - * code if the pin cannot support the requested pull setting. - * - * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP. -*/ -extern int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull); - -/** - * s3c_gpio_getpull() - get the pull resistor state of a gpio pin - * @pin: The pin number to get the settings for - * - * Read the pull resistor value for the specified pin. -*/ -extern samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin); - -/* configure `all` aspects of an gpio */ - -/** - * s3c_gpio_cfgall_range() - configure range of gpio functtion and pull. - * @start: The gpio number to start at. - * @nr: The number of gpio to configure from @start. - * @cfg: The configuration to use - * @pull: The pull setting to use. - * - * Run s3c_gpio_cfgpin() and s3c_gpio_setpull() over the gpio range starting - * @gpio and running for @size. - * - * @sa s3c_gpio_cfgpin - * @sa s3c_gpio_setpull - * @sa s3c_gpio_cfgpin_range - */ -extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, - unsigned int cfg, samsung_gpio_pull_t pull); - -static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size, - unsigned int cfg) -{ - return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE); -} - -#endif /* __PLAT_GPIO_CFG_H */ diff --git a/arch/arm/mach-s3c/include/plat/gpio-core.h b/arch/arm/mach-s3c/include/plat/gpio-core.h deleted file mode 100644 index c0bfceb88340..000000000000 --- a/arch/arm/mach-s3c/include/plat/gpio-core.h +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C Platform - GPIO core - */ - -#ifndef __PLAT_SAMSUNG_GPIO_CORE_H -#define __PLAT_SAMSUNG_GPIO_CORE_H - -/* Bring in machine-local definitions, especially S3C_GPIO_END */ -#include -#include - -#define GPIOCON_OFF (0x00) -#define GPIODAT_OFF (0x04) - -#define con_4bit_shift(__off) ((__off) * 4) - -/* Define the core gpiolib support functions that the s3c platforms may - * need to extend or change depending on the hardware and the s3c chip - * selected at build or found at run time. - * - * These definitions are not intended for driver inclusion, there is - * nothing here that should not live outside the platform and core - * specific code. -*/ - -struct samsung_gpio_chip; - -/** - * struct samsung_gpio_pm - power management (suspend/resume) information - * @save: Routine to save the state of the GPIO block - * @resume: Routine to resume the GPIO block. - */ -struct samsung_gpio_pm { - void (*save)(struct samsung_gpio_chip *chip); - void (*resume)(struct samsung_gpio_chip *chip); -}; - -struct samsung_gpio_cfg; - -/** - * struct samsung_gpio_chip - wrapper for specific implementation of gpio - * @chip: The chip structure to be exported via gpiolib. - * @base: The base pointer to the gpio configuration registers. - * @group: The group register number for gpio interrupt support. - * @irq_base: The base irq number. - * @config: special function and pull-resistor control information. - * @lock: Lock for exclusive access to this gpio bank. - * @pm_save: Save information for suspend/resume support. - * @bitmap_gpio_int: Bitmap for representing GPIO interrupt or not. - * - * This wrapper provides the necessary information for the Samsung - * specific gpios being registered with gpiolib. - * - * The lock protects each gpio bank from multiple access of the shared - * configuration registers, or from reading of data whilst another thread - * is writing to the register set. - * - * Each chip has its own lock to avoid any contention between different - * CPU cores trying to get one lock for different GPIO banks, where each - * bank of GPIO has its own register space and configuration registers. - */ -struct samsung_gpio_chip { - struct gpio_chip chip; - struct samsung_gpio_cfg *config; - struct samsung_gpio_pm *pm; - void __iomem *base; - int irq_base; - int group; - spinlock_t lock; -#ifdef CONFIG_PM - u32 pm_save[4]; -#endif - u32 bitmap_gpio_int; -}; - -static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc) -{ - return container_of(gpc, struct samsung_gpio_chip, chip); -} - -/** - * samsung_gpiolib_to_irq - convert gpio pin to irq number - * @chip: The gpio chip that the pin belongs to. - * @offset: The offset of the pin in the chip. - * - * This helper returns the irq number calculated from the chip->irq_base and - * the provided offset. - */ -extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset); - -/* exported for core SoC support to change */ -extern struct samsung_gpio_cfg s3c24xx_gpiocfg_default; - -#ifdef CONFIG_S3C_GPIO_TRACK -extern struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END]; - -static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int chip) -{ - return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; -} -#else -/* machine specific code should provide samsung_gpiolib_getchip */ - -extern struct samsung_gpio_chip s3c24xx_gpios[]; - -static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin) -{ - struct samsung_gpio_chip *chip; - - if (pin > S3C_GPIO_END) - return NULL; - - chip = &s3c24xx_gpios[pin/32]; - return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL; -} - -static inline void s3c_gpiolib_track(struct samsung_gpio_chip *chip) { } -#endif - -#ifdef CONFIG_PM -extern struct samsung_gpio_pm samsung_gpio_pm_1bit; -extern struct samsung_gpio_pm samsung_gpio_pm_2bit; -extern struct samsung_gpio_pm samsung_gpio_pm_4bit; -#define __gpio_pm(x) x -#else -#define samsung_gpio_pm_1bit NULL -#define samsung_gpio_pm_2bit NULL -#define samsung_gpio_pm_4bit NULL -#define __gpio_pm(x) NULL - -#endif /* CONFIG_PM */ - -/* locking wrappers to deal with multiple access to the same gpio bank */ -#define samsung_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) -#define samsung_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) - -#endif /* __PLAT_SAMSUNG_GPIO_CORE_H */ diff --git a/arch/arm/mach-s3c/include/plat/iic-core.h b/arch/arm/mach-s3c/include/plat/iic-core.h deleted file mode 100644 index c5cfd5af3874..000000000000 --- a/arch/arm/mach-s3c/include/plat/iic-core.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * - * S3C - I2C Controller core functions - */ - -#ifndef __ASM_ARCH_IIC_CORE_H -#define __ASM_ARCH_IIC_CORE_H __FILE__ - -/* These functions are only for use with the core support code, such as - * the cpu specific initialisation code - */ - -/* re-define device name depending on support. */ -static inline void s3c_i2c0_setname(char *name) -{ - /* currently this device is always compiled in */ - s3c_device_i2c0.name = name; -} - -static inline void s3c_i2c1_setname(char *name) -{ -#ifdef CONFIG_S3C_DEV_I2C1 - s3c_device_i2c1.name = name; -#endif -} - -static inline void s3c_i2c2_setname(char *name) -{ -#ifdef CONFIG_S3C_DEV_I2C2 - s3c_device_i2c2.name = name; -#endif -} - -#endif /* __ASM_ARCH_IIC_H */ diff --git a/arch/arm/mach-s3c/include/plat/keypad.h b/arch/arm/mach-s3c/include/plat/keypad.h deleted file mode 100644 index 9754b9a29945..000000000000 --- a/arch/arm/mach-s3c/include/plat/keypad.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Samsung Platform - Keypad platform data definitions - * - * Copyright (C) 2010 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim - */ - -#ifndef __PLAT_SAMSUNG_KEYPAD_H -#define __PLAT_SAMSUNG_KEYPAD_H - -#include - -/** - * samsung_keypad_set_platdata - Set platform data for Samsung Keypad device. - * @pd: Platform data to register to device. - * - * Register the given platform data for use with Samsung Keypad device. - * The call will copy the platform data, so the board definitions can - * make the structure itself __initdata. - */ -extern void samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd); - -/* defined by architecture to configure gpio. */ -extern void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols); - -#endif /* __PLAT_SAMSUNG_KEYPAD_H */ diff --git a/arch/arm/mach-s3c/include/plat/map-base.h b/arch/arm/mach-s3c/include/plat/map-base.h deleted file mode 100644 index 34b39ded0e2e..000000000000 --- a/arch/arm/mach-s3c/include/plat/map-base.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2003, 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C - Memory map definitions (virtual addresses) - */ - -#ifndef __ASM_PLAT_MAP_H -#define __ASM_PLAT_MAP_H __FILE__ - -/* Fit all our registers in at 0xF6000000 upwards, trying to use as - * little of the VA space as possible so vmalloc and friends have a - * better chance of getting memory. - * - * we try to ensure stuff like the IRQ registers are available for - * an single MOVS instruction (ie, only 8 bits of set data) - */ - -#define S3C_ADDR_BASE 0xF6000000 - -#ifndef __ASSEMBLY__ -#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) -#else -#define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) -#endif - -#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ -#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ -#define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ -#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ -#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ -#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ - -/* This is used for the CPU specific mappings that may be needed, so that - * they do not need to directly used S3C_ADDR() and thus make it easier to - * modify the space for mapping. - */ -#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x)) - -#endif /* __ASM_PLAT_MAP_H */ diff --git a/arch/arm/mach-s3c/include/plat/map-s3c.h b/arch/arm/mach-s3c/include/plat/map-s3c.h deleted file mode 100644 index bf247d836684..000000000000 --- a/arch/arm/mach-s3c/include/plat/map-s3c.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks - * - * S3C24XX - Memory map definitions - */ - -#ifndef __ASM_PLAT_MAP_S3C_H -#define __ASM_PLAT_MAP_S3C_H __FILE__ - -#include - -#define S3C24XX_VA_IRQ S3C_VA_IRQ -#define S3C24XX_VA_MEMCTRL S3C_VA_MEM -#define S3C24XX_VA_UART S3C_VA_UART - -#define S3C24XX_VA_TIMER S3C_VA_TIMER -#define S3C24XX_VA_CLKPWR S3C_VA_SYS -#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG - -#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000) -#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00100000) - -#define S3C2410_PA_UART (0x50000000) -#define S3C24XX_PA_UART S3C2410_PA_UART - -/* - * GPIO ports - * - * the calculation for the VA of this must ensure that - * it is the same distance apart from the UART in the - * phsyical address space, as the initial mapping for the IO - * is done as a 1:1 mapping. This puts it (currently) at - * 0xFA800000, which is not in the way of any current mapping - * by the base system. -*/ - -#define S3C2410_PA_GPIO (0x56000000) -#define S3C24XX_PA_GPIO S3C2410_PA_GPIO - -#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) -#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000) - -#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000) -#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000) - -#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY - -#define S3C2410_ADDR(x) S3C_ADDR(x) - -/* deal with the registers that move under the 2412/2413 */ - -#if defined(CONFIG_CPU_S3C2412) -#ifndef __ASSEMBLY__ -extern void __iomem *s3c24xx_va_gpio2; -#endif -#ifdef CONFIG_CPU_S3C2412_ONLY -#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) -#else -#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 -#endif -#else -#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO -#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO -#endif - -#include - -#endif /* __ASM_PLAT_MAP_S3C_H */ diff --git a/arch/arm/mach-s3c/include/plat/map-s5p.h b/arch/arm/mach-s3c/include/plat/map-s5p.h deleted file mode 100644 index 3812085f8761..000000000000 --- a/arch/arm/mach-s3c/include/plat/map-s5p.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5P - Memory map definitions - */ - -#ifndef __ASM_PLAT_MAP_S5P_H -#define __ASM_PLAT_MAP_S5P_H __FILE__ - -#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) -#define VA_VIC0 VA_VIC(0) -#define VA_VIC1 VA_VIC(1) -#define VA_VIC2 VA_VIC(2) -#define VA_VIC3 VA_VIC(3) - -#include - -#endif /* __ASM_PLAT_MAP_S5P_H */ diff --git a/arch/arm/mach-s3c/include/plat/pm-common.h b/arch/arm/mach-s3c/include/plat/pm-common.h deleted file mode 100644 index 18b9607e1e39..000000000000 --- a/arch/arm/mach-s3c/include/plat/pm-common.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2013 Samsung Electronics Co., Ltd. - * Tomasz Figa - * Copyright (c) 2004 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Written by Ben Dooks, - */ - -#ifndef __PLAT_SAMSUNG_PM_COMMON_H -#define __PLAT_SAMSUNG_PM_COMMON_H __FILE__ - -#include -#include - -/* sleep save info */ - -/** - * struct sleep_save - save information for shared peripherals. - * @reg: Pointer to the register to save. - * @val: Holder for the value saved from reg. - * - * This describes a list of registers which is used by the pm core and - * other subsystem to save and restore register values over suspend. - */ -struct sleep_save { - void __iomem *reg; - unsigned long val; -}; - -#define SAVE_ITEM(x) \ - { .reg = (x) } - -/* helper functions to save/restore lists of registers. */ - -extern void s3c_pm_do_save(struct sleep_save *ptr, int count); -extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count); -extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count); - -#endif diff --git a/arch/arm/mach-s3c/include/plat/pm.h b/arch/arm/mach-s3c/include/plat/pm.h deleted file mode 100644 index 2746137f9794..000000000000 --- a/arch/arm/mach-s3c/include/plat/pm.h +++ /dev/null @@ -1,109 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2004 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Written by Ben Dooks, - */ - -/* s3c_pm_init - * - * called from board at initialisation time to setup the power - * management -*/ - -#include - -struct device; - -#ifdef CONFIG_SAMSUNG_PM - -extern __init int s3c_pm_init(void); -extern __init int s3c64xx_pm_init(void); - -#else - -static inline int s3c_pm_init(void) -{ - return 0; -} - -static inline int s3c64xx_pm_init(void) -{ - return 0; -} -#endif - -/* configuration for the IRQ mask over sleep */ -extern unsigned long s3c_irqwake_intmask; -extern unsigned long s3c_irqwake_eintmask; - -/* per-cpu sleep functions */ - -extern void (*pm_cpu_prep)(void); -extern int (*pm_cpu_sleep)(unsigned long); - -/* Flags for PM Control */ - -extern unsigned long s3c_pm_flags; - -/* from sleep.S */ - -extern int s3c2410_cpu_suspend(unsigned long); - -#ifdef CONFIG_PM_SLEEP -extern int s3c_irq_wake(struct irq_data *data, unsigned int state); -extern void s3c_cpu_resume(void); -#else -#define s3c_irq_wake NULL -#define s3c_cpu_resume NULL -#endif - -#ifdef CONFIG_SAMSUNG_PM -extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); -#else -#define s3c_irqext_wake NULL -#endif - -#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK -/** - * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs - * @set: set bits for the state of the LEDs - * @clear: clear bits for the state of the LEDs. - */ -extern void s3c_pm_debug_smdkled(u32 set, u32 clear); - -#else -static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { } -#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */ - -/** - * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ - * - * Setup all the necessary GPIO pins for waking the system on external - * interrupt. - */ -extern void s3c_pm_configure_extint(void); - -#ifdef CONFIG_GPIO_SAMSUNG -/** - * samsung_pm_restore_gpios() - restore the state of the gpios after sleep. - * - * Restore the state of the GPIO pins after sleep, which may involve ensuring - * that we do not glitch the state of the pins from that the bootloader's - * resume code has done. -*/ -extern void samsung_pm_restore_gpios(void); - -/** - * samsung_pm_save_gpios() - save the state of the GPIOs for restoring after sleep. - * - * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios(). - */ -extern void samsung_pm_save_gpios(void); -#else -static inline void samsung_pm_restore_gpios(void) {} -static inline void samsung_pm_save_gpios(void) {} -#endif - -extern void s3c_pm_save_core(void); -extern void s3c_pm_restore_core(void); diff --git a/arch/arm/mach-s3c/include/plat/pwm-core.h b/arch/arm/mach-s3c/include/plat/pwm-core.h deleted file mode 100644 index 05e3448642a1..000000000000 --- a/arch/arm/mach-s3c/include/plat/pwm-core.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2013 Tomasz Figa - * - * Samsung PWM controller platform data helpers. - */ - -#ifndef __ASM_ARCH_PWM_CORE_H -#define __ASM_ARCH_PWM_CORE_H __FILE__ - -#include - -#ifdef CONFIG_SAMSUNG_DEV_PWM -extern void samsung_pwm_set_platdata(struct samsung_pwm_variant *pd); -#else -static inline void samsung_pwm_set_platdata(struct samsung_pwm_variant *pd) { } -#endif - -#endif /* __ASM_ARCH_PWM_CORE_H */ diff --git a/arch/arm/mach-s3c/include/plat/regs-adc.h b/arch/arm/mach-s3c/include/plat/regs-adc.h deleted file mode 100644 index 58953c7381dd..000000000000 --- a/arch/arm/mach-s3c/include/plat/regs-adc.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2004 Shannon Holland - * - * S3C2410 ADC registers - */ - -#ifndef __ASM_ARCH_REGS_ADC_H -#define __ASM_ARCH_REGS_ADC_H "regs-adc.h" - -#define S3C2410_ADCREG(x) (x) - -#define S3C2410_ADCCON S3C2410_ADCREG(0x00) -#define S3C2410_ADCTSC S3C2410_ADCREG(0x04) -#define S3C2410_ADCDLY S3C2410_ADCREG(0x08) -#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) -#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) -#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) -#define S3C2443_ADCMUX S3C2410_ADCREG(0x18) -#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) -#define S5P_ADCMUX S3C2410_ADCREG(0x1C) -#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) - - -/* ADCCON Register Bits */ -#define S3C64XX_ADCCON_RESSEL (1<<16) -#define S3C2410_ADCCON_ECFLG (1<<15) -#define S3C2410_ADCCON_PRSCEN (1<<14) -#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) -#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) -#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) -#define S3C2410_ADCCON_MUXMASK (0x7<<3) -#define S3C2416_ADCCON_RESSEL (1 << 3) -#define S3C2410_ADCCON_STDBM (1<<2) -#define S3C2410_ADCCON_READ_START (1<<1) -#define S3C2410_ADCCON_ENABLE_START (1<<0) -#define S3C2410_ADCCON_STARTMASK (0x3<<0) - - -/* ADCTSC Register Bits */ -#define S3C2443_ADCTSC_UD_SEN (1 << 8) -#define S3C2410_ADCTSC_YM_SEN (1<<7) -#define S3C2410_ADCTSC_YP_SEN (1<<6) -#define S3C2410_ADCTSC_XM_SEN (1<<5) -#define S3C2410_ADCTSC_XP_SEN (1<<4) -#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) -#define S3C2410_ADCTSC_AUTO_PST (1<<2) -#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0) - -/* ADCDAT0 Bits */ -#define S3C2410_ADCDAT0_UPDOWN (1<<15) -#define S3C2410_ADCDAT0_AUTO_PST (1<<14) -#define S3C2410_ADCDAT0_XY_PST (0x3<<12) -#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) - -/* ADCDAT1 Bits */ -#define S3C2410_ADCDAT1_UPDOWN (1<<15) -#define S3C2410_ADCDAT1_AUTO_PST (1<<14) -#define S3C2410_ADCDAT1_XY_PST (0x3<<12) -#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) - -#endif /* __ASM_ARCH_REGS_ADC_H */ - - diff --git a/arch/arm/mach-s3c/include/plat/regs-irqtype.h b/arch/arm/mach-s3c/include/plat/regs-irqtype.h deleted file mode 100644 index ec5c4c5fdd8f..000000000000 --- a/arch/arm/mach-s3c/include/plat/regs-irqtype.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C - IRQ detection types. - */ - -/* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including - * the S3C64XX -*/ -#define S3C2410_EXTINT_LOWLEV (0x00) -#define S3C2410_EXTINT_HILEV (0x01) -#define S3C2410_EXTINT_FALLEDGE (0x02) -#define S3C2410_EXTINT_RISEEDGE (0x04) -#define S3C2410_EXTINT_BOTHEDGE (0x06) diff --git a/arch/arm/mach-s3c/include/plat/sdhci.h b/arch/arm/mach-s3c/include/plat/sdhci.h deleted file mode 100644 index 5731e42ea208..000000000000 --- a/arch/arm/mach-s3c/include/plat/sdhci.h +++ /dev/null @@ -1,162 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C Platform - SDHCI (HSMMC) platform data definitions - */ - -#ifndef __PLAT_S3C_SDHCI_H -#define __PLAT_S3C_SDHCI_H __FILE__ - -#include -#include - -/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data - * @pd: The default platform data for this device. - * @set: Pointer to the platform data to fill in. - */ -extern void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd, - struct s3c_sdhci_platdata *set); - -/** - * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device. - * @pd: Platform data to register to device. - * - * Register the given platform data for use withe S3C SDHCI device. - * The call will copy the platform data, so the board definitions can - * make the structure itself __initdata. - */ -extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd); -extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd); -extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd); -extern void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd); - -/* Default platform data, exported so that per-cpu initialisation can - * set the correct one when there are more than one cpu type selected. -*/ - -extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata; -extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; -extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata; -extern struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata; - -/* Helper function availability */ - -extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w); -extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w); -extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); -extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); -extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); - -/* S3C2416 SDHCI setup */ - -#ifdef CONFIG_S3C2416_SETUP_SDHCI -static inline void s3c2416_default_sdhci0(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; -#endif /* CONFIG_S3C_DEV_HSMMC */ -} - -static inline void s3c2416_default_sdhci1(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; -#endif /* CONFIG_S3C_DEV_HSMMC1 */ -} - -#else -static inline void s3c2416_default_sdhci0(void) { } -static inline void s3c2416_default_sdhci1(void) { } - -#endif /* CONFIG_S3C2416_SETUP_SDHCI */ - -/* S3C64XX SDHCI setup */ - -#ifdef CONFIG_S3C64XX_SETUP_SDHCI -static inline void s3c6400_default_sdhci0(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; -#endif -} - -static inline void s3c6400_default_sdhci1(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; -#endif -} - -static inline void s3c6400_default_sdhci2(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; -#endif -} - -static inline void s3c6410_default_sdhci0(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; -#endif -} - -static inline void s3c6410_default_sdhci1(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; -#endif -} - -static inline void s3c6410_default_sdhci2(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; -#endif -} - -#else -static inline void s3c6410_default_sdhci0(void) { } -static inline void s3c6410_default_sdhci1(void) { } -static inline void s3c6410_default_sdhci2(void) { } -static inline void s3c6400_default_sdhci0(void) { } -static inline void s3c6400_default_sdhci1(void) { } -static inline void s3c6400_default_sdhci2(void) { } - -#endif /* CONFIG_S3C64XX_SETUP_SDHCI */ - -static inline void s3c_sdhci_setname(int id, char *name) -{ - switch (id) { -#ifdef CONFIG_S3C_DEV_HSMMC - case 0: - s3c_device_hsmmc0.name = name; - break; -#endif -#ifdef CONFIG_S3C_DEV_HSMMC1 - case 1: - s3c_device_hsmmc1.name = name; - break; -#endif -#ifdef CONFIG_S3C_DEV_HSMMC2 - case 2: - s3c_device_hsmmc2.name = name; - break; -#endif -#ifdef CONFIG_S3C_DEV_HSMMC3 - case 3: - s3c_device_hsmmc3.name = name; - break; -#endif - default: - break; - } -} -#endif /* __PLAT_S3C_SDHCI_H */ diff --git a/arch/arm/mach-s3c/include/plat/usb-phy.h b/arch/arm/mach-s3c/include/plat/usb-phy.h deleted file mode 100644 index 759d66a0773a..000000000000 --- a/arch/arm/mach-s3c/include/plat/usb-phy.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim - */ - -#ifndef __PLAT_SAMSUNG_USB_PHY_H -#define __PLAT_SAMSUNG_USB_PHY_H __FILE__ - -extern int s3c_usb_phy_init(struct platform_device *pdev, int type); -extern int s3c_usb_phy_exit(struct platform_device *pdev, int type); - -#endif /* __PLAT_SAMSUNG_USB_PHY_H */ diff --git a/arch/arm/mach-s3c/include/plat/wakeup-mask.h b/arch/arm/mach-s3c/include/plat/wakeup-mask.h deleted file mode 100644 index 630909e6630b..000000000000 --- a/arch/arm/mach-s3c/include/plat/wakeup-mask.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2010 Ben Dooks - * - * Support for wakeup mask interrupts on newer SoCs - */ - -#ifndef __PLAT_WAKEUP_MASK_H -#define __PLAT_WAKEUP_MASK_H __file__ - -/* if no irq yet defined, but still want to mask */ -#define NO_WAKEUP_IRQ (0x90000000) - -/** - * struct samsung_wakeup_mask - wakeup mask information - * @irq: The interrupt associated with this wakeup. - * @bit: The bit, as a (1 << bitno) controlling this source. - */ -struct samsung_wakeup_mask { - unsigned int irq; - u32 bit; -}; - -/** - * samsung_sync_wakemask - sync wakeup mask information for pm - * @reg: The register that is used. - * @masks: The list of masks to use. - * @nr_masks: The number of entries pointed to buy @masks. - * - * Synchronise the wakeup mask information at suspend time from the list - * of interrupts and control bits in @masks. We do this at suspend time - * as overriding the relevant irq chips is harder and the register is only - * required to be correct before we enter sleep. - */ -extern void samsung_sync_wakemask(void __iomem *reg, - const struct samsung_wakeup_mask *masks, - int nr_masks); - -#endif /* __PLAT_WAKEUP_MASK_H */ diff --git a/arch/arm/mach-s3c/init.c b/arch/arm/mach-s3c/init.c index e9acf02ef3c3..9d92f03e9bc1 100644 --- a/arch/arm/mach-s3c/init.c +++ b/arch/arm/mach-s3c/init.c @@ -23,8 +23,8 @@ #include #include -#include -#include +#include "cpu.h" +#include "devs.h" static struct cpu_table *cpu; diff --git a/arch/arm/mach-s3c/iotiming-s3c2410.c b/arch/arm/mach-s3c/iotiming-s3c2410.c index d91f26efd07a..28d9f473e24a 100644 --- a/arch/arm/mach-s3c/iotiming-s3c2410.c +++ b/arch/arm/mach-s3c/iotiming-s3c2410.c @@ -14,8 +14,8 @@ #include #include -#include -#include +#include "map.h" +#include "regs-clock.h" #include diff --git a/arch/arm/mach-s3c/iotiming-s3c2412.c b/arch/arm/mach-s3c/iotiming-s3c2412.c index a22b5611697d..003f89c4dc53 100644 --- a/arch/arm/mach-s3c/iotiming-s3c2412.c +++ b/arch/arm/mach-s3c/iotiming-s3c2412.c @@ -23,10 +23,10 @@ #include #include -#include +#include "cpu.h" #include -#include +#include "s3c2412.h" #define print_ns(x) ((x) / 10), ((x) % 10) diff --git a/arch/arm/mach-s3c/irq-pm-s3c24xx.c b/arch/arm/mach-s3c/irq-pm-s3c24xx.c index e0131b16a4af..4d5e28312d91 100644 --- a/arch/arm/mach-s3c/irq-pm-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-pm-s3c24xx.c @@ -13,14 +13,14 @@ #include #include -#include -#include -#include -#include - -#include -#include -#include +#include "cpu.h" +#include "pm.h" +#include +#include "map-s3c.h" + +#include "regs-irq.h" +#include "regs-gpio.h" +#include "pm-core.h" #include diff --git a/arch/arm/mach-s3c/irq-pm-s3c64xx.c b/arch/arm/mach-s3c/irq-pm-s3c64xx.c index 31b221190479..4a1e935bada1 100644 --- a/arch/arm/mach-s3c/irq-pm-s3c64xx.c +++ b/arch/arm/mach-s3c/irq-pm-s3c64xx.c @@ -20,11 +20,11 @@ #include #include -#include +#include "map.h" -#include -#include -#include +#include "regs-gpio.h" +#include "cpu.h" +#include "pm.h" /* We handled all the IRQ types in this code, to save having to make several * small files to handle each different type separately. Having the EINT_GRP diff --git a/arch/arm/mach-s3c/irq-s3c24xx-fiq.S b/arch/arm/mach-s3c/irq-s3c24xx-fiq.S index 2a84535a14fd..b54cbd012241 100644 --- a/arch/arm/mach-s3c/irq-s3c24xx-fiq.S +++ b/arch/arm/mach-s3c/irq-s3c24xx-fiq.S @@ -10,8 +10,8 @@ #include #include -#include -#include +#include "map.h" +#include "regs-irq.h" #include diff --git a/arch/arm/mach-s3c/irq-s3c24xx.c b/arch/arm/mach-s3c/irq-s3c24xx.c index 3965347cacf0..79b5f19af7a5 100644 --- a/arch/arm/mach-s3c/irq-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-s3c24xx.c @@ -26,12 +26,12 @@ #include #include -#include -#include +#include "regs-irq.h" +#include "regs-gpio.h" -#include -#include -#include +#include "cpu.h" +#include "regs-irqtype.h" +#include "pm.h" #define S3C_IRQTYPE_NONE 0 #define S3C_IRQTYPE_EINT 1 diff --git a/arch/arm/mach-s3c/keypad.h b/arch/arm/mach-s3c/keypad.h new file mode 100644 index 000000000000..9754b9a29945 --- /dev/null +++ b/arch/arm/mach-s3c/keypad.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Samsung Platform - Keypad platform data definitions + * + * Copyright (C) 2010 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim + */ + +#ifndef __PLAT_SAMSUNG_KEYPAD_H +#define __PLAT_SAMSUNG_KEYPAD_H + +#include + +/** + * samsung_keypad_set_platdata - Set platform data for Samsung Keypad device. + * @pd: Platform data to register to device. + * + * Register the given platform data for use with Samsung Keypad device. + * The call will copy the platform data, so the board definitions can + * make the structure itself __initdata. + */ +extern void samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd); + +/* defined by architecture to configure gpio. */ +extern void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols); + +#endif /* __PLAT_SAMSUNG_KEYPAD_H */ diff --git a/arch/arm/mach-s3c/mach-amlm5900.c b/arch/arm/mach-s3c/mach-amlm5900.c index 724240e1b662..f73a5223663b 100644 --- a/arch/arm/mach-s3c/mach-amlm5900.c +++ b/arch/arm/mach-s3c/mach-amlm5900.c @@ -31,13 +31,13 @@ #include #include -#include -#include +#include "regs-gpio.h" +#include "gpio-samsung.h" #include -#include -#include -#include +#include "devs.h" +#include "cpu.h" +#include "gpio-cfg.h" #include #include diff --git a/arch/arm/mach-s3c/mach-anubis.c b/arch/arm/mach-s3c/mach-anubis.c index 83b2f7fb268e..522bb10e8a19 100644 --- a/arch/arm/mach-s3c/mach-anubis.c +++ b/arch/arm/mach-s3c/mach-anubis.c @@ -27,8 +27,8 @@ #include #include -#include -#include +#include "regs-gpio.h" +#include "gpio-samsung.h" #include #include @@ -39,8 +39,8 @@ #include -#include -#include +#include "devs.h" +#include "cpu.h" #include #include "anubis.h" diff --git a/arch/arm/mach-s3c/mach-anw6410.c b/arch/arm/mach-s3c/mach-anw6410.c index ff183ced8e6e..b4f08e5c9858 100644 --- a/arch/arm/mach-s3c/mach-anw6410.c +++ b/arch/arm/mach-s3c/mach-anw6410.c @@ -30,19 +30,19 @@ #include #include -#include +#include "map.h" #include #include #include -#include +#include "fb.h" -#include -#include +#include "devs.h" +#include "cpu.h" #include -#include -#include +#include "regs-gpio.h" +#include "gpio-samsung.h" #include "s3c64xx.h" #include "regs-modem-s3c64xx.h" diff --git a/arch/arm/mach-s3c/mach-at2440evb.c b/arch/arm/mach-s3c/mach-at2440evb.c index 1ae61ae913d4..13d014bc8371 100644 --- a/arch/arm/mach-s3c/mach-at2440evb.c +++ b/arch/arm/mach-s3c/mach-at2440evb.c @@ -28,8 +28,8 @@ #include #include -#include -#include +#include "regs-gpio.h" +#include "gpio-samsung.h" #include #include @@ -38,8 +38,8 @@ #include #include -#include -#include +#include "devs.h" +#include "cpu.h" #include #include "s3c24xx.h" diff --git a/arch/arm/mach-s3c/mach-bast.c b/arch/arm/mach-s3c/mach-bast.c index f971cbf99d29..1cb2193256e1 100644 --- a/arch/arm/mach-s3c/mach-bast.c +++ b/arch/arm/mach-s3c/mach-bast.c @@ -41,13 +41,13 @@ #include #include -#include -#include +#include "regs-gpio.h" +#include "gpio-samsung.h" -#include +#include "cpu.h" #include -#include -#include +#include "devs.h" +#include "gpio-cfg.h" #include "bast.h" #include "s3c24xx.h" diff --git a/arch/arm/mach-s3c/mach-crag6410-module.c b/arch/arm/mach-s3c/mach-crag6410-module.c index 43b587e79d21..407ad493493e 100644 --- a/arch/arm/mach-s3c/mach-crag6410-module.c +++ b/arch/arm/mach-s3c/mach-crag6410-module.c @@ -27,7 +27,7 @@ #include -#include +#include "cpu.h" #include #include "crag6410.h" diff --git a/arch/arm/mach-s3c/mach-crag6410.c b/arch/arm/mach-s3c/mach-crag6410.c index 8e7f637833f2..0bfcb79cc0a6 100644 --- a/arch/arm/mach-s3c/mach-crag6410.c +++ b/arch/arm/mach-s3c/mach-crag6410.c @@ -44,22 +44,22 @@ #include #include