From 9556175183ddf19e9a7afa449c259a0a5081fa29 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 15 Feb 2010 09:26:51 -0800 Subject: omap2/3: Make get_irqnr_and_base common for mach-omap2 multiboot Make get_irqnr_and_base common for mach-omap2 multiboot Thanks to a tip from Russell King , this also optimizes the code for non-multiboot configurations by using get_irqnr_preamble. Note that this will only work currently for 24xx and 34xx. Support for 44xx can be added later on for basic multiboot, and similar patch should be done for mach-omap1/entry-macro.S. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/include/mach/entry-macro.S | 77 +++++++++++++++++++------- 1 file changed, 57 insertions(+), 20 deletions(-) (limited to 'arch/arm/mach-omap2/include/mach/entry-macro.S') diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index c7f1720bf282..4fd6b1bdcb2b 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -17,47 +17,84 @@ #include #include - -/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ -#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) -#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) -#elif defined(CONFIG_ARCH_OMAP34XX) -#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) -#endif -#if defined(CONFIG_ARCH_OMAP4) #include -#endif -#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ -#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ .macro disable_fiq .endm - .macro get_irqnr_preamble, base, tmp - .endm - .macro arch_ret_to_user, tmp1, tmp2 .endm -#ifndef CONFIG_ARCH_OMAP4 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) + +#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) +#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) +#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ +#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ + + .pushsection .data +omap_irq_base: .word 0 + .popsection + +#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_ARCH_OMAP3) + /* Configure the interrupt base on the first interrupt */ + .macro get_irqnr_preamble, base, tmp +9: + ldr \base, =omap_irq_base @ irq base address + ldr \base, [\base, #0] @ irq base value + cmp \base, #0 @ already configured? + bne 9998f @ nothing to do + + mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision + and \tmp, \tmp, #0x000f0000 @ only check architecture + cmp \tmp, #0x00060000 @ is v6? + beq 2400f @ found v6 so it's omap24xx + cmp \tmp, #0x000f0000 @ is cortex? + beq 3400f @ found v7 so it's omap34xx +2400: ldr \base, =OMAP2_IRQ_BASE + ldr \tmp, =omap_irq_base + str \base, [\tmp, #0] + b 9b +3400: ldr \base, =OMAP3_IRQ_BASE + ldr \tmp, =omap_irq_base + str \base, [\tmp, #0] + b 9b +9998: + .endm +#else + .macro get_irqnr_preamble, base, tmp +#ifdef CONFIG_ARCH_OMAP2 + ldr \base, =OMAP2_IRQ_BASE +#else + ldr \base, =OMAP3_IRQ_BASE +#endif + .endm +#endif + /* Check the pending interrupts. Note that base already set */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =OMAP2_VA_IC_BASE ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ cmp \irqnr, #0x0 - bne 2222f + bne 9999f ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ cmp \irqnr, #0x0 - bne 2222f + bne 9999f ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ cmp \irqnr, #0x0 -2222: +9999: ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ .endm -#else +#endif + + +#ifdef CONFIG_ARCH_OMAP4 + #define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) + .macro get_irqnr_preamble, base, tmp + .endm + /* * The interrupt numbering scheme is defined in the * interrupt controller spec. To wit: -- cgit v1.2.3 From 95d2b4e9cbba4c9a2ac63205e846e7ccfebe69b4 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 15 Feb 2010 09:27:24 -0800 Subject: omap2/3/4: Clean up defines for entry-macro.S Define the irq base the same way as for omap2 and omap3, and start using get_irqnr_preamble. Acked-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/include/mach/entry-macro.S | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'arch/arm/mach-omap2/include/mach/entry-macro.S') diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index 4fd6b1bdcb2b..3e63aaabebe7 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -19,6 +19,12 @@ #include #include +#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) +#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) +#define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) +#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */ +#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ + .macro disable_fiq .endm @@ -27,11 +33,6 @@ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) -#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) -#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) -#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ -#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ - .pushsection .data omap_irq_base: .word 0 .popsection @@ -90,8 +91,6 @@ omap_irq_base: .word 0 #ifdef CONFIG_ARCH_OMAP4 -#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) - .macro get_irqnr_preamble, base, tmp .endm @@ -115,7 +114,7 @@ omap_irq_base: .word 0 * valid range for an IRQ (30-1020 inclusive). */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =OMAP44XX_VA_GIC_CPU_BASE + ldr \base, =OMAP4_IRQ_BASE ldr \irqstat, [\base, #GIC_CPU_INTACK] ldr \tmp, =1021 -- cgit v1.2.3 From be8f317740f218bda59cc5ae5aefcdd7a333762a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 15 Feb 2010 09:27:25 -0800 Subject: omap4: Use get_irqnr_preamble Use get_irqnr_preamble Acked-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/include/mach/entry-macro.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/include/mach/entry-macro.S') diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index 3e63aaabebe7..101ed79deec4 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -92,6 +92,7 @@ omap_irq_base: .word 0 #ifdef CONFIG_ARCH_OMAP4 .macro get_irqnr_preamble, base, tmp + ldr \base, =OMAP4_IRQ_BASE .endm /* @@ -114,7 +115,6 @@ omap_irq_base: .word 0 * valid range for an IRQ (30-1020 inclusive). */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =OMAP4_IRQ_BASE ldr \irqstat, [\base, #GIC_CPU_INTACK] ldr \tmp, =1021 -- cgit v1.2.3 From e735aa8a20fdc60439141b7b0c0382a3ce031f3b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 15 Feb 2010 09:27:25 -0800 Subject: omap2/3/4: Clean up entry-macro.s for adding support for omap4 multiboot Move defines around and set up handlers based on MULTI_OMAP2. Note that this will only allow compiling in omap4 with omap2 and omap3. It will not yet make omap4 boot with multi-omap. Acked-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/include/mach/entry-macro.S | 38 +++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-omap2/include/mach/entry-macro.S') diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index 101ed79deec4..fe3c9ad59450 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -19,6 +19,8 @@ #include #include +#include + #define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) #define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) @@ -31,13 +33,15 @@ .macro arch_ret_to_user, tmp1, tmp2 .endm -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +/* + * Unoptimized irq functions for multi-omap2, 3 and 4 + */ +#ifdef MULTI_OMAP2 .pushsection .data omap_irq_base: .word 0 .popsection -#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_ARCH_OMAP3) /* Configure the interrupt base on the first interrupt */ .macro get_irqnr_preamble, base, tmp 9: @@ -62,7 +66,32 @@ omap_irq_base: .word 0 b 9b 9998: .endm -#else + + /* Check the pending interrupts. Note that base already set */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ + cmp \irqnr, #0x0 + bne 9999f + ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ + cmp \irqnr, #0x0 + bne 9999f + ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ + cmp \irqnr, #0x0 +9999: + ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] + and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ + + .endm + + +#else /* MULTI_OMAP2 */ + + +/* + * Optimized irq functions for omap2, 3 and 4 + */ + +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) .macro get_irqnr_preamble, base, tmp #ifdef CONFIG_ARCH_OMAP2 ldr \base, =OMAP2_IRQ_BASE @@ -70,7 +99,7 @@ omap_irq_base: .word 0 ldr \base, =OMAP3_IRQ_BASE #endif .endm -#endif + /* Check the pending interrupts. Note that base already set */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ @@ -155,6 +184,7 @@ omap_irq_base: .word 0 cmp \tmp, #0 .endm #endif +#endif /* MULTI_OMAP2 */ .macro irq_prio_table .endm -- cgit v1.2.3 From 61a07c80a7cf7333475e7eda9934dac9a8a9c8b9 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 15 Feb 2010 09:27:25 -0800 Subject: omap2/3/4: Allow booting omap4 with multi-omap configuration Allow booting omap4 with multi-omap configuration. Tested only on omap2 and omap3, please somebody test on omap4 and ack. Acked-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/include/mach/entry-macro.S | 36 +++++++++++++++++++++----- 1 file changed, 29 insertions(+), 7 deletions(-) (limited to 'arch/arm/mach-omap2/include/mach/entry-macro.S') diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index fe3c9ad59450..ff25c7e4e606 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -48,14 +48,18 @@ omap_irq_base: .word 0 ldr \base, =omap_irq_base @ irq base address ldr \base, [\base, #0] @ irq base value cmp \base, #0 @ already configured? - bne 9998f @ nothing to do + bne 9997f @ nothing to do mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision and \tmp, \tmp, #0x000f0000 @ only check architecture cmp \tmp, #0x00060000 @ is v6? beq 2400f @ found v6 so it's omap24xx - cmp \tmp, #0x000f0000 @ is cortex? - beq 3400f @ found v7 so it's omap34xx + mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision + and \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9 + cmp \tmp, #0x00000080 @ cortex A-8? + beq 3400f @ found A-8 so it's omap34xx + cmp \tmp, #0x00000090 @ cortex A-9? + beq 4400f @ found A-9 so it's omap44xx 2400: ldr \base, =OMAP2_IRQ_BASE ldr \tmp, =omap_irq_base str \base, [\tmp, #0] @@ -64,23 +68,41 @@ omap_irq_base: .word 0 ldr \tmp, =omap_irq_base str \base, [\tmp, #0] b 9b -9998: +4400: ldr \base, =OMAP4_IRQ_BASE + ldr \tmp, =omap_irq_base + str \base, [\tmp, #0] + b 9b +9997: .endm /* Check the pending interrupts. Note that base already set */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + tst \base, #0x100 @ gic address? + bne 4401f @ found gic + + /* Handle omap2 and omap3 */ ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ cmp \irqnr, #0x0 - bne 9999f + bne 9998f ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ cmp \irqnr, #0x0 - bne 9999f + bne 9998f ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ cmp \irqnr, #0x0 -9999: +9998: ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ + b 9999f + /* Handle omap4 */ +4401: ldr \irqstat, [\base, #GIC_CPU_INTACK] + ldr \tmp, =1021 + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #29 + cmpcc \irqnr, \irqnr + cmpne \irqnr, \tmp + cmpcs \irqnr, \irqnr +9999: .endm -- cgit v1.2.3