From b27f48227c59754e1c881bd8e2b327ac02fe17b6 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 14 Jun 2012 16:16:16 +0200 Subject: ARM: LPC32xx: Clock initialization for NAND controllers This patch adds clock initialization for the MLC NAND controller of the LPC32xx SoC and adjusts it for the SLC controller. Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/clock.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index f6a3ffec1f4b..bf0c3d91af9c 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -691,10 +691,21 @@ static struct clk clk_nand = { .parent = &clk_hclk, .enable = local_onoff_enable, .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN, + .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN | + LPC32XX_CLKPWR_NANDCLK_SEL_SLC, .get_rate = local_return_parent_rate, }; +static struct clk clk_nand_mlc = { + .parent = &clk_hclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN | + LPC32XX_CLKPWR_NANDCLK_DMA_INT | + LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC, + .get_rate = local_return_parent_rate, +}; + static struct clk clk_i2s0 = { .parent = &clk_hclk, .enable = local_onoff_enable, @@ -1121,7 +1132,8 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0), CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1), CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan), - CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand), + CLKDEV_INIT("20020000.flash", NULL, &clk_nand), + CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc), CLKDEV_INIT("40048000.adc", NULL, &clk_adc), CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0), CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1), -- cgit v1.2.3 From ba225a0ea225902501487a2c9f620c26dce1cee6 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 14 Jun 2012 16:16:16 +0200 Subject: ARM: LPC32xx: Remove SLC controller initialization from platform init Since we now support two MTD NAND controllers (MLC and SLC) for LPC32xx via DT, we don't initialize the SLC controller statically anymore, but do it via the clock setup (see previous patch). Signed-off-by: Roland Stigge Tested-by: Alexandre Pereira da Silva --- arch/arm/mach-lpc32xx/phy3250.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 540106cdb9ec..42a078eb1665 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -241,10 +241,6 @@ static void __init lpc3250_machine_init(void) { u32 tmp; - /* Setup SLC NAND controller muxing */ - __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC, - LPC32XX_CLKPWR_NAND_CLK_CTRL); - /* Setup LCD muxing to RGB565 */ tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) & ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK | -- cgit v1.2.3 From d807af4793a464f7331f92461a619e5e7ddf9089 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 14 Jun 2012 16:16:17 +0200 Subject: ARM: LPC32xx: Add DMA configuration to platform data This patch adds DMA channel configuration to the LPC32xx platform file. The configured DMA signalling is generic for LPC32xx SoC and is not board specific. Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/phy3250.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 42a078eb1665..eade77fbebdd 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -226,7 +226,38 @@ static int __init phy3250_spi_board_register(void) } arch_initcall(phy3250_spi_board_register); +static struct pl08x_channel_data pl08x_slave_channels[] = { + { + .bus_id = "nand-slc", + .min_signal = 1, /* SLC NAND Flash */ + .max_signal = 1, + .periph_buses = PL08X_AHB1, + }, + { + .bus_id = "nand-mlc", + .min_signal = 12, /* MLC NAND Flash */ + .max_signal = 12, + .periph_buses = PL08X_AHB1, + }, +}; + +/* NOTE: These will change, according to RMK */ +static int pl08x_get_signal(struct pl08x_dma_chan *ch) +{ + return ch->cd->min_signal; +} + +static void pl08x_put_signal(struct pl08x_dma_chan *ch) +{ +} + static struct pl08x_platform_data pl08x_pd = { + .slave_channels = &pl08x_slave_channels[0], + .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels), + .get_signal = pl08x_get_signal, + .put_signal = pl08x_put_signal, + .lli_buses = PL08X_AHB1, + .mem_buses = PL08X_AHB1, }; static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { -- cgit v1.2.3 From 821e7edd5130a1efd8754bcd7e4c30ccb1fc9c71 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 14 Jun 2012 16:16:17 +0200 Subject: ARM: LPC32xx: Clock adjustment for key matrix controller The clock.c file needs to be changed to match the automatic device name to its clock. Signed-off-by: Roland Stigge Acked-by: Rob Herring --- arch/arm/mach-lpc32xx/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index bf0c3d91af9c..963d12a9fc3d 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -1131,7 +1131,7 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2), CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0), CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1), - CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan), + CLKDEV_INIT("40050000.key", NULL, &clk_kscan), CLKDEV_INIT("20020000.flash", NULL, &clk_nand), CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc), CLKDEV_INIT("40048000.adc", NULL, &clk_adc), -- cgit v1.2.3 From 291dd71fe48c0b696a9391ed1ba476c8878d6fca Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 14 Jun 2012 16:16:17 +0200 Subject: ARM: LPC32xx: Add MMC controller support This patch adds support for the MMC controller of the LPC32xx SoC to the platform initialization via the pl08x primecell driver. Lacking more complete DT support, done via DT auxdata. Signed-off-by: Roland Stigge Acked-by: Alexandre Pereira da Silva --- arch/arm/mach-lpc32xx/phy3250.c | 43 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 39 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index eade77fbebdd..03ee3491b7cf 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -30,12 +30,13 @@ #include #include #include +#include +#include #include #include #include #include #include -#include #include #include @@ -50,9 +51,12 @@ /* * Mapped GPIOLIB GPIOs */ -#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) -#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) -#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) +#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) +#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) +#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) +#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5) +#define MMC_CD_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1) +#define MMC_WP_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0) /* * AMBA LCD controller @@ -260,11 +264,32 @@ static struct pl08x_platform_data pl08x_pd = { .mem_buses = PL08X_AHB1, }; +static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios) +{ + /* Only on and off are supported */ + if (ios->power_mode == MMC_POWER_OFF) + gpio_set_value(MMC_PWR_ENABLE_GPIO, 0); + else + gpio_set_value(MMC_PWR_ENABLE_GPIO, 1); + return 0; +} + +static struct mmci_platform_data lpc32xx_mmci_data = { + .ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 | + MMC_VDD_32_33 | MMC_VDD_33_34, + .ios_handler = mmc_handle_ios, + .dma_filter = NULL, + /* No DMA for now since AMBA PL080 dmaengine driver only does scatter + * gather, and the MMCI driver doesn't do it this way */ +}; + static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data), OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data), OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), + OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd", + &lpc32xx_mmci_data), { } }; @@ -308,6 +333,11 @@ static void __init lpc3250_machine_init(void) * detection or a data fault will occur, so enable the clocks * here. */ + tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); + tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | + LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; + __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); + tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), LPC32XX_CLKPWR_LCDCLK_CTRL); @@ -335,6 +365,11 @@ static void __init lpc3250_machine_init(void) else if (gpio_direction_output(SPI0_CS_GPIO, 1)) printk(KERN_ERR "Error setting gpio %u to output", SPI0_CS_GPIO); + + if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en")) + pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO); + else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1)) + pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO); } static char const *lpc32xx_dt_compat[] __initdata = { -- cgit v1.2.3 From c70426f1534a7d8e52e478ce67fd4634cc588741 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 14 Jun 2012 16:16:18 +0200 Subject: ARM: LPC32xx: DT conversion of Standard UARTs This patch switches from static serial driver initialization to devicetree configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled individually via DT. E.g., instead of Kconfig configuration, the phy3250.dts activates UARTs 3 and 5. Signed-off-by: Roland Stigge Tested-by: Alexandre Pereira da Silva --- arch/arm/Kconfig | 2 - arch/arm/boot/dts/lpc32xx.dtsi | 34 +++++++++++++---- arch/arm/boot/dts/phy3250.dts | 8 ++++ arch/arm/mach-lpc32xx/Kconfig | 32 ---------------- arch/arm/mach-lpc32xx/serial.c | 85 +----------------------------------------- 5 files changed, 35 insertions(+), 126 deletions(-) delete mode 100644 arch/arm/mach-lpc32xx/Kconfig (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 84449dd8f031..973d5380a431 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1019,8 +1019,6 @@ source "arch/arm/mach-kirkwood/Kconfig" source "arch/arm/mach-ks8695/Kconfig" -source "arch/arm/mach-lpc32xx/Kconfig" - source "arch/arm/mach-msm/Kconfig" source "arch/arm/mach-mv78xx0/Kconfig" diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index a9b2a6a22024..acb68171d04d 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -126,24 +126,42 @@ reg = <0x2009C000 0x1000>; }; + /* UART5 first since it is the default console, ttyS0 */ + uart5: serial@40090000 { + /* actually, ns16550a w/ 64 byte fifos! */ + compatible = "nxp,lpc3220-uart"; + reg = <0x40090000 0x1000>; + interrupts = <9 0>; + clock-frequency = <13000000>; + reg-shift = <2>; + status = "disabled"; + }; + uart3: serial@40080000 { - compatible = "nxp,serial"; + compatible = "nxp,lpc3220-uart"; reg = <0x40080000 0x1000>; + interrupts = <7 0>; + clock-frequency = <13000000>; + reg-shift = <2>; + status = "disabled"; }; uart4: serial@40088000 { - compatible = "nxp,serial"; + compatible = "nxp,lpc3220-uart"; reg = <0x40088000 0x1000>; - }; - - uart5: serial@40090000 { - compatible = "nxp,serial"; - reg = <0x40090000 0x1000>; + interrupts = <8 0>; + clock-frequency = <13000000>; + reg-shift = <2>; + status = "disabled"; }; uart6: serial@40098000 { - compatible = "nxp,serial"; + compatible = "nxp,lpc3220-uart"; reg = <0x40098000 0x1000>; + interrupts = <10 0>; + clock-frequency = <13000000>; + reg-shift = <2>; + status = "disabled"; }; i2c1: i2c@400A0000 { diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index d5432378f234..57d4961372d4 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -94,6 +94,14 @@ }; apb { + uart5: serial@40090000 { + status = "okay"; + }; + + uart3: serial@40080000 { + status = "okay"; + }; + i2c1: i2c@400A0000 { clock-frequency = <100000>; diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig deleted file mode 100644 index e0b3eee83834..000000000000 --- a/arch/arm/mach-lpc32xx/Kconfig +++ /dev/null @@ -1,32 +0,0 @@ -if ARCH_LPC32XX - -menu "Individual UART enable selections" - -config ARCH_LPC32XX_UART3_SELECT - bool "Add support for standard UART3" - help - Adds support for standard UART 3 when the 8250 serial support - is enabled. - -config ARCH_LPC32XX_UART4_SELECT - bool "Add support for standard UART4" - help - Adds support for standard UART 4 when the 8250 serial support - is enabled. - -config ARCH_LPC32XX_UART5_SELECT - bool "Add support for standard UART5" - default y - help - Adds support for standard UART 5 when the 8250 serial support - is enabled. - -config ARCH_LPC32XX_UART6_SELECT - bool "Add support for standard UART6" - help - Adds support for standard UART 6 when the 8250 serial support - is enabled. - -endmenu - -endif diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c index f2735281616a..b5a3f3423f63 100644 --- a/arch/arm/mach-lpc32xx/serial.c +++ b/arch/arm/mach-lpc32xx/serial.c @@ -31,59 +31,6 @@ #define LPC32XX_SUART_FIFO_SIZE 64 -/* Standard 8250/16550 compatible serial ports */ -static struct plat_serial8250_port serial_std_platform_data[] = { -#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT - { - .membase = io_p2v(LPC32XX_UART5_BASE), - .mapbase = LPC32XX_UART5_BASE, - .irq = IRQ_LPC32XX_UART_IIR5, - .uartclk = LPC32XX_MAIN_OSC_FREQ, - .regshift = 2, - .iotype = UPIO_MEM32, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | - UPF_SKIP_TEST, - }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT - { - .membase = io_p2v(LPC32XX_UART3_BASE), - .mapbase = LPC32XX_UART3_BASE, - .irq = IRQ_LPC32XX_UART_IIR3, - .uartclk = LPC32XX_MAIN_OSC_FREQ, - .regshift = 2, - .iotype = UPIO_MEM32, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | - UPF_SKIP_TEST, - }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT - { - .membase = io_p2v(LPC32XX_UART4_BASE), - .mapbase = LPC32XX_UART4_BASE, - .irq = IRQ_LPC32XX_UART_IIR4, - .uartclk = LPC32XX_MAIN_OSC_FREQ, - .regshift = 2, - .iotype = UPIO_MEM32, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | - UPF_SKIP_TEST, - }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT - { - .membase = io_p2v(LPC32XX_UART6_BASE), - .mapbase = LPC32XX_UART6_BASE, - .irq = IRQ_LPC32XX_UART_IIR6, - .uartclk = LPC32XX_MAIN_OSC_FREQ, - .regshift = 2, - .iotype = UPIO_MEM32, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | - UPF_SKIP_TEST, - }, -#endif - { }, -}; - struct uartinit { char *uart_ck_name; u32 ck_mode_mask; @@ -92,7 +39,6 @@ struct uartinit { }; static struct uartinit uartinit_data[] __initdata = { -#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT { .uart_ck_name = "uart5_ck", .ck_mode_mask = @@ -100,8 +46,6 @@ static struct uartinit uartinit_data[] __initdata = { .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, .mapbase = LPC32XX_UART5_BASE, }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT { .uart_ck_name = "uart3_ck", .ck_mode_mask = @@ -109,8 +53,6 @@ static struct uartinit uartinit_data[] __initdata = { .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, .mapbase = LPC32XX_UART3_BASE, }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT { .uart_ck_name = "uart4_ck", .ck_mode_mask = @@ -118,8 +60,6 @@ static struct uartinit uartinit_data[] __initdata = { .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, .mapbase = LPC32XX_UART4_BASE, }, -#endif -#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT { .uart_ck_name = "uart6_ck", .ck_mode_mask = @@ -127,19 +67,6 @@ static struct uartinit uartinit_data[] __initdata = { .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, .mapbase = LPC32XX_UART6_BASE, }, -#endif -}; - -static struct platform_device serial_std_platform_device = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = serial_std_platform_data, - }, -}; - -static struct platform_device *lpc32xx_serial_devs[] __initdata = { - &serial_std_platform_device, }; void __init lpc32xx_serial_init(void) @@ -156,15 +83,8 @@ void __init lpc32xx_serial_init(void) clk = clk_get(NULL, uartinit_data[i].uart_ck_name); if (!IS_ERR(clk)) { clk_enable(clk); - serial_std_platform_data[i].uartclk = - clk_get_rate(clk); } - /* Fall back on main osc rate if clock rate return fails */ - if (serial_std_platform_data[i].uartclk == 0) - serial_std_platform_data[i].uartclk = - LPC32XX_MAIN_OSC_FREQ; - /* Setup UART clock modes for all UARTs, disable autoclock */ clkmodes |= uartinit_data[i].ck_mode_mask; @@ -189,7 +109,7 @@ void __init lpc32xx_serial_init(void) __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { /* Force a flush of the RX FIFOs to work around a HW bug */ - puart = serial_std_platform_data[i].mapbase; + puart = uartinit_data[i].mapbase; __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); j = LPC32XX_SUART_FIFO_SIZE; @@ -202,7 +122,4 @@ void __init lpc32xx_serial_init(void) tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); - - platform_add_devices(lpc32xx_serial_devs, - ARRAY_SIZE(lpc32xx_serial_devs)); } -- cgit v1.2.3 From 1a6e29c913d25eae0e232926fd9f7ceaf5306dc2 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 14 Jun 2012 16:16:18 +0200 Subject: ARM: LPC32xx: Remove mach specific ARCH_NR_GPIOS, use default ARCH_NR_GPIOS was defined statically to include exactly all SoC specific GPIOs. Now if additional GPIOs need to be added dynamically, e.g. via DT, none are available. Removing the mach specific setting, leaving ARCH_NR_GPIOS to the default of 256 (currently in include/asm-generic/gpio.h). Signed-off-by: Roland Stigge Acked-by: Alexandre Pereira da Silva --- arch/arm/mach-lpc32xx/include/mach/gpio.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h index 2ba6ca412bef..0052e7a76179 100644 --- a/arch/arm/mach-lpc32xx/include/mach/gpio.h +++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h @@ -3,6 +3,4 @@ #include "gpio-lpc32xx.h" -#define ARCH_NR_GPIOS (LPC32XX_GPO_P3_GRP + LPC32XX_GPO_P3_MAX) - #endif /* __MACH_GPIO_H */ -- cgit v1.2.3 From 1440837440a31672973eedaf632f54c9dfc08c4d Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Tue, 12 Jun 2012 10:23:27 -0300 Subject: ARM: LPC32xx: Build arch dtbs Add ea3250.dtb and phy3250.dtb to the list of dtbs to be built Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/Makefile.boot | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot index 2cfe0ee635c5..697323b5f92d 100644 --- a/arch/arm/mach-lpc32xx/Makefile.boot +++ b/arch/arm/mach-lpc32xx/Makefile.boot @@ -2,3 +2,4 @@ params_phys-y := 0x80000100 initrd_phys-y := 0x82000000 +dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb -- cgit v1.2.3 From c05a8b145cb84e8101a57b6876f14cdb79fa12b8 Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Tue, 12 Jun 2012 11:34:28 -0300 Subject: ARM: LPC32xx: Remove spi chipselect request from board init The lpc32xx spi0 chipselect will be requested directly from the pl022 driver Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/phy3250.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 03ee3491b7cf..4ba238395be9 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -359,13 +359,6 @@ static void __init lpc3250_machine_init(void) lpc32xx_auxdata_lookup, NULL); /* Register GPIOs used on this board */ - if (gpio_request(SPI0_CS_GPIO, "spi0 cs")) - printk(KERN_ERR "Error requesting gpio %u", - SPI0_CS_GPIO); - else if (gpio_direction_output(SPI0_CS_GPIO, 1)) - printk(KERN_ERR "Error setting gpio %u to output", - SPI0_CS_GPIO); - if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en")) pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO); else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1)) -- cgit v1.2.3 From 72b78cf713176f376f369df8ccca865c5d51c42b Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Mon, 11 Jun 2012 00:25:15 -0300 Subject: ARM: LPC32xx: Remove spi chip definitions Leave chipselect and spi devices binding to the devicetree Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/phy3250.c | 56 ----------------------------------------- 1 file changed, 56 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 4ba238395be9..93408883eaca 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -162,24 +162,6 @@ static struct clcd_board lpc32xx_clcd_data = { /* * AMBA SSP (SPI) */ -static void phy3250_spi_cs_set(u32 control) -{ - gpio_set_value(SPI0_CS_GPIO, (int) control); -} - -static struct pl022_config_chip spi0_chip_info = { - .com_mode = INTERRUPT_TRANSFER, - .iface = SSP_INTERFACE_MOTOROLA_SPI, - .hierarchy = SSP_MASTER, - .slave_tx_disable = 0, - .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, - .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, - .ctrl_len = SSP_BITS_8, - .wait_state = SSP_MWIRE_WAIT_ZERO, - .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, - .cs_control = phy3250_spi_cs_set, -}; - static struct pl022_ssp_controller lpc32xx_ssp0_data = { .bus_id = 0, .num_chipselect = 1, @@ -192,44 +174,6 @@ static struct pl022_ssp_controller lpc32xx_ssp1_data = { .enable_dma = 0, }; -/* AT25 driver registration */ -static int __init phy3250_spi_board_register(void) -{ -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) - static struct spi_board_info info[] = { - { - .modalias = "spidev", - .max_speed_hz = 5000000, - .bus_num = 0, - .chip_select = 0, - .controller_data = &spi0_chip_info, - }, - }; - -#else - static struct spi_eeprom eeprom = { - .name = "at25256a", - .byte_len = 0x8000, - .page_size = 64, - .flags = EE_ADDR2, - }; - - static struct spi_board_info info[] = { - { - .modalias = "at25", - .max_speed_hz = 5000000, - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - .platform_data = &eeprom, - .controller_data = &spi0_chip_info, - }, - }; -#endif - return spi_register_board_info(info, ARRAY_SIZE(info)); -} -arch_initcall(phy3250_spi_board_register); - static struct pl08x_channel_data pl08x_slave_channels[] = { { .bus_id = "nand-slc", -- cgit v1.2.3 From 112e9adda4ddcd56895f20c4c886d2493d7907f3 Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Wed, 13 Jun 2012 19:28:23 -0300 Subject: ARM: LPC32xx: Cleanup board init, remove duplicate clock init Remove SSP0, CLCD and DMA clocks that are already migrated to the clock framework. Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/phy3250.c | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 93408883eaca..d7389598c21a 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -272,28 +272,11 @@ static void __init lpc3250_machine_init(void) lpc32xx_serial_init(); - /* - * AMBA peripheral clocks need to be enabled prior to AMBA device - * detection or a data fault will occur, so enable the clocks - * here. - */ tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); - tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); - __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), - LPC32XX_CLKPWR_LCDCLK_CTRL); - - tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL); - __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN), - LPC32XX_CLKPWR_SSP_CLK_CTRL); - - tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL); - __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN), - LPC32XX_CLKPWR_DMA_CLK_CTRL); - /* Test clock needed for UDA1380 initial init */ __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, -- cgit v1.2.3 From 5fe8f11ccb63298bcaab34994c3ca04fd6d30887 Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Wed, 13 Jun 2012 19:34:25 -0300 Subject: ARM: LPC32xx: Move uart6 irda disable to serial.c Move the irda configuration to serial.c where other special cases are handled Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/phy3250.c | 5 ----- arch/arm/mach-lpc32xx/serial.c | 5 +++++ 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index d7389598c21a..eb22fbf029ea 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -260,11 +260,6 @@ static void __init lpc3250_machine_init(void) LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE; __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); - /* Disable IrDA pulsing support on UART6 */ - tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); - tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS; - __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); - /* Enable DMA for I2S1 channel */ tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL); tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA; diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c index b5a3f3423f63..05621a29fba2 100644 --- a/arch/arm/mach-lpc32xx/serial.c +++ b/arch/arm/mach-lpc32xx/serial.c @@ -118,6 +118,11 @@ void __init lpc32xx_serial_init(void) __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); } + /* Disable IrDA pulsing support on UART6 */ + tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); + tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS; + __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); + /* Disable UART5->USB transparent mode or USB won't work */ tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; -- cgit v1.2.3 From df072717eb0050326f0f63eed98200412c395831 Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Wed, 13 Jun 2012 19:38:48 -0300 Subject: ARM: LPC32xx: Move i2s1 dma enabling to clock.c Move i2s1 dma init to be done when it's clock is enabled. Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/clock.c | 3 ++- arch/arm/mach-lpc32xx/phy3250.c | 5 ----- 2 files changed, 2 insertions(+), 6 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index 963d12a9fc3d..e8d315e6db09 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -718,7 +718,8 @@ static struct clk clk_i2s1 = { .parent = &clk_hclk, .enable = local_onoff_enable, .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN, + .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN | + LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA, .get_rate = local_return_parent_rate, }; diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index eb22fbf029ea..c1aabfcbde49 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -260,11 +260,6 @@ static void __init lpc3250_machine_init(void) LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE; __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); - /* Enable DMA for I2S1 channel */ - tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL); - tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA; - __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL); - lpc32xx_serial_init(); tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); -- cgit v1.2.3 From 5df5d01dd04ce0dde58e305dd258c7e54f079e65 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 1 Jul 2012 21:06:44 +0200 Subject: ARM: LPC32xx: Init MMC via clock This patch moves MMC/SD controller initialization from the board specific file phy3250.c to clock.c. Signed-off-by: Roland Stigge Acked-by: Alexandre Pereira da Silva --- arch/arm/mach-lpc32xx/clock.c | 6 ++++-- arch/arm/mach-lpc32xx/phy3250.c | 5 ----- 2 files changed, 4 insertions(+), 7 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index e8d315e6db09..345c28d5615b 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -812,11 +812,13 @@ static int mmc_onoff_enable(struct clk *clk, int enable) u32 tmp; tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & - ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN; + ~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN | + LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN); /* If rate is 0, disable clock */ if (enable != 0) - tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN; + tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | + LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index c1aabfcbde49..5be2cbfb4d99 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -262,11 +262,6 @@ static void __init lpc3250_machine_init(void) lpc32xx_serial_init(); - tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); - tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | - LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; - __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); - /* Test clock needed for UDA1380 initial init */ __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, -- cgit v1.2.3 From b0d9ef0e2df67685ffc74b1bafa648261ede30c0 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 1 Jul 2012 21:06:44 +0200 Subject: ARM: LPC32xx: Add further bits to MMC init This patch makes sure certain MMC bits are cleared as they should for initialization. Signed-off-by: Roland Stigge Acked-by: Alexandre Pereira da Silva --- arch/arm/mach-lpc32xx/clock.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index 345c28d5615b..eb1b12092951 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -813,7 +813,11 @@ static int mmc_onoff_enable(struct clk *clk, int enable) tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & ~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN | - LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN); + LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN | + LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS | + LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS | + LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS | + LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS); /* If rate is 0, disable clock */ if (enable != 0) -- cgit v1.2.3 From a0a30b6a69275c54542130a8391e0fda30a4553b Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 1 Jul 2012 21:06:45 +0200 Subject: ARM: LPC32xx: Remove wrong re-initialization of MMC clock register This patch fixes a bug, (wrongfully) resetting the value of LPC32XX_CLKPWR_MS_CTRL back to its initial contents (after careful setup). This was discovered only with a board/bootloader combination (EA3250) where the contents of the respective register wasn't already at the correct value on Linux boot. Signed-off-by: Roland Stigge Acked-by: Alexandre Pereira da Silva --- arch/arm/mach-lpc32xx/clock.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index eb1b12092951..b64f98537b5d 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -871,7 +871,7 @@ static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate) static int mmc_set_rate(struct clk *clk, unsigned long rate) { - u32 oldclk, tmp; + u32 tmp; unsigned long prate, div, crate = mmc_round_rate(clk, rate); prate = clk->parent->get_rate(clk->parent); @@ -879,16 +879,12 @@ static int mmc_set_rate(struct clk *clk, unsigned long rate) div = prate / crate; /* The MMC clock must be on when accessing an MMC register */ - oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); - __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN, - LPC32XX_CLKPWR_MS_CTRL); tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf); - tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div); + tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) | + LPC32XX_CLKPWR_MSCARD_SDCARD_EN; __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); - __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL); - return 0; } -- cgit v1.2.3 From a408e8f423e91a50727e7e85461cf7677d25ebf6 Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Sun, 1 Jul 2012 21:06:45 +0200 Subject: ARM: LPC32xx: Cleanup USB clock init Move most of usb clock initialization from lpc32xx_udc and ohci-nxp to clock.c. Also adds ohci clocks and otg clocks. Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/clock.c | 68 ++++++++++++++++++++++++++- arch/arm/mach-lpc32xx/include/mach/platform.h | 14 ++++++ 2 files changed, 81 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index b64f98537b5d..8a4e7cb74ae1 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -739,14 +739,77 @@ static struct clk clk_rtc = { .get_rate = local_return_parent_rate, }; +static int local_usb_enable(struct clk *clk, int enable) +{ + u32 tmp; + + if (enable) { + /* Set up I2C pull levels */ + tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); + tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE; + __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); + } + + return local_onoff_enable(clk, enable); +} + static struct clk clk_usbd = { .parent = &clk_usbpll, - .enable = local_onoff_enable, + .enable = local_usb_enable, .enable_reg = LPC32XX_CLKPWR_USB_CTRL, .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN, .get_rate = local_return_parent_rate, }; +#define OTG_ALWAYS_MASK (LPC32XX_USB_OTG_OTG_CLOCK_ON | \ + LPC32XX_USB_OTG_I2C_CLOCK_ON) + +static int local_usb_otg_enable(struct clk *clk, int enable) +{ + int to = 1000; + + if (enable) { + __raw_writel(clk->enable_mask, clk->enable_reg); + + while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) & + clk->enable_mask) != clk->enable_mask) && (to > 0)) + to--; + } else { + __raw_writel(OTG_ALWAYS_MASK, clk->enable_reg); + + while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) & + OTG_ALWAYS_MASK) != OTG_ALWAYS_MASK) && (to > 0)) + to--; + } + + if (to) + return 0; + else + return -1; +} + +static struct clk clk_usb_otg_dev = { + .parent = &clk_usbpll, + .enable = local_usb_otg_enable, + .enable_reg = LPC32XX_USB_OTG_CLK_CTRL, + .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON | + LPC32XX_USB_OTG_OTG_CLOCK_ON | + LPC32XX_USB_OTG_DEV_CLOCK_ON | + LPC32XX_USB_OTG_I2C_CLOCK_ON, + .get_rate = local_return_parent_rate, +}; + +static struct clk clk_usb_otg_host = { + .parent = &clk_usbpll, + .enable = local_usb_otg_enable, + .enable_reg = LPC32XX_USB_OTG_CLK_CTRL, + .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON | + LPC32XX_USB_OTG_OTG_CLOCK_ON | + LPC32XX_USB_OTG_HOST_CLOCK_ON | + LPC32XX_USB_OTG_I2C_CLOCK_ON, + .get_rate = local_return_parent_rate, +}; + static int tsc_onoff_enable(struct clk *clk, int enable) { u32 tmp; @@ -1145,6 +1208,9 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT("31060000.ethernet", NULL, &clk_net), CLKDEV_INIT("dev:clcd", NULL, &clk_lcd), CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd), + CLKDEV_INIT("31020000.ohci", "ck_usbd", &clk_usbd), + CLKDEV_INIT("31020000.usbd", "ck_usb_otg", &clk_usb_otg_dev), + CLKDEV_INIT("31020000.ohci", "ck_usb_otg", &clk_usb_otg_host), CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc), }; diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h index c584f5bb164f..acc4aabf1c7b 100644 --- a/arch/arm/mach-lpc32xx/include/mach/platform.h +++ b/arch/arm/mach-lpc32xx/include/mach/platform.h @@ -694,4 +694,18 @@ #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) +/* + * USB Otg Registers + */ +#define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x)) +#define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4) +#define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8) + +/* USB OTG CLK CTRL bit defines */ +#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4) +#define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3) +#define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2) +#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1) +#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0) + #endif -- cgit v1.2.3 From 382656d81be23853f1a1a49d6669a92f70f5938b Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 1 Jul 2012 21:06:45 +0200 Subject: ARM: LPC32xx: Remove USB and I2C init from phy3250.c USB and I2C initialization can be removed safely from the board specific phy3250.c, now that initialization moved to the generalized clock.c. Signed-off-by: Roland Stigge Tested-by: Alexandre Pereira da Silva --- arch/arm/mach-lpc32xx/phy3250.c | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 5be2cbfb4d99..ff3c1f4aa500 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -248,18 +248,6 @@ static void __init lpc3250_machine_init(void) tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); - /* Set up USB power */ - tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); - tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN | - LPC32XX_CLKPWR_USBCTRL_USBI2C_EN; - __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL); - - /* Set up I2C pull levels */ - tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); - tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE | - LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE; - __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); - lpc32xx_serial_init(); /* Test clock needed for UDA1380 initial init */ -- cgit v1.2.3 From dcdd1339a3cda33f216628142eea78f3d41b47fe Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Sun, 1 Jul 2012 21:06:45 +0200 Subject: ARM: LPC32xx: Remove unused gpios Remove SPI0_CS, MMC_CD and MMC_WP gpios as they moved to devicetree. Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/phy3250.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index ff3c1f4aa500..8625237ce656 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -51,12 +51,9 @@ /* * Mapped GPIOLIB GPIOs */ -#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) #define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) #define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) #define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5) -#define MMC_CD_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1) -#define MMC_WP_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0) /* * AMBA LCD controller -- cgit v1.2.3 From 8ba85f8bffdfbac98dac8630406f7d020103db70 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 12 Jul 2012 14:01:04 +0200 Subject: ARM: LPC32xx: Adjust to pl08x DMA interface changes This patch adjusts the LPC32xx platform support to the new pl08x DMA interface, fixing the compile error resulting from changed pl08x structures. Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/phy3250.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 8625237ce656..b07dcc90829d 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -186,13 +186,12 @@ static struct pl08x_channel_data pl08x_slave_channels[] = { }, }; -/* NOTE: These will change, according to RMK */ -static int pl08x_get_signal(struct pl08x_dma_chan *ch) +static int pl08x_get_signal(const struct pl08x_channel_data *cd) { - return ch->cd->min_signal; + return cd->min_signal; } -static void pl08x_put_signal(struct pl08x_dma_chan *ch) +static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch) { } -- cgit v1.2.3 From e39942f527fb02b73236d872d22c1b6b8335266c Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Fri, 20 Jul 2012 14:01:51 +0200 Subject: ARM: LPC32xx: Set system serial based on cpu unique id LPC32xx SoC has a 128 bits unique id that can be used as a system serial number, if none has been provided by atags or dt. Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/common.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index 5c96057b6d78..a48dc2dec485 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -224,7 +225,7 @@ void lpc23xx_restart(char mode, const char *cmd) ; } -static int __init lpc32xx_display_uid(void) +static int __init lpc32xx_check_uid(void) { u32 uid[4]; @@ -233,6 +234,11 @@ static int __init lpc32xx_display_uid(void) printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n", uid[3], uid[2], uid[1], uid[0]); + if (!system_serial_low && !system_serial_high) { + system_serial_low = uid[0]; + system_serial_high = uid[1]; + } + return 1; } -arch_initcall(lpc32xx_display_uid); +arch_initcall(lpc32xx_check_uid); -- cgit v1.2.3 From 1f37a3a32b86c443396293b1f9d3e23b0a0344e5 Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Fri, 20 Jul 2012 14:01:51 +0200 Subject: ARM: LPC32xx: Add PWM clock Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/clock.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/mach-lpc32xx') diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index 8a4e7cb74ae1..f48c2e961b84 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -607,6 +607,19 @@ static struct clk clk_dma = { .get_rate = local_return_parent_rate, }; +static struct clk clk_pwm = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_PWM_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN | + LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK | + LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) | + LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN | + LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK | + LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1), + .get_rate = local_return_parent_rate, +}; + static struct clk clk_uart3 = { .parent = &clk_pclk, .enable = local_onoff_enable, @@ -1188,6 +1201,7 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9), CLKDEV_INIT("pl08xdmac", NULL, &clk_dma), CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt), + CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm), CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3), CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4), CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5), -- cgit v1.2.3