From 7dcad376e85b6eff56f29ee21e10e1fe855f1ed7 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Sun, 29 Apr 2007 09:31:51 +0100 Subject: [ARM] 4341/1: iop13xx: fix i/o address translation PCI devices were being programmed with an incorrect base address value. This patch moves I/O space into a 16-bit addressable region and corrects the i/o offset. Much thanks to Martin Michlmayr for tracking this issue and testing debug patches. Cc: Martin Michlmayr Signed-off-by: Dan Williams Signed-off-by: Russell King --- arch/arm/mach-iop13xx/pci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-iop13xx') diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 89ec70ea3187..d907a2aadfe6 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -1023,7 +1023,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) << IOP13XX_ATUX_PCIXSR_FUNC_NUM; __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); - res[0].start = IOP13XX_PCIX_LOWER_IO_PA; + res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET; res[0].end = IOP13XX_PCIX_UPPER_IO_PA; res[0].name = "IQ81340 ATUX PCI I/O Space"; res[0].flags = IORESOURCE_IO; @@ -1033,7 +1033,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) res[1].name = "IQ81340 ATUX PCI Memory Space"; res[1].flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; - sys->io_offset = IOP13XX_PCIX_IO_OFFSET; + sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA; break; case IOP13XX_INIT_ATU_ATUE: /* Note: the function number field in the PCSR is ro */ @@ -1044,7 +1044,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) __raw_writel(pcsr, IOP13XX_ATUE_PCSR); - res[0].start = IOP13XX_PCIE_LOWER_IO_PA; + res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET; res[0].end = IOP13XX_PCIE_UPPER_IO_PA; res[0].name = "IQ81340 ATUE PCI I/O Space"; res[0].flags = IORESOURCE_IO; @@ -1054,7 +1054,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) res[1].name = "IQ81340 ATUE PCI Memory Space"; res[1].flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; - sys->io_offset = IOP13XX_PCIE_IO_OFFSET; + sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA; sys->map_irq = iop13xx_pcie_map_irq; break; default: -- cgit v1.2.3 From 84c981ffb371828ad6d1d220f076453b54734302 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Sun, 29 Apr 2007 09:32:51 +0100 Subject: [ARM] 4343/1: iop13xx: automatically detect the internal bus frequency Signed-off-by: Dan Williams Signed-off-by: Russell King --- arch/arm/mach-iop13xx/iq81340mc.c | 4 ++- arch/arm/mach-iop13xx/iq81340sc.c | 4 ++- include/asm-arm/arch-iop13xx/iop13xx.h | 1 + include/asm-arm/arch-iop13xx/time.h | 56 ++++++++++++++++++++++++++++++++++ 4 files changed, 63 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-iop13xx') diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c index a519d707571c..1ae08cc04b48 100644 --- a/arch/arm/mach-iop13xx/iq81340mc.c +++ b/arch/arm/mach-iop13xx/iq81340mc.c @@ -79,7 +79,9 @@ static void __init iq81340mc_init(void) static void __init iq81340mc_timer_init(void) { - iop_init_time(400000000); + unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio(); + printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq); + iop_init_time(bus_freq); } static struct sys_timer iq81340mc_timer = { diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c index 0e71fbcabe00..0f8801406f23 100644 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ b/arch/arm/mach-iop13xx/iq81340sc.c @@ -81,7 +81,9 @@ static void __init iq81340sc_init(void) static void __init iq81340sc_timer_init(void) { - iop_init_time(400000000); + unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio(); + printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq); + iop_init_time(bus_freq); } static struct sys_timer iq81340sc_timer = { diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index 2d1e23ba67c6..c8762ae8f628 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -455,4 +455,5 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) +#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180) #endif /* _IOP13XX_HW_H_ */ diff --git a/include/asm-arm/arch-iop13xx/time.h b/include/asm-arm/arch-iop13xx/time.h index 77a837a02dec..49213d9d7cad 100644 --- a/include/asm-arm/arch-iop13xx/time.h +++ b/include/asm-arm/arch-iop13xx/time.h @@ -7,9 +7,65 @@ #define IOP_TMR_PRIVILEGED 0x08 #define IOP_TMR_RATIO_1_1 0x00 +#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19) +#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19) +#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19) +#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19) +#define IOP13XX_CORE_FREQ_MASK (7 << 16) +#define IOP13XX_CORE_FREQ_600 (0 << 16) +#define IOP13XX_CORE_FREQ_667 (1 << 16) +#define IOP13XX_CORE_FREQ_800 (2 << 16) +#define IOP13XX_CORE_FREQ_933 (3 << 16) +#define IOP13XX_CORE_FREQ_1000 (4 << 16) +#define IOP13XX_CORE_FREQ_1200 (5 << 16) + void iop_init_time(unsigned long tickrate); unsigned long iop_gettimeoffset(void); +static inline unsigned long iop13xx_core_freq(void) +{ + unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ); + freq &= IOP13XX_CORE_FREQ_MASK; + switch (freq) { + case IOP13XX_CORE_FREQ_600: + return 600000000; + case IOP13XX_CORE_FREQ_667: + return 667000000; + case IOP13XX_CORE_FREQ_800: + return 800000000; + case IOP13XX_CORE_FREQ_933: + return 933000000; + case IOP13XX_CORE_FREQ_1000: + return 1000000000; + case IOP13XX_CORE_FREQ_1200: + return 1200000000; + default: + printk("%s: warning unknown frequency, defaulting to 800Mhz\n", + __FUNCTION__); + } + + return 800000000; +} + +static inline unsigned long iop13xx_xsi_bus_ratio(void) +{ + unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ); + ratio &= IOP13XX_XSI_FREQ_RATIO_MASK; + switch (ratio) { + case IOP13XX_XSI_FREQ_RATIO_2: + return 2; + case IOP13XX_XSI_FREQ_RATIO_3: + return 3; + case IOP13XX_XSI_FREQ_RATIO_4: + return 4; + default: + printk("%s: warning unknown ratio, defaulting to 2\n", + __FUNCTION__); + } + + return 2; +} + static inline void write_tmr0(u32 val) { asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); -- cgit v1.2.3 From fa543f005de175080640266ca536d45b4b0b1a61 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Sun, 29 Apr 2007 09:33:22 +0100 Subject: [ARM] 4344/1: iop13xx: do not claim both uarts by default on iop342 Signed-off-by: Dan Williams Signed-off-by: Russell King --- arch/arm/mach-iop13xx/setup.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch/arm/mach-iop13xx') diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c index 9a46bcd5f18e..bc4871553f6a 100644 --- a/arch/arm/mach-iop13xx/setup.c +++ b/arch/arm/mach-iop13xx/setup.c @@ -258,15 +258,11 @@ void __init iop13xx_platform_init(void) if (init_uart == IOP13XX_INIT_UART_DEFAULT) { switch (iop13xx_dev_id()) { - /* enable both uarts on iop341 and iop342 */ + /* enable both uarts on iop341 */ case 0x3380: case 0x3384: case 0x3388: case 0x338c: - case 0x3382: - case 0x3386: - case 0x338a: - case 0x338e: init_uart |= IOP13XX_INIT_UART_0; init_uart |= IOP13XX_INIT_UART_1; break; -- cgit v1.2.3 From d2dd8b1fed314d22c50965f78f6895117c4abfc8 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 2 May 2007 17:47:47 +0100 Subject: [ARM] 4342/2: iop13xx: add resource definitions for the tpmi units The tpmi units interface with the SAS controller on iop348. Signed-off-by: Dan Williams Signed-off-by: Russell King --- arch/arm/mach-iop13xx/Makefile | 1 + arch/arm/mach-iop13xx/iq81340mc.c | 1 + arch/arm/mach-iop13xx/iq81340sc.c | 1 + arch/arm/mach-iop13xx/tpmi.c | 234 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-iop13xx/iop13xx.h | 1 + 5 files changed, 238 insertions(+) create mode 100644 arch/arm/mach-iop13xx/tpmi.c (limited to 'arch/arm/mach-iop13xx') diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile index 4185e0586c33..da1609dc0dee 100644 --- a/arch/arm/mach-iop13xx/Makefile +++ b/arch/arm/mach-iop13xx/Makefile @@ -7,5 +7,6 @@ obj-$(CONFIG_ARCH_IOP13XX) += setup.o obj-$(CONFIG_ARCH_IOP13XX) += irq.o obj-$(CONFIG_ARCH_IOP13XX) += pci.o obj-$(CONFIG_ARCH_IOP13XX) += io.o +obj-$(CONFIG_ARCH_IOP13XX) += tpmi.o obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c index 1ae08cc04b48..268a8d84999c 100644 --- a/arch/arm/mach-iop13xx/iq81340mc.c +++ b/arch/arm/mach-iop13xx/iq81340mc.c @@ -75,6 +75,7 @@ static void __init iq81340mc_init(void) { iop13xx_platform_init(); iq81340mc_pci_init(); + iop13xx_add_tpmi_devices(); } static void __init iq81340mc_timer_init(void) diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c index 0f8801406f23..a51ffd2683e5 100644 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ b/arch/arm/mach-iop13xx/iq81340sc.c @@ -77,6 +77,7 @@ static void __init iq81340sc_init(void) { iop13xx_platform_init(); iq81340sc_pci_init(); + iop13xx_add_tpmi_devices(); } static void __init iq81340sc_timer_init(void) diff --git a/arch/arm/mach-iop13xx/tpmi.c b/arch/arm/mach-iop13xx/tpmi.c new file mode 100644 index 000000000000..d3dc278213da --- /dev/null +++ b/arch/arm/mach-iop13xx/tpmi.c @@ -0,0 +1,234 @@ +/* + * iop13xx tpmi device resources + * Copyright (c) 2005-2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place - Suite 330, Boston, MA 02111-1307 USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */ +#define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12)) +#define IOP13XX_TPMI_MEM(dev) IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13)) +#define IOP13XX_TPMI_CTRL(dev) IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10)) +#define IOP13XX_TPMI_MMR_SIZE (SZ_4K - 1) +#define IOP13XX_TPMI_MEM_SIZE (255) +#define IOP13XX_TPMI_MEM_CTRL (SZ_1K - 1) +#define IOP13XX_TPMI_RESOURCE_MMR 0 +#define IOP13XX_TPMI_RESOURCE_MEM 1 +#define IOP13XX_TPMI_RESOURCE_CTRL 2 +#define IOP13XX_TPMI_RESOURCE_IRQ 3 + +static struct resource iop13xx_tpmi_0_resources[] = { + [IOP13XX_TPMI_RESOURCE_MMR] = { + .start = IOP13XX_TPMI_MMR(4), /* tpmi0 starts at dev == 4 */ + .end = IOP13XX_TPMI_MMR(4) + IOP13XX_TPMI_MMR_SIZE, + .flags = IORESOURCE_MEM, + }, + [IOP13XX_TPMI_RESOURCE_MEM] = { + .start = IOP13XX_TPMI_MEM(0), + .end = IOP13XX_TPMI_MEM(0) + IOP13XX_TPMI_MEM_SIZE, + .flags = IORESOURCE_MEM, + }, + [IOP13XX_TPMI_RESOURCE_CTRL] = { + .start = IOP13XX_TPMI_CTRL(0), + .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL, + .flags = IORESOURCE_MEM, + }, + [IOP13XX_TPMI_RESOURCE_IRQ] = { + .start = IRQ_IOP13XX_TPMI0_OUT, + .end = IRQ_IOP13XX_TPMI0_OUT, + .flags = IORESOURCE_IRQ + } +}; + +static struct resource iop13xx_tpmi_1_resources[] = { + [IOP13XX_TPMI_RESOURCE_MMR] = { + .start = IOP13XX_TPMI_MMR(1), + .end = IOP13XX_TPMI_MMR(1) + IOP13XX_TPMI_MMR_SIZE, + .flags = IORESOURCE_MEM, + }, + [IOP13XX_TPMI_RESOURCE_MEM] = { + .start = IOP13XX_TPMI_MEM(1), + .end = IOP13XX_TPMI_MEM(1) + IOP13XX_TPMI_MEM_SIZE, + .flags = IORESOURCE_MEM, + }, + [IOP13XX_TPMI_RESOURCE_CTRL] = { + .start = IOP13XX_TPMI_CTRL(1), + .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL, + .flags = IORESOURCE_MEM, + }, + [IOP13XX_TPMI_RESOURCE_IRQ] = { + .start = IRQ_IOP13XX_TPMI1_OUT, + .end = IRQ_IOP13XX_TPMI1_OUT, + .flags = IORESOURCE_IRQ + } +}; + +static struct resource iop13xx_tpmi_2_resources[] = { + [IOP13XX_TPMI_RESOURCE_MMR] = { + .start = IOP13XX_TPMI_MMR(2), + .end = IOP13XX_TPMI_MMR(2) + IOP13XX_TPMI_MMR_SIZE, + .flags = IORESOURCE_MEM, + }, + [IOP13XX_TPMI_RESOURCE_MEM] = { + .start = IOP13XX_TPMI_MEM(2), + .end = IOP13XX_TPMI_MEM(2) + IOP13XX_TPMI_MEM_SIZE, + .flags = IORESOURCE_MEM, + }, + [IOP13XX_TPMI_RESOURCE_CTRL] = { + .start = IOP13XX_TPMI_CTRL(2), + .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL, + .flags = IORESOURCE_MEM, + }, + [IOP13XX_TPMI_RESOURCE_IRQ] = { + .start = IRQ_IOP13XX_TPMI2_OUT, + .end = IRQ_IOP13XX_TPMI2_OUT, + .flags = IORESOURCE_IRQ + } +}; + +static struct resource iop13xx_tpmi_3_resources[] = { + [IOP13XX_TPMI_RESOURCE_MMR] = { + .start = IOP13XX_TPMI_MMR(3), + .end = IOP13XX_TPMI_MMR(3) + IOP13XX_TPMI_MMR_SIZE, + .flags = IORESOURCE_MEM, + }, + [IOP13XX_TPMI_RESOURCE_MEM] = { + .start = IOP13XX_TPMI_MEM(3), + .end = IOP13XX_TPMI_MEM(3) + IOP13XX_TPMI_MEM_SIZE, + .flags = IORESOURCE_MEM, + }, + [IOP13XX_TPMI_RESOURCE_CTRL] = { + .start = IOP13XX_TPMI_CTRL(3), + .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL, + .flags = IORESOURCE_MEM, + }, + [IOP13XX_TPMI_RESOURCE_IRQ] = { + .start = IRQ_IOP13XX_TPMI3_OUT, + .end = IRQ_IOP13XX_TPMI3_OUT, + .flags = IORESOURCE_IRQ + } +}; + +u64 iop13xx_tpmi_mask = DMA_64BIT_MASK; +static struct platform_device iop13xx_tpmi_0_device = { + .name = "iop-tpmi", + .id = 0, + .num_resources = 4, + .resource = iop13xx_tpmi_0_resources, + .dev = { + .dma_mask = &iop13xx_tpmi_mask, + .coherent_dma_mask = DMA_64BIT_MASK, + }, +}; + +static struct platform_device iop13xx_tpmi_1_device = { + .name = "iop-tpmi", + .id = 1, + .num_resources = 4, + .resource = iop13xx_tpmi_1_resources, + .dev = { + .dma_mask = &iop13xx_tpmi_mask, + .coherent_dma_mask = DMA_64BIT_MASK, + }, +}; + +static struct platform_device iop13xx_tpmi_2_device = { + .name = "iop-tpmi", + .id = 2, + .num_resources = 4, + .resource = iop13xx_tpmi_2_resources, + .dev = { + .dma_mask = &iop13xx_tpmi_mask, + .coherent_dma_mask = DMA_64BIT_MASK, + }, +}; + +static struct platform_device iop13xx_tpmi_3_device = { + .name = "iop-tpmi", + .id = 3, + .num_resources = 4, + .resource = iop13xx_tpmi_3_resources, + .dev = { + .dma_mask = &iop13xx_tpmi_mask, + .coherent_dma_mask = DMA_64BIT_MASK, + }, +}; + +__init void iop13xx_add_tpmi_devices(void) +{ + unsigned short device_id; + + /* tpmi's not present on iop341 or iop342 */ + if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) + /* ATUE must be present */ + device_id = __raw_readw(IOP13XX_ATUE_DID); + else + /* ATUX must be present */ + device_id = __raw_readw(IOP13XX_ATUX_DID); + + switch (device_id) { + /* iop34[1|2] 0-tpmi */ + case 0x3380: + case 0x3384: + case 0x3388: + case 0x338c: + case 0x3382: + case 0x3386: + case 0x338a: + case 0x338e: + return; + /* iop348 1-tpmi */ + case 0x3310: + case 0x3312: + case 0x3314: + case 0x3318: + case 0x331a: + case 0x331c: + case 0x33c0: + case 0x33c2: + case 0x33c4: + case 0x33c8: + case 0x33ca: + case 0x33cc: + case 0x33b0: + case 0x33b2: + case 0x33b4: + case 0x33b8: + case 0x33ba: + case 0x33bc: + case 0x3320: + case 0x3322: + case 0x3324: + case 0x3328: + case 0x332a: + case 0x332c: + platform_device_register(&iop13xx_tpmi_0_device); + return; + default: + platform_device_register(&iop13xx_tpmi_0_device); + platform_device_register(&iop13xx_tpmi_1_device); + platform_device_register(&iop13xx_tpmi_2_device); + platform_device_register(&iop13xx_tpmi_3_device); + return; + } +} diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index c8762ae8f628..85707e9c3325 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -8,6 +8,7 @@ extern u32 iop13xx_atue_pmmr_offset; void iop13xx_init_irq(void); void iop13xx_map_io(void); void iop13xx_platform_init(void); +void iop13xx_add_tpmi_devices(void); void iop13xx_init_irq(void); /* CPUID CP6 R0 Page 0 */ -- cgit v1.2.3