From 2674dd0b1c07d8b8dfb4872fc7b41841f05cb957 Mon Sep 17 00:00:00 2001 From: Javi Merino Date: Wed, 16 Nov 2011 12:21:24 +0100 Subject: ARM: 7163/2: PL330: Only register usable channels When the manager is running non-secure, the only channels that can issue interrupts are the ones that have a 1 in their corresponding bit in Configuration Register 3. The other ones will generate an abort when trying to signal the end of the transaction so they are useless in non-secure mode. Reference: <1320244259-10496-2-git-send-email-javi.merino@arm.com> Signed-off-by: Javi Merino Acked-by: Jassi Brar Signed-off-by: Russell King --- arch/arm/common/pl330.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/arm/common') diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c index 7129cfbdacd6..f748a385693f 100644 --- a/arch/arm/common/pl330.c +++ b/arch/arm/common/pl330.c @@ -1623,6 +1623,11 @@ static inline int _alloc_event(struct pl330_thread *thrd) return -1; } +static bool _chan_ns(const struct pl330_info *pi, int i) +{ + return pi->pcfg.irq_ns & (1 << i); +} + /* Upon success, returns IdentityToken for the * allocated channel, NULL otherwise. */ @@ -1647,7 +1652,8 @@ void *pl330_request_channel(const struct pl330_info *pi) for (i = 0; i < chans; i++) { thrd = &pl330->channels[i]; - if (thrd->free) { + if ((thrd->free) && (!_manager_ns(thrd) || + _chan_ns(pi, i))) { thrd->ev = _alloc_event(thrd); if (thrd->ev >= 0) { thrd->free = false; -- cgit v1.2.3 From 1c8a7c1fbfc7ae2362d26559df26b99c806b68b5 Mon Sep 17 00:00:00 2001 From: Javi Merino Date: Wed, 16 Nov 2011 12:45:39 +0100 Subject: ARM: 7165/2: PL330: Fix typo in _prepare_ccr() scctl should be shifted by CC_SRCCTRL_SHFT and dcctl by CC_DSTCCTRL_SHFT, not the other way round. Reference: <1320244259-10496-4-git-send-email-javi.merino@arm.com> Signed-off-by: Javi Merino Acked-by: Jassi Brar Signed-off-by: Russell King --- arch/arm/common/pl330.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/common') diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c index f748a385693f..f407a6b35d3d 100644 --- a/arch/arm/common/pl330.c +++ b/arch/arm/common/pl330.c @@ -1211,8 +1211,8 @@ static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); - ccr |= (rqc->dcctl << CC_SRCCCTRL_SHFT); - ccr |= (rqc->scctl << CC_DSTCCTRL_SHFT); + ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); + ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); ccr |= (rqc->swap << CC_SWAP_SHFT); -- cgit v1.2.3 From abdd7b91dab2f8b2e32e90e4b7e809ffb462a662 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Fri, 25 Nov 2011 17:58:19 +0100 Subject: ARM: 7176/1: cpu_pm: register GIC PM notifier only once When multiple GICs exist on a platform (RealView PB1176/11MP), we must make sure the PM notifier block is only registered once, otherwise we end up corrupting the PM notifier list. The fix is to only register the notifier when initializing the first GIC, as the power management functions seem to iterate over all the registered GICs. Tested on PB11MP and PB1176. Reported-by: Will Deacon Tested-by: Will Deacon Cc: Colin Cross Signed-off-by: Marc Zyngier Signed-off-by: Russell King --- arch/arm/common/gic.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/common') diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 0e6ae470c94f..43240f315dea 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -526,7 +526,8 @@ static void __init gic_pm_init(struct gic_chip_data *gic) sizeof(u32)); BUG_ON(!gic->saved_ppi_conf); - cpu_pm_register_notifier(&gic_notifier_block); + if (gic == &gic_data[0]) + cpu_pm_register_notifier(&gic_notifier_block); } #else static void __init gic_pm_init(struct gic_chip_data *gic) -- cgit v1.2.3 From fe41db7b3aca512e19b8ef4fbd5ad55545005d25 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 25 Nov 2011 19:23:36 +0100 Subject: ARM: 7177/1: GIC: avoid skipping non-existent PPIs in irq_start calculation Commit 4294f8baa ("ARM: gic: add irq_domain support") defines irq_start as irq_start = (irq_start & ~31) + 16; On a platform with a GIC and a CPU without PPIs, this results in irq_start being off by 16. This patch fixes gic_init so that we only carve out a PPI space when PPIs exist for the GIC being initialised. Cc: Rob Herring Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/common/gic.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'arch/arm/common') diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 43240f315dea..410a546060a2 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -582,13 +582,16 @@ void __init gic_init(unsigned int gic_nr, int irq_start, * For primary GICs, skip over SGIs. * For secondary GICs, skip over PPIs, too. */ + domain->hwirq_base = 32; if (gic_nr == 0) { gic_cpu_base_addr = cpu_base; - domain->hwirq_base = 16; - if (irq_start > 0) - irq_start = (irq_start & ~31) + 16; - } else - domain->hwirq_base = 32; + + if ((irq_start & 31) > 0) { + domain->hwirq_base = 16; + if (irq_start != -1) + irq_start = (irq_start & ~31) + 16; + } + } /* * Find out how many interrupts are supported. -- cgit v1.2.3