From 4961cfd508357bf7c3d9c0198cdfc471724fb75f Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Mon, 26 Aug 2013 02:37:59 +0900 Subject: ARM: dts: Add basic dts include files for Samsung S3C64xx SoCs This patch adds basic device tree definitions for Samsung S3C64xx SoCs. Since all the SoCs in the series are very similar, the files are created hierarchically - one file for the whole series and then separate files for particular SoCs including the common one. Signed-off-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/s3c6400.dtsi | 41 ++ arch/arm/boot/dts/s3c6410.dtsi | 57 +++ arch/arm/boot/dts/s3c64xx-pinctrl.dtsi | 687 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/s3c64xx.dtsi | 199 ++++++++++ 4 files changed, 984 insertions(+) create mode 100644 arch/arm/boot/dts/s3c6400.dtsi create mode 100644 arch/arm/boot/dts/s3c6410.dtsi create mode 100644 arch/arm/boot/dts/s3c64xx-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/s3c64xx.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/s3c6400.dtsi b/arch/arm/boot/dts/s3c6400.dtsi new file mode 100644 index 000000000000..a7d1c8ec150d --- /dev/null +++ b/arch/arm/boot/dts/s3c6400.dtsi @@ -0,0 +1,41 @@ +/* + * Samsung's S3C6400 SoC device tree source + * + * Copyright (c) 2013 Tomasz Figa + * + * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "s3c64xx.dtsi" + +/ { + compatible = "samsung,s3c6400"; +}; + +&vic0 { + valid-mask = <0xfffffe1f>; + valid-wakeup-mask = <0x00200004>; +}; + +&vic1 { + valid-mask = <0xffffffff>; + valid-wakeup-mask = <0x53020000>; +}; + +&soc { + clocks: clock-controller@7e00f000 { + compatible = "samsung,s3c6400-clock"; + reg = <0x7e00f000 0x1000>; + #clock-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/s3c6410.dtsi b/arch/arm/boot/dts/s3c6410.dtsi new file mode 100644 index 000000000000..eb4226b3407c --- /dev/null +++ b/arch/arm/boot/dts/s3c6410.dtsi @@ -0,0 +1,57 @@ +/* + * Samsung's S3C6410 SoC device tree source + * + * Copyright (c) 2013 Tomasz Figa + * + * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "s3c64xx.dtsi" + +/ { + compatible = "samsung,s3c6410"; + + aliases { + i2c1 = &i2c1; + }; +}; + +&vic0 { + valid-mask = <0xffffff7f>; + valid-wakeup-mask = <0x00200004>; +}; + +&vic1 { + valid-mask = <0xffffffff>; + valid-wakeup-mask = <0x53020000>; +}; + +&soc { + clocks: clock-controller@7e00f000 { + compatible = "samsung,s3c6410-clock"; + reg = <0x7e00f000 0x1000>; + #clock-cells = <1>; + }; + + i2c1: i2c@7f00f000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x7f00f000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <5>; + clock-names = "i2c"; + clocks = <&clocks PCLK_IIC1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi new file mode 100644 index 000000000000..b1197d8b04de --- /dev/null +++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi @@ -0,0 +1,687 @@ +/* + * Samsung's S3C64xx SoC series common device tree source + * - pin control-related definitions + * + * Copyright (c) 2013 Tomasz Figa + * + * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are + * listed as device tree nodes in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define PIN_PULL_NONE 0 +#define PIN_PULL_DOWN 1 +#define PIN_PULL_UP 2 + +&pinctrl0 { + /* + * Pin banks + */ + + gpa: gpa { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc: gpc { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd: gpd { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe: gpe { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf: gpf { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg: gpg { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph: gph { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpi: gpi { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj: gpj { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk: gpk { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl: gpl { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm: gpm { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpn: gpn { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpo: gpo { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp: gpp { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpq: gpq { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* + * Pin groups + */ + + uart0_data: uart0-data { + samsung,pins = "gpa-0", "gpa-1"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa-2", "gpa-3"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa-4", "gpa-5"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa-6", "gpa-7"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + uart2_data: uart2-data { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + uart3_data: uart3-data { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + ext_dma_0: ext-dma-0 { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + ext_dma_1: ext-dma-1 { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = <4>; + samsung,pin-pud = ; + }; + + irda_data_0: irda-data-0 { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = <4>; + samsung,pin-pud = ; + }; + + irda_data_1: irda-data-1 { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + irda_sdbw: irda-sdbw { + samsung,pins = "gpb-4"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpb-5", "gpb-6"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + i2c1_bus: i2c1-bus { + /* S3C6410-only */ + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = <6>; + samsung,pin-pud = ; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpc-0", "gpc-1", "gpc-2"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + spi0_cs: spi0-cs { + samsung,pins = "gpc-3"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpc-4", "gpc-5", "gpc-6"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + spi1_cs: spi1-cs { + samsung,pins = "gpc-7"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpg-1"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpg-0"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + sd0_bus1: sd0-bus1 { + samsung,pins = "gpg-2"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + sd0_bus4: sd0-bus4 { + samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpg-6"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gph-1"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gph-0"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + sd1_bus1: sd1-bus1 { + samsung,pins = "gph-2"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + sd1_bus4: sd1-bus4 { + samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + sd1_bus8: sd1-bus8 { + samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", + "gph-6", "gph-7", "gph-8", "gph-9"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpg-6"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpc-4"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpc-5"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + sd2_bus1: sd2-bus1 { + samsung,pins = "gph-6"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + sd2_bus4: sd2-bus4 { + samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + i2s0_cdclk: i2s0-cdclk { + samsung,pins = "gpd-1"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + i2s1_cdclk: i2s1-cdclk { + samsung,pins = "gpe-1"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + i2s2_bus: i2s2-bus { + /* S3C6410-only */ + samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", + "gph-8", "gph-9"; + samsung,pin-function = <5>; + samsung,pin-pud = ; + }; + + i2s2_cdclk: i2s2-cdclk { + /* S3C6410-only */ + samsung,pins = "gph-7"; + samsung,pin-function = <5>; + samsung,pin-pud = ; + }; + + pcm0_bus: pcm0-bus { + samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + pcm0_extclk: pcm0-extclk { + samsung,pins = "gpd-1"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + pcm1_extclk: pcm1-extclk { + samsung,pins = "gpe-1"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + ac97_bus_0: ac97-bus-0 { + samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; + samsung,pin-function = <4>; + samsung,pin-pud = ; + }; + + ac97_bus_1: ac97-bus-1 { + samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; + samsung,pin-function = <4>; + samsung,pin-pud = ; + }; + + cam_port: cam-port { + samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", + "gpf-5", "gpf-6", "gpf-7", "gpf-8", + "gpf-9", "gpf-10", "gpf-11", "gpf-12"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + cam_rst: cam-rst { + samsung,pins = "gpf-3"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + cam_field: cam-field { + /* S3C6410-only */ + samsung,pins = "gpb-4"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + pwm_extclk: pwm-extclk { + samsung,pins = "gpf-13"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpf-14"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpf-15"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + clkout0: clkout-0 { + samsung,pins = "gpf-14"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_col0_0: keypad-col0-0 { + samsung,pins = "gph-0"; + samsung,pin-function = <4>; + samsung,pin-pud = ; + }; + + keypad_col1_0: keypad-col1-0 { + samsung,pins = "gph-1"; + samsung,pin-function = <4>; + samsung,pin-pud = ; + }; + + keypad_col2_0: keypad-col2-0 { + samsung,pins = "gph-2"; + samsung,pin-function = <4>; + samsung,pin-pud = ; + }; + + keypad_col3_0: keypad-col3-0 { + samsung,pins = "gph-3"; + samsung,pin-function = <4>; + samsung,pin-pud = ; + }; + + keypad_col4_0: keypad-col4-0 { + samsung,pins = "gph-4"; + samsung,pin-function = <4>; + samsung,pin-pud = ; + }; + + keypad_col5_0: keypad-col5-0 { + samsung,pins = "gph-5"; + samsung,pin-function = <4>; + samsung,pin-pud = ; + }; + + keypad_col6_0: keypad-col6-0 { + samsung,pins = "gph-6"; + samsung,pin-function = <4>; + samsung,pin-pud = ; + }; + + keypad_col7_0: keypad-col7-0 { + samsung,pins = "gph-7"; + samsung,pin-function = <4>; + samsung,pin-pud = ; + }; + + keypad_col0_1: keypad-col0-1 { + samsung,pins = "gpl-0"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_col1_1: keypad-col1-1 { + samsung,pins = "gpl-1"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_col2_1: keypad-col2-1 { + samsung,pins = "gpl-2"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_col3_1: keypad-col3-1 { + samsung,pins = "gpl-3"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_col4_1: keypad-col4-1 { + samsung,pins = "gpl-4"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_col5_1: keypad-col5-1 { + samsung,pins = "gpl-5"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_col6_1: keypad-col6-1 { + samsung,pins = "gpl-6"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_col7_1: keypad-col7-1 { + samsung,pins = "gpl-7"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row0_0: keypad-row0-0 { + samsung,pins = "gpk-8"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row1_0: keypad-row1-0 { + samsung,pins = "gpk-9"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row2_0: keypad-row2-0 { + samsung,pins = "gpk-10"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row3_0: keypad-row3-0 { + samsung,pins = "gpk-11"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row4_0: keypad-row4-0 { + samsung,pins = "gpk-12"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row5_0: keypad-row5-0 { + samsung,pins = "gpk-13"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row6_0: keypad-row6-0 { + samsung,pins = "gpk-14"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row7_0: keypad-row7-0 { + samsung,pins = "gpk-15"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row0_1: keypad-row0-1 { + samsung,pins = "gpn-0"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row1_1: keypad-row1-1 { + samsung,pins = "gpn-1"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row2_1: keypad-row2-1 { + samsung,pins = "gpn-2"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row3_1: keypad-row3-1 { + samsung,pins = "gpn-3"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row4_1: keypad-row4-1 { + samsung,pins = "gpn-4"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row5_1: keypad-row5-1 { + samsung,pins = "gpn-5"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row6_1: keypad-row6-1 { + samsung,pins = "gpn-6"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + keypad_row7_1: keypad-row7-1 { + samsung,pins = "gpn-7"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; + + lcd_ctrl: lcd-ctrl { + samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + lcd_data16: lcd-data-width16 { + samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6", + "gpi-7", "gpi-10", "gpi-11", "gpi-12", + "gpi-13", "gpi-14", "gpi-15", "gpj-3", + "gpj-4", "gpj-5", "gpj-6", "gpj-7"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + lcd_data18: lcd-data-width18 { + samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5", + "gpi-6", "gpi-7", "gpi-10", "gpi-11", + "gpi-12", "gpi-13", "gpi-14", "gpi-15", + "gpj-2", "gpj-3", "gpj-4", "gpj-5", + "gpj-6", "gpj-7"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + lcd_data24: lcd-data-width24 { + samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", + "gpi-4", "gpi-5", "gpi-6", "gpi-7", + "gpi-8", "gpi-9", "gpi-10", "gpi-11", + "gpi-12", "gpi-13", "gpi-14", "gpi-15", + "gpj-0", "gpj-1", "gpj-2", "gpj-3", + "gpj-4", "gpj-5", "gpj-6", "gpj-7"; + samsung,pin-function = <2>; + samsung,pin-pud = ; + }; + + hsi_bus: hsi-bus { + samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", + "gpk-4", "gpk-5", "gpk-6", "gpk-7"; + samsung,pin-function = <3>; + samsung,pin-pud = ; + }; +}; diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi new file mode 100644 index 000000000000..4e3be4d3493d --- /dev/null +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -0,0 +1,199 @@ +/* + * Samsung's S3C64xx SoC series common device tree source + * + * Copyright (c) 2013 Tomasz Figa + * + * Samsung's S3C64xx SoC series device nodes are listed in this file. + * Particular SoCs from S3C64xx series can include this file and provide + * values for SoCs specfic bindings. + * + * Note: This file does not include device nodes for all the controllers in + * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "skeleton.dtsi" +#include + +/ { + aliases { + i2c0 = &i2c0; + pinctrl0 = &pinctrl0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm1176jzf-s", "arm,arm1176"; + reg = <0x0>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic0: interrupt-controller@71200000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0x71200000 0x1000>; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@71300000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0x71300000 0x1000>; + #interrupt-cells = <1>; + }; + + sdhci0: sdhci@7c200000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0x7c200000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <24>; + clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; + clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, + <&clocks SCLK_MMC0>; + status = "disabled"; + }; + + sdhci1: sdhci@7c300000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0x7c300000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <25>; + clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; + clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, + <&clocks SCLK_MMC1>; + status = "disabled"; + }; + + sdhci2: sdhci@7c400000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0x7c400000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <17>; + clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; + clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>, + <&clocks SCLK_MMC2>; + status = "disabled"; + }; + + watchdog: watchdog@7e004000 { + compatible = "samsung,s3c2410-wdt"; + reg = <0x7e004000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <26>; + clock-names = "watchdog"; + clocks = <&clocks PCLK_WDT>; + status = "disabled"; + }; + + i2c0: i2c@7f004000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x7f004000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <18>; + clock-names = "i2c"; + clocks = <&clocks PCLK_IIC0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: serial@7f005000 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <5>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, + <&clocks SCLK_UART>; + status = "disabled"; + }; + + uart1: serial@7f005400 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005400 0x100>; + interrupt-parent = <&vic1>; + interrupts = <6>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, + <&clocks SCLK_UART>; + status = "disabled"; + }; + + uart2: serial@7f005800 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005800 0x100>; + interrupt-parent = <&vic1>; + interrupts = <7>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, + <&clocks SCLK_UART>; + status = "disabled"; + }; + + uart3: serial@7f005c00 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005c00 0x100>; + interrupt-parent = <&vic1>; + interrupts = <8>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, + <&clocks SCLK_UART>; + status = "disabled"; + }; + + pwm: pwm@7f006000 { + compatible = "samsung,s3c6400-pwm"; + reg = <0x7f006000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <23>, <24>, <25>, <27>, <28>; + clock-names = "timers"; + clocks = <&clocks PCLK_PWM>; + samsung,pwm-outputs = <0>, <1>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pinctrl0: pinctrl@7f008000 { + compatible = "samsung,s3c64xx-pinctrl"; + reg = <0x7f008000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <21>; + + pctrl_int_map: pinctrl-interrupt-map { + interrupt-map = <0 &vic0 0>, + <1 &vic0 1>, + <2 &vic1 0>, + <3 &vic1 1>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <1>; + }; + + wakeup-interrupt-controller { + compatible = "samsung,s3c64xx-wakeup-eint"; + interrupts = <0>, <1>, <2>, <3>; + interrupt-parent = <&pctrl_int_map>; + }; + }; + }; +}; + +#include "s3c64xx-pinctrl.dtsi" -- cgit v1.2.3 From a43736deb47d21bdb936afd5fbd92f938d10a121 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Mon, 26 Aug 2013 02:38:24 +0900 Subject: ARM: dts: Add dts file for S3C6410-based Mini6410 board This patch adds basic device tree sources for FriendlyARM Mini6410 board based on Samsung S3C6410 SoC. Signed-off-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/s3c6410-mini6410.dts | 228 +++++++++++++++++++++++++++++++++ 2 files changed, 229 insertions(+) create mode 100644 arch/arm/boot/dts/s3c6410-mini6410.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index cc0f1fb61753..e8318e68de91 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -194,6 +194,7 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ ste-ccu8540.dtb \ ste-ccu9540.dtb dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb +dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ emev2-kzm9d-reference.dtb \ r8a7740-armadillo800eva.dtb \ diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts new file mode 100644 index 000000000000..57e00f9bce99 --- /dev/null +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -0,0 +1,228 @@ +/* + * Samsung's S3C6410 based Mini6410 board device tree source + * + * Copyright (c) 2013 Tomasz Figa + * + * Device tree source file for FriendlyARM Mini6410 board which is based on + * Samsung's S3C6410 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; + +#include +#include + +#include "s3c6410.dtsi" + +/ { + model = "FriendlyARM Mini6410 board based on S3C6410"; + compatible = "friendlyarm,mini6410", "samsung,s3c6410"; + + memory { + reg = <0x50000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + fin_pll: oscillator@0 { + compatible = "fixed-clock"; + reg = <0>; + clock-frequency = <12000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + xusbxti: oscillator@1 { + compatible = "fixed-clock"; + reg = <1>; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + }; + + srom-cs1@18000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x18000000 0x8000000>; + ranges; + + ethernet@18000000 { + compatible = "davicom,dm9000"; + reg = <0x18000000 0x2 0x18000004 0x2>; + interrupt-parent = <&gpn>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + davicom,no-eeprom; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + autorepeat; + + button-k1 { + label = "K1"; + gpios = <&gpn 0 GPIO_ACTIVE_LOW>; + linux,code = <2>; + debounce-interval = <20>; + }; + + button-k2 { + label = "K2"; + gpios = <&gpn 1 GPIO_ACTIVE_LOW>; + linux,code = <3>; + debounce-interval = <20>; + }; + + button-k3 { + label = "K3"; + gpios = <&gpn 2 GPIO_ACTIVE_LOW>; + linux,code = <4>; + debounce-interval = <20>; + }; + + button-k4 { + label = "K4"; + gpios = <&gpn 3 GPIO_ACTIVE_LOW>; + linux,code = <5>; + debounce-interval = <20>; + }; + + button-k5 { + label = "K5"; + gpios = <&gpn 4 GPIO_ACTIVE_LOW>; + linux,code = <6>; + debounce-interval = <20>; + }; + + button-k6 { + label = "K6"; + gpios = <&gpn 5 GPIO_ACTIVE_LOW>; + linux,code = <7>; + debounce-interval = <20>; + }; + + button-k7 { + label = "K7"; + gpios = <&gpl 11 GPIO_ACTIVE_LOW>; + linux,code = <8>; + debounce-interval = <20>; + }; + + button-k8 { + label = "K8"; + gpios = <&gpl 12 GPIO_ACTIVE_LOW>; + linux,code = <9>; + debounce-interval = <20>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_leds>; + + led-1 { + label = "LED1"; + gpios = <&gpk 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + label = "LED2"; + gpios = <&gpk 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + }; + + led-3 { + label = "LED3"; + gpios = <&gpk 6 GPIO_ACTIVE_LOW>; + }; + + led-4 { + label = "LED4"; + gpios = <&gpk 7 GPIO_ACTIVE_LOW>; + }; + }; + + buzzer { + compatible = "pwm-beeper"; + pwms = <&pwm 0 1000000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; + }; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_data>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_data>, <&uart1_fctl>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_data>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_data>; + status = "okay"; +}; + +&pwm { + status = "okay"; +}; + +&pinctrl0 { + gpio_leds: gpio-leds { + samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; + samsung,pin-pud = ; + }; + + gpio_keys: gpio-keys { + samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", + "gpn-4", "gpn-5", "gpl-11", "gpl-12"; + samsung,pin-pud = ; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; +}; -- cgit v1.2.3 From 2ec35a4252eae3d5277af041bd1b5ae4f6183cad Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Mon, 26 Aug 2013 02:38:41 +0900 Subject: ARM: dts: Add dts file for S3C6410-based SMDK6410 board This patch adds basic device tree sources for SAMSUNG SMDK6410 board based on SAMSUNG S3C6410 SoC. Currently only UARTs, SD channel 0 and 100Mbps ethernet (SMSC911x) are supported. Signed-off-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/s3c6410-smdk6410.dts | 103 +++++++++++++++++++++++++++++++++ 2 files changed, 105 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/s3c6410-smdk6410.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8318e68de91..76330c18c3a6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -194,7 +194,8 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ ste-ccu8540.dtb \ ste-ccu9540.dtb dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb -dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb +dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ + s3c6410-smdk6410.dtb dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ emev2-kzm9d-reference.dtb \ r8a7740-armadillo800eva.dtb \ diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts new file mode 100644 index 000000000000..ecf35ec466f7 --- /dev/null +++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts @@ -0,0 +1,103 @@ +/* + * Samsung S3C6410 based SMDK6410 board device tree source. + * + * Copyright (c) 2013 Tomasz Figa + * + * Device tree source file for SAMSUNG SMDK6410 board which is based on + * Samsung's S3C6410 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; + +#include +#include + +#include "s3c6410.dtsi" + +/ { + model = "SAMSUNG SMDK6410 board based on S3C6410"; + compatible = "samsung,mini6410", "samsung,s3c6410"; + + memory { + reg = <0x50000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + fin_pll: oscillator@0 { + compatible = "fixed-clock"; + reg = <0>; + clock-frequency = <12000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + xusbxti: oscillator@1 { + compatible = "fixed-clock"; + reg = <1>; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + }; + + srom-cs1@18000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x18000000 0x8000000>; + ranges; + + ethernet@18000000 { + compatible = "smsc,lan9115"; + reg = <0x18000000 0x10000>; + interrupt-parent = <&gpn>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,force-internal-phy; + }; + }; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_data>, <&uart0_fctl>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_data>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_data>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_data>; + status = "okay"; +}; -- cgit v1.2.3 From 2bad969f782e6da1ab35ebd2897212387e797fa7 Mon Sep 17 00:00:00 2001 From: Oliver Schinagl Date: Tue, 3 Sep 2013 12:33:28 +0200 Subject: ARM: sunxi: dt: Add sunxi-sid to dts for sun4i, sun5i and sun7i This patch shall add support for the sunxi-sid driver to the device tree for A10, A10s, A13 and A20. Signed-off-by: Oliver Schinagl Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 5 +++++ arch/arm/boot/dts/sun5i-a10s.dtsi | 5 +++++ arch/arm/boot/dts/sun5i-a13.dtsi | 5 +++++ arch/arm/boot/dts/sun7i-a20.dtsi | 5 +++++ 4 files changed, 20 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index c32770a28acf..319cc6b509da 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -266,6 +266,11 @@ reg = <0x01c20c90 0x10>; }; + sid: eeprom@01c23800 { + compatible = "allwinner,sun4i-sid"; + reg = <0x01c23800 0x10>; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 3b4a0574f068..52476742a104 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -255,6 +255,11 @@ reg = <0x01c20c90 0x10>; }; + sid: eeprom@01c23800 { + compatible = "allwinner,sun4i-sid"; + reg = <0x01c23800 0x10>; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index f6091dc0936c..ce8ef2a45be0 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -222,6 +222,11 @@ reg = <0x01c20c90 0x10>; }; + sid: eeprom@01c23800 { + compatible = "allwinner,sun4i-sid"; + reg = <0x01c23800 0x10>; + }; + uart1: serial@01c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 80559cbdbc87..282c775ee11e 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -244,6 +244,11 @@ reg = <0x01c20c90 0x10>; }; + sid: eeprom@01c23800 { + compatible = "allwinner,sun7i-a20-sid"; + reg = <0x01c23800 0x200>; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- cgit v1.2.3 From 238493e34d3f6aea8531d3c0ee0583c4c929e12f Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 22 Aug 2013 16:19:29 +0200 Subject: ARM: dts: mvebu: Update with the new compatible string for mv64xxx-i2c The mv64xxx-i2c embedded in the Armada XP have a new feature to offload i2c transaction. This new version of the IP come also with some errata. This lead to the introduction to a another compatible string. This commit split the i2c information into armada-370.dtsi and armada-xp.dtsi. Most of the data remains the same and stay in the common file Armada-370-xp.dtsi. With this new feature the size of the registers are bigger for Armada XP and the new compatible string is used. Signed-off-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 2 -- arch/arm/boot/dts/armada-370.dtsi | 8 ++++++++ arch/arm/boot/dts/armada-xp.dtsi | 10 ++++++++++ 3 files changed, 18 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 1de2dae0fdae..57dbc5dbc360 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -176,7 +176,6 @@ i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; interrupts = <31>; @@ -187,7 +186,6 @@ i2c1: i2c@11100 { compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; interrupts = <32>; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index e134d7a90c9a..b8d376170959 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -218,6 +218,14 @@ }; }; + i2c0: i2c@11000 { + reg = <0x11000 0x20>; + }; + + i2c1: i2c@11100 { + reg = <0x11100 0x20>; + }; + usb@50000 { clocks = <&coreclk 0>; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index def125c0eeaa..84fcd861b6e7 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -145,6 +145,16 @@ }; }; + i2c0: i2c@11000 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; + }; + usb@50000 { clocks = <&gateclk 18>; }; -- cgit v1.2.3 From 428abbb8b89173e5ca2750cd407d1125b231caf2 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 31 Aug 2013 23:07:24 +0200 Subject: ARM: sun7i: Enable the I2C controllers The Allwinner A20 shares the same I2C controller than the one that could be found on earlier SoCs from Allwinner. There is only a few more of these controllers. Add all of them in the DTSI. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 45 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 282c775ee11e..a6829efb8ccf 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -329,6 +329,51 @@ status = "disabled"; }; + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <0 7 1>; + clocks = <&apb1_gates 0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <0 8 1>; + clocks = <&apb1_gates 1>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <0 9 1>; + clocks = <&apb1_gates 2>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@01c2b800 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b800 0x400>; + interrupts = <0 88 1>; + clocks = <&apb1_gates 3>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c4: i2c@01c2bc00 { + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2bc00 0x400>; + interrupts = <0 89 1>; + clocks = <&apb1_gates 15>; + clock-frequency = <100000>; + status = "disabled"; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, -- cgit v1.2.3 From e5496a31d99c01b156522ce9877632db7c82257b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 31 Aug 2013 23:08:49 +0200 Subject: ARM: sun7i: Add the pin muxing options for the I2C controllers The A20 boards we currently have share the same pins for the i2c controllers they share. Add them to the DTSI. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index a6829efb8ccf..e46cfedde74c 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -215,6 +215,27 @@ allwinner,pull = <0>; }; + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "i2c0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PB18", "PB19"; + allwinner,function = "i2c1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PB20", "PB21"; + allwinner,function = "i2c2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + emac_pins_a: emac0@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", -- cgit v1.2.3 From ce0106c5bbf689949c752b2a389ee82721c0e5d6 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 31 Aug 2013 23:12:58 +0200 Subject: ARM: sun7i: cubieboard2: Enable the I2C controllers The Cubieboard2 uses both the i2c0 and i2c1 controllers. Enable them in the DT. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 15e625eca312..5c51cb8a98b0 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -48,6 +48,18 @@ pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; }; leds { -- cgit v1.2.3 From d6d3f9e65406e0e3f90843b13afc823905e33a81 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 31 Aug 2013 23:14:19 +0200 Subject: ARM: sun7i: olinuxino-micro: Enable the I2C controllers The A20-olinuxino-micro uses the first three I2C controllers found on the A20. Enable them in the DT. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 9e778557fadb..ead3013f9aca 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -60,6 +60,24 @@ pinctrl-0 = <&uart7_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; }; leds { -- cgit v1.2.3 From 6be3cf7228692cfe6ff935848f4bbb9f0f4e3739 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 18 Sep 2013 18:37:22 +0530 Subject: ARM: tegra: add palmas pincontrol to Dalmore device tree Add Palmas pincontrol to Dalmore device tree and make following configuration as default: - Disable DVFS1 and DVFS2. - Set GPIO6 to gpio mode. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-dalmore.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 60230288884b..dc5cdd7fd215 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1011,6 +1011,19 @@ interrupt-parent = <&palmas>; interrupts = <8 0>; }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio6 { + pins = "gpio6"; + function = "gpio"; + }; + }; + }; }; }; -- cgit v1.2.3 From e6e646e6778783037ea42db3034ce17d2a97583f Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 18 Sep 2013 18:52:32 +0530 Subject: ARM: tegra: use dt-binding header for key code In place of hardcoding the key code in DTS file and comment the key code as side notes, use the key code macro defines in the dt-bindings/input/input.h directly. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-dalmore.dts | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index dc5cdd7fd215..871aff5e2b87 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include #include "tegra114.dtsi" / { @@ -1094,26 +1095,26 @@ home { label = "Home"; gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - linux,code = <102>; /* KEY_HOME */ + linux,code = ; }; power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ + linux,code = ; gpio-key,wakeup; }; volume_down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = <114>; /* KEY_VOLUMEDOWN */ + linux,code = ; }; volume_up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = <115>; /* KEY_VOLUMEUP */ + linux,code = ; }; }; -- cgit v1.2.3 From dbffb5a1525dc88f1c871c48574634f14845b43d Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 1 Aug 2013 09:41:21 +0200 Subject: ARM: shmobile: ape6evm-reference: add MMCIF and SDHI DT nodes This patch adds MMCIF0, SDHI0 and SDHI1 DT nodes and a fixed voltage reglator for them to the ape6evm-reference platform. Signed-off-by: Guennadi Liakhovetski Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 72 +++++++++++++++++++++++++ 1 file changed, 72 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts index f444624eb097..2b49b05ae2f4 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts @@ -10,6 +10,7 @@ /dts-v1/; /include/ "r8a73a4.dtsi" +#include / { model = "APE6EVM"; @@ -24,6 +25,34 @@ reg = <0 0x40000000 0 0x40000000>; }; + vcc_mmc0: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "MMC0 Vcc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vcc_sdhi0: regulator@1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pfc 76 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* Common 3.3V rail, used by several devices on APE6EVM */ + ape6evm_fixed_3v3: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + lbsc { compatible = "simple-bus"; #address-cells = <1>; @@ -62,4 +91,47 @@ renesas,groups = "scifa0_data"; renesas,function = "scifa0"; }; + + mmc0_pins: mmcif { + renesas,groups = "mmc0_data8", "mmc0_ctrl"; + renesas,function = "mmc0"; + }; + + sdhi0_pins: sdhi0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; + renesas,function = "sdhi0"; + }; + + sdhi1_pins: sdhi1 { + renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; + renesas,function = "sdhi1"; + }; +}; + +&mmcif0 { + vmmc-supply = <&vcc_mmc0>; + bus-width = <8>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "okay"; +}; + +&sdhi0 { + vmmc-supply = <&vcc_sdhi0>; + bus-width = <4>; + toshiba,mmc-wrprotect-disable; + pinctrl-names = "default"; + pinctrl-0 = <&sdhi0_pins>; + status = "okay"; +}; + +&sdhi1 { + vmmc-supply = <&ape6evm_fixed_3v3>; + bus-width = <4>; + broken-cd; + toshiba,mmc-wrprotect-disable; + pinctrl-names = "default"; + pinctrl-0 = <&sdhi1_pins>; + status = "okay"; }; -- cgit v1.2.3 From 44a26877080825ab55080ad4ff9293a728bf5a98 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 13 Aug 2013 08:55:02 +0800 Subject: ARM: dts: imx6sl reuses imx6q sdma firmware There is no imx6sl specific sdma firmware. Instead, imx6sl reuses imx6q sdma firmware. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c46651e4d966..9fec772a5390 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -619,7 +619,8 @@ <&clks IMX6SL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin"; + /* imx6sl reuses imx6q sdma firmware */ + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; pxp: pxp@020f0000 { -- cgit v1.2.3 From 727b8124f5c714c687d9aabbdfe7ca9593db735f Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 21 Aug 2013 11:28:23 +0400 Subject: ARM: dts: i.MX51: Separate TXD/RXD and RTS/CTS pinmux entries for UARTs RTS/CTS pins can be used for different purposes, so create separate definitions for these pins. Signed-off-by: Alexander Shiyan Acked-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 4 ++-- arch/arm/boot/dts/imx51.dtsi | 10 ++++++++++ 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 1d337d99ecd5..f13f33906dde 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -95,7 +95,7 @@ &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_1>; + pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>; fsl,uart-has-rtscts; status = "okay"; }; @@ -252,7 +252,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>; fsl,uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 54cee6517902..1db97deb64b6 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -747,6 +747,11 @@ fsl,pins = < MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + >; + }; + + pinctrl_uart1_rtscts_1: uart1rtscts-1 { + fsl,pins = < MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 >; @@ -767,6 +772,11 @@ fsl,pins = < MX51_PAD_EIM_D25__UART3_RXD 0x1c5 MX51_PAD_EIM_D26__UART3_TXD 0x1c5 + >; + }; + + pinctrl_uart3_rtscts_1: uart3rtscts-1 { + fsl,pins = < MX51_PAD_EIM_D27__UART3_RTS 0x1c5 MX51_PAD_EIM_D24__UART3_CTS 0x1c5 >; -- cgit v1.2.3 From da38ea33360f7c86fa7089a9e5c29102ee1790d6 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 21 Aug 2013 11:28:24 +0400 Subject: ARM: dts: i.MX51: Add IRAM devicetree node This patch adds the missing IRAM devicetree node for i.MX51 CPUs. Signed-off-by: Alexander Shiyan Acked-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 1db97deb64b6..fdedb86d0f4e 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -86,6 +86,11 @@ interrupt-parent = <&tzic>; ranges; + iram: iram@1ffe0000 { + compatible = "mmio-sram"; + reg = <0x1ffe0000 0x20000>; + }; + ipu: ipu@40000000 { #crtc-cells = <1>; compatible = "fsl,imx51-ipu"; -- cgit v1.2.3 From ad15f08ccc74db52b74dd46bf4541bb430dfce76 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 21 Aug 2013 11:28:25 +0400 Subject: ARM: dts: i.MX51: Add W1 devicetree node This patch adds the missing W1 (onewire) devicetree node for i.MX51 CPUs. Signed-off-by: Alexander Shiyan Acked-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index fdedb86d0f4e..f4dcff3a9969 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -379,6 +379,14 @@ clocks = <&clks 107>; }; + owire: owire@83fa4000 { + compatible = "fsl,imx51-owire", "fsl,imx21-owire"; + reg = <0x83fa4000 0x4000>; + interrupts = <88>; + clocks = <&clks 159>; + status = "disabled"; + }; + ecspi2: ecspi@83fac000 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From e9ac890a9309a75193a8f07c1de3b1d702353f28 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 21 Aug 2013 10:27:02 -0300 Subject: ARM: dts: imx6qdl-wandboard: Add usbotg support Tested via g_ether: $ modprobe g_ether using random self ethernet address using random host ethernet address usb0: HOST MAC 42:b5:26:a9:48:21 usb0: MAC 36:a6:85:9b:9e:13 using random self ethernet address using random host ethernet address g_ether gadget: Ethernet Gadget, version: Memorial Day 2008 g_ether gadget: g_ether ready $ g_ether gadget: high-speed config #1: CDC Ethernet (ECM) $ ifconfig usb0 10.0.0.2 Then on the PC host side: ~$ sudo ifconfig usb0 10.0.0.1 ~$ ping 10.0.0.2 PING 10.0.0.2 (10.0.0.2) 56(84) bytes of data. 64 bytes from 10.0.0.2: icmp_req=1 ttl=64 time=1.26 ms 64 bytes from 10.0.0.2: icmp_req=2 ttl=64 time=0.280 ms 64 bytes from 10.0.0.2: icmp_req=3 ttl=64 time=0.297 ms Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index a55113e65bcb..b46208016b8d 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -115,6 +115,14 @@ status = "okay"; }; +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_1>; + disable-over-current; + dr_mode = "peripheral"; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1_2>; -- cgit v1.2.3 From 69c02f9593b62a27ccee11293b21ad889a59cb5e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 21 Aug 2013 10:27:03 -0300 Subject: ARM: dts: imx28-evk: Allow usb peripheral mode to work Testing g_ether results in the following: [ 1.648022] using random self ethernet address [ 1.652778] using random host ethernet address [ 1.660504] usb0: HOST MAC c6:28:6a:81:dc:ff [ 1.666360] usb0: MAC 7e:81:54:16:c0:c6 [ 1.670504] using random self ethernet address [ 1.675842] using random host ethernet address [ 1.682655] g_ether gadget: Ethernet Gadget, version: Memorial Day 2008 [ 1.689332] g_ether gadget: g_ether ready [ 3.328974] irq 237: nobody cared (try booting with the "irqpoll" option) [ 3.335831] CPU: 0 PID: 1 Comm: swapper Not tainted 3.11.0-rc6-next-20130819 #1035 [ 3.343500] [] (unwind_backtrace+0x0/0xf0) from [] (show_stack+0x10/0x14) [ 3.352098] [] (show_stack+0x10/0x14) from [] (__report_bad_irq+0x20/0xc0) [ 3.360763] [] (__report_bad_irq+0x20/0xc0) from [] (note_interrupt+0x1d4/0x234) [ 3.369943] [] (note_interrupt+0x1d4/0x234) from [] (handle_irq_event_percpu+0xc4/0x268) [ 3.379815] [] (handle_irq_event_percpu+0xc4/0x268) from [] (handle_irq_event+0x3c/0x5c) [ 3.389686] [] (handle_irq_event+0x3c/0x5c) from [] (handle_level_irq+0x8c/0xe8) [ 3.398865] [] (handle_level_irq+0x8c/0xe8) from [] (generic_handle_irq+0x20/0x30) [ 3.408213] [] (generic_handle_irq+0x20/0x30) from [] (handle_IRQ+0x30/0x84) [ 3.417040] [] (handle_IRQ+0x30/0x84) from [] (__irq_svc+0x44/0x54) [ 3.425094] [] (__irq_svc+0x44/0x54) from [] (__do_softirq+0x90/0x268) [ 3.433400] [] (__do_softirq+0x90/0x268) from [] (irq_exit+0x9c/0xd8) [ 3.441619] [] (irq_exit+0x9c/0xd8) from [] (handle_IRQ+0x34/0x84) [ 3.449577] [] (handle_IRQ+0x34/0x84) from [] (__irq_svc+0x44/0x54) [ 3.457629] [] (__irq_svc+0x44/0x54) from [] (_raw_spin_unlock_irqrestore+0x34/0x44) [ 3.467164] [] (_raw_spin_unlock_irqrestore+0x34/0x44) from [] (input_register_handler+0x98/0xb4) [ 3.477835] [] (input_register_handler+0x98/0xb4) from [] (mousedev_init+0x30/0x60) [ 3.487275] [] (mousedev_init+0x30/0x60) from [] (do_one_initcall+0xe8/0x154) [ 3.496198] [] (do_one_initcall+0xe8/0x154) from [] (kernel_init_freeable+0xf0/0x1b4) [ 3.505810] [] (kernel_init_freeable+0xf0/0x1b4) from [] (kernel_init+0x8/0xe4) [ 3.514899] [] (kernel_init+0x8/0xe4) from [] (ret_from_fork+0x14/0x34) [ 3.523263] handlers: [ 3.525578] [] ci_irq [ 3.528757] Disabling IRQ #237 Provide the USB0_ID pin in the usb0 node, so that g_ether can operate correctly. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-evk.dts | 2 ++ arch/arm/boot/dts/imx28.dtsi | 10 ++++++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 15715d921d14..8cb6b6acb27e 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -242,6 +242,8 @@ ahb@80080000 { usb0: usb@80080000 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_pins_a>; vbus-supply = <®_usb0_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 7363fded95ee..c596b6da3872 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -740,6 +740,16 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + usb0_id_pins_a: usb0id@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3071 /* MX28_PAD_AUART1_RTS__USB0_ID */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; }; digctl: digctl@8001c000 { -- cgit v1.2.3 From d39a5834dca4d3331515e3d622768a8a33e408c1 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 21 Aug 2013 10:27:04 -0300 Subject: ARM: dts: imx53-qsb: Allow usb peripheral mode to work Trying to use the usb otg port on mx53qsb results in the following error: $ modprobe g_ether using random self ethernet address using random host ethernet address usb0: HOST MAC 52:0f:8a:1e:aa:09 usb0: MAC de:f3:70:d8:6c:62 using random self ethernet address using random host ethernet address g_ether gadget: Ethernet Gadget, version: Memorial Day 2008 g_ether gadget: g_ether ready (Connect the USB cable) $ ci_hdrc ci_hdrc.0: remove, state 4 usb usb1: USB disconnect, device number 1 ci_hdrc ci_hdrc.0: USB bus 1 deregistered ci_hdrc ci_hdrc.0: timeout waiting for 00000800 in 11 USB otg port goes to connector J3 (mini USB) and also to the USB combo (J2). As mx53qsb does not provide a USB ID pin, pass the dr_mode as 'peripheral' so that we can have usb device working. Tested via g_ether. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-qsb.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index e97ddae09d74..94597c3c2eb6 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -318,5 +318,6 @@ }; &usbotg { - status = "okay"; + dr_mode = "peripheral"; + status = "okay"; }; -- cgit v1.2.3 From 2422d437db921ffe37263ed71686d06ab5ece532 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 27 Aug 2013 23:33:36 -0300 Subject: ARM: dts: imx6q-sabrelite: Put the nodes in alphabetical order Put the nodes in alphabetical order so that further node additions can be better organized. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabrelite.dts | 78 +++++++++++++++++------------------ 1 file changed, 39 insertions(+), 39 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 3530280f5150..b96a72ee5297 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -65,8 +65,10 @@ }; }; -&sata { +&audmux { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_1>; }; &ecspi1 { @@ -83,11 +85,29 @@ }; }; -&ssi1 { - fsl,mode = "i2s-slave"; +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 0>; status = "okay"; }; +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -108,23 +128,30 @@ }; }; -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_1>; - disable-over-current; +&sata { + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart2 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; }; &usbh1 { status = "okay"; }; -&fec { +&usbotg { + vbus-supply = <®_usb_otg_vbus>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_1>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 0>; + pinctrl-0 = <&pinctrl_usbotg_1>; + disable-over-current; status = "okay"; }; @@ -145,30 +172,3 @@ vmmc-supply = <®_3p3v>; status = "okay"; }; - -&audmux { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_1>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_1>; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_1>; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks 201>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; -- cgit v1.2.3 From a09644b1236137c4a8679c542a2ec69da4deb1a5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 27 Aug 2013 23:33:37 -0300 Subject: ARM: dts: imx6q-sabrelite: Add LVDS support imx6q-sabrelite board can be connected to a 1024x768 Hannstar LVDS panel. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabrelite.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index b96a72ee5297..e1c1777a80d5 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -128,6 +128,31 @@ }; }; +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + &sata { status = "okay"; }; -- cgit v1.2.3 From d7a9d8e2ab0e35a96b8f13785c5fb05654d91dde Mon Sep 17 00:00:00 2001 From: Chao Fu Date: Fri, 30 Aug 2013 11:19:48 +0800 Subject: ARM: dts: vf610: Add DSPI nodes Add Freescale DSPI node into vf610 dts. Signed-off-by: Chao Fu Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index 67d929cf9804..d31ce1b4a7b0 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -123,6 +123,18 @@ status = "disabled"; }; + dspi0: dspi0@4002c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x4002c000 0x1000>; + interrupts = <0 67 0x04>; + clocks = <&clks VF610_CLK_DSPI0>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + status = "disabled"; + }; + sai2: sai@40031000 { compatible = "fsl,vf610-sai"; reg = <0x40031000 0x1000>; -- cgit v1.2.3 From dc03a50f940db68250a3eadc6fc98bfe5a7d850a Mon Sep 17 00:00:00 2001 From: Chao Fu Date: Fri, 30 Aug 2013 11:19:49 +0800 Subject: ARM: dts: vf610-twr: Enable DSPI0 devices and Flash at26df081a This patch enables DSPI0 and at26df081a flash device for Vybrid VF610 TOWER board. Signed-off-by: Chao Fu Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-twr.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index 1a58678b93fa..c8047ca16501 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -36,6 +36,23 @@ }; +&dspi0 { + bus-num = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi0_1>; + status = "okay"; + + sflash: at26df081a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at26df081a"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + &fec0 { phy-mode = "rmii"; pinctrl-names = "default"; -- cgit v1.2.3 From c9d96df207a2caadfb521c7b6108ef9172f5bf55 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 2 Sep 2013 23:51:41 -0300 Subject: ARM: imx6qdl-wandboard: Add spdif support Signed-off-by: Fabio Estevam Reviewed-by: Nicolin Chen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 13 +++++++++++++ arch/arm/boot/dts/imx6qdl.dtsi | 21 +++++++++++++++++++++ 2 files changed, 34 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index b46208016b8d..df42d3ccb70e 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -43,6 +43,13 @@ mux-int-port = <1>; mux-ext-port = <3>; }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; }; &audmux { @@ -93,6 +100,12 @@ status = "okay"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_3>; + status = "okay"; +}; + &ssi1 { fsl,mode = "i2s-slave"; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index ccd55c2fdb67..2a3abf822378 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -136,8 +136,23 @@ ranges; spdif: spdif@02004000 { + compatible = "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; interrupts = <0 52 0x04>; + dmas = <&sdma 14 18 0>, + <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks 197>, <&clks 3>, + <&clks 197>, <&clks 107>, + <&clks 0>, <&clks 118>, + <&clks 62>, <&clks 139>, + <&clks 0>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7"; + status = "disabled"; }; ecspi1: ecspi@02008000 { @@ -1010,6 +1025,12 @@ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 >; }; + + pinctrl_spdif_3: spdifgrp-3 { + fsl,pins = < + MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 + >; + }; }; uart1 { -- cgit v1.2.3 From e03d10f98956c56d0ef92cb9e9f6cafcdd19bee2 Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Tue, 3 Sep 2013 12:26:22 +0800 Subject: ARM: dts: add iomuxc-gpr device node for imx6sl Add iomuxc gpr device node for imx6sl. Signed-off-by: Fugang Duan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 9fec772a5390..eda00e88f22f 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -528,6 +528,11 @@ interrupts = <0 89 0x04>; }; + gpr: iomuxc-gpr@020e0000 { + compatible = "fsl,imx6sl-iomuxc-gpr", "syscon"; + reg = <0x020e0000 0x38>; + }; + iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6sl-iomuxc"; reg = <0x020e0000 0x4000>; -- cgit v1.2.3 From 6022232b5405d9a917459e1590f0732517f83d09 Mon Sep 17 00:00:00 2001 From: Peter Chen Date: Tue, 10 Sep 2013 10:23:16 +0800 Subject: ARM: imx: mx6sl-evk: Enable USB function Enable USB function for OTG 1 and OTG 2 at mx6sololite evk. Besides, fix the wrong interrupt number for OTG2 and host 1. Signed-off-by: Peter Chen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-evk.dts | 39 +++++++++++++++++++++++++ arch/arm/boot/dts/imx6sl.dtsi | 62 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 99 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 2886a590823d..36ea01e308d3 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -17,6 +17,28 @@ memory { reg = <0x80000000 0x40000000>; }; + + regulators { + compatible = "simple-bus"; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 0>; + enable-active-high; + }; + + reg_usb_otg2_vbus: usb_otg2_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 0>; + enable-active-high; + }; + }; }; &fec { @@ -38,6 +60,8 @@ MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 + MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 >; }; }; @@ -49,6 +73,21 @@ status = "okay"; }; +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_1>; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1_1>; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index eda00e88f22f..bcdbc6cb50e9 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -562,6 +562,64 @@ }; }; + usbotg1 { + pinctrl_usbotg1_1: usbotg1grp-1 { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_2: usbotg1grp-2 { + fsl,pins = < + MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_3: usbotg1grp-3 { + fsl,pins = < + MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_4: usbotg1grp-4 { + fsl,pins = < + MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_5: usbotg1grp-5 { + fsl,pins = < + MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059 + >; + }; + }; + + usbotg2 { + pinctrl_usbotg2_1: usbotg2grp-1 { + fsl,pins = < + MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059 + >; + }; + + pinctrl_usbotg2_2: usbotg2grp-2 { + fsl,pins = < + MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059 + >; + }; + + pinctrl_usbotg2_3: usbotg2grp-3 { + fsl,pins = < + MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059 + >; + }; + + pinctrl_usbotg2_4: usbotg2grp-4 { + fsl,pins = < + MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059 + >; + }; + }; + usdhc1 { pinctrl_usdhc1_1: usdhc1grp-1 { fsl,pins = < @@ -669,7 +727,7 @@ usbotg2: usb@02184200 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; - interrupts = <0 40 0x04>; + interrupts = <0 42 0x04>; clocks = <&clks IMX6SL_CLK_USBOH3>; fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; @@ -679,7 +737,7 @@ usbh: usb@02184400 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; - interrupts = <0 42 0x04>; + interrupts = <0 40 0x04>; clocks = <&clks IMX6SL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 2>; status = "disabled"; -- cgit v1.2.3 From 640a7f3f0fd54dd12bd20c43e32da0ff3993bf05 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 13 Sep 2013 18:13:00 -0300 Subject: ARM: dts: imx6sl: Add spi aliases Add spi aliases. While at it, keep the aliases entries sorted. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index bcdbc6cb50e9..f295290d29fc 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -13,16 +13,20 @@ / { aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; }; cpus { -- cgit v1.2.3 From 93e2ca0285da7eb9fe800663bbaa23cc74e0372b Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Fri, 13 Sep 2013 19:11:38 +0800 Subject: ARM: dts: imx6qdl: add uhs pinctrl state for usdhc3 This is needed for supporting ultra high speed cards like SD3.0 cards. Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 5 ++++- arch/arm/boot/dts/imx6qdl.dtsi | 30 ++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 1cbbc5160d27..ff6f1e8f2dd9 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -54,6 +54,7 @@ fsl,pins = < MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 + MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 >; }; }; @@ -74,8 +75,10 @@ }; &usdhc3 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; cd-gpios = <&gpio6 15 0>; wp-gpios = <&gpio1 13 0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 2a3abf822378..ef51342be314 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1205,6 +1205,36 @@ >; }; + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */ + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */ + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 + >; + }; + pinctrl_usdhc3_2: usdhc3grp-2 { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 -- cgit v1.2.3 From e367817a0ae7065a60815933df0980e53b14c517 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 17 Sep 2013 13:46:23 -0300 Subject: ARM: dts: imx6qdl-sabresd: SDHC ports are 8 bit-wide On imx6qdl-sabresd the SDHC2 and SDHC3 are 8 bit-wide, so pass the bus-width property to reflect that. Otherwise the mmc driver will operate with the default bus-width value of 4. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 39eafc222a2e..64e454bcc4a3 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -229,6 +229,7 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2_1>; + bus-width = <8>; cd-gpios = <&gpio2 2 0>; wp-gpios = <&gpio2 3 0>; status = "okay"; @@ -237,6 +238,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3_1>; + bus-width = <8>; cd-gpios = <&gpio2 0 0>; wp-gpios = <&gpio2 1 0>; status = "okay"; -- cgit v1.2.3 From 289604df397e0d5dbe71673f8a15bfc5c8c0079f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 17 Sep 2013 16:18:38 -0300 Subject: ARM: dts: imx28-evk: Enable touchscreen support Provide 'lradc-touchscreen-wires' property to the LRADC driver, so that touchscreen can be functional. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-evk.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 8cb6b6acb27e..5f9c0a0dcc5a 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -182,6 +182,7 @@ }; lradc@80050000 { + fsl,lradc-touchscreen-wires = <4>; status = "okay"; }; -- cgit v1.2.3 From ff04b40152d04260f04664cecae4194f4c6d399d Mon Sep 17 00:00:00 2001 From: Lothar Waßmann Date: Thu, 19 Sep 2013 08:59:47 +0200 Subject: ARM: dts: mxs: add pinctrl header files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the list of possible pin configurations from the documentation file and create header files containing those definitions. This eliminates the need for error-prone manual lookup of those values in the documentation and guarantees consistency between the human readable representation of the pad function in the .dts file and the actual binary value used in DT. Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo --- .../bindings/pinctrl/fsl,mxs-pinctrl.txt | 859 +-------------------- arch/arm/boot/dts/imx23-pinfunc.h | 333 ++++++++ arch/arm/boot/dts/imx28-pinfunc.h | 506 ++++++++++++ arch/arm/boot/dts/mxs-pinfunc.h | 31 + 4 files changed, 902 insertions(+), 827 deletions(-) create mode 100644 arch/arm/boot/dts/imx23-pinfunc.h create mode 100644 arch/arm/boot/dts/imx28-pinfunc.h create mode 100644 arch/arm/boot/dts/mxs-pinfunc.h (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt index 3077370c89af..1e70a8aff260 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt @@ -59,16 +59,16 @@ Required subnode-properties: Optional subnode-properties: - fsl,drive-strength: Integer. - 0: 4 mA - 1: 8 mA - 2: 12 mA - 3: 16 mA + 0: MXS_DRIVE_4mA + 1: MXS_DRIVE_8mA + 2: MXS_DRIVE_12mA + 3: MXS_DRIVE_16mA - fsl,voltage: Integer. - 0: 1.8 V - 1: 3.3 V + 0: MXS_VOLTAGE_LOW - 1.8 V + 1: MXS_VOLTAGE_HIGH - 3.3 V - fsl,pull-up: Integer. - 0: Disable the internal pull-up - 1: Enable the internal pull-up + 0: MXS_PULL_DISABLE - Disable the internal pull-up + 1: MXS_PULL_ENABLE - Enable the internal pull-up Note that when enabling the pull-up, the internal pad keeper gets disabled. Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up @@ -85,23 +85,32 @@ pinctrl@80018000 { mmc0_8bit_pins_a: mmc0-8bit@0 { reg = <0>; fsl,pinmux-ids = < - 0x2000 0x2010 0x2020 0x2030 - 0x2040 0x2050 0x2060 0x2070 - 0x2080 0x2090 0x20a0>; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + MX28_PAD_SSP0_DATA0__SSP0_D0 + MX28_PAD_SSP0_DATA1__SSP0_D1 + MX28_PAD_SSP0_DATA2__SSP0_D2 + MX28_PAD_SSP0_DATA3__SSP0_D3 + MX28_PAD_SSP0_DATA4__SSP0_D4 + MX28_PAD_SSP0_DATA5__SSP0_D5 + MX28_PAD_SSP0_DATA6__SSP0_D6 + MX28_PAD_SSP0_DATA7__SSP0_D7 + MX28_PAD_SSP0_CMD__SSP0_CMD + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT + MX28_PAD_SSP0_SCK__SSP0_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; mmc_cd_cfg: mmc-cd-cfg { - fsl,pinmux-ids = <0x2090>; - fsl,pull-up = <0>; + fsl,pinmux-ids = ; + fsl,pull-up = ; }; mmc_sck_cfg: mmc-sck-cfg { - fsl,pinmux-ids = <0x20a0>; - fsl,drive-strength = <2>; - fsl,pull-up = <0>; + fsl,pinmux-ids = ; + fsl,drive-strength = ; + fsl,pull-up = ; }; }; @@ -112,811 +121,7 @@ adjusting the configuration for pins card-detection and clock from what group node mmc0-8bit defines. Only the configuration properties to be adjusted need to be listed in the config nodes. -Valid values for i.MX28 pinmux-id: - -pinmux id ------- -- -MX28_PAD_GPMI_D00__GPMI_D0 0x0000 -MX28_PAD_GPMI_D01__GPMI_D1 0x0010 -MX28_PAD_GPMI_D02__GPMI_D2 0x0020 -MX28_PAD_GPMI_D03__GPMI_D3 0x0030 -MX28_PAD_GPMI_D04__GPMI_D4 0x0040 -MX28_PAD_GPMI_D05__GPMI_D5 0x0050 -MX28_PAD_GPMI_D06__GPMI_D6 0x0060 -MX28_PAD_GPMI_D07__GPMI_D7 0x0070 -MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 -MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 -MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 -MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 -MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 -MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 -MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 -MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 -MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 -MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 -MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 -MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 -MX28_PAD_LCD_D00__LCD_D0 0x1000 -MX28_PAD_LCD_D01__LCD_D1 0x1010 -MX28_PAD_LCD_D02__LCD_D2 0x1020 -MX28_PAD_LCD_D03__LCD_D3 0x1030 -MX28_PAD_LCD_D04__LCD_D4 0x1040 -MX28_PAD_LCD_D05__LCD_D5 0x1050 -MX28_PAD_LCD_D06__LCD_D6 0x1060 -MX28_PAD_LCD_D07__LCD_D7 0x1070 -MX28_PAD_LCD_D08__LCD_D8 0x1080 -MX28_PAD_LCD_D09__LCD_D9 0x1090 -MX28_PAD_LCD_D10__LCD_D10 0x10a0 -MX28_PAD_LCD_D11__LCD_D11 0x10b0 -MX28_PAD_LCD_D12__LCD_D12 0x10c0 -MX28_PAD_LCD_D13__LCD_D13 0x10d0 -MX28_PAD_LCD_D14__LCD_D14 0x10e0 -MX28_PAD_LCD_D15__LCD_D15 0x10f0 -MX28_PAD_LCD_D16__LCD_D16 0x1100 -MX28_PAD_LCD_D17__LCD_D17 0x1110 -MX28_PAD_LCD_D18__LCD_D18 0x1120 -MX28_PAD_LCD_D19__LCD_D19 0x1130 -MX28_PAD_LCD_D20__LCD_D20 0x1140 -MX28_PAD_LCD_D21__LCD_D21 0x1150 -MX28_PAD_LCD_D22__LCD_D22 0x1160 -MX28_PAD_LCD_D23__LCD_D23 0x1170 -MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 -MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 -MX28_PAD_LCD_RS__LCD_RS 0x11a0 -MX28_PAD_LCD_CS__LCD_CS 0x11b0 -MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 -MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 -MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 -MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 -MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 -MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 -MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 -MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 -MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 -MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 -MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 -MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 -MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 -MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 -MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 -MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 -MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 -MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 -MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 -MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 -MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 -MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 -MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 -MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 -MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 -MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 -MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 -MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 -MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 -MX28_PAD_AUART0_RX__AUART0_RX 0x3000 -MX28_PAD_AUART0_TX__AUART0_TX 0x3010 -MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 -MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 -MX28_PAD_AUART1_RX__AUART1_RX 0x3040 -MX28_PAD_AUART1_TX__AUART1_TX 0x3050 -MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 -MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 -MX28_PAD_AUART2_RX__AUART2_RX 0x3080 -MX28_PAD_AUART2_TX__AUART2_TX 0x3090 -MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 -MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 -MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 -MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 -MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 -MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 -MX28_PAD_PWM0__PWM_0 0x3100 -MX28_PAD_PWM1__PWM_1 0x3110 -MX28_PAD_PWM2__PWM_2 0x3120 -MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 -MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 -MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 -MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 -MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 -MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 -MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 -MX28_PAD_SPDIF__SPDIF_TX 0x31b0 -MX28_PAD_PWM3__PWM_3 0x31c0 -MX28_PAD_PWM4__PWM_4 0x31d0 -MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 -MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 -MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 -MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 -MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 -MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 -MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 -MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 -MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 -MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 -MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 -MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 -MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 -MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 -MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 -MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 -MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 -MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 -MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 -MX28_PAD_EMI_D00__EMI_DATA0 0x5000 -MX28_PAD_EMI_D01__EMI_DATA1 0x5010 -MX28_PAD_EMI_D02__EMI_DATA2 0x5020 -MX28_PAD_EMI_D03__EMI_DATA3 0x5030 -MX28_PAD_EMI_D04__EMI_DATA4 0x5040 -MX28_PAD_EMI_D05__EMI_DATA5 0x5050 -MX28_PAD_EMI_D06__EMI_DATA6 0x5060 -MX28_PAD_EMI_D07__EMI_DATA7 0x5070 -MX28_PAD_EMI_D08__EMI_DATA8 0x5080 -MX28_PAD_EMI_D09__EMI_DATA9 0x5090 -MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 -MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 -MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 -MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 -MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 -MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 -MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 -MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 -MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 -MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 -MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 -MX28_PAD_EMI_CLK__EMI_CLK 0x5150 -MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 -MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 -MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 -MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 -MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 -MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 -MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 -MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 -MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 -MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 -MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 -MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 -MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 -MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 -MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 -MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 -MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 -MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 -MX28_PAD_EMI_BA0__EMI_BA0 0x6100 -MX28_PAD_EMI_BA1__EMI_BA1 0x6110 -MX28_PAD_EMI_BA2__EMI_BA2 0x6120 -MX28_PAD_EMI_CASN__EMI_CASN 0x6130 -MX28_PAD_EMI_RASN__EMI_RASN 0x6140 -MX28_PAD_EMI_WEN__EMI_WEN 0x6150 -MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 -MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 -MX28_PAD_EMI_CKE__EMI_CKE 0x6180 -MX28_PAD_GPMI_D00__SSP1_D0 0x0001 -MX28_PAD_GPMI_D01__SSP1_D1 0x0011 -MX28_PAD_GPMI_D02__SSP1_D2 0x0021 -MX28_PAD_GPMI_D03__SSP1_D3 0x0031 -MX28_PAD_GPMI_D04__SSP1_D4 0x0041 -MX28_PAD_GPMI_D05__SSP1_D5 0x0051 -MX28_PAD_GPMI_D06__SSP1_D6 0x0061 -MX28_PAD_GPMI_D07__SSP1_D7 0x0071 -MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 -MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 -MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 -MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 -MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 -MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 -MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 -MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 -MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 -MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 -MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 -MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 -MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 -MX28_PAD_LCD_D03__ETM_DA8 0x1031 -MX28_PAD_LCD_D04__ETM_DA9 0x1041 -MX28_PAD_LCD_D08__ETM_DA3 0x1081 -MX28_PAD_LCD_D09__ETM_DA4 0x1091 -MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 -MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 -MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 -MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 -MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 -MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 -MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 -MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 -MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 -MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 -MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 -MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 -MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 -MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 -MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 -MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 -MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 -MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 -MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 -MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 -MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 -MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 -MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 -MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 -MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 -MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 -MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 -MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 -MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 -MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 -MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 -MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 -MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 -MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 -MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 -MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 -MX28_PAD_AUART1_RTS__USB0_ID 0x3071 -MX28_PAD_AUART2_RX__SSP3_D1 0x3081 -MX28_PAD_AUART2_TX__SSP3_D2 0x3091 -MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 -MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 -MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 -MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 -MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 -MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 -MX28_PAD_PWM0__I2C1_SCL 0x3101 -MX28_PAD_PWM1__I2C1_SDA 0x3111 -MX28_PAD_PWM2__USB0_ID 0x3121 -MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 -MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 -MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 -MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 -MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 -MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 -MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 -MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 -MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 -MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 -MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 -MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 -MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 -MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 -MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 -MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 -MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 -MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 -MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 -MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 -MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 -MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 -MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 -MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 -MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 -MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 -MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 -MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 -MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 -MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 -MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 -MX28_PAD_LCD_D00__ETM_DA0 0x1002 -MX28_PAD_LCD_D01__ETM_DA1 0x1012 -MX28_PAD_LCD_D02__ETM_DA2 0x1022 -MX28_PAD_LCD_D03__ETM_DA3 0x1032 -MX28_PAD_LCD_D04__ETM_DA4 0x1042 -MX28_PAD_LCD_D05__ETM_DA5 0x1052 -MX28_PAD_LCD_D06__ETM_DA6 0x1062 -MX28_PAD_LCD_D07__ETM_DA7 0x1072 -MX28_PAD_LCD_D08__ETM_DA8 0x1082 -MX28_PAD_LCD_D09__ETM_DA9 0x1092 -MX28_PAD_LCD_D10__ETM_DA10 0x10a2 -MX28_PAD_LCD_D11__ETM_DA11 0x10b2 -MX28_PAD_LCD_D12__ETM_DA12 0x10c2 -MX28_PAD_LCD_D13__ETM_DA13 0x10d2 -MX28_PAD_LCD_D14__ETM_DA14 0x10e2 -MX28_PAD_LCD_D15__ETM_DA15 0x10f2 -MX28_PAD_LCD_D16__ETM_DA7 0x1102 -MX28_PAD_LCD_D17__ETM_DA6 0x1112 -MX28_PAD_LCD_D18__ETM_DA5 0x1122 -MX28_PAD_LCD_D19__ETM_DA4 0x1132 -MX28_PAD_LCD_D20__ETM_DA3 0x1142 -MX28_PAD_LCD_D21__ETM_DA2 0x1152 -MX28_PAD_LCD_D22__ETM_DA1 0x1162 -MX28_PAD_LCD_D23__ETM_DA0 0x1172 -MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 -MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 -MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 -MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 -MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 -MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 -MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 -MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 -MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 -MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 -MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 -MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 -MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 -MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 -MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 -MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 -MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 -MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 -MX28_PAD_AUART0_RX__DUART_CTS 0x3002 -MX28_PAD_AUART0_TX__DUART_RTS 0x3012 -MX28_PAD_AUART0_CTS__DUART_RX 0x3022 -MX28_PAD_AUART0_RTS__DUART_TX 0x3032 -MX28_PAD_AUART1_RX__PWM_0 0x3042 -MX28_PAD_AUART1_TX__PWM_1 0x3052 -MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 -MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 -MX28_PAD_AUART2_RX__SSP3_D4 0x3082 -MX28_PAD_AUART2_TX__SSP3_D5 0x3092 -MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 -MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 -MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 -MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 -MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 -MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 -MX28_PAD_PWM0__DUART_RX 0x3102 -MX28_PAD_PWM1__DUART_TX 0x3112 -MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 -MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 -MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 -MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 -MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 -MX28_PAD_I2C0_SCL__DUART_RX 0x3182 -MX28_PAD_I2C0_SDA__DUART_TX 0x3192 -MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 -MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 -MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 -MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 -MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 -MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 -MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 -MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 -MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 -MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 -MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 -MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 -MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 -MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 -MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 -MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 -MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 -MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 -MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 -MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 -MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 -MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 -MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 -MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 -MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 -MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 -MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 -MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 -MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 -MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 -MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 -MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 -MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 -MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 -MX28_PAD_LCD_D00__GPIO_1_0 0x1003 -MX28_PAD_LCD_D01__GPIO_1_1 0x1013 -MX28_PAD_LCD_D02__GPIO_1_2 0x1023 -MX28_PAD_LCD_D03__GPIO_1_3 0x1033 -MX28_PAD_LCD_D04__GPIO_1_4 0x1043 -MX28_PAD_LCD_D05__GPIO_1_5 0x1053 -MX28_PAD_LCD_D06__GPIO_1_6 0x1063 -MX28_PAD_LCD_D07__GPIO_1_7 0x1073 -MX28_PAD_LCD_D08__GPIO_1_8 0x1083 -MX28_PAD_LCD_D09__GPIO_1_9 0x1093 -MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 -MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 -MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 -MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 -MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 -MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 -MX28_PAD_LCD_D16__GPIO_1_16 0x1103 -MX28_PAD_LCD_D17__GPIO_1_17 0x1113 -MX28_PAD_LCD_D18__GPIO_1_18 0x1123 -MX28_PAD_LCD_D19__GPIO_1_19 0x1133 -MX28_PAD_LCD_D20__GPIO_1_20 0x1143 -MX28_PAD_LCD_D21__GPIO_1_21 0x1153 -MX28_PAD_LCD_D22__GPIO_1_22 0x1163 -MX28_PAD_LCD_D23__GPIO_1_23 0x1173 -MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 -MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 -MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 -MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 -MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 -MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 -MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 -MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 -MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 -MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 -MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 -MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 -MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 -MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 -MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 -MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 -MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 -MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 -MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 -MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 -MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 -MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 -MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 -MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 -MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 -MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 -MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 -MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 -MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 -MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 -MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 -MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 -MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 -MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 -MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 -MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 -MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 -MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 -MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 -MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 -MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 -MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 -MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 -MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 -MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 -MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 -MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 -MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 -MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 -MX28_PAD_PWM0__GPIO_3_16 0x3103 -MX28_PAD_PWM1__GPIO_3_17 0x3113 -MX28_PAD_PWM2__GPIO_3_18 0x3123 -MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 -MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 -MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 -MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 -MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 -MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 -MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 -MX28_PAD_SPDIF__GPIO_3_27 0x31b3 -MX28_PAD_PWM3__GPIO_3_28 0x31c3 -MX28_PAD_PWM4__GPIO_3_29 0x31d3 -MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 -MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 -MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 -MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 -MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 -MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 -MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 -MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 -MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 -MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 -MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 -MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 -MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 -MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 -MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 -MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 -MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 -MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 -MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 - -Valid values for i.MX23 pinmux-id: - -pinmux id ------- -- -MX23_PAD_GPMI_D00__GPMI_D00 0x0000 -MX23_PAD_GPMI_D01__GPMI_D01 0x0010 -MX23_PAD_GPMI_D02__GPMI_D02 0x0020 -MX23_PAD_GPMI_D03__GPMI_D03 0x0030 -MX23_PAD_GPMI_D04__GPMI_D04 0x0040 -MX23_PAD_GPMI_D05__GPMI_D05 0x0050 -MX23_PAD_GPMI_D06__GPMI_D06 0x0060 -MX23_PAD_GPMI_D07__GPMI_D07 0x0070 -MX23_PAD_GPMI_D08__GPMI_D08 0x0080 -MX23_PAD_GPMI_D09__GPMI_D09 0x0090 -MX23_PAD_GPMI_D10__GPMI_D10 0x00a0 -MX23_PAD_GPMI_D11__GPMI_D11 0x00b0 -MX23_PAD_GPMI_D12__GPMI_D12 0x00c0 -MX23_PAD_GPMI_D13__GPMI_D13 0x00d0 -MX23_PAD_GPMI_D14__GPMI_D14 0x00e0 -MX23_PAD_GPMI_D15__GPMI_D15 0x00f0 -MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100 -MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110 -MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130 -MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140 -MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150 -MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160 -MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170 -MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180 -MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190 -MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0 -MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0 -MX23_PAD_AUART1_RX__AUART1_RX 0x01c0 -MX23_PAD_AUART1_TX__AUART1_TX 0x01d0 -MX23_PAD_I2C_SCL__I2C_SCL 0x01e0 -MX23_PAD_I2C_SDA__I2C_SDA 0x01f0 -MX23_PAD_LCD_D00__LCD_D00 0x1000 -MX23_PAD_LCD_D01__LCD_D01 0x1010 -MX23_PAD_LCD_D02__LCD_D02 0x1020 -MX23_PAD_LCD_D03__LCD_D03 0x1030 -MX23_PAD_LCD_D04__LCD_D04 0x1040 -MX23_PAD_LCD_D05__LCD_D05 0x1050 -MX23_PAD_LCD_D06__LCD_D06 0x1060 -MX23_PAD_LCD_D07__LCD_D07 0x1070 -MX23_PAD_LCD_D08__LCD_D08 0x1080 -MX23_PAD_LCD_D09__LCD_D09 0x1090 -MX23_PAD_LCD_D10__LCD_D10 0x10a0 -MX23_PAD_LCD_D11__LCD_D11 0x10b0 -MX23_PAD_LCD_D12__LCD_D12 0x10c0 -MX23_PAD_LCD_D13__LCD_D13 0x10d0 -MX23_PAD_LCD_D14__LCD_D14 0x10e0 -MX23_PAD_LCD_D15__LCD_D15 0x10f0 -MX23_PAD_LCD_D16__LCD_D16 0x1100 -MX23_PAD_LCD_D17__LCD_D17 0x1110 -MX23_PAD_LCD_RESET__LCD_RESET 0x1120 -MX23_PAD_LCD_RS__LCD_RS 0x1130 -MX23_PAD_LCD_WR__LCD_WR 0x1140 -MX23_PAD_LCD_CS__LCD_CS 0x1150 -MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160 -MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170 -MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180 -MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190 -MX23_PAD_PWM0__PWM0 0x11a0 -MX23_PAD_PWM1__PWM1 0x11b0 -MX23_PAD_PWM2__PWM2 0x11c0 -MX23_PAD_PWM3__PWM3 0x11d0 -MX23_PAD_PWM4__PWM4 0x11e0 -MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000 -MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010 -MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020 -MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030 -MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040 -MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050 -MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060 -MX23_PAD_ROTARYA__ROTARYA 0x2070 -MX23_PAD_ROTARYB__ROTARYB 0x2080 -MX23_PAD_EMI_A00__EMI_A00 0x2090 -MX23_PAD_EMI_A01__EMI_A01 0x20a0 -MX23_PAD_EMI_A02__EMI_A02 0x20b0 -MX23_PAD_EMI_A03__EMI_A03 0x20c0 -MX23_PAD_EMI_A04__EMI_A04 0x20d0 -MX23_PAD_EMI_A05__EMI_A05 0x20e0 -MX23_PAD_EMI_A06__EMI_A06 0x20f0 -MX23_PAD_EMI_A07__EMI_A07 0x2100 -MX23_PAD_EMI_A08__EMI_A08 0x2110 -MX23_PAD_EMI_A09__EMI_A09 0x2120 -MX23_PAD_EMI_A10__EMI_A10 0x2130 -MX23_PAD_EMI_A11__EMI_A11 0x2140 -MX23_PAD_EMI_A12__EMI_A12 0x2150 -MX23_PAD_EMI_BA0__EMI_BA0 0x2160 -MX23_PAD_EMI_BA1__EMI_BA1 0x2170 -MX23_PAD_EMI_CASN__EMI_CASN 0x2180 -MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190 -MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0 -MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0 -MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0 -MX23_PAD_EMI_CKE__EMI_CKE 0x21d0 -MX23_PAD_EMI_RASN__EMI_RASN 0x21e0 -MX23_PAD_EMI_WEN__EMI_WEN 0x21f0 -MX23_PAD_EMI_D00__EMI_D00 0x3000 -MX23_PAD_EMI_D01__EMI_D01 0x3010 -MX23_PAD_EMI_D02__EMI_D02 0x3020 -MX23_PAD_EMI_D03__EMI_D03 0x3030 -MX23_PAD_EMI_D04__EMI_D04 0x3040 -MX23_PAD_EMI_D05__EMI_D05 0x3050 -MX23_PAD_EMI_D06__EMI_D06 0x3060 -MX23_PAD_EMI_D07__EMI_D07 0x3070 -MX23_PAD_EMI_D08__EMI_D08 0x3080 -MX23_PAD_EMI_D09__EMI_D09 0x3090 -MX23_PAD_EMI_D10__EMI_D10 0x30a0 -MX23_PAD_EMI_D11__EMI_D11 0x30b0 -MX23_PAD_EMI_D12__EMI_D12 0x30c0 -MX23_PAD_EMI_D13__EMI_D13 0x30d0 -MX23_PAD_EMI_D14__EMI_D14 0x30e0 -MX23_PAD_EMI_D15__EMI_D15 0x30f0 -MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100 -MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110 -MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120 -MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130 -MX23_PAD_EMI_CLK__EMI_CLK 0x3140 -MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150 -MX23_PAD_GPMI_D00__LCD_D8 0x0001 -MX23_PAD_GPMI_D01__LCD_D9 0x0011 -MX23_PAD_GPMI_D02__LCD_D10 0x0021 -MX23_PAD_GPMI_D03__LCD_D11 0x0031 -MX23_PAD_GPMI_D04__LCD_D12 0x0041 -MX23_PAD_GPMI_D05__LCD_D13 0x0051 -MX23_PAD_GPMI_D06__LCD_D14 0x0061 -MX23_PAD_GPMI_D07__LCD_D15 0x0071 -MX23_PAD_GPMI_D08__LCD_D18 0x0081 -MX23_PAD_GPMI_D09__LCD_D19 0x0091 -MX23_PAD_GPMI_D10__LCD_D20 0x00a1 -MX23_PAD_GPMI_D11__LCD_D21 0x00b1 -MX23_PAD_GPMI_D12__LCD_D22 0x00c1 -MX23_PAD_GPMI_D13__LCD_D23 0x00d1 -MX23_PAD_GPMI_D14__AUART2_RX 0x00e1 -MX23_PAD_GPMI_D15__AUART2_TX 0x00f1 -MX23_PAD_GPMI_CLE__LCD_D16 0x0101 -MX23_PAD_GPMI_ALE__LCD_D17 0x0111 -MX23_PAD_GPMI_CE2N__ATA_A2 0x0121 -MX23_PAD_AUART1_RTS__IR_CLK 0x01b1 -MX23_PAD_AUART1_RX__IR_RX 0x01c1 -MX23_PAD_AUART1_TX__IR_TX 0x01d1 -MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1 -MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1 -MX23_PAD_LCD_D00__ETM_DA8 0x1001 -MX23_PAD_LCD_D01__ETM_DA9 0x1011 -MX23_PAD_LCD_D02__ETM_DA10 0x1021 -MX23_PAD_LCD_D03__ETM_DA11 0x1031 -MX23_PAD_LCD_D04__ETM_DA12 0x1041 -MX23_PAD_LCD_D05__ETM_DA13 0x1051 -MX23_PAD_LCD_D06__ETM_DA14 0x1061 -MX23_PAD_LCD_D07__ETM_DA15 0x1071 -MX23_PAD_LCD_D08__ETM_DA0 0x1081 -MX23_PAD_LCD_D09__ETM_DA1 0x1091 -MX23_PAD_LCD_D10__ETM_DA2 0x10a1 -MX23_PAD_LCD_D11__ETM_DA3 0x10b1 -MX23_PAD_LCD_D12__ETM_DA4 0x10c1 -MX23_PAD_LCD_D13__ETM_DA5 0x10d1 -MX23_PAD_LCD_D14__ETM_DA6 0x10e1 -MX23_PAD_LCD_D15__ETM_DA7 0x10f1 -MX23_PAD_LCD_RESET__ETM_TCTL 0x1121 -MX23_PAD_LCD_RS__ETM_TCLK 0x1131 -MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161 -MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171 -MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181 -MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191 -MX23_PAD_PWM0__ROTARYA 0x11a1 -MX23_PAD_PWM1__ROTARYB 0x11b1 -MX23_PAD_PWM2__GPMI_RDY3 0x11c1 -MX23_PAD_PWM3__ETM_TCTL 0x11d1 -MX23_PAD_PWM4__ETM_TCLK 0x11e1 -MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011 -MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031 -MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041 -MX23_PAD_ROTARYA__AUART2_RTS 0x2071 -MX23_PAD_ROTARYB__AUART2_CTS 0x2081 -MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002 -MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012 -MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022 -MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032 -MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042 -MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052 -MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062 -MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072 -MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082 -MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092 -MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2 -MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2 -MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2 -MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132 -MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142 -MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182 -MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2 -MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2 -MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2 -MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2 -MX23_PAD_I2C_SCL__AUART1_TX 0x01e2 -MX23_PAD_I2C_SDA__AUART1_RX 0x01f2 -MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082 -MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092 -MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2 -MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2 -MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2 -MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2 -MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2 -MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2 -MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102 -MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122 -MX23_PAD_PWM0__DUART_RX 0x11a2 -MX23_PAD_PWM1__DUART_TX 0x11b2 -MX23_PAD_PWM3__AUART1_CTS 0x11d2 -MX23_PAD_PWM4__AUART1_RTS 0x11e2 -MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002 -MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012 -MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022 -MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032 -MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042 -MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052 -MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062 -MX23_PAD_ROTARYA__SPDIF 0x2072 -MX23_PAD_ROTARYB__GPMI_CE3N 0x2082 -MX23_PAD_GPMI_D00__GPIO_0_0 0x0003 -MX23_PAD_GPMI_D01__GPIO_0_1 0x0013 -MX23_PAD_GPMI_D02__GPIO_0_2 0x0023 -MX23_PAD_GPMI_D03__GPIO_0_3 0x0033 -MX23_PAD_GPMI_D04__GPIO_0_4 0x0043 -MX23_PAD_GPMI_D05__GPIO_0_5 0x0053 -MX23_PAD_GPMI_D06__GPIO_0_6 0x0063 -MX23_PAD_GPMI_D07__GPIO_0_7 0x0073 -MX23_PAD_GPMI_D08__GPIO_0_8 0x0083 -MX23_PAD_GPMI_D09__GPIO_0_9 0x0093 -MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3 -MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3 -MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3 -MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3 -MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3 -MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3 -MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103 -MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113 -MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133 -MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143 -MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153 -MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163 -MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173 -MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183 -MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193 -MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3 -MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3 -MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3 -MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3 -MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3 -MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3 -MX23_PAD_LCD_D00__GPIO_1_0 0x1003 -MX23_PAD_LCD_D01__GPIO_1_1 0x1013 -MX23_PAD_LCD_D02__GPIO_1_2 0x1023 -MX23_PAD_LCD_D03__GPIO_1_3 0x1033 -MX23_PAD_LCD_D04__GPIO_1_4 0x1043 -MX23_PAD_LCD_D05__GPIO_1_5 0x1053 -MX23_PAD_LCD_D06__GPIO_1_6 0x1063 -MX23_PAD_LCD_D07__GPIO_1_7 0x1073 -MX23_PAD_LCD_D08__GPIO_1_8 0x1083 -MX23_PAD_LCD_D09__GPIO_1_9 0x1093 -MX23_PAD_LCD_D10__GPIO_1_10 0x10a3 -MX23_PAD_LCD_D11__GPIO_1_11 0x10b3 -MX23_PAD_LCD_D12__GPIO_1_12 0x10c3 -MX23_PAD_LCD_D13__GPIO_1_13 0x10d3 -MX23_PAD_LCD_D14__GPIO_1_14 0x10e3 -MX23_PAD_LCD_D15__GPIO_1_15 0x10f3 -MX23_PAD_LCD_D16__GPIO_1_16 0x1103 -MX23_PAD_LCD_D17__GPIO_1_17 0x1113 -MX23_PAD_LCD_RESET__GPIO_1_18 0x1123 -MX23_PAD_LCD_RS__GPIO_1_19 0x1133 -MX23_PAD_LCD_WR__GPIO_1_20 0x1143 -MX23_PAD_LCD_CS__GPIO_1_21 0x1153 -MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163 -MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173 -MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183 -MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193 -MX23_PAD_PWM0__GPIO_1_26 0x11a3 -MX23_PAD_PWM1__GPIO_1_27 0x11b3 -MX23_PAD_PWM2__GPIO_1_28 0x11c3 -MX23_PAD_PWM3__GPIO_1_29 0x11d3 -MX23_PAD_PWM4__GPIO_1_30 0x11e3 -MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003 -MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013 -MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023 -MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033 -MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043 -MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053 -MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063 -MX23_PAD_ROTARYA__GPIO_2_7 0x2073 -MX23_PAD_ROTARYB__GPIO_2_8 0x2083 -MX23_PAD_EMI_A00__GPIO_2_9 0x2093 -MX23_PAD_EMI_A01__GPIO_2_10 0x20a3 -MX23_PAD_EMI_A02__GPIO_2_11 0x20b3 -MX23_PAD_EMI_A03__GPIO_2_12 0x20c3 -MX23_PAD_EMI_A04__GPIO_2_13 0x20d3 -MX23_PAD_EMI_A05__GPIO_2_14 0x20e3 -MX23_PAD_EMI_A06__GPIO_2_15 0x20f3 -MX23_PAD_EMI_A07__GPIO_2_16 0x2103 -MX23_PAD_EMI_A08__GPIO_2_17 0x2113 -MX23_PAD_EMI_A09__GPIO_2_18 0x2123 -MX23_PAD_EMI_A10__GPIO_2_19 0x2133 -MX23_PAD_EMI_A11__GPIO_2_20 0x2143 -MX23_PAD_EMI_A12__GPIO_2_21 0x2153 -MX23_PAD_EMI_BA0__GPIO_2_22 0x2163 -MX23_PAD_EMI_BA1__GPIO_2_23 0x2173 -MX23_PAD_EMI_CASN__GPIO_2_24 0x2183 -MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193 -MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3 -MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3 -MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3 -MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3 -MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3 -MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3 +Valid values for i.MX28/i.MX23 pinmux-id are defined in +arch/arm/boot/dts/imx28-pinfunc.h and arch/arm/boot/dts/imx23-pinfunc.h. +The definitions for the padconfig properties can be found in +arch/arm/boot/dts/mxs-pinfunc.h. diff --git a/arch/arm/boot/dts/imx23-pinfunc.h b/arch/arm/boot/dts/imx23-pinfunc.h new file mode 100644 index 000000000000..5c0f32ca3a93 --- /dev/null +++ b/arch/arm/boot/dts/imx23-pinfunc.h @@ -0,0 +1,333 @@ +/* + * Header providing constants for i.MX23 pinctrl bindings. + * + * Copyright (C) 2013 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DT_BINDINGS_MX23_PINCTRL_H__ +#define __DT_BINDINGS_MX23_PINCTRL_H__ + +#include "mxs-pinfunc.h" + +#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000 +#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010 +#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020 +#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030 +#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040 +#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050 +#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060 +#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070 +#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080 +#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090 +#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0 +#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0 +#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0 +#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0 +#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0 +#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0 +#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100 +#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110 +#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 +#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130 +#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140 +#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150 +#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160 +#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170 +#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180 +#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190 +#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0 +#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0 +#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0 +#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0 +#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0 +#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0 +#define MX23_PAD_LCD_D00__LCD_D00 0x1000 +#define MX23_PAD_LCD_D01__LCD_D01 0x1010 +#define MX23_PAD_LCD_D02__LCD_D02 0x1020 +#define MX23_PAD_LCD_D03__LCD_D03 0x1030 +#define MX23_PAD_LCD_D04__LCD_D04 0x1040 +#define MX23_PAD_LCD_D05__LCD_D05 0x1050 +#define MX23_PAD_LCD_D06__LCD_D06 0x1060 +#define MX23_PAD_LCD_D07__LCD_D07 0x1070 +#define MX23_PAD_LCD_D08__LCD_D08 0x1080 +#define MX23_PAD_LCD_D09__LCD_D09 0x1090 +#define MX23_PAD_LCD_D10__LCD_D10 0x10a0 +#define MX23_PAD_LCD_D11__LCD_D11 0x10b0 +#define MX23_PAD_LCD_D12__LCD_D12 0x10c0 +#define MX23_PAD_LCD_D13__LCD_D13 0x10d0 +#define MX23_PAD_LCD_D14__LCD_D14 0x10e0 +#define MX23_PAD_LCD_D15__LCD_D15 0x10f0 +#define MX23_PAD_LCD_D16__LCD_D16 0x1100 +#define MX23_PAD_LCD_D17__LCD_D17 0x1110 +#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120 +#define MX23_PAD_LCD_RS__LCD_RS 0x1130 +#define MX23_PAD_LCD_WR__LCD_WR 0x1140 +#define MX23_PAD_LCD_CS__LCD_CS 0x1150 +#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160 +#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170 +#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180 +#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190 +#define MX23_PAD_PWM0__PWM0 0x11a0 +#define MX23_PAD_PWM1__PWM1 0x11b0 +#define MX23_PAD_PWM2__PWM2 0x11c0 +#define MX23_PAD_PWM3__PWM3 0x11d0 +#define MX23_PAD_PWM4__PWM4 0x11e0 +#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000 +#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010 +#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020 +#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030 +#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040 +#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050 +#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060 +#define MX23_PAD_ROTARYA__ROTARYA 0x2070 +#define MX23_PAD_ROTARYB__ROTARYB 0x2080 +#define MX23_PAD_EMI_A00__EMI_A00 0x2090 +#define MX23_PAD_EMI_A01__EMI_A01 0x20a0 +#define MX23_PAD_EMI_A02__EMI_A02 0x20b0 +#define MX23_PAD_EMI_A03__EMI_A03 0x20c0 +#define MX23_PAD_EMI_A04__EMI_A04 0x20d0 +#define MX23_PAD_EMI_A05__EMI_A05 0x20e0 +#define MX23_PAD_EMI_A06__EMI_A06 0x20f0 +#define MX23_PAD_EMI_A07__EMI_A07 0x2100 +#define MX23_PAD_EMI_A08__EMI_A08 0x2110 +#define MX23_PAD_EMI_A09__EMI_A09 0x2120 +#define MX23_PAD_EMI_A10__EMI_A10 0x2130 +#define MX23_PAD_EMI_A11__EMI_A11 0x2140 +#define MX23_PAD_EMI_A12__EMI_A12 0x2150 +#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160 +#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170 +#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180 +#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190 +#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0 +#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0 +#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0 +#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0 +#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0 +#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0 +#define MX23_PAD_EMI_D00__EMI_D00 0x3000 +#define MX23_PAD_EMI_D01__EMI_D01 0x3010 +#define MX23_PAD_EMI_D02__EMI_D02 0x3020 +#define MX23_PAD_EMI_D03__EMI_D03 0x3030 +#define MX23_PAD_EMI_D04__EMI_D04 0x3040 +#define MX23_PAD_EMI_D05__EMI_D05 0x3050 +#define MX23_PAD_EMI_D06__EMI_D06 0x3060 +#define MX23_PAD_EMI_D07__EMI_D07 0x3070 +#define MX23_PAD_EMI_D08__EMI_D08 0x3080 +#define MX23_PAD_EMI_D09__EMI_D09 0x3090 +#define MX23_PAD_EMI_D10__EMI_D10 0x30a0 +#define MX23_PAD_EMI_D11__EMI_D11 0x30b0 +#define MX23_PAD_EMI_D12__EMI_D12 0x30c0 +#define MX23_PAD_EMI_D13__EMI_D13 0x30d0 +#define MX23_PAD_EMI_D14__EMI_D14 0x30e0 +#define MX23_PAD_EMI_D15__EMI_D15 0x30f0 +#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100 +#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110 +#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120 +#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130 +#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140 +#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150 +#define MX23_PAD_GPMI_D00__LCD_D8 0x0001 +#define MX23_PAD_GPMI_D01__LCD_D9 0x0011 +#define MX23_PAD_GPMI_D02__LCD_D10 0x0021 +#define MX23_PAD_GPMI_D03__LCD_D11 0x0031 +#define MX23_PAD_GPMI_D04__LCD_D12 0x0041 +#define MX23_PAD_GPMI_D05__LCD_D13 0x0051 +#define MX23_PAD_GPMI_D06__LCD_D14 0x0061 +#define MX23_PAD_GPMI_D07__LCD_D15 0x0071 +#define MX23_PAD_GPMI_D08__LCD_D18 0x0081 +#define MX23_PAD_GPMI_D09__LCD_D19 0x0091 +#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1 +#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1 +#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1 +#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1 +#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1 +#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1 +#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101 +#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111 +#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121 +#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1 +#define MX23_PAD_AUART1_RX__IR_RX 0x01c1 +#define MX23_PAD_AUART1_TX__IR_TX 0x01d1 +#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1 +#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1 +#define MX23_PAD_LCD_D00__ETM_DA8 0x1001 +#define MX23_PAD_LCD_D01__ETM_DA9 0x1011 +#define MX23_PAD_LCD_D02__ETM_DA10 0x1021 +#define MX23_PAD_LCD_D03__ETM_DA11 0x1031 +#define MX23_PAD_LCD_D04__ETM_DA12 0x1041 +#define MX23_PAD_LCD_D05__ETM_DA13 0x1051 +#define MX23_PAD_LCD_D06__ETM_DA14 0x1061 +#define MX23_PAD_LCD_D07__ETM_DA15 0x1071 +#define MX23_PAD_LCD_D08__ETM_DA0 0x1081 +#define MX23_PAD_LCD_D09__ETM_DA1 0x1091 +#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1 +#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1 +#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1 +#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1 +#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1 +#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1 +#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121 +#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131 +#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161 +#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171 +#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181 +#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191 +#define MX23_PAD_PWM0__ROTARYA 0x11a1 +#define MX23_PAD_PWM1__ROTARYB 0x11b1 +#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1 +#define MX23_PAD_PWM3__ETM_TCTL 0x11d1 +#define MX23_PAD_PWM4__ETM_TCLK 0x11e1 +#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011 +#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031 +#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041 +#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071 +#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081 +#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002 +#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012 +#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022 +#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032 +#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042 +#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052 +#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062 +#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072 +#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082 +#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092 +#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2 +#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2 +#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2 +#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132 +#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142 +#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182 +#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2 +#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2 +#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2 +#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2 +#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2 +#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2 +#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082 +#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092 +#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2 +#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2 +#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2 +#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2 +#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2 +#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2 +#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102 +#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122 +#define MX23_PAD_PWM0__DUART_RX 0x11a2 +#define MX23_PAD_PWM1__DUART_TX 0x11b2 +#define MX23_PAD_PWM3__AUART1_CTS 0x11d2 +#define MX23_PAD_PWM4__AUART1_RTS 0x11e2 +#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002 +#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012 +#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022 +#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032 +#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042 +#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052 +#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062 +#define MX23_PAD_ROTARYA__SPDIF 0x2072 +#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082 +#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003 +#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013 +#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023 +#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033 +#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043 +#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053 +#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063 +#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073 +#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083 +#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093 +#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3 +#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3 +#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3 +#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3 +#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3 +#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3 +#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103 +#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113 +#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123 +#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133 +#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143 +#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153 +#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163 +#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173 +#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183 +#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193 +#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3 +#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3 +#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3 +#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3 +#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3 +#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3 +#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003 +#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013 +#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023 +#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033 +#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043 +#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053 +#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063 +#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073 +#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083 +#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093 +#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3 +#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3 +#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3 +#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3 +#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3 +#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3 +#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103 +#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113 +#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123 +#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133 +#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143 +#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153 +#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163 +#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173 +#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183 +#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193 +#define MX23_PAD_PWM0__GPIO_1_26 0x11a3 +#define MX23_PAD_PWM1__GPIO_1_27 0x11b3 +#define MX23_PAD_PWM2__GPIO_1_28 0x11c3 +#define MX23_PAD_PWM3__GPIO_1_29 0x11d3 +#define MX23_PAD_PWM4__GPIO_1_30 0x11e3 +#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003 +#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013 +#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023 +#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033 +#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043 +#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053 +#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063 +#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073 +#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083 +#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093 +#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3 +#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3 +#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3 +#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3 +#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3 +#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3 +#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103 +#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113 +#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123 +#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133 +#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143 +#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153 +#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163 +#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173 +#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183 +#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193 +#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3 +#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3 +#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3 +#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3 +#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3 +#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3 + +#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/imx28-pinfunc.h b/arch/arm/boot/dts/imx28-pinfunc.h new file mode 100644 index 000000000000..e11f69ba0fe4 --- /dev/null +++ b/arch/arm/boot/dts/imx28-pinfunc.h @@ -0,0 +1,506 @@ +/* + * Header providing constants for i.MX28 pinctrl bindings. + * + * Copyright (C) 2013 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DT_BINDINGS_MX28_PINCTRL_H__ +#define __DT_BINDINGS_MX28_PINCTRL_H__ + +#include "mxs-pinfunc.h" + +#define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 +#define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 +#define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 +#define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 +#define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 +#define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 +#define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 +#define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 +#define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 +#define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 +#define MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 +#define MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 +#define MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 +#define MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 +#define MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 +#define MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 +#define MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 +#define MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 +#define MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 +#define MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 +#define MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 +#define MX28_PAD_LCD_D00__LCD_D0 0x1000 +#define MX28_PAD_LCD_D01__LCD_D1 0x1010 +#define MX28_PAD_LCD_D02__LCD_D2 0x1020 +#define MX28_PAD_LCD_D03__LCD_D3 0x1030 +#define MX28_PAD_LCD_D04__LCD_D4 0x1040 +#define MX28_PAD_LCD_D05__LCD_D5 0x1050 +#define MX28_PAD_LCD_D06__LCD_D6 0x1060 +#define MX28_PAD_LCD_D07__LCD_D7 0x1070 +#define MX28_PAD_LCD_D08__LCD_D8 0x1080 +#define MX28_PAD_LCD_D09__LCD_D9 0x1090 +#define MX28_PAD_LCD_D10__LCD_D10 0x10a0 +#define MX28_PAD_LCD_D11__LCD_D11 0x10b0 +#define MX28_PAD_LCD_D12__LCD_D12 0x10c0 +#define MX28_PAD_LCD_D13__LCD_D13 0x10d0 +#define MX28_PAD_LCD_D14__LCD_D14 0x10e0 +#define MX28_PAD_LCD_D15__LCD_D15 0x10f0 +#define MX28_PAD_LCD_D16__LCD_D16 0x1100 +#define MX28_PAD_LCD_D17__LCD_D17 0x1110 +#define MX28_PAD_LCD_D18__LCD_D18 0x1120 +#define MX28_PAD_LCD_D19__LCD_D19 0x1130 +#define MX28_PAD_LCD_D20__LCD_D20 0x1140 +#define MX28_PAD_LCD_D21__LCD_D21 0x1150 +#define MX28_PAD_LCD_D22__LCD_D22 0x1160 +#define MX28_PAD_LCD_D23__LCD_D23 0x1170 +#define MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 +#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 +#define MX28_PAD_LCD_RS__LCD_RS 0x11a0 +#define MX28_PAD_LCD_CS__LCD_CS 0x11b0 +#define MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 +#define MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 +#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 +#define MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 +#define MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 +#define MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 +#define MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 +#define MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 +#define MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 +#define MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 +#define MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 +#define MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 +#define MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 +#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 +#define MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 +#define MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 +#define MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 +#define MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 +#define MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 +#define MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 +#define MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 +#define MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 +#define MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 +#define MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 +#define MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 +#define MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 +#define MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 +#define MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 +#define MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 +#define MX28_PAD_AUART0_RX__AUART0_RX 0x3000 +#define MX28_PAD_AUART0_TX__AUART0_TX 0x3010 +#define MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 +#define MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 +#define MX28_PAD_AUART1_RX__AUART1_RX 0x3040 +#define MX28_PAD_AUART1_TX__AUART1_TX 0x3050 +#define MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 +#define MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 +#define MX28_PAD_AUART2_RX__AUART2_RX 0x3080 +#define MX28_PAD_AUART2_TX__AUART2_TX 0x3090 +#define MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 +#define MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 +#define MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 +#define MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 +#define MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 +#define MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 +#define MX28_PAD_PWM0__PWM_0 0x3100 +#define MX28_PAD_PWM1__PWM_1 0x3110 +#define MX28_PAD_PWM2__PWM_2 0x3120 +#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 +#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 +#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 +#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 +#define MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 +#define MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 +#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 +#define MX28_PAD_SPDIF__SPDIF_TX 0x31b0 +#define MX28_PAD_PWM3__PWM_3 0x31c0 +#define MX28_PAD_PWM4__PWM_4 0x31d0 +#define MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 +#define MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 +#define MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 +#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 +#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 +#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 +#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 +#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 +#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 +#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 +#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 +#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 +#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 +#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 +#define MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 +#define MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 +#define MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 +#define MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 +#define MX28_PAD_EMI_D00__EMI_DATA0 0x5000 +#define MX28_PAD_EMI_D01__EMI_DATA1 0x5010 +#define MX28_PAD_EMI_D02__EMI_DATA2 0x5020 +#define MX28_PAD_EMI_D03__EMI_DATA3 0x5030 +#define MX28_PAD_EMI_D04__EMI_DATA4 0x5040 +#define MX28_PAD_EMI_D05__EMI_DATA5 0x5050 +#define MX28_PAD_EMI_D06__EMI_DATA6 0x5060 +#define MX28_PAD_EMI_D07__EMI_DATA7 0x5070 +#define MX28_PAD_EMI_D08__EMI_DATA8 0x5080 +#define MX28_PAD_EMI_D09__EMI_DATA9 0x5090 +#define MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 +#define MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 +#define MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 +#define MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 +#define MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 +#define MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 +#define MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 +#define MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 +#define MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 +#define MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 +#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 +#define MX28_PAD_EMI_CLK__EMI_CLK 0x5150 +#define MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 +#define MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 +#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 +#define MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 +#define MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 +#define MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 +#define MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 +#define MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 +#define MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 +#define MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 +#define MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 +#define MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 +#define MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 +#define MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 +#define MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 +#define MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 +#define MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 +#define MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 +#define MX28_PAD_EMI_BA0__EMI_BA0 0x6100 +#define MX28_PAD_EMI_BA1__EMI_BA1 0x6110 +#define MX28_PAD_EMI_BA2__EMI_BA2 0x6120 +#define MX28_PAD_EMI_CASN__EMI_CASN 0x6130 +#define MX28_PAD_EMI_RASN__EMI_RASN 0x6140 +#define MX28_PAD_EMI_WEN__EMI_WEN 0x6150 +#define MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 +#define MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 +#define MX28_PAD_EMI_CKE__EMI_CKE 0x6180 +#define MX28_PAD_GPMI_D00__SSP1_D0 0x0001 +#define MX28_PAD_GPMI_D01__SSP1_D1 0x0011 +#define MX28_PAD_GPMI_D02__SSP1_D2 0x0021 +#define MX28_PAD_GPMI_D03__SSP1_D3 0x0031 +#define MX28_PAD_GPMI_D04__SSP1_D4 0x0041 +#define MX28_PAD_GPMI_D05__SSP1_D5 0x0051 +#define MX28_PAD_GPMI_D06__SSP1_D6 0x0061 +#define MX28_PAD_GPMI_D07__SSP1_D7 0x0071 +#define MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 +#define MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 +#define MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 +#define MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 +#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 +#define MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 +#define MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 +#define MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 +#define MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 +#define MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 +#define MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 +#define MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 +#define MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 +#define MX28_PAD_LCD_D03__ETM_DA8 0x1031 +#define MX28_PAD_LCD_D04__ETM_DA9 0x1041 +#define MX28_PAD_LCD_D08__ETM_DA3 0x1081 +#define MX28_PAD_LCD_D09__ETM_DA4 0x1091 +#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 +#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 +#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 +#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 +#define MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 +#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 +#define MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 +#define MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 +#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 +#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 +#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 +#define MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 +#define MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 +#define MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 +#define MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 +#define MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 +#define MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 +#define MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 +#define MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 +#define MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 +#define MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 +#define MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 +#define MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 +#define MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 +#define MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 +#define MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 +#define MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 +#define MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 +#define MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 +#define MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 +#define MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 +#define MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 +#define MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 +#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 +#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 +#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 +#define MX28_PAD_AUART1_RTS__USB0_ID 0x3071 +#define MX28_PAD_AUART2_RX__SSP3_D1 0x3081 +#define MX28_PAD_AUART2_TX__SSP3_D2 0x3091 +#define MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 +#define MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 +#define MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 +#define MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 +#define MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 +#define MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 +#define MX28_PAD_PWM0__I2C1_SCL 0x3101 +#define MX28_PAD_PWM1__I2C1_SDA 0x3111 +#define MX28_PAD_PWM2__USB0_ID 0x3121 +#define MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 +#define MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 +#define MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 +#define MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 +#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 +#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 +#define MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 +#define MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 +#define MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 +#define MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 +#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 +#define MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 +#define MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 +#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 +#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 +#define MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 +#define MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 +#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 +#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 +#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 +#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 +#define MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 +#define MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 +#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 +#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 +#define MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 +#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 +#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 +#define MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 +#define MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 +#define MX28_PAD_LCD_D00__ETM_DA0 0x1002 +#define MX28_PAD_LCD_D01__ETM_DA1 0x1012 +#define MX28_PAD_LCD_D02__ETM_DA2 0x1022 +#define MX28_PAD_LCD_D03__ETM_DA3 0x1032 +#define MX28_PAD_LCD_D04__ETM_DA4 0x1042 +#define MX28_PAD_LCD_D05__ETM_DA5 0x1052 +#define MX28_PAD_LCD_D06__ETM_DA6 0x1062 +#define MX28_PAD_LCD_D07__ETM_DA7 0x1072 +#define MX28_PAD_LCD_D08__ETM_DA8 0x1082 +#define MX28_PAD_LCD_D09__ETM_DA9 0x1092 +#define MX28_PAD_LCD_D10__ETM_DA10 0x10a2 +#define MX28_PAD_LCD_D11__ETM_DA11 0x10b2 +#define MX28_PAD_LCD_D12__ETM_DA12 0x10c2 +#define MX28_PAD_LCD_D13__ETM_DA13 0x10d2 +#define MX28_PAD_LCD_D14__ETM_DA14 0x10e2 +#define MX28_PAD_LCD_D15__ETM_DA15 0x10f2 +#define MX28_PAD_LCD_D16__ETM_DA7 0x1102 +#define MX28_PAD_LCD_D17__ETM_DA6 0x1112 +#define MX28_PAD_LCD_D18__ETM_DA5 0x1122 +#define MX28_PAD_LCD_D19__ETM_DA4 0x1132 +#define MX28_PAD_LCD_D20__ETM_DA3 0x1142 +#define MX28_PAD_LCD_D21__ETM_DA2 0x1152 +#define MX28_PAD_LCD_D22__ETM_DA1 0x1162 +#define MX28_PAD_LCD_D23__ETM_DA0 0x1172 +#define MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 +#define MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 +#define MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 +#define MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 +#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 +#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 +#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 +#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 +#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 +#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 +#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 +#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 +#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 +#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 +#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 +#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 +#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 +#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 +#define MX28_PAD_AUART0_RX__DUART_CTS 0x3002 +#define MX28_PAD_AUART0_TX__DUART_RTS 0x3012 +#define MX28_PAD_AUART0_CTS__DUART_RX 0x3022 +#define MX28_PAD_AUART0_RTS__DUART_TX 0x3032 +#define MX28_PAD_AUART1_RX__PWM_0 0x3042 +#define MX28_PAD_AUART1_TX__PWM_1 0x3052 +#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 +#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 +#define MX28_PAD_AUART2_RX__SSP3_D4 0x3082 +#define MX28_PAD_AUART2_TX__SSP3_D5 0x3092 +#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 +#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 +#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 +#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 +#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 +#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 +#define MX28_PAD_PWM0__DUART_RX 0x3102 +#define MX28_PAD_PWM1__DUART_TX 0x3112 +#define MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 +#define MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 +#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 +#define MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 +#define MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 +#define MX28_PAD_I2C0_SCL__DUART_RX 0x3182 +#define MX28_PAD_I2C0_SDA__DUART_TX 0x3192 +#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 +#define MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 +#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 +#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 +#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 +#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 +#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 +#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 +#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 +#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 +#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 +#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 +#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 +#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 +#define MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 +#define MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 +#define MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 +#define MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 +#define MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 +#define MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 +#define MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 +#define MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 +#define MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 +#define MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 +#define MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 +#define MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 +#define MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 +#define MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 +#define MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 +#define MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 +#define MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 +#define MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 +#define MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 +#define MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 +#define MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 +#define MX28_PAD_LCD_D00__GPIO_1_0 0x1003 +#define MX28_PAD_LCD_D01__GPIO_1_1 0x1013 +#define MX28_PAD_LCD_D02__GPIO_1_2 0x1023 +#define MX28_PAD_LCD_D03__GPIO_1_3 0x1033 +#define MX28_PAD_LCD_D04__GPIO_1_4 0x1043 +#define MX28_PAD_LCD_D05__GPIO_1_5 0x1053 +#define MX28_PAD_LCD_D06__GPIO_1_6 0x1063 +#define MX28_PAD_LCD_D07__GPIO_1_7 0x1073 +#define MX28_PAD_LCD_D08__GPIO_1_8 0x1083 +#define MX28_PAD_LCD_D09__GPIO_1_9 0x1093 +#define MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 +#define MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 +#define MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 +#define MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 +#define MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 +#define MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 +#define MX28_PAD_LCD_D16__GPIO_1_16 0x1103 +#define MX28_PAD_LCD_D17__GPIO_1_17 0x1113 +#define MX28_PAD_LCD_D18__GPIO_1_18 0x1123 +#define MX28_PAD_LCD_D19__GPIO_1_19 0x1133 +#define MX28_PAD_LCD_D20__GPIO_1_20 0x1143 +#define MX28_PAD_LCD_D21__GPIO_1_21 0x1153 +#define MX28_PAD_LCD_D22__GPIO_1_22 0x1163 +#define MX28_PAD_LCD_D23__GPIO_1_23 0x1173 +#define MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 +#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 +#define MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 +#define MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 +#define MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 +#define MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 +#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 +#define MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 +#define MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 +#define MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 +#define MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 +#define MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 +#define MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 +#define MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 +#define MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 +#define MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 +#define MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 +#define MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 +#define MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 +#define MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 +#define MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 +#define MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 +#define MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 +#define MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 +#define MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 +#define MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 +#define MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 +#define MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 +#define MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 +#define MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 +#define MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 +#define MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 +#define MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 +#define MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 +#define MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 +#define MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 +#define MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 +#define MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 +#define MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 +#define MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 +#define MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 +#define MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 +#define MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 +#define MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 +#define MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 +#define MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 +#define MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 +#define MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 +#define MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 +#define MX28_PAD_PWM0__GPIO_3_16 0x3103 +#define MX28_PAD_PWM1__GPIO_3_17 0x3113 +#define MX28_PAD_PWM2__GPIO_3_18 0x3123 +#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 +#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 +#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 +#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 +#define MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 +#define MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 +#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 +#define MX28_PAD_SPDIF__GPIO_3_27 0x31b3 +#define MX28_PAD_PWM3__GPIO_3_28 0x31c3 +#define MX28_PAD_PWM4__GPIO_3_29 0x31d3 +#define MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 +#define MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 +#define MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 +#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 +#define MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 +#define MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 +#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 +#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 +#define MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 +#define MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 +#define MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 +#define MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 +#define MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 +#define MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 +#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 +#define MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 +#define MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 +#define MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 +#define MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 + +#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/mxs-pinfunc.h b/arch/arm/boot/dts/mxs-pinfunc.h new file mode 100644 index 000000000000..c6da987b20cb --- /dev/null +++ b/arch/arm/boot/dts/mxs-pinfunc.h @@ -0,0 +1,31 @@ +/* + * Header providing constants for i.MX28 pinctrl bindings. + * + * Copyright (C) 2013 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DT_BINDINGS_MXS_PINCTRL_H__ +#define __DT_BINDINGS_MXS_PINCTRL_H__ + +/* fsl,drive-strength property */ +#define MXS_DRIVE_4mA 0 +#define MXS_DRIVE_8mA 1 +#define MXS_DRIVE_12mA 2 +#define MXS_DRIVE_16mA 3 + +/* fsl,voltage property */ +#define MXS_VOLTAGE_LOW 0 +#define MXS_VOLTAGE_HIGH 1 + +/* fsl,pull-up property */ +#define MXS_PULL_DISABLE 0 +#define MXS_PULL_ENABLE 1 + +#endif /* __DT_BINDINGS_MXS_PINCTRL_H__ */ -- cgit v1.2.3 From bc3875f1a61e30dc56b00ffbd55daabce271e2ee Mon Sep 17 00:00:00 2001 From: Lothar Waßmann Date: Thu, 19 Sep 2013 08:59:48 +0200 Subject: ARM: dts: mxs: modify mx23/mx28 dts files to use pinctrl headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert mx23/mx28 dts filed to use the pinctrl header files. NOTE: During automatic conversion of these files to use the pinconfig definitions an inconsistency has been found in: arch/arm/boot/dts/imx28-apx4devkit.dts According to the comment the function for pad SSP2_SS0 should have been MX28_PAD_SSP2_SS0__GPIO_2_19, while the given value 0x2131 represents: MX28_PAD_SSP2_SS0__AUART3_TX I used the later (though probably wrong) definition because that's what is actually being used in the DTB. Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23-evk.dts | 10 +- arch/arm/boot/dts/imx23-olinuxino.dts | 6 +- arch/arm/boot/dts/imx23-stmp378x_devb.dts | 6 +- arch/arm/boot/dts/imx23.dtsi | 163 ++++++++------- arch/arm/boot/dts/imx28-apf28.dts | 2 +- arch/arm/boot/dts/imx28-apf28dev.dts | 24 +-- arch/arm/boot/dts/imx28-apx4devkit.dts | 38 ++-- arch/arm/boot/dts/imx28-cfa10036.dts | 8 +- arch/arm/boot/dts/imx28-cfa10037.dts | 6 +- arch/arm/boot/dts/imx28-cfa10049.dts | 84 ++++---- arch/arm/boot/dts/imx28-cfa10055.dts | 56 ++--- arch/arm/boot/dts/imx28-cfa10056.dts | 20 +- arch/arm/boot/dts/imx28-cfa10057.dts | 48 ++--- arch/arm/boot/dts/imx28-cfa10058.dts | 12 +- arch/arm/boot/dts/imx28-evk.dts | 32 +-- arch/arm/boot/dts/imx28-m28evk.dts | 16 +- arch/arm/boot/dts/imx28-sps1.dts | 8 +- arch/arm/boot/dts/imx28-tx28.dts | 2 +- arch/arm/boot/dts/imx28.dtsi | 337 +++++++++++++++--------------- 19 files changed, 440 insertions(+), 438 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 185c7c01102a..fdd8b27adb17 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "imx23.dtsi" +#include "imx23.dtsi" / { model = "Freescale i.MX23 Evaluation Kit"; @@ -45,10 +45,10 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ - 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ - 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ - 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ + MX23_PAD_LCD_RESET__GPIO_1_18 + MX23_PAD_PWM3__GPIO_1_29 + MX23_PAD_PWM4__GPIO_1_30 + MX23_PAD_SSP1_DETECT__SSP1_DETECT >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index fc766ae12e24..f575434d22ae 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -12,7 +12,7 @@ */ /dts-v1/; -/include/ "imx23.dtsi" +#include "imx23.dtsi" / { model = "i.MX23 Olinuxino Low Cost Board"; @@ -40,7 +40,7 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */ + MX23_PAD_GPMI_ALE__GPIO_0_17 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -50,7 +50,7 @@ led_pin_gpio2_1: led_gpio2_1@0 { reg = <0>; fsl,pinmux-ids = < - 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ + MX23_PAD_SSP1_DETECT__GPIO_2_1 >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts index 85c3864b6a56..2c8a9b0b9f43 100644 --- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts +++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "imx23.dtsi" +#include "imx23.dtsi" / { model = "Freescale STMP378x Development Board"; @@ -39,8 +39,8 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ - 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ + MX23_PAD_PWM3__GPIO_1_29 + MX23_PAD_PWM4__GPIO_1_30 >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 28b5ce289662..ff96e592ec3c 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -9,7 +9,8 @@ * http://www.gnu.org/copyleft/gpl.html */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include "imx23-pinfunc.h" / { interrupt-parent = <&icoll>; @@ -137,8 +138,8 @@ duart_pins_a: duart@0 { reg = <0>; fsl,pinmux-ids = < - 0x11a2 /* MX23_PAD_PWM0__DUART_RX */ - 0x11b2 /* MX23_PAD_PWM1__DUART_TX */ + MX23_PAD_PWM0__DUART_RX + MX23_PAD_PWM1__DUART_TX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -148,10 +149,10 @@ auart0_pins_a: auart0@0 { reg = <0>; fsl,pinmux-ids = < - 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */ - 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */ - 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */ - 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */ + MX23_PAD_AUART1_RX__AUART1_RX + MX23_PAD_AUART1_TX__AUART1_TX + MX23_PAD_AUART1_CTS__AUART1_CTS + MX23_PAD_AUART1_RTS__AUART1_RTS >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -161,8 +162,8 @@ auart0_2pins_a: auart0-2pins@0 { reg = <0>; fsl,pinmux-ids = < - 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */ - 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */ + MX23_PAD_I2C_SCL__AUART1_TX + MX23_PAD_I2C_SDA__AUART1_RX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -172,23 +173,23 @@ gpmi_pins_a: gpmi-nand@0 { reg = <0>; fsl,pinmux-ids = < - 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */ - 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */ - 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */ - 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */ - 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */ - 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */ - 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */ - 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */ - 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */ - 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */ - 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */ - 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */ - 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */ - 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */ - 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */ - 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */ - 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */ + MX23_PAD_GPMI_D00__GPMI_D00 + MX23_PAD_GPMI_D01__GPMI_D01 + MX23_PAD_GPMI_D02__GPMI_D02 + MX23_PAD_GPMI_D03__GPMI_D03 + MX23_PAD_GPMI_D04__GPMI_D04 + MX23_PAD_GPMI_D05__GPMI_D05 + MX23_PAD_GPMI_D06__GPMI_D06 + MX23_PAD_GPMI_D07__GPMI_D07 + MX23_PAD_GPMI_CLE__GPMI_CLE + MX23_PAD_GPMI_ALE__GPMI_ALE + MX23_PAD_GPMI_RDY0__GPMI_RDY0 + MX23_PAD_GPMI_RDY1__GPMI_RDY1 + MX23_PAD_GPMI_WPN__GPMI_WPN + MX23_PAD_GPMI_WRN__GPMI_WRN + MX23_PAD_GPMI_RDN__GPMI_RDN + MX23_PAD_GPMI_CE1N__GPMI_CE1N + MX23_PAD_GPMI_CE0N__GPMI_CE0N >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -197,9 +198,9 @@ gpmi_pins_fixup: gpmi-pins-fixup { fsl,pinmux-ids = < - 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */ - 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */ - 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */ + MX23_PAD_GPMI_WPN__GPMI_WPN + MX23_PAD_GPMI_WRN__GPMI_WRN + MX23_PAD_GPMI_RDN__GPMI_RDN >; fsl,drive-strength = <2>; }; @@ -207,12 +208,12 @@ mmc0_4bit_pins_a: mmc0-4bit@0 { reg = <0>; fsl,pinmux-ids = < - 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */ - 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */ - 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ - 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ - 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ - 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ + MX23_PAD_SSP1_DATA0__SSP1_DATA0 + MX23_PAD_SSP1_DATA1__SSP1_DATA1 + MX23_PAD_SSP1_DATA2__SSP1_DATA2 + MX23_PAD_SSP1_DATA3__SSP1_DATA3 + MX23_PAD_SSP1_CMD__SSP1_CMD + MX23_PAD_SSP1_SCK__SSP1_SCK >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -222,17 +223,17 @@ mmc0_8bit_pins_a: mmc0-8bit@0 { reg = <0>; fsl,pinmux-ids = < - 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */ - 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */ - 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ - 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ - 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */ - 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */ - 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */ - 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */ - 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ - 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ - 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ + MX23_PAD_SSP1_DATA0__SSP1_DATA0 + MX23_PAD_SSP1_DATA1__SSP1_DATA1 + MX23_PAD_SSP1_DATA2__SSP1_DATA2 + MX23_PAD_SSP1_DATA3__SSP1_DATA3 + MX23_PAD_GPMI_D08__SSP1_DATA4 + MX23_PAD_GPMI_D09__SSP1_DATA5 + MX23_PAD_GPMI_D10__SSP1_DATA6 + MX23_PAD_GPMI_D11__SSP1_DATA7 + MX23_PAD_SSP1_CMD__SSP1_CMD + MX23_PAD_SSP1_DETECT__SSP1_DETECT + MX23_PAD_SSP1_SCK__SSP1_SCK >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -241,8 +242,8 @@ mmc0_pins_fixup: mmc0-pins-fixup { fsl,pinmux-ids = < - 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ - 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ + MX23_PAD_SSP1_DETECT__SSP1_DETECT + MX23_PAD_SSP1_SCK__SSP1_SCK >; fsl,pull-up = <0>; }; @@ -250,7 +251,7 @@ pwm2_pins_a: pwm2@0 { reg = <0>; fsl,pinmux-ids = < - 0x11c0 /* MX23_PAD_PWM2__PWM2 */ + MX23_PAD_PWM2__PWM2 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -260,34 +261,34 @@ lcdif_24bit_pins_a: lcdif-24bit@0 { reg = <0>; fsl,pinmux-ids = < - 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */ - 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */ - 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */ - 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */ - 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */ - 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */ - 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */ - 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */ - 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */ - 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */ - 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */ - 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */ - 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */ - 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */ - 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */ - 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */ - 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */ - 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */ - 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */ - 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */ - 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */ - 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */ - 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */ - 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */ - 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */ - 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */ - 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */ - 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */ + MX23_PAD_LCD_D00__LCD_D00 + MX23_PAD_LCD_D01__LCD_D01 + MX23_PAD_LCD_D02__LCD_D02 + MX23_PAD_LCD_D03__LCD_D03 + MX23_PAD_LCD_D04__LCD_D04 + MX23_PAD_LCD_D05__LCD_D05 + MX23_PAD_LCD_D06__LCD_D06 + MX23_PAD_LCD_D07__LCD_D07 + MX23_PAD_LCD_D08__LCD_D08 + MX23_PAD_LCD_D09__LCD_D09 + MX23_PAD_LCD_D10__LCD_D10 + MX23_PAD_LCD_D11__LCD_D11 + MX23_PAD_LCD_D12__LCD_D12 + MX23_PAD_LCD_D13__LCD_D13 + MX23_PAD_LCD_D14__LCD_D14 + MX23_PAD_LCD_D15__LCD_D15 + MX23_PAD_LCD_D16__LCD_D16 + MX23_PAD_LCD_D17__LCD_D17 + MX23_PAD_GPMI_D08__LCD_D18 + MX23_PAD_GPMI_D09__LCD_D19 + MX23_PAD_GPMI_D10__LCD_D20 + MX23_PAD_GPMI_D11__LCD_D21 + MX23_PAD_GPMI_D12__LCD_D22 + MX23_PAD_GPMI_D13__LCD_D23 + MX23_PAD_LCD_DOTCK__LCD_DOTCK + MX23_PAD_LCD_ENABLE__LCD_ENABLE + MX23_PAD_LCD_HSYNC__LCD_HSYNC + MX23_PAD_LCD_VSYNC__LCD_VSYNC >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -297,10 +298,10 @@ spi2_pins_a: spi2@0 { reg = <0>; fsl,pinmux-ids = < - 0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */ - 0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */ - 0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */ - 0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */ + MX23_PAD_GPMI_WRN__SSP2_SCK + MX23_PAD_GPMI_RDY1__SSP2_CMD + MX23_PAD_GPMI_D00__SSP2_DATA0 + MX23_PAD_GPMI_D03__SSP2_DATA3 >; fsl,drive-strength = <1>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts index 7eb075876c4c..7198fe3798c6 100644 --- a/arch/arm/boot/dts/imx28-apf28.dts +++ b/arch/arm/boot/dts/imx28-apf28.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "imx28.dtsi" +#include "imx28.dtsi" / { model = "Armadeus Systems APF28 module"; diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index b602494c152b..7d923cc56a93 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -10,7 +10,7 @@ */ /* APF28Dev is a docking board for the APF28 SOM */ -/include/ "imx28-apf28.dts" +#include "imx28-apf28.dts" / { model = "Armadeus Systems APF28Dev docking/development board"; @@ -41,13 +41,13 @@ hog_pins_apf28dev: hog@0 { reg = <0>; fsl,pinmux-ids = < - 0x1103 /* MX28_PAD_LCD_D16__GPIO_1_16 */ - 0x1113 /* MX28_PAD_LCD_D17__GPIO_1_17 */ - 0x1123 /* MX28_PAD_LCD_D18__GPIO_1_18 */ - 0x1133 /* MX28_PAD_LCD_D19__GPIO_1_19 */ - 0x1143 /* MX28_PAD_LCD_D20__GPIO_1_20 */ - 0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */ - 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ + MX28_PAD_LCD_D16__GPIO_1_16 + MX28_PAD_LCD_D17__GPIO_1_17 + MX28_PAD_LCD_D18__GPIO_1_18 + MX28_PAD_LCD_D19__GPIO_1_19 + MX28_PAD_LCD_D20__GPIO_1_20 + MX28_PAD_LCD_D21__GPIO_1_21 + MX28_PAD_LCD_D22__GPIO_1_22 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -57,10 +57,10 @@ lcdif_pins_apf28dev: lcdif-apf28dev@0 { reg = <0>; fsl,pinmux-ids = < - 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ - 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ - 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ - 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index 0e7fed47bd8d..cb19dc1e7743 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -1,5 +1,5 @@ /dts-v1/; -/include/ "imx28.dtsi" +#include "imx28.dtsi" / { model = "Bluegiga APX4 Development Kit"; @@ -40,13 +40,13 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ - 0x0153 /* MX28_PAD_GPMI_RDY1__GPIO_0_21 */ - 0x2123 /* MX28_PAD_SSP2_MISO__GPIO_2_18 */ - 0x2131 /* MX28_PAD_SSP2_SS0__GPIO_2_19 */ - 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ - 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ - 0x4143 /* MX28_PAD_JTAG_RTCK__GPIO_4_20 */ + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_RDY1__GPIO_0_21 + MX28_PAD_SSP2_MISO__GPIO_2_18 + MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */ + MX28_PAD_PWM3__GPIO_3_28 + MX28_PAD_LCD_RESET__GPIO_3_30 + MX28_PAD_JTAG_RTCK__GPIO_4_20 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -56,10 +56,10 @@ lcdif_pins_apx4: lcdif-apx4@0 { reg = <0>; fsl,pinmux-ids = < - 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ - 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ - 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ - 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -69,12 +69,12 @@ mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { reg = <0>; fsl,pinmux-ids = < - 0x2041 /* MX28_PAD_SSP0_DATA4__SSP2_D0 */ - 0x2051 /* MX28_PAD_SSP0_DATA5__SSP2_D3 */ - 0x2061 /* MX28_PAD_SSP0_DATA6__SSP2_CMD */ - 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ - 0x2141 /* MX28_PAD_SSP2_SS1__SSP2_D1 */ - 0x2151 /* MX28_PAD_SSP2_SS2__SSP2_D2 */ + MX28_PAD_SSP0_DATA4__SSP2_D0 + MX28_PAD_SSP0_DATA5__SSP2_D3 + MX28_PAD_SSP0_DATA6__SSP2_CMD + MX28_PAD_SSP0_DATA7__SSP2_SCK + MX28_PAD_SSP2_SS1__SSP2_D1 + MX28_PAD_SSP2_SS2__SSP2_D2 >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -83,7 +83,7 @@ mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 { fsl,pinmux-ids = < - 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ + MX28_PAD_SSP0_DATA7__SSP2_SCK >; fsl,drive-strength = <2>; fsl,pull-up = <0>; diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index 1ec8c94bbac9..2474207951fb 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "imx28.dtsi" +#include "imx28.dtsi" / { model = "Crystalfontz CFA-10036 Board"; @@ -26,7 +26,7 @@ ssd1306_cfa10036: ssd1306-10036@0 { reg = <0>; fsl,pinmux-ids = < - 0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */ + MX28_PAD_SSP0_DATA7__GPIO_2_7 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -36,7 +36,7 @@ led_pins_cfa10036: leds-10036@0 { reg = <0>; fsl,pinmux-ids = < - 0x3043 /* MX28_PAD_AUART1_RX__GPIO_3_4 */ + MX28_PAD_AUART1_RX__GPIO_3_4 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -46,7 +46,7 @@ usb0_otg_cfa10036: otg-10036@0 { reg = <0>; fsl,pinmux-ids = < - 0x0142 /* MX28_PAD_GPMI_READY0__USB0_ID */ + MX28_PAD_GPMI_RDY0__USB0_ID >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts index 182b99fe35f3..42a9a99880af 100644 --- a/arch/arm/boot/dts/imx28-cfa10037.dts +++ b/arch/arm/boot/dts/imx28-cfa10037.dts @@ -13,7 +13,7 @@ * The CFA-10049 is an expansion board for the CFA-10036 module, thus we * need to include the CFA-10036 DTS. */ -/include/ "imx28-cfa10036.dts" +#include "imx28-cfa10036.dts" / { model = "Crystalfontz CFA-10037 Board"; @@ -25,7 +25,7 @@ usb_pins_cfa10037: usb-10037@0 { reg = <0>; fsl,pinmux-ids = < - 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ + MX28_PAD_GPMI_D07__GPIO_0_7 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -35,7 +35,7 @@ mac0_pins_cfa10037: mac0-10037@0 { reg = <0>; fsl,pinmux-ids = < - 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ + MX28_PAD_SSP2_SS2__GPIO_2_21 >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 06e4cfaf7dd2..9ee2566bf4cb 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -13,7 +13,7 @@ * The CFA-10049 is an expansion board for the CFA-10036 module, thus we * need to include the CFA-10036 DTS. */ -/include/ "imx28-cfa10036.dts" +#include "imx28-cfa10036.dts" / { model = "Crystalfontz CFA-10049 Board"; @@ -25,7 +25,7 @@ usb_pins_cfa10049: usb-10049@0 { reg = <0>; fsl,pinmux-ids = < - 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ + MX28_PAD_GPMI_D07__GPIO_0_7 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -35,8 +35,8 @@ i2cmux_pins_cfa10049: i2cmux-10049@0 { reg = <0>; fsl,pinmux-ids = < - 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ - 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */ + MX28_PAD_LCD_D22__GPIO_1_22 + MX28_PAD_LCD_D23__GPIO_1_23 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -46,7 +46,7 @@ mac0_pins_cfa10049: mac0-10049@0 { reg = <0>; fsl,pinmux-ids = < - 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ + MX28_PAD_SSP2_SS2__GPIO_2_21 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -56,7 +56,7 @@ pca_pins_cfa10049: pca-10049@0 { reg = <0>; fsl,pinmux-ids = < - 0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */ + MX28_PAD_SSP2_SS0__GPIO_2_19 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -66,8 +66,8 @@ rotary_pins_cfa10049: rotary-10049@0 { reg = <0>; fsl,pinmux-ids = < - 0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */ - 0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */ + MX28_PAD_I2C0_SCL__GPIO_3_24 + MX28_PAD_I2C0_SDA__GPIO_3_25 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -77,7 +77,7 @@ rotary_btn_pins_cfa10049: rotary-btn-10049@0 { reg = <0>; fsl,pinmux-ids = < - 0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */ + MX28_PAD_SAIF1_SDATA0__GPIO_3_26 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -87,10 +87,10 @@ spi2_pins_cfa10049: spi2-cfa10049@0 { reg = <0>; fsl,pinmux-ids = < - 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ - 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ - 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ - 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ + MX28_PAD_SSP2_SCK__GPIO_2_16 + MX28_PAD_SSP2_MOSI__GPIO_2_17 + MX28_PAD_SSP2_MISO__GPIO_2_18 + MX28_PAD_AUART1_TX__GPIO_3_5 >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -100,11 +100,11 @@ spi3_pins_cfa10049: spi3-cfa10049@0 { reg = <0>; fsl,pinmux-ids = < - 0x0183 /* MX28_PAD_GPMI_RDN__GPIO_0_24 */ - 0x01c3 /* MX28_PAD_GPMI_RESETN__GPIO_0_28 */ - 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ - 0x01a3 /* MX28_PAD_GPMI_ALE__GPIO_0_26 */ - 0x01b3 /* MX28_PAD_GPMI_CLE__GPIO_0_27 */ + MX28_PAD_GPMI_RDN__GPIO_0_24 + MX28_PAD_GPMI_RESETN__GPIO_0_28 + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_ALE__GPIO_0_26 + MX28_PAD_GPMI_CLE__GPIO_0_27 >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -114,24 +114,24 @@ lcdif_18bit_pins_cfa10049: lcdif-18bit@0 { reg = <0>; fsl,pinmux-ids = < - 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ - 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ - 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ - 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ - 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ - 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ - 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ - 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ - 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ - 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ - 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ - 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ - 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ - 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ - 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ - 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ - 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ - 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -141,10 +141,10 @@ lcdif_pins_cfa10049: lcdif-evk@0 { reg = <0>; fsl,pinmux-ids = < - 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ - 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ - 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ - 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -154,7 +154,7 @@ lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 { reg = <0>; fsl,pinmux-ids = < - 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + MX28_PAD_LCD_RESET__GPIO_3_30 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -164,7 +164,7 @@ w1_gpio_pins: w1-gpio@0 { reg = <0>; fsl,pinmux-ids = < - 0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */ + MX28_PAD_LCD_D21__GPIO_1_21 >; fsl,drive-strength = <1>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts index 171bcbe1ec4b..8b262a26f50c 100644 --- a/arch/arm/boot/dts/imx28-cfa10055.dts +++ b/arch/arm/boot/dts/imx28-cfa10055.dts @@ -14,7 +14,7 @@ * The CFA-10055 is an expansion board for the CFA-10036 module and * CFA-10037, thus we need to include the CFA-10037 DTS. */ -/include/ "imx28-cfa10037.dts" +#include "imx28-cfa10037.dts" / { model = "Crystalfontz CFA-10055 Board"; @@ -26,10 +26,10 @@ spi2_pins_cfa10055: spi2-cfa10055@0 { reg = <0>; fsl,pinmux-ids = < - 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ - 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ - 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ - 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ + MX28_PAD_SSP2_SCK__GPIO_2_16 + MX28_PAD_SSP2_MOSI__GPIO_2_17 + MX28_PAD_SSP2_MISO__GPIO_2_18 + MX28_PAD_AUART1_TX__GPIO_3_5 >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -39,24 +39,24 @@ lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { reg = <0>; fsl,pinmux-ids = < - 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ - 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ - 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ - 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ - 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ - 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ - 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ - 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ - 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ - 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ - 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ - 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ - 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ - 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ - 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ - 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ - 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ - 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -66,10 +66,10 @@ lcdif_pins_cfa10055: lcdif-evk@0 { reg = <0>; fsl,pinmux-ids = < - 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ - 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ - 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ - 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -79,7 +79,7 @@ lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 { reg = <0>; fsl,pinmux-ids = < - 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + MX28_PAD_LCD_RESET__GPIO_3_30 >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts index b45dd0e4ee57..f65199878122 100644 --- a/arch/arm/boot/dts/imx28-cfa10056.dts +++ b/arch/arm/boot/dts/imx28-cfa10056.dts @@ -13,7 +13,7 @@ * The CFA-10055 is an expansion board for the CFA-10036 module and * CFA-10037, thus we need to include the CFA-10037 DTS. */ -/include/ "imx28-cfa10037.dts" +#include "imx28-cfa10037.dts" / { model = "Crystalfontz CFA-10056 Board"; @@ -25,10 +25,10 @@ spi2_pins_cfa10056: spi2-cfa10056@0 { reg = <0>; fsl,pinmux-ids = < - 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ - 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ - 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ - 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ + MX28_PAD_SSP2_SCK__GPIO_2_16 + MX28_PAD_SSP2_MOSI__GPIO_2_17 + MX28_PAD_SSP2_MISO__GPIO_2_18 + MX28_PAD_AUART1_TX__GPIO_3_5 >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -38,10 +38,10 @@ lcdif_pins_cfa10056: lcdif-10056@0 { reg = <0>; fsl,pinmux-ids = < - 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ - 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ - 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ - 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -51,7 +51,7 @@ lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 { reg = <0>; fsl,pinmux-ids = < - 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + MX28_PAD_LCD_RESET__GPIO_3_30 >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts index 0333c0532f28..76430ca3e53d 100644 --- a/arch/arm/boot/dts/imx28-cfa10057.dts +++ b/arch/arm/boot/dts/imx28-cfa10057.dts @@ -14,7 +14,7 @@ * The CFA-10057 is an expansion board for the CFA-10036 module, thus we * need to include the CFA-10036 DTS. */ -/include/ "imx28-cfa10036.dts" +#include "imx28-cfa10036.dts" / { model = "Crystalfontz CFA-10057 Board"; @@ -26,7 +26,7 @@ usb_pins_cfa10057: usb-10057@0 { reg = <0>; fsl,pinmux-ids = < - 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ + MX28_PAD_GPMI_D07__GPIO_0_7 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -36,24 +36,24 @@ lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { reg = <0>; fsl,pinmux-ids = < - 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ - 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ - 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ - 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ - 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ - 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ - 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ - 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ - 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ - 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ - 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ - 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ - 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ - 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ - 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ - 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ - 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ - 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -63,10 +63,10 @@ lcdif_pins_cfa10057: lcdif-evk@0 { reg = <0>; fsl,pinmux-ids = < - 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ - 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ - 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ - 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts index 64c64c55a82a..502be77d32b8 100644 --- a/arch/arm/boot/dts/imx28-cfa10058.dts +++ b/arch/arm/boot/dts/imx28-cfa10058.dts @@ -14,7 +14,7 @@ * The CFA-10058 is an expansion board for the CFA-10036 module, thus we * need to include the CFA-10036 DTS. */ -/include/ "imx28-cfa10036.dts" +#include "imx28-cfa10036.dts" / { model = "Crystalfontz CFA-10058 Board"; @@ -26,7 +26,7 @@ usb_pins_cfa10058: usb-10058@0 { reg = <0>; fsl,pinmux-ids = < - 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ + MX28_PAD_GPMI_D07__GPIO_0_7 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -36,10 +36,10 @@ lcdif_pins_cfa10058: lcdif-10058@0 { reg = <0>; fsl,pinmux-ids = < - 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ - 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ - 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ - 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 5f9c0a0dcc5a..023eaf775487 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "imx28.dtsi" +#include "imx28.dtsi" / { model = "Freescale i.MX28 Evaluation Kit"; @@ -70,14 +70,14 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ - 0x20f3 /* MX28_PAD_SSP1_DATA3__GPIO_2_15 */ - 0x40d3 /* MX28_PAD_ENET0_RX_CLK__GPIO_4_13 */ - 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */ - 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ - 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ - 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */ - 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */ + MX28_PAD_SSP1_CMD__GPIO_2_13 + MX28_PAD_SSP1_DATA3__GPIO_2_15 + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 + MX28_PAD_SSP1_SCK__GPIO_2_12 + MX28_PAD_PWM3__GPIO_3_28 + MX28_PAD_LCD_RESET__GPIO_3_30 + MX28_PAD_AUART2_RX__GPIO_3_8 + MX28_PAD_AUART2_TX__GPIO_3_9 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -87,7 +87,7 @@ led_pin_gpio3_5: led_gpio3_5@0 { reg = <0>; fsl,pinmux-ids = < - 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ + MX28_PAD_AUART1_TX__GPIO_3_5 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -97,8 +97,8 @@ gpmi_pins_evk: gpmi-nand-evk@0 { reg = <0>; fsl,pinmux-ids = < - 0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */ - 0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */ + MX28_PAD_GPMI_CE1N__GPMI_CE1N + MX28_PAD_GPMI_RDY1__GPMI_READY1 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -108,10 +108,10 @@ lcdif_pins_evk: lcdif-evk@0 { reg = <0>; fsl,pinmux-ids = < - 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ - 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ - 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ - 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 0d322a2bebaf..9f3271dcc7d9 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "imx28.dtsi" +#include "imx28.dtsi" / { model = "DENX M28EVK"; @@ -92,11 +92,11 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ - 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ - 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ - 0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */ - 0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */ + MX28_PAD_PWM3__GPIO_3_28 + MX28_PAD_AUART2_CTS__GPIO_3_10 + MX28_PAD_AUART2_RTS__GPIO_3_11 + MX28_PAD_AUART3_RX__GPIO_3_12 + MX28_PAD_AUART3_TX__GPIO_3_13 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -106,8 +106,8 @@ lcdif_pins_m28: lcdif-m28@0 { reg = <0>; fsl,pinmux-ids = < - 0x11e0 /* MX28_PAD_LCD_DOTCLK__LCD_DOTCLK */ - 0x11f0 /* MX28_PAD_LCD_ENABLE__LCD_ENABLE */ + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK + MX28_PAD_LCD_ENABLE__LCD_ENABLE >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts index 6c6a5442800a..4613522a1cbe 100644 --- a/arch/arm/boot/dts/imx28-sps1.dts +++ b/arch/arm/boot/dts/imx28-sps1.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "imx28.dtsi" +#include "imx28.dtsi" / { model = "SchulerControl GmbH, SC SPS 1"; @@ -29,9 +29,9 @@ hog_pins_a: hog-gpios@0 { reg = <0>; fsl,pinmux-ids = < - 0x0003 /* MX28_PAD_GPMI_D00__GPIO_0_0 */ - 0x0033 /* MX28_PAD_GPMI_D03__GPIO_0_3 */ - 0x0063 /* MX28_PAD_GPMI_D06__GPIO_0_6 */ + MX28_PAD_GPMI_D00__GPIO_0_0 + MX28_PAD_GPMI_D03__GPIO_0_3 + MX28_PAD_GPMI_D06__GPIO_0_6 >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 37be532f0055..3dbe1d7da467 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -1,5 +1,5 @@ /dts-v1/; -/include/ "imx28.dtsi" +#include "imx28.dtsi" / { model = "Ka-Ro electronics TX28 module"; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index c596b6da3872..1f16193f3da9 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -9,7 +9,8 @@ * http://www.gnu.org/copyleft/gpl.html */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include "imx28-pinfunc.h" / { interrupt-parent = <&icoll>; @@ -207,8 +208,8 @@ duart_pins_a: duart@0 { reg = <0>; fsl,pinmux-ids = < - 0x3102 /* MX28_PAD_PWM0__DUART_RX */ - 0x3112 /* MX28_PAD_PWM1__DUART_TX */ + MX28_PAD_PWM0__DUART_RX + MX28_PAD_PWM1__DUART_TX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -218,8 +219,8 @@ duart_pins_b: duart@1 { reg = <1>; fsl,pinmux-ids = < - 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ - 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ + MX28_PAD_AUART0_CTS__DUART_RX + MX28_PAD_AUART0_RTS__DUART_TX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -229,10 +230,10 @@ duart_4pins_a: duart-4pins@0 { reg = <0>; fsl,pinmux-ids = < - 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ - 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ - 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */ - 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */ + MX28_PAD_AUART0_CTS__DUART_RX + MX28_PAD_AUART0_RTS__DUART_TX + MX28_PAD_AUART0_RX__DUART_CTS + MX28_PAD_AUART0_TX__DUART_RTS >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -242,21 +243,21 @@ gpmi_pins_a: gpmi-nand@0 { reg = <0>; fsl,pinmux-ids = < - 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */ - 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */ - 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */ - 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */ - 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */ - 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */ - 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */ - 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */ - 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */ - 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */ - 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ - 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ - 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */ - 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */ - 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ + MX28_PAD_GPMI_D00__GPMI_D0 + MX28_PAD_GPMI_D01__GPMI_D1 + MX28_PAD_GPMI_D02__GPMI_D2 + MX28_PAD_GPMI_D03__GPMI_D3 + MX28_PAD_GPMI_D04__GPMI_D4 + MX28_PAD_GPMI_D05__GPMI_D5 + MX28_PAD_GPMI_D06__GPMI_D6 + MX28_PAD_GPMI_D07__GPMI_D7 + MX28_PAD_GPMI_CE0N__GPMI_CE0N + MX28_PAD_GPMI_RDY0__GPMI_READY0 + MX28_PAD_GPMI_RDN__GPMI_RDN + MX28_PAD_GPMI_WRN__GPMI_WRN + MX28_PAD_GPMI_ALE__GPMI_ALE + MX28_PAD_GPMI_CLE__GPMI_CLE + MX28_PAD_GPMI_RESETN__GPMI_RESETN >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -265,9 +266,9 @@ gpmi_status_cfg: gpmi-status-cfg { fsl,pinmux-ids = < - 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ - 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ - 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ + MX28_PAD_GPMI_RDN__GPMI_RDN + MX28_PAD_GPMI_WRN__GPMI_WRN + MX28_PAD_GPMI_RESETN__GPMI_RESETN >; fsl,drive-strength = <2>; }; @@ -275,10 +276,10 @@ auart0_pins_a: auart0@0 { reg = <0>; fsl,pinmux-ids = < - 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ - 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ - 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */ - 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */ + MX28_PAD_AUART0_RX__AUART0_RX + MX28_PAD_AUART0_TX__AUART0_TX + MX28_PAD_AUART0_CTS__AUART0_CTS + MX28_PAD_AUART0_RTS__AUART0_RTS >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -288,8 +289,8 @@ auart0_2pins_a: auart0-2pins@0 { reg = <0>; fsl,pinmux-ids = < - 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ - 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ + MX28_PAD_AUART0_RX__AUART0_RX + MX28_PAD_AUART0_TX__AUART0_TX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -299,10 +300,10 @@ auart1_pins_a: auart1@0 { reg = <0>; fsl,pinmux-ids = < - 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ - 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ - 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */ - 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */ + MX28_PAD_AUART1_RX__AUART1_RX + MX28_PAD_AUART1_TX__AUART1_TX + MX28_PAD_AUART1_CTS__AUART1_CTS + MX28_PAD_AUART1_RTS__AUART1_RTS >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -312,8 +313,8 @@ auart1_2pins_a: auart1-2pins@0 { reg = <0>; fsl,pinmux-ids = < - 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ - 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ + MX28_PAD_AUART1_RX__AUART1_RX + MX28_PAD_AUART1_TX__AUART1_TX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -323,8 +324,8 @@ auart2_2pins_a: auart2-2pins@0 { reg = <0>; fsl,pinmux-ids = < - 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */ - 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */ + MX28_PAD_SSP2_SCK__AUART2_RX + MX28_PAD_SSP2_MOSI__AUART2_TX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -334,8 +335,8 @@ auart2_2pins_b: auart2-2pins@1 { reg = <1>; fsl,pinmux-ids = < - 0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */ - 0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */ + MX28_PAD_AUART2_RX__AUART2_RX + MX28_PAD_AUART2_TX__AUART2_TX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -345,10 +346,10 @@ auart3_pins_a: auart3@0 { reg = <0>; fsl,pinmux-ids = < - 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ - 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ - 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */ - 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */ + MX28_PAD_AUART3_RX__AUART3_RX + MX28_PAD_AUART3_TX__AUART3_TX + MX28_PAD_AUART3_CTS__AUART3_CTS + MX28_PAD_AUART3_RTS__AUART3_RTS >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -358,8 +359,8 @@ auart3_2pins_a: auart3-2pins@0 { reg = <0>; fsl,pinmux-ids = < - 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */ - 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */ + MX28_PAD_SSP2_MISO__AUART3_RX + MX28_PAD_SSP2_SS0__AUART3_TX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -369,8 +370,8 @@ auart3_2pins_b: auart3-2pins@1 { reg = <1>; fsl,pinmux-ids = < - 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ - 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ + MX28_PAD_AUART3_RX__AUART3_RX + MX28_PAD_AUART3_TX__AUART3_TX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -380,8 +381,8 @@ auart4_2pins_a: auart4@0 { reg = <0>; fsl,pinmux-ids = < - 0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */ - 0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */ + MX28_PAD_SSP3_SCK__AUART4_TX + MX28_PAD_SSP3_MOSI__AUART4_RX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -391,15 +392,15 @@ mac0_pins_a: mac0@0 { reg = <0>; fsl,pinmux-ids = < - 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */ - 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */ - 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */ - 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */ - 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */ - 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */ - 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */ - 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */ - 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */ + MX28_PAD_ENET0_MDC__ENET0_MDC + MX28_PAD_ENET0_MDIO__ENET0_MDIO + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN + MX28_PAD_ENET0_RXD0__ENET0_RXD0 + MX28_PAD_ENET0_RXD1__ENET0_RXD1 + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN + MX28_PAD_ENET0_TXD0__ENET0_TXD0 + MX28_PAD_ENET0_TXD1__ENET0_TXD1 + MX28_PAD_ENET_CLK__CLKCTRL_ENET >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -409,12 +410,12 @@ mac1_pins_a: mac1@0 { reg = <0>; fsl,pinmux-ids = < - 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */ - 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */ - 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */ - 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */ - 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */ - 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */ + MX28_PAD_ENET0_CRS__ENET1_RX_EN + MX28_PAD_ENET0_RXD2__ENET1_RXD0 + MX28_PAD_ENET0_RXD3__ENET1_RXD1 + MX28_PAD_ENET0_COL__ENET1_TX_EN + MX28_PAD_ENET0_TXD2__ENET1_TXD0 + MX28_PAD_ENET0_TXD3__ENET1_TXD1 >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -424,17 +425,17 @@ mmc0_8bit_pins_a: mmc0-8bit@0 { reg = <0>; fsl,pinmux-ids = < - 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ - 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ - 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ - 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ - 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */ - 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */ - 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */ - 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */ - 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ - 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ - 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ + MX28_PAD_SSP0_DATA0__SSP0_D0 + MX28_PAD_SSP0_DATA1__SSP0_D1 + MX28_PAD_SSP0_DATA2__SSP0_D2 + MX28_PAD_SSP0_DATA3__SSP0_D3 + MX28_PAD_SSP0_DATA4__SSP0_D4 + MX28_PAD_SSP0_DATA5__SSP0_D5 + MX28_PAD_SSP0_DATA6__SSP0_D6 + MX28_PAD_SSP0_DATA7__SSP0_D7 + MX28_PAD_SSP0_CMD__SSP0_CMD + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT + MX28_PAD_SSP0_SCK__SSP0_SCK >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -444,13 +445,13 @@ mmc0_4bit_pins_a: mmc0-4bit@0 { reg = <0>; fsl,pinmux-ids = < - 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ - 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ - 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ - 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ - 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ - 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ - 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ + MX28_PAD_SSP0_DATA0__SSP0_D0 + MX28_PAD_SSP0_DATA1__SSP0_D1 + MX28_PAD_SSP0_DATA2__SSP0_D2 + MX28_PAD_SSP0_DATA3__SSP0_D3 + MX28_PAD_SSP0_CMD__SSP0_CMD + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT + MX28_PAD_SSP0_SCK__SSP0_SCK >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -459,14 +460,14 @@ mmc0_cd_cfg: mmc0-cd-cfg { fsl,pinmux-ids = < - 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT >; fsl,pull-up = <0>; }; mmc0_sck_cfg: mmc0-sck-cfg { fsl,pinmux-ids = < - 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ + MX28_PAD_SSP0_SCK__SSP0_SCK >; fsl,drive-strength = <2>; fsl,pull-up = <0>; @@ -475,8 +476,8 @@ i2c0_pins_a: i2c0@0 { reg = <0>; fsl,pinmux-ids = < - 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */ - 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */ + MX28_PAD_I2C0_SCL__I2C0_SCL + MX28_PAD_I2C0_SDA__I2C0_SDA >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -486,8 +487,8 @@ i2c0_pins_b: i2c0@1 { reg = <1>; fsl,pinmux-ids = < - 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */ - 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */ + MX28_PAD_AUART0_RX__I2C0_SCL + MX28_PAD_AUART0_TX__I2C0_SDA >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -497,8 +498,8 @@ i2c1_pins_a: i2c1@0 { reg = <0>; fsl,pinmux-ids = < - 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */ - 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */ + MX28_PAD_PWM0__I2C1_SCL + MX28_PAD_PWM1__I2C1_SDA >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -508,10 +509,10 @@ saif0_pins_a: saif0@0 { reg = <0>; fsl,pinmux-ids = < - 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */ - 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ - 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ - 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ + MX28_PAD_SAIF0_MCLK__SAIF0_MCLK + MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK + MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK + MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 >; fsl,drive-strength = <2>; fsl,voltage = <1>; @@ -521,9 +522,9 @@ saif0_pins_b: saif0@1 { reg = <1>; fsl,pinmux-ids = < - 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ - 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ - 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ + MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK + MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK + MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 >; fsl,drive-strength = <2>; fsl,voltage = <1>; @@ -533,7 +534,7 @@ saif1_pins_a: saif1@0 { reg = <0>; fsl,pinmux-ids = < - 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */ + MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 >; fsl,drive-strength = <2>; fsl,voltage = <1>; @@ -543,7 +544,7 @@ pwm0_pins_a: pwm0@0 { reg = <0>; fsl,pinmux-ids = < - 0x3100 /* MX28_PAD_PWM0__PWM_0 */ + MX28_PAD_PWM0__PWM_0 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -553,7 +554,7 @@ pwm2_pins_a: pwm2@0 { reg = <0>; fsl,pinmux-ids = < - 0x3120 /* MX28_PAD_PWM2__PWM_2 */ + MX28_PAD_PWM2__PWM_2 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -563,7 +564,7 @@ pwm3_pins_a: pwm3@0 { reg = <0>; fsl,pinmux-ids = < - 0x31c0 /* MX28_PAD_PWM3__PWM_3 */ + MX28_PAD_PWM3__PWM_3 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -573,7 +574,7 @@ pwm3_pins_b: pwm3@1 { reg = <1>; fsl,pinmux-ids = < - 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */ + MX28_PAD_SAIF0_MCLK__PWM_3 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -583,7 +584,7 @@ pwm4_pins_a: pwm4@0 { reg = <0>; fsl,pinmux-ids = < - 0x31d0 /* MX28_PAD_PWM4__PWM_4 */ + MX28_PAD_PWM4__PWM_4 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -593,30 +594,30 @@ lcdif_24bit_pins_a: lcdif-24bit@0 { reg = <0>; fsl,pinmux-ids = < - 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ - 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ - 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ - 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ - 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ - 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ - 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ - 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ - 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ - 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ - 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ - 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ - 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ - 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ - 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ - 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ - 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ - 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ - 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */ - 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */ - 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */ - 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */ - 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */ - 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */ + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + MX28_PAD_LCD_D18__LCD_D18 + MX28_PAD_LCD_D19__LCD_D19 + MX28_PAD_LCD_D20__LCD_D20 + MX28_PAD_LCD_D21__LCD_D21 + MX28_PAD_LCD_D22__LCD_D22 + MX28_PAD_LCD_D23__LCD_D23 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -626,22 +627,22 @@ lcdif_16bit_pins_a: lcdif-16bit@0 { reg = <0>; fsl,pinmux-ids = < - 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ - 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ - 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ - 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ - 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ - 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ - 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ - 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ - 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ - 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ - 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ - 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ - 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ - 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ - 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ - 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -651,10 +652,10 @@ lcdif_sync_pins_a: lcdif-sync@0 { reg = <0>; fsl,pinmux-ids = < - 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ - 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ - 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ - 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -664,8 +665,8 @@ can0_pins_a: can0@0 { reg = <0>; fsl,pinmux-ids = < - 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */ - 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */ + MX28_PAD_GPMI_RDY2__CAN0_TX + MX28_PAD_GPMI_RDY3__CAN0_RX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -675,8 +676,8 @@ can1_pins_a: can1@0 { reg = <0>; fsl,pinmux-ids = < - 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */ - 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */ + MX28_PAD_GPMI_CE2N__CAN1_TX + MX28_PAD_GPMI_CE3N__CAN1_RX >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -686,10 +687,10 @@ spi2_pins_a: spi2@0 { reg = <0>; fsl,pinmux-ids = < - 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */ - 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */ - 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */ - 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */ + MX28_PAD_SSP2_SCK__SSP2_SCK + MX28_PAD_SSP2_MOSI__SSP2_CMD + MX28_PAD_SSP2_MISO__SSP2_D0 + MX28_PAD_SSP2_SS0__SSP2_D3 >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -699,12 +700,12 @@ spi3_pins_a: spi3@0 { reg = <0>; fsl,pinmux-ids = < - 0x3082 /* MX28_PAD_AUART2_RX__SSP3_D4 */ - 0x3092 /* MX28_PAD_AUART2_TX__SSP3_D5 */ - 0x2180 /* MX28_PAD_SSP3_SCK__SSP3_SCK */ - 0x2190 /* MX28_PAD_SSP3_MOSI__SSP3_CMD */ - 0x21A0 /* MX28_PAD_SSP3_MISO__SSP3_D0 */ - 0x21B0 /* MX28_PAD_SSP3_SS0__SSP3_D3 */ + MX28_PAD_AUART2_RX__SSP3_D4 + MX28_PAD_AUART2_TX__SSP3_D5 + MX28_PAD_SSP3_SCK__SSP3_SCK + MX28_PAD_SSP3_MOSI__SSP3_CMD + MX28_PAD_SSP3_MISO__SSP3_D0 + MX28_PAD_SSP3_SS0__SSP3_D3 >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -714,7 +715,7 @@ usbphy0_pins_a: usbphy0@0 { reg = <0>; fsl,pinmux-ids = < - 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */ + MX28_PAD_SSP2_SS2__USB0_OVERCURRENT >; fsl,drive-strength = <2>; fsl,voltage = <1>; @@ -724,7 +725,7 @@ usbphy0_pins_b: usbphy0@1 { reg = <1>; fsl,pinmux-ids = < - 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */ + MX28_PAD_AUART1_CTS__USB0_OVERCURRENT >; fsl,drive-strength = <2>; fsl,voltage = <1>; @@ -734,7 +735,7 @@ usbphy1_pins_a: usbphy1@0 { reg = <0>; fsl,pinmux-ids = < - 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */ + MX28_PAD_SSP2_SS1__USB1_OVERCURRENT >; fsl,drive-strength = <2>; fsl,voltage = <1>; -- cgit v1.2.3 From 4191c3401179a3c068fccd5ff84401a7e3d596e3 Mon Sep 17 00:00:00 2001 From: Lothar Waßmann Date: Sun, 22 Sep 2013 14:02:59 +0800 Subject: ARM: dts: mxs: modify mx23/mx28 dts files to use padconfig defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert mx23/mx28 dts files to use the padconfig defintions from mxs-pinfunc.h. Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23-evk.dts | 6 +- arch/arm/boot/dts/imx23-olinuxino.dts | 12 +- arch/arm/boot/dts/imx23-stmp378x_devb.dts | 6 +- arch/arm/boot/dts/imx23.dtsi | 58 +++---- arch/arm/boot/dts/imx28-apf28dev.dts | 12 +- arch/arm/boot/dts/imx28-apx4devkit.dts | 22 +-- arch/arm/boot/dts/imx28-cfa10036.dts | 18 +-- arch/arm/boot/dts/imx28-cfa10037.dts | 12 +- arch/arm/boot/dts/imx28-cfa10049.dts | 72 ++++----- arch/arm/boot/dts/imx28-cfa10055.dts | 24 +-- arch/arm/boot/dts/imx28-cfa10056.dts | 18 +-- arch/arm/boot/dts/imx28-cfa10057.dts | 18 +-- arch/arm/boot/dts/imx28-cfa10058.dts | 12 +- arch/arm/boot/dts/imx28-evk.dts | 24 +-- arch/arm/boot/dts/imx28-m28evk.dts | 12 +- arch/arm/boot/dts/imx28-sps1.dts | 6 +- arch/arm/boot/dts/imx28.dtsi | 242 +++++++++++++++--------------- 17 files changed, 287 insertions(+), 287 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index fdd8b27adb17..1f026adefd45 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -50,9 +50,9 @@ MX23_PAD_PWM4__GPIO_1_30 MX23_PAD_SSP1_DETECT__SSP1_DETECT >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index f575434d22ae..526bfdbd87f9 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -42,9 +42,9 @@ fsl,pinmux-ids = < MX23_PAD_GPMI_ALE__GPIO_0_17 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; led_pin_gpio2_1: led_gpio2_1@0 { @@ -52,9 +52,9 @@ fsl,pinmux-ids = < MX23_PAD_SSP1_DETECT__GPIO_2_1 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts index 2c8a9b0b9f43..cb64e2b191ea 100644 --- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts +++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts @@ -42,9 +42,9 @@ MX23_PAD_PWM3__GPIO_1_29 MX23_PAD_PWM4__GPIO_1_30 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; }; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index ff96e592ec3c..87faa6e8b6e7 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -141,9 +141,9 @@ MX23_PAD_PWM0__DUART_RX MX23_PAD_PWM1__DUART_TX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; auart0_pins_a: auart0@0 { @@ -154,9 +154,9 @@ MX23_PAD_AUART1_CTS__AUART1_CTS MX23_PAD_AUART1_RTS__AUART1_RTS >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; auart0_2pins_a: auart0-2pins@0 { @@ -165,9 +165,9 @@ MX23_PAD_I2C_SCL__AUART1_TX MX23_PAD_I2C_SDA__AUART1_RX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; gpmi_pins_a: gpmi-nand@0 { @@ -191,9 +191,9 @@ MX23_PAD_GPMI_CE1N__GPMI_CE1N MX23_PAD_GPMI_CE0N__GPMI_CE0N >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; gpmi_pins_fixup: gpmi-pins-fixup { @@ -202,7 +202,7 @@ MX23_PAD_GPMI_WRN__GPMI_WRN MX23_PAD_GPMI_RDN__GPMI_RDN >; - fsl,drive-strength = <2>; + fsl,drive-strength = ; }; mmc0_4bit_pins_a: mmc0-4bit@0 { @@ -215,9 +215,9 @@ MX23_PAD_SSP1_CMD__SSP1_CMD MX23_PAD_SSP1_SCK__SSP1_SCK >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; mmc0_8bit_pins_a: mmc0-8bit@0 { @@ -235,9 +235,9 @@ MX23_PAD_SSP1_DETECT__SSP1_DETECT MX23_PAD_SSP1_SCK__SSP1_SCK >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; mmc0_pins_fixup: mmc0-pins-fixup { @@ -245,7 +245,7 @@ MX23_PAD_SSP1_DETECT__SSP1_DETECT MX23_PAD_SSP1_SCK__SSP1_SCK >; - fsl,pull-up = <0>; + fsl,pull-up = ; }; pwm2_pins_a: pwm2@0 { @@ -253,9 +253,9 @@ fsl,pinmux-ids = < MX23_PAD_PWM2__PWM2 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_24bit_pins_a: lcdif-24bit@0 { @@ -290,9 +290,9 @@ MX23_PAD_LCD_HSYNC__LCD_HSYNC MX23_PAD_LCD_VSYNC__LCD_VSYNC >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; spi2_pins_a: spi2@0 { @@ -303,9 +303,9 @@ MX23_PAD_GPMI_D00__SSP2_DATA0 MX23_PAD_GPMI_D03__SSP2_DATA3 >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index 7d923cc56a93..e2efd8d89c4f 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -49,9 +49,9 @@ MX28_PAD_LCD_D21__GPIO_1_21 MX28_PAD_LCD_D22__GPIO_1_22 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_pins_apf28dev: lcdif-apf28dev@0 { @@ -62,9 +62,9 @@ MX28_PAD_LCD_RS__LCD_DOTCLK MX28_PAD_LCD_CS__LCD_ENABLE >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index cb19dc1e7743..6f254ca816cb 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -48,9 +48,9 @@ MX28_PAD_LCD_RESET__GPIO_3_30 MX28_PAD_JTAG_RTCK__GPIO_4_20 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_pins_apx4: lcdif-apx4@0 { @@ -61,9 +61,9 @@ MX28_PAD_LCD_RS__LCD_DOTCLK MX28_PAD_LCD_CS__LCD_ENABLE >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { @@ -76,17 +76,17 @@ MX28_PAD_SSP2_SS1__SSP2_D1 MX28_PAD_SSP2_SS2__SSP2_D2 >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 { fsl,pinmux-ids = < MX28_PAD_SSP0_DATA7__SSP2_SCK >; - fsl,drive-strength = <2>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index 2474207951fb..cabb6171a19d 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -28,9 +28,9 @@ fsl,pinmux-ids = < MX28_PAD_SSP0_DATA7__GPIO_2_7 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; led_pins_cfa10036: leds-10036@0 { @@ -38,9 +38,9 @@ fsl,pinmux-ids = < MX28_PAD_AUART1_RX__GPIO_3_4 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; usb0_otg_cfa10036: otg-10036@0 { @@ -48,9 +48,9 @@ fsl,pinmux-ids = < MX28_PAD_GPMI_RDY0__USB0_ID >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts index 42a9a99880af..f93e9a700e52 100644 --- a/arch/arm/boot/dts/imx28-cfa10037.dts +++ b/arch/arm/boot/dts/imx28-cfa10037.dts @@ -27,9 +27,9 @@ fsl,pinmux-ids = < MX28_PAD_GPMI_D07__GPIO_0_7 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; mac0_pins_cfa10037: mac0-10037@0 { @@ -37,9 +37,9 @@ fsl,pinmux-ids = < MX28_PAD_SSP2_SS2__GPIO_2_21 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 9ee2566bf4cb..7087b4bf6a8f 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -27,9 +27,9 @@ fsl,pinmux-ids = < MX28_PAD_GPMI_D07__GPIO_0_7 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; i2cmux_pins_cfa10049: i2cmux-10049@0 { @@ -38,9 +38,9 @@ MX28_PAD_LCD_D22__GPIO_1_22 MX28_PAD_LCD_D23__GPIO_1_23 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; mac0_pins_cfa10049: mac0-10049@0 { @@ -48,9 +48,9 @@ fsl,pinmux-ids = < MX28_PAD_SSP2_SS2__GPIO_2_21 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; pca_pins_cfa10049: pca-10049@0 { @@ -58,9 +58,9 @@ fsl,pinmux-ids = < MX28_PAD_SSP2_SS0__GPIO_2_19 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; rotary_pins_cfa10049: rotary-10049@0 { @@ -69,9 +69,9 @@ MX28_PAD_I2C0_SCL__GPIO_3_24 MX28_PAD_I2C0_SDA__GPIO_3_25 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; rotary_btn_pins_cfa10049: rotary-btn-10049@0 { @@ -79,9 +79,9 @@ fsl,pinmux-ids = < MX28_PAD_SAIF1_SDATA0__GPIO_3_26 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; spi2_pins_cfa10049: spi2-cfa10049@0 { @@ -92,9 +92,9 @@ MX28_PAD_SSP2_MISO__GPIO_2_18 MX28_PAD_AUART1_TX__GPIO_3_5 >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; spi3_pins_cfa10049: spi3-cfa10049@0 { @@ -106,9 +106,9 @@ MX28_PAD_GPMI_ALE__GPIO_0_26 MX28_PAD_GPMI_CLE__GPIO_0_27 >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_18bit_pins_cfa10049: lcdif-18bit@0 { @@ -133,9 +133,9 @@ MX28_PAD_LCD_D16__LCD_D16 MX28_PAD_LCD_D17__LCD_D17 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_pins_cfa10049: lcdif-evk@0 { @@ -146,9 +146,9 @@ MX28_PAD_LCD_RS__LCD_DOTCLK MX28_PAD_LCD_CS__LCD_ENABLE >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 { @@ -156,9 +156,9 @@ fsl,pinmux-ids = < MX28_PAD_LCD_RESET__GPIO_3_30 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; w1_gpio_pins: w1-gpio@0 { @@ -166,9 +166,9 @@ fsl,pinmux-ids = < MX28_PAD_LCD_D21__GPIO_1_21 >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <0>; /* 0 will enable the keeper */ + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; /* 0 will enable the keeper */ }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts index 8b262a26f50c..c3900e7ba331 100644 --- a/arch/arm/boot/dts/imx28-cfa10055.dts +++ b/arch/arm/boot/dts/imx28-cfa10055.dts @@ -31,9 +31,9 @@ MX28_PAD_SSP2_MISO__GPIO_2_18 MX28_PAD_AUART1_TX__GPIO_3_5 >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { @@ -58,9 +58,9 @@ MX28_PAD_LCD_D16__LCD_D16 MX28_PAD_LCD_D17__LCD_D17 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_pins_cfa10055: lcdif-evk@0 { @@ -71,9 +71,9 @@ MX28_PAD_LCD_RS__LCD_DOTCLK MX28_PAD_LCD_CS__LCD_ENABLE >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 { @@ -81,9 +81,9 @@ fsl,pinmux-ids = < MX28_PAD_LCD_RESET__GPIO_3_30 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts index f65199878122..cef959a97219 100644 --- a/arch/arm/boot/dts/imx28-cfa10056.dts +++ b/arch/arm/boot/dts/imx28-cfa10056.dts @@ -30,9 +30,9 @@ MX28_PAD_SSP2_MISO__GPIO_2_18 MX28_PAD_AUART1_TX__GPIO_3_5 >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_pins_cfa10056: lcdif-10056@0 { @@ -43,9 +43,9 @@ MX28_PAD_LCD_RS__LCD_DOTCLK MX28_PAD_LCD_CS__LCD_ENABLE >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 { @@ -53,9 +53,9 @@ fsl,pinmux-ids = < MX28_PAD_LCD_RESET__GPIO_3_30 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts index 76430ca3e53d..3c1312885ae0 100644 --- a/arch/arm/boot/dts/imx28-cfa10057.dts +++ b/arch/arm/boot/dts/imx28-cfa10057.dts @@ -28,9 +28,9 @@ fsl,pinmux-ids = < MX28_PAD_GPMI_D07__GPIO_0_7 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { @@ -55,9 +55,9 @@ MX28_PAD_LCD_D16__LCD_D16 MX28_PAD_LCD_D17__LCD_D17 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_pins_cfa10057: lcdif-evk@0 { @@ -68,9 +68,9 @@ MX28_PAD_LCD_RS__LCD_DOTCLK MX28_PAD_LCD_CS__LCD_ENABLE >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts index 502be77d32b8..2469d34df0ae 100644 --- a/arch/arm/boot/dts/imx28-cfa10058.dts +++ b/arch/arm/boot/dts/imx28-cfa10058.dts @@ -28,9 +28,9 @@ fsl,pinmux-ids = < MX28_PAD_GPMI_D07__GPIO_0_7 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_pins_cfa10058: lcdif-10058@0 { @@ -41,9 +41,9 @@ MX28_PAD_LCD_RS__LCD_DOTCLK MX28_PAD_LCD_CS__LCD_ENABLE >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 023eaf775487..1f63845b8ce0 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -79,9 +79,9 @@ MX28_PAD_AUART2_RX__GPIO_3_8 MX28_PAD_AUART2_TX__GPIO_3_9 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; led_pin_gpio3_5: led_gpio3_5@0 { @@ -89,9 +89,9 @@ fsl,pinmux-ids = < MX28_PAD_AUART1_TX__GPIO_3_5 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; gpmi_pins_evk: gpmi-nand-evk@0 { @@ -100,9 +100,9 @@ MX28_PAD_GPMI_CE1N__GPMI_CE1N MX28_PAD_GPMI_RDY1__GPMI_READY1 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_pins_evk: lcdif-evk@0 { @@ -113,9 +113,9 @@ MX28_PAD_LCD_RS__LCD_DOTCLK MX28_PAD_LCD_CS__LCD_ENABLE >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 9f3271dcc7d9..8e2477fbe1d7 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -98,9 +98,9 @@ MX28_PAD_AUART3_RX__GPIO_3_12 MX28_PAD_AUART3_TX__GPIO_3_13 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_pins_m28: lcdif-m28@0 { @@ -109,9 +109,9 @@ MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MX28_PAD_LCD_ENABLE__LCD_ENABLE >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts index 4613522a1cbe..4870f07bf56a 100644 --- a/arch/arm/boot/dts/imx28-sps1.dts +++ b/arch/arm/boot/dts/imx28-sps1.dts @@ -33,9 +33,9 @@ MX28_PAD_GPMI_D03__GPIO_0_3 MX28_PAD_GPMI_D06__GPIO_0_6 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 1f16193f3da9..44151f54a4df 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -211,9 +211,9 @@ MX28_PAD_PWM0__DUART_RX MX28_PAD_PWM1__DUART_TX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; duart_pins_b: duart@1 { @@ -222,9 +222,9 @@ MX28_PAD_AUART0_CTS__DUART_RX MX28_PAD_AUART0_RTS__DUART_TX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; duart_4pins_a: duart-4pins@0 { @@ -235,9 +235,9 @@ MX28_PAD_AUART0_RX__DUART_CTS MX28_PAD_AUART0_TX__DUART_RTS >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; gpmi_pins_a: gpmi-nand@0 { @@ -259,9 +259,9 @@ MX28_PAD_GPMI_CLE__GPMI_CLE MX28_PAD_GPMI_RESETN__GPMI_RESETN >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; gpmi_status_cfg: gpmi-status-cfg { @@ -270,7 +270,7 @@ MX28_PAD_GPMI_WRN__GPMI_WRN MX28_PAD_GPMI_RESETN__GPMI_RESETN >; - fsl,drive-strength = <2>; + fsl,drive-strength = ; }; auart0_pins_a: auart0@0 { @@ -281,9 +281,9 @@ MX28_PAD_AUART0_CTS__AUART0_CTS MX28_PAD_AUART0_RTS__AUART0_RTS >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; auart0_2pins_a: auart0-2pins@0 { @@ -292,9 +292,9 @@ MX28_PAD_AUART0_RX__AUART0_RX MX28_PAD_AUART0_TX__AUART0_TX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; auart1_pins_a: auart1@0 { @@ -305,9 +305,9 @@ MX28_PAD_AUART1_CTS__AUART1_CTS MX28_PAD_AUART1_RTS__AUART1_RTS >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; auart1_2pins_a: auart1-2pins@0 { @@ -316,9 +316,9 @@ MX28_PAD_AUART1_RX__AUART1_RX MX28_PAD_AUART1_TX__AUART1_TX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; auart2_2pins_a: auart2-2pins@0 { @@ -327,9 +327,9 @@ MX28_PAD_SSP2_SCK__AUART2_RX MX28_PAD_SSP2_MOSI__AUART2_TX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; auart2_2pins_b: auart2-2pins@1 { @@ -338,9 +338,9 @@ MX28_PAD_AUART2_RX__AUART2_RX MX28_PAD_AUART2_TX__AUART2_TX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; auart3_pins_a: auart3@0 { @@ -351,9 +351,9 @@ MX28_PAD_AUART3_CTS__AUART3_CTS MX28_PAD_AUART3_RTS__AUART3_RTS >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; auart3_2pins_a: auart3-2pins@0 { @@ -362,9 +362,9 @@ MX28_PAD_SSP2_MISO__AUART3_RX MX28_PAD_SSP2_SS0__AUART3_TX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; auart3_2pins_b: auart3-2pins@1 { @@ -373,9 +373,9 @@ MX28_PAD_AUART3_RX__AUART3_RX MX28_PAD_AUART3_TX__AUART3_TX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; auart4_2pins_a: auart4@0 { @@ -384,9 +384,9 @@ MX28_PAD_SSP3_SCK__AUART4_TX MX28_PAD_SSP3_MOSI__AUART4_RX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; mac0_pins_a: mac0@0 { @@ -402,9 +402,9 @@ MX28_PAD_ENET0_TXD1__ENET0_TXD1 MX28_PAD_ENET_CLK__CLKCTRL_ENET >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; mac1_pins_a: mac1@0 { @@ -417,9 +417,9 @@ MX28_PAD_ENET0_TXD2__ENET1_TXD0 MX28_PAD_ENET0_TXD3__ENET1_TXD1 >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; mmc0_8bit_pins_a: mmc0-8bit@0 { @@ -437,9 +437,9 @@ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MX28_PAD_SSP0_SCK__SSP0_SCK >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; mmc0_4bit_pins_a: mmc0-4bit@0 { @@ -453,24 +453,24 @@ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MX28_PAD_SSP0_SCK__SSP0_SCK >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; mmc0_cd_cfg: mmc0-cd-cfg { fsl,pinmux-ids = < MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT >; - fsl,pull-up = <0>; + fsl,pull-up = ; }; mmc0_sck_cfg: mmc0-sck-cfg { fsl,pinmux-ids = < MX28_PAD_SSP0_SCK__SSP0_SCK >; - fsl,drive-strength = <2>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,pull-up = ; }; i2c0_pins_a: i2c0@0 { @@ -479,9 +479,9 @@ MX28_PAD_I2C0_SCL__I2C0_SCL MX28_PAD_I2C0_SDA__I2C0_SDA >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; i2c0_pins_b: i2c0@1 { @@ -490,9 +490,9 @@ MX28_PAD_AUART0_RX__I2C0_SCL MX28_PAD_AUART0_TX__I2C0_SDA >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; i2c1_pins_a: i2c1@0 { @@ -501,9 +501,9 @@ MX28_PAD_PWM0__I2C1_SCL MX28_PAD_PWM1__I2C1_SDA >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; saif0_pins_a: saif0@0 { @@ -514,9 +514,9 @@ MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 >; - fsl,drive-strength = <2>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; saif0_pins_b: saif0@1 { @@ -526,9 +526,9 @@ MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 >; - fsl,drive-strength = <2>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; saif1_pins_a: saif1@0 { @@ -536,9 +536,9 @@ fsl,pinmux-ids = < MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 >; - fsl,drive-strength = <2>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; pwm0_pins_a: pwm0@0 { @@ -546,9 +546,9 @@ fsl,pinmux-ids = < MX28_PAD_PWM0__PWM_0 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; pwm2_pins_a: pwm2@0 { @@ -556,9 +556,9 @@ fsl,pinmux-ids = < MX28_PAD_PWM2__PWM_2 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; pwm3_pins_a: pwm3@0 { @@ -566,9 +566,9 @@ fsl,pinmux-ids = < MX28_PAD_PWM3__PWM_3 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; pwm3_pins_b: pwm3@1 { @@ -576,9 +576,9 @@ fsl,pinmux-ids = < MX28_PAD_SAIF0_MCLK__PWM_3 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; pwm4_pins_a: pwm4@0 { @@ -586,9 +586,9 @@ fsl,pinmux-ids = < MX28_PAD_PWM4__PWM_4 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_24bit_pins_a: lcdif-24bit@0 { @@ -619,9 +619,9 @@ MX28_PAD_LCD_D22__LCD_D22 MX28_PAD_LCD_D23__LCD_D23 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_16bit_pins_a: lcdif-16bit@0 { @@ -644,9 +644,9 @@ MX28_PAD_LCD_D14__LCD_D14 MX28_PAD_LCD_D15__LCD_D15 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; lcdif_sync_pins_a: lcdif-sync@0 { @@ -657,9 +657,9 @@ MX28_PAD_LCD_RD_E__LCD_VSYNC MX28_PAD_LCD_WR_RWN__LCD_HSYNC >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; can0_pins_a: can0@0 { @@ -668,9 +668,9 @@ MX28_PAD_GPMI_RDY2__CAN0_TX MX28_PAD_GPMI_RDY3__CAN0_RX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; can1_pins_a: can1@0 { @@ -679,9 +679,9 @@ MX28_PAD_GPMI_CE2N__CAN1_TX MX28_PAD_GPMI_CE3N__CAN1_RX >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; spi2_pins_a: spi2@0 { @@ -692,9 +692,9 @@ MX28_PAD_SSP2_MISO__SSP2_D0 MX28_PAD_SSP2_SS0__SSP2_D3 >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; spi3_pins_a: spi3@0 { @@ -707,9 +707,9 @@ MX28_PAD_SSP3_MISO__SSP3_D0 MX28_PAD_SSP3_SS0__SSP3_D3 >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; usbphy0_pins_a: usbphy0@0 { @@ -717,9 +717,9 @@ fsl,pinmux-ids = < MX28_PAD_SSP2_SS2__USB0_OVERCURRENT >; - fsl,drive-strength = <2>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; usbphy0_pins_b: usbphy0@1 { @@ -727,9 +727,9 @@ fsl,pinmux-ids = < MX28_PAD_AUART1_CTS__USB0_OVERCURRENT >; - fsl,drive-strength = <2>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; usbphy1_pins_a: usbphy1@0 { @@ -737,9 +737,9 @@ fsl,pinmux-ids = < MX28_PAD_SSP2_SS1__USB1_OVERCURRENT >; - fsl,drive-strength = <2>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; usb0_id_pins_a: usb0id@0 { -- cgit v1.2.3 From d1d67d71d5e86e0c401bb91f91c6a44b8f408b1d Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 1 Aug 2013 12:22:04 +0800 Subject: ARM: dts: imx6q: add quirky select input for USB_OTG_ID For some reason, the select input of pin function USB_OTG_ID is not implemented via a regular select input register but using the bit USB_OTG_ID_ SEL (shift 13) of IOMUXC_GPR1 register (offset 0x4). As per the workaround for such quirk implemented in pinctrl driver, we need to compose the input_val cell as below. 31 23 15 7 0 | 0xff | shift | width | select | Thus, we have 0xff0d0100 for MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID and 0xff0d0101 for MX6QDL_PAD_GPIO_1__USB_OTG_ID in input_val cell. Signed-off-by: Shawn Guo Tested-by: Peter Chen Acked-by: Linus Walleij --- arch/arm/boot/dts/imx6q-pinfunc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h index 9bbe82bdee41..97ed0816a6e0 100644 --- a/arch/arm/boot/dts/imx6q-pinfunc.h +++ b/arch/arm/boot/dts/imx6q-pinfunc.h @@ -536,7 +536,7 @@ #define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 #define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 #define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0 +#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100 #define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 #define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 #define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 @@ -654,7 +654,7 @@ #define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 #define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 #define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 -#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101 #define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 #define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 #define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 -- cgit v1.2.3 From af67a755376df068aae678e96e42c72fb631b87b Mon Sep 17 00:00:00 2001 From: Lothar Waßmann Date: Mon, 23 Sep 2013 12:20:48 +0200 Subject: ARM: dts: tx28: restructure and update DTS file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the Ka-Ro TX28 DTS file. - add Copyright header - use label references for better readability - sort the entries alphabetically - add some aliases used by U-Boot to modify the DT data Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-tx28.dts | 701 ++++++++++++++++++++++++++++++++++----- 1 file changed, 619 insertions(+), 82 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 3dbe1d7da467..be5a0550d58c 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -1,106 +1,139 @@ +/* + * Copyright 2012 Shawn Guo + * Copyright 2013 Lothar Waßmann + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + /dts-v1/; #include "imx28.dtsi" +#include / { model = "Ka-Ro electronics TX28 module"; compatible = "karo,tx28", "fsl,imx28"; + aliases { + can0 = &can0; + can1 = &can1; + display = &display; + ds1339 = &ds1339; + gpio5 = &gpio5; + lcdif = &lcdif; + lcdif_23bit_pins = &tx28_lcdif_23bit_pins; + lcdif_24bit_pins = &lcdif_24bit_pins_a; + stk5led = &user_led; + usbotg = &usb0; + }; + memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; - }; + reg = <0 0>; /* will be filled in by U-Boot */ + }; - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - - mac0_pins_gpio: mac0-gpio-mode@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */ - 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */ - 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */ - 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */ - 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */ - 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */ - 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */ - 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */ - 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - }; + onewire { + compatible = "w1-gpio"; + gpios = <&gpio2 7 0>; + status = "disabled"; + }; + + regulators { + compatible = "simple-bus"; + + reg_usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 18 0>; + enable-active-high; }; - apbx@80040000 { - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; + reg_usb1_vbus: usb1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 27 0>; + enable-active-high; + }; - ds1339: rtc@68 { - compatible = "mxim,ds1339"; - reg = <0x68>; - }; - }; + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; - }; + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_4pins_a>; - status = "okay"; - }; + reg_can_xcvr: can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 0 0>; + enable-active-low; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_flexcan_xcvr_pins>; + }; - auart1: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_pins_a>; - status = "okay"; - }; + reg_lcd: lcd-power { + compatible = "regulator-fixed"; + regulator-name = "LCD POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 31 0>; + enable-active-high; + }; + + reg_lcd_reset: lcd-reset { + compatible = "regulator-fixed"; + regulator-name = "LCD RESET"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 30 0>; + startup-delay-us = <300000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; }; }; - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default", "gpio_mode"; - pinctrl-0 = <&mac0_pins_a>; - pinctrl-1 = <&mac0_pins_gpio>; - status = "okay"; + clocks { + #address-cells = <1>; + #size-cells = <0>; + mclk: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <27000000>; }; }; + sound { + compatible = "fsl,imx28-tx28-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "imx28-tx28-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; + leds { compatible = "gpio-leds"; - user { + user_led: user { label = "Heartbeat"; gpios = <&gpio4 10 0>; linux,default-trigger = "heartbeat"; @@ -109,8 +142,512 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; + pwms = <&pwm 0 500000>; + /* + * a silly way to create a 1:1 relationship between the + * PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + matrix_keypad: matrix-keypad@0 { + compatible = "gpio-matrix-keypad"; + col-gpios = < + &gpio5 0 0 + &gpio5 1 0 + &gpio5 2 0 + &gpio5 3 0 + >; + row-gpios = < + &gpio5 4 0 + &gpio5 5 0 + &gpio5 6 0 + &gpio5 7 0 + >; + /* sample keymap */ + linux,keymap = < + 0x00000074 /* row 0, col 0, KEY_POWER */ + 0x00010052 /* row 0, col 1, KEY_KP0 */ + 0x0002004f /* row 0, col 2, KEY_KP1 */ + 0x00030050 /* row 0, col 3, KEY_KP2 */ + 0x01000051 /* row 1, col 0, KEY_KP3 */ + 0x0101004b /* row 1, col 1, KEY_KP4 */ + 0x0102004c /* row 1, col 2, KEY_KP5 */ + 0x0103004d /* row 1, col 3, KEY_KP6 */ + 0x02000047 /* row 2, col 0, KEY_KP7 */ + 0x02010048 /* row 2, col 1, KEY_KP8 */ + 0x02020049 /* row 2, col 2, KEY_KP9 */ + >; + gpio-activelow; + linux,wakeup; + debounce-delay-ms = <100>; + col-scan-delay-us = <5000>; + linux,no-autorepeat; + }; +}; + +/* 2nd TX-Std UART - (A)UART1 */ +&auart1 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_pins_a>; + status = "okay"; +}; + +/* 3rd TX-Std UART - (A)UART3 */ +&auart3 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&digctl { + status = "okay"; +}; + +/* 1st TX-Std UART - (D)UART */ +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_4pins_a>; + status = "okay"; +}; + +&gpmi { + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + clock-frequency = <400000>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + clocks = <&mclk>; + }; + + gpio5: pca953x@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_pca9554_pins>; + interrupt-parent = <&gpio3>; + interrupts = <28 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + polytouch: edt-ft5x06@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_edt_ft5x06_pins>; + interrupt-parent = <&gpio2>; + interrupts = <5 0>; + reset-gpios = <&gpio2 6 1>; + wake-gpios = <&gpio4 9 0>; + }; + + touchscreen: tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_tsc2007_pins>; + interrupt-parent = <&gpio3>; + interrupts = <20 0>; + pendown-gpio = <&gpio3 20 1>; + ti,x-plate-ohms = /bits/ 16 <660>; + }; + + ds1339: rtc@68 { + compatible = "mxim,ds1339"; + reg = <0x68>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>; + lcd-supply = <®_lcd>; + display = <&display>; + status = "okay"; + + display: display@0 { + bits-per-pixel = <32>; + bus-width = <24>; + display-timings { + native-mode = <&timing5>; + timing0: timing0 { + panel-name = "VGA"; + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + timing1: timing1 { + panel-name = "ETV570"; + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + timing2: timing2 { + panel-name = "ET0350"; + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + timing3: timing3 { + panel-name = "ET0430"; + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + timing4: timing4 { + panel-name = "ET0500", "ET0700"; + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + timing5: timing5 { + panel-name = "ETQ570"; + clock-frequency = <6400000>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default", "gpio_mode"; + pinctrl-0 = <&mac0_pins_a>; + pinctrl-1 = <&tx28_mac0_pins_gpio>; + status = "okay"; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + /* not enabled by default */ +}; + +&mxs_rtc { + status = "okay"; +}; + +&ocotp { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_RXD3__GPIO_4_10 /* module LED */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins { + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */ + MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */ + MX28_PAD_ENET0_RXD2__GPIO_4_9 /* WAKE */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins { + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__GPIO_1_0 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_lcdif_23bit_pins: tx28-lcdif-23bit { + fsl,pinmux-ids = < + /* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */ + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + MX28_PAD_LCD_D18__LCD_D18 + MX28_PAD_LCD_D19__LCD_D19 + MX28_PAD_LCD_D20__LCD_D20 + MX28_PAD_LCD_D21__LCD_D21 + MX28_PAD_LCD_D22__LCD_D22 + MX28_PAD_LCD_D23__LCD_D23 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl { + fsl,pinmux-ids = < + MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */ + MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_mac0_pins_gpio: tx28-mac0-gpio-pins { + fsl,pinmux-ids = < + MX28_PAD_ENET0_MDC__GPIO_4_0 + MX28_PAD_ENET0_MDIO__GPIO_4_1 + MX28_PAD_ENET0_RX_EN__GPIO_4_2 + MX28_PAD_ENET0_RXD0__GPIO_4_3 + MX28_PAD_ENET0_RXD1__GPIO_4_4 + MX28_PAD_ENET0_TX_EN__GPIO_4_6 + MX28_PAD_ENET0_TXD0__GPIO_4_7 + MX28_PAD_ENET0_TXD1__GPIO_4_8 + MX28_PAD_ENET_CLK__GPIO_4_16 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_pca9554_pins: tx28-pca9554-pins { + fsl,pinmux-ids = < + MX28_PAD_PWM3__GPIO_3_28 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_tsc2007_pins: tx28-tsc2007-pins { + fsl,pinmux-ids = < + MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + + tx28_usbphy0_pins: tx28-usbphy0-pins { + fsl,pinmux-ids = < + MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */ + MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + tx28_usbphy1_pins: tx28-usbphy1-pins { + fsl,pinmux-ids = < + MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */ + MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_b>; + fsl,saif-master; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default", "special"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; +}; + +&ssp3 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins_a>; + clock-frequency = <57600000>; + status = "okay"; + + spidev0: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <57600000>; + }; + + spidev1: spi@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <57600000>; }; }; + +&usb0 { + vbus-supply = <®_usb0_vbus>; + disable-over-current; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy0 { + pinctrl-names = "default"; + pinctrl-0 = <&tx28_usbphy0_pins>; + phy_type = "utmi"; + status = "okay"; +}; + +&usbphy1 { + pinctrl-names = "default"; + pinctrl-0 = <&tx28_usbphy1_pins>; + phy_type = "utmi"; + status = "okay"; +}; -- cgit v1.2.3 From e96e1782d89f7538971954b4f78f44a0be1b9144 Mon Sep 17 00:00:00 2001 From: Lothar Waßmann Date: Mon, 23 Sep 2013 14:20:27 +0200 Subject: ARM: dts: mxs: convert usb0_id_pins_a to use symbolic pin defs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This pin definition had been added after the initial patch to use symbolic pin names in DTS files. Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 44151f54a4df..918d419772dd 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -745,11 +745,11 @@ usb0_id_pins_a: usb0id@0 { reg = <0>; fsl,pinmux-ids = < - 0x3071 /* MX28_PAD_AUART1_RTS__USB0_ID */ + MX28_PAD_AUART1_RTS__USB0_ID >; - fsl,drive-strength = <2>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; }; }; -- cgit v1.2.3 From 931398ecd51bc7d6f3a22561c31bfd34d030c94a Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Mon, 23 Sep 2013 11:14:44 -0400 Subject: ARM: dts: add initial VF610 Cosmic/Cosmic+ board support Add initial PHYTEC VF610 Cosmic/Cosmic+ board support with UART and FEC enabled. Signed-off-by: Matt Porter Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/vf610-cosmic.dts | 47 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 arch/arm/boot/dts/vf610-cosmic.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e95af3f5433b..c703da2581cf 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-sbc6x.dtb \ imx6q-wandboard.dtb \ imx6sl-evk.dtb \ + vf610-cosmic.dtb \ vf610-twr.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx23-olinuxino.dtb \ diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts new file mode 100644 index 000000000000..c42e4f938dcd --- /dev/null +++ b/arch/arm/boot/dts/vf610-cosmic.dts @@ -0,0 +1,47 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "PHYTEC Cosmic/Cosmic+ Board"; + compatible = "phytec,vf610-cosmic", "fsl,vf610"; + + chosen { + bootargs = "console=ttyLP1,115200"; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + clocks { + enet_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1_1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; -- cgit v1.2.3 From ffefbd7511addbb9811023ce25347dc3e6477d26 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 10 Sep 2013 13:49:02 +0100 Subject: ARM: ux500: Remove PrimeCell IDs from Nomadik I2C DT nodes Turns out that they're actually not required and the driver probes just fine without them. The ID is incorrect at the moment anyway. They actually currently specify the stn8815. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 1c1091eedade..0c1338e36a83 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -559,7 +559,6 @@ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80004000 0x1000>; interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; - arm,primecell-periphid = <0x180024>; #address-cells = <1>; #size-cells = <0>; @@ -572,7 +571,6 @@ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80122000 0x1000>; interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; - arm,primecell-periphid = <0x180024>; #address-cells = <1>; #size-cells = <0>; @@ -585,7 +583,6 @@ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80128000 0x1000>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; - arm,primecell-periphid = <0x180024>; #address-cells = <1>; #size-cells = <0>; @@ -598,7 +595,6 @@ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80110000 0x1000>; interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; - arm,primecell-periphid = <0x180024>; #address-cells = <1>; #size-cells = <0>; @@ -611,7 +607,6 @@ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x8012a000 0x1000>; interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; - arm,primecell-periphid = <0x180024>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 8cc3168ccd39258a31d6ca0c609c0461db67d7c5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 16 Aug 2013 13:40:55 +0200 Subject: ARM: ux500: delete surplus PRCMU regulator defines The Ux500 boards are layered like this: ste-snowball.dts includes ste-href.dtsi that includes ste-dbx500.dtsi. The dbx500.dtsi defines the PRCMU SoC regulators so the SoC will probe and you can use ampersand references where need be. However the HREF common dtsi and these two boards redefine the same PRCMU SoC regulators with the very same names and properties for no reason. This is like filling in the same line three times instead of drawing it once. Just delete the surplus references and have the PRCMU regulators defines in the SoC files ste-dbx500.dtsi, this is enough. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href.dtsi | 82 ----------------------------------- arch/arm/boot/dts/ste-hrefv60plus.dts | 82 ----------------------------------- arch/arm/boot/dts/ste-snowball.dts | 82 ----------------------------------- 3 files changed, 246 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 370e03f5e7b2..f88a659aea3b 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -167,88 +167,6 @@ }; prcmu@80157000 { - db8500-prcmu-regulators { - db8500_vape_reg: db8500_vape { - regulator-name = "db8500-vape"; - }; - - db8500_varm_reg: db8500_varm { - regulator-name = "db8500-varm"; - }; - - db8500_vmodem_reg: db8500_vmodem { - regulator-name = "db8500-vmodem"; - }; - - db8500_vpll_reg: db8500_vpll { - regulator-name = "db8500-vpll"; - }; - - db8500_vsmps1_reg: db8500_vsmps1 { - regulator-name = "db8500-vsmps1"; - }; - - db8500_vsmps2_reg: db8500_vsmps2 { - regulator-name = "db8500-vsmps2"; - }; - - db8500_vsmps3_reg: db8500_vsmps3 { - regulator-name = "db8500-vsmps3"; - }; - - db8500_vrf1_reg: db8500_vrf1 { - regulator-name = "db8500-vrf1"; - }; - - db8500_sva_mmdsp_reg: db8500_sva_mmdsp { - regulator-name = "db8500-sva-mmdsp"; - }; - - db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { - regulator-name = "db8500-sva-mmdsp-ret"; - }; - - db8500_sva_pipe_reg: db8500_sva_pipe { - regulator-name = "db8500_sva_pipe"; - }; - - db8500_sia_mmdsp_reg: db8500_sia_mmdsp { - regulator-name = "db8500_sia_mmdsp"; - }; - - db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { - regulator-name = "db8500-sia-mmdsp-ret"; - }; - - db8500_sia_pipe_reg: db8500_sia_pipe { - regulator-name = "db8500-sia-pipe"; - }; - - db8500_sga_reg: db8500_sga { - regulator-name = "db8500-sga"; - }; - - db8500_b2r2_mcde_reg: db8500_b2r2_mcde { - regulator-name = "db8500-b2r2-mcde"; - }; - - db8500_esram12_reg: db8500_esram12 { - regulator-name = "db8500-esram12"; - }; - - db8500_esram12_ret_reg: db8500_esram12_ret { - regulator-name = "db8500-esram12-ret"; - }; - - db8500_esram34_reg: db8500_esram34 { - regulator-name = "db8500-esram34"; - }; - - db8500_esram34_ret_reg: db8500_esram34_ret { - regulator-name = "db8500-esram34-ret"; - }; - }; - ab8500 { ab8500-regulators { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dts b/arch/arm/boot/dts/ste-hrefv60plus.dts index 6e52ebbf113f..0e2be7acd70c 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dts +++ b/arch/arm/boot/dts/ste-hrefv60plus.dts @@ -76,88 +76,6 @@ }; prcmu@80157000 { - db8500-prcmu-regulators { - db8500_vape_reg: db8500_vape { - regulator-name = "db8500-vape"; - }; - - db8500_varm_reg: db8500_varm { - regulator-name = "db8500-varm"; - }; - - db8500_vmodem_reg: db8500_vmodem { - regulator-name = "db8500-vmodem"; - }; - - db8500_vpll_reg: db8500_vpll { - regulator-name = "db8500-vpll"; - }; - - db8500_vsmps1_reg: db8500_vsmps1 { - regulator-name = "db8500-vsmps1"; - }; - - db8500_vsmps2_reg: db8500_vsmps2 { - regulator-name = "db8500-vsmps2"; - }; - - db8500_vsmps3_reg: db8500_vsmps3 { - regulator-name = "db8500-vsmps3"; - }; - - db8500_vrf1_reg: db8500_vrf1 { - regulator-name = "db8500-vrf1"; - }; - - db8500_sva_mmdsp_reg: db8500_sva_mmdsp { - regulator-name = "db8500-sva-mmdsp"; - }; - - db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { - regulator-name = "db8500-sva-mmdsp-ret"; - }; - - db8500_sva_pipe_reg: db8500_sva_pipe { - regulator-name = "db8500_sva_pipe"; - }; - - db8500_sia_mmdsp_reg: db8500_sia_mmdsp { - regulator-name = "db8500_sia_mmdsp"; - }; - - db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { - regulator-name = "db8500-sia-mmdsp-ret"; - }; - - db8500_sia_pipe_reg: db8500_sia_pipe { - regulator-name = "db8500-sia-pipe"; - }; - - db8500_sga_reg: db8500_sga { - regulator-name = "db8500-sga"; - }; - - db8500_b2r2_mcde_reg: db8500_b2r2_mcde { - regulator-name = "db8500-b2r2-mcde"; - }; - - db8500_esram12_reg: db8500_esram12 { - regulator-name = "db8500-esram12"; - }; - - db8500_esram12_ret_reg: db8500_esram12_ret { - regulator-name = "db8500-esram12-ret"; - }; - - db8500_esram34_reg: db8500_esram34 { - regulator-name = "db8500-esram34"; - }; - - db8500_esram34_ret_reg: db8500_esram34_ret { - regulator-name = "db8500-esram34-ret"; - }; - }; - ab8500 { ab8500-regulators { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index f1fc128e249d..acf99ece8499 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -170,88 +170,6 @@ }; prcmu@80157000 { - db8500-prcmu-regulators { - db8500_vape_reg: db8500_vape { - regulator-name = "db8500-vape"; - }; - - db8500_varm_reg: db8500_varm { - regulator-name = "db8500-varm"; - }; - - db8500_vmodem_reg: db8500_vmodem { - regulator-name = "db8500-vmodem"; - }; - - db8500_vpll_reg: db8500_vpll { - regulator-name = "db8500-vpll"; - }; - - db8500_vsmps1_reg: db8500_vsmps1 { - regulator-name = "db8500-vsmps1"; - }; - - db8500_vsmps2_reg: db8500_vsmps2 { - regulator-name = "db8500-vsmps2"; - }; - - db8500_vsmps3_reg: db8500_vsmps3 { - regulator-name = "db8500-vsmps3"; - }; - - db8500_vrf1_reg: db8500_vrf1 { - regulator-name = "db8500-vrf1"; - }; - - db8500_sva_mmdsp_reg: db8500_sva_mmdsp { - regulator-name = "db8500-sva-mmdsp"; - }; - - db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { - regulator-name = "db8500-sva-mmdsp-ret"; - }; - - db8500_sva_pipe_reg: db8500_sva_pipe { - regulator-name = "db8500_sva_pipe"; - }; - - db8500_sia_mmdsp_reg: db8500_sia_mmdsp { - regulator-name = "db8500_sia_mmdsp"; - }; - - db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { - regulator-name = "db8500-sia-mmdsp-ret"; - }; - - db8500_sia_pipe_reg: db8500_sia_pipe { - regulator-name = "db8500-sia-pipe"; - }; - - db8500_sga_reg: db8500_sga { - regulator-name = "db8500-sga"; - }; - - db8500_b2r2_mcde_reg: db8500_b2r2_mcde { - regulator-name = "db8500-b2r2-mcde"; - }; - - db8500_esram12_reg: db8500_esram12 { - regulator-name = "db8500-esram12"; - }; - - db8500_esram12_ret_reg: db8500_esram12_ret { - regulator-name = "db8500-esram12-ret"; - }; - - db8500_esram34_reg: db8500_esram34 { - regulator-name = "db8500-esram34"; - }; - - db8500_esram34_ret_reg: db8500_esram34_ret { - regulator-name = "db8500-esram34-ret"; - }; - }; - thermal@801573c0 { num-trips = <4>; -- cgit v1.2.3 From 7e3fbea959500c490b6453234597d54a05603482 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 16 Aug 2013 13:53:14 +0200 Subject: ARM: ux500: skip redefined regulator names on v60plus board These regulator rail names are already set in the ste-href.dtsi file included by this file, this is just redoing the naming for no benefit, so delete it. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-hrefv60plus.dts | 50 ----------------------------------- 1 file changed, 50 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dts b/arch/arm/boot/dts/ste-hrefv60plus.dts index 0e2be7acd70c..bb3cfc7280e8 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dts +++ b/arch/arm/boot/dts/ste-hrefv60plus.dts @@ -74,55 +74,5 @@ status = "okay"; }; - - prcmu@80157000 { - ab8500 { - ab8500-regulators { - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-name = "V-DISPLAY"; - }; - - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-name = "V-eMMC1"; - }; - - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-name = "V-MMC-SD"; - }; - - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - regulator-name = "V-INTCORE"; - }; - - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - regulator-name = "V-TVOUT"; - }; - - ab8500_ldo_usb_reg: ab8500_ldo_usb { - regulator-name = "dummy"; - }; - - ab8500_ldo_audio_reg: ab8500_ldo_audio { - regulator-name = "V-AUD"; - }; - - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - regulator-name = "V-AMIC1"; - }; - - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - regulator-name = "V-AMIC2"; - }; - - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - regulator-name = "V-DMIC"; - }; - - ab8500_ldo_ana_reg: ab8500_ldo_ana { - regulator-name = "V-CSI/DSI"; - }; - }; - }; - }; }; }; -- cgit v1.2.3 From 4a6cd43fb7a16ecb08d0cce40b35656c6447c7b8 Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Tue, 20 Aug 2013 18:40:27 +0200 Subject: dt: dbx5x0: remove mentor,musb binding The "mentor,musb" binding isn't documented so I was about to document it. The node is missing a few properties for configuration like "multipoint", "dyn_fifo", "num_eps" or "ram_bits". However I am not sure "missing" is the right word here because some of those informations might be obtained from the chip itself but it is not done (yet). Further the ePARP 2.3.1 says the matching goes from left to right taking the fist match. Right now there is jus a driver for "stericsson,db8500-musb" and none for "mentor,musb". I'm not 100% that it is simply possible to have a generic since even for DMA we have ifdefs in the driver between "generic mentor dma" and "ux500 dma" and I mean within musb and not the dma code. For that reason (that I am not sure a generic musb binding is possible and how its binding / required properties will look like) and the reason that we have here a minor binding without a driver to look at I suggest to remove that binding. If the majority of people prefer to keep this binding I'm curious how the documentation of the binding should look like. Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/usb/ux500-usb.txt | 2 +- arch/arm/boot/dts/ste-dbx5x0.dtsi | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/usb/ux500-usb.txt b/Documentation/devicetree/bindings/usb/ux500-usb.txt index 330d6ec15401..439a41c79afa 100644 --- a/Documentation/devicetree/bindings/usb/ux500-usb.txt +++ b/Documentation/devicetree/bindings/usb/ux500-usb.txt @@ -15,7 +15,7 @@ Optional properties: Example: usb_per5@a03e0000 { - compatible = "stericsson,db8500-musb", "mentor,musb"; + compatible = "stericsson,db8500-musb"; reg = <0xa03e0000 0x10000>; interrupts = <0 23 0x4>; interrupt-names = "mc"; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 0c1338e36a83..111d062dc8cc 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -177,8 +177,7 @@ }; usb_per5@a03e0000 { - compatible = "stericsson,db8500-musb", - "mentor,musb"; + compatible = "stericsson,db8500-musb"; reg = <0xa03e0000 0x10000>; interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc"; -- cgit v1.2.3 From 841cd0c0d815901137418705f81bf3be08c801c1 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 18 Sep 2013 09:53:10 +0100 Subject: ARM: ux500: Add PRCMU clock node to DBx500 Device Tree Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 111d062dc8cc..3f94a5e6a231 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -10,6 +10,7 @@ */ #include +#include #include "skeleton.dtsi" / { @@ -42,6 +43,14 @@ interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; }; + clocks { + compatible = "stericsson,u8500-clks"; + + prcmu_clk: prcmu-clock { + #clock-cells = <1>; + }; + }; + timer@a0410600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xa0410600 0x20>; -- cgit v1.2.3 From e064cb24f249714cc9ce4e9b8f19d8afb395db4c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 3 Jun 2013 13:13:54 +0100 Subject: ARM: ux500: Supply the DMA clock lookup to the DBX500 DT Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 3f94a5e6a231..ac43e6f999c9 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -228,6 +228,8 @@ #dma-cells = <3>; memcpy-channels = <56 57 58 59 60>; + + clocks = <&prcmu_clk PRCMU_DMACLK>; }; prcmu: prcmu@80157000 { -- cgit v1.2.3 From fcbe5e90f87fa45da40d39c7da8709b403c7e8a0 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 6 Jun 2013 10:51:04 +0100 Subject: ARM: ux500: Add PRCC Peripheral clock node to DBx500 Device Tree Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index ac43e6f999c9..505404e4d3e4 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -49,6 +49,10 @@ prcmu_clk: prcmu-clock { #clock-cells = <1>; }; + + prcc_pclk: prcc-periph-clock { + #clock-cells = <2>; + }; }; timer@a0410600 { -- cgit v1.2.3 From 9d8910737413415114eb72d7b03f4b5c1f305c75 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 3 Jun 2013 13:07:51 +0100 Subject: ARM: ux500: Supply the GPIO clocks lookup to the DBX500 DT Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 505404e4d3e4..da188a2078ab 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -78,6 +78,8 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <0>; + + clocks = <&prcc_pclk 1 9>; }; gpio1: gpio@8012e080 { @@ -91,6 +93,8 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <1>; + + clocks = <&prcc_pclk 1 9>; }; gpio2: gpio@8000e000 { @@ -104,6 +108,8 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <2>; + + clocks = <&prcc_pclk 3 8>; }; gpio3: gpio@8000e080 { @@ -117,6 +123,8 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <3>; + + clocks = <&prcc_pclk 3 8>; }; gpio4: gpio@8000e100 { @@ -130,6 +138,8 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <4>; + + clocks = <&prcc_pclk 3 8>; }; gpio5: gpio@8000e180 { @@ -143,6 +153,8 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <5>; + + clocks = <&prcc_pclk 3 8>; }; gpio6: gpio@8011e000 { @@ -156,6 +168,8 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <6>; + + clocks = <&prcc_pclk 2 1>; }; gpio7: gpio@8011e080 { @@ -169,6 +183,8 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <7>; + + clocks = <&prcc_pclk 2 1>; }; gpio8: gpio@a03fe000 { @@ -182,6 +198,8 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <8>; + + clocks = <&prcc_pclk 6 1>; }; pinctrl { -- cgit v1.2.3 From e47339fff2e01fb3edbbd3a284e6f7101dd89cb0 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 3 Jun 2013 13:08:26 +0100 Subject: ARM: ux500: Supply the USB clock lookup to the DBX500 DT Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index da188a2078ab..244e44a7f696 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -240,6 +240,8 @@ "iep_6_14", "oep_6_14", "iep_7_15", "oep_7_15", "iep_8", "oep_8"; + + clocks = <&prcc_pclk 5 0>; }; dma: dma-controller@801C0000 { -- cgit v1.2.3 From 7fb2afc781cdc4db2d16b65bdee98dc615f4df20 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 3 Jun 2013 13:06:13 +0100 Subject: ARM: ux500: Supply the Ethernet clock lookup to Snowball's DT Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-snowball.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index acf99ece8499..3abec3205f13 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -111,12 +111,13 @@ vdd33a-supply = <&en_3v3_reg>; vddvario-supply = <&db8500_vape_reg>; - reg-shift = <1>; reg-io-width = <2>; smsc,force-internal-phy; smsc,irq-active-high; smsc,irq-push-pull; + + clocks = <&prcc_pclk 3 0>; }; }; -- cgit v1.2.3 From 2588fea6a531a15a6b926d0cdaff6dd6242d8dfd Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 6 Jun 2013 10:52:50 +0100 Subject: ARM: ux500: Add PRCC Kernel clock node to DBx500 Device Tree Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 244e44a7f696..3accea064e3e 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -53,6 +53,10 @@ prcc_pclk: prcc-periph-clock { #clock-cells = <2>; }; + + prcc_kclk: prcc-kernel-clock { + #clock-cells = <2>; + }; }; timer@a0410600 { -- cgit v1.2.3 From afd653e97d289cfc311f01f510864edd5f4a6f45 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 3 Jun 2013 13:15:22 +0100 Subject: ARM: ux500: Supply the I2C clocks lookup to the DBX500 DT Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 3accea064e3e..924490256b4d 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -603,6 +603,8 @@ v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; + clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; + clock-names = "i2cclk", "apb_pclk"; }; i2c@80122000 { @@ -615,6 +617,9 @@ v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; + + clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; + clock-names = "i2cclk", "apb_pclk"; }; i2c@80128000 { @@ -627,6 +632,9 @@ v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; + + clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; + clock-names = "i2cclk", "apb_pclk"; }; i2c@80110000 { @@ -639,6 +647,9 @@ v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; + + clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; + clock-names = "i2cclk", "apb_pclk"; }; i2c@8012a000 { @@ -651,6 +662,9 @@ v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; + + clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 9>; + clock-names = "i2cclk", "apb_pclk"; }; ssp@80002000 { -- cgit v1.2.3 From 5a323fb4f759fe5327e22d45f2ef761330ce7015 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 3 Jun 2013 13:17:17 +0100 Subject: ARM: ux500: Supply the UART clocks lookup to the DBX500 DT Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 924490256b4d..fe3df41fddb7 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -685,6 +685,9 @@ <&dma 13 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; + clock-names = "uart", "apb_pclk"; + status = "disabled"; }; @@ -697,6 +700,9 @@ <&dma 12 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; + clock-names = "uart", "apb_pclk"; + status = "disabled"; }; @@ -709,6 +715,9 @@ <&dma 11 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; + clock-names = "uart", "apb_pclk"; + status = "disabled"; }; -- cgit v1.2.3 From 604be898461dd49bbd2024eb65443e590da3177a Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 6 Jun 2013 12:28:50 +0100 Subject: ARM: ux500: Supply the SDI (MMC) clocks lookup to the DBX500 DT Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index fe3df41fddb7..981107f115fe 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -730,6 +730,9 @@ <&dma 29 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; + clock-names = "sdi", "apb_pclk"; + status = "disabled"; }; @@ -742,6 +745,9 @@ <&dma 32 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; + clock-names = "sdi", "apb_pclk"; + status = "disabled"; }; @@ -754,6 +760,9 @@ <&dma 28 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; + clock-names = "sdi", "apb_pclk"; + status = "disabled"; }; @@ -761,6 +770,10 @@ compatible = "arm,pl18x", "arm,primecell"; reg = <0x80119000 0x1000>; interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; + clock-names = "sdi", "apb_pclk"; + status = "disabled"; }; @@ -773,6 +786,9 @@ <&dma 42 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; + clock-names = "sdi", "apb_pclk"; + status = "disabled"; }; @@ -780,6 +796,10 @@ compatible = "arm,pl18x", "arm,primecell"; reg = <0x80008000 0x1000>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; + clock-names = "sdi", "apb_pclk"; + status = "disabled"; }; -- cgit v1.2.3 From 133e6027e7afee018bf189187a2cb9c8b7224208 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 3 Jun 2013 13:18:00 +0100 Subject: ARM: ux500: Supply the MSP (Audio) clocks lookup to the DBX500 DT Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 981107f115fe..5b11c7bb93f3 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -808,6 +808,10 @@ reg = <0x80123000 0x1000>; interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + + clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; + clock-names = "msp", "apb_pclk"; + status = "disabled"; }; @@ -816,6 +820,10 @@ reg = <0x80124000 0x1000>; interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + + clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; + clock-names = "msp", "apb_pclk"; + status = "disabled"; }; @@ -825,6 +833,10 @@ reg = <0x80117000 0x1000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + + clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; + clock-names = "msp", "apb_pclk"; + status = "disabled"; }; @@ -833,6 +845,10 @@ reg = <0x80125000 0x1000>; interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + + clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; + clock-names = "msp", "apb_pclk"; + status = "disabled"; }; -- cgit v1.2.3 From 589d9839df6a5955eeda785a164e515d35ac3cad Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 6 Jun 2013 10:54:27 +0100 Subject: ARM: ux500: Add RTC (fixed-frequency) clock node to DBx500 Device Tree Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 5b11c7bb93f3..60e8c198e981 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -57,6 +57,10 @@ prcc_kclk: prcc-kernel-clock { #clock-cells = <2>; }; + + rtc_clk: rtc32k-clock { + #clock-cells = <0>; + }; }; timer@a0410600 { -- cgit v1.2.3 From d299b5a5ee96cae1639968429a89cb5e76e1f4f9 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 5 Jun 2013 12:27:24 +0100 Subject: ARM: ux500: Supply the RTC clock lookup to the DBX500 DT Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 60e8c198e981..8c52f3f28b62 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -73,6 +73,9 @@ compatible = "arm,rtc-pl031", "arm,primecell"; reg = <0x80154000 0x1000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&rtc_clk>; + clock-names = "apb_pclk"; }; gpio0: gpio@8012e000 { -- cgit v1.2.3 From 309012d7e0c136211957755288d74e243af40201 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 6 Jun 2013 10:54:48 +0100 Subject: ARM: ux500: Add TWD (fixed-factor) clock node to DBx500 Device Tree Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 8c52f3f28b62..cc45052ce0b9 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -61,6 +61,10 @@ rtc_clk: rtc32k-clock { #clock-cells = <0>; }; + + smp_twd_clk: smp-twd-clock { + #clock-cells = <0>; + }; }; timer@a0410600 { -- cgit v1.2.3 From a8acb1ecc5490645a9fc53ecc5181dae9ba8703f Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 5 Jun 2013 12:26:52 +0100 Subject: ARM: ux500: Supply the TWD Timer clock lookup to the DBX500 DT Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index cc45052ce0b9..80b0304dd441 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -71,6 +71,8 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xa0410600 0x20>; interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ + + clocks = <&smp_twd_clk>; }; rtc@80154000 { -- cgit v1.2.3 From 8132ed1bb81471b3ced3cdcd7a7f46caff4c2a2f Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 18 Sep 2013 09:54:07 +0100 Subject: ARM: ux500: Add a DT node for the Nomadik System Timer (MTU0) The MTU0 is required for full booting of the system. The driver has been previously DT:ed and is in use on the Nomadik platform, but we also need to enable it on ux500 based systems. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 80b0304dd441..c417cb8a24ab 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -43,6 +43,7 @@ interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; }; + clocks { compatible = "stericsson,u8500-clks"; @@ -67,6 +68,16 @@ }; }; + mtu@a03c6000 { + /* Nomadik System Timer */ + compatible = "st,nomadik-mtu"; + reg = <0xa03c6000 0x1000>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; + clock-names = "timclk", "apb_pclk"; + }; + timer@a0410600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xa0410600 0x20>; -- cgit v1.2.3 From d460d28bfb516afe44a85a4738c459f18de582ce Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 18 Sep 2013 16:05:04 +0100 Subject: ARM: ux500: Fix trivial white-space error in the DBX500 DTSI file Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index c417cb8a24ab..23810f233774 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -888,7 +888,7 @@ cpufreq-cooling { compatible = "stericsson,db8500-cpufreq-cooling"; status = "disabled"; - }; + }; vmmci: regulator-gpio { compatible = "regulator-gpio"; -- cgit v1.2.3 From d2f898cec8c2971b49fd872551924e902d2f627f Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 18 Sep 2013 16:05:52 +0100 Subject: ARM: ux500: Provide a clock lookup for the Crypto driver The common clock framework will use the 'clock' property provided to do a clock lookup when Device Tree is enabled. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 23810f233774..c4000179794e 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -913,6 +913,7 @@ interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + clocks = <&prcc_pclk 6 1>; }; hash@a03c2000 { -- cgit v1.2.3 From 024cfe880b4eafe6dfb81380ae39dc0ad2b48180 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 18 Sep 2013 16:07:27 +0100 Subject: ARM: ux500: Provide a clock lookup for the Hash driver The common clock framework will use the 'clock' property provided to do a clock lookup when Device Tree is enabled. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index c4000179794e..8c8af1502054 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -921,6 +921,7 @@ reg = <0xa03c2000 0x1000>; v-ape-supply = <&db8500_vape_reg>; + clocks = <&prcc_pclk 6 2>; }; }; }; -- cgit v1.2.3 From 985856167d4b5c5cb5c326bd52cf17444658ae9c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 18 Sep 2013 16:07:44 +0100 Subject: ARM: ux500: Provide a Device Tree node for CPUFreq in the DBx500 This is required to fetch the ARMSS clock when booting with DT. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 8c8af1502054..2ef30c1c1997 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -300,6 +300,13 @@ reg = <0x80157450 0xC>; }; + cpufreq { + compatible = "stericsson,cpufreq-ux500"; + clocks = <&prcmu_clk PRCMU_ARMSS>; + clock-names = "armss"; + status = "disabled"; + }; + thermal@801573c0 { compatible = "stericsson,db8500-thermal"; reg = <0x801573c0 0x40>; -- cgit v1.2.3 From 6cb7ea99fd83c9cd23c3f3dc75d987913f572e9b Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 18 Sep 2013 16:03:07 +0100 Subject: ARM: ux500: Enable CPUFreq on Snowball Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-snowball.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 3abec3205f13..f0b39f835914 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -171,6 +171,10 @@ }; prcmu@80157000 { + cpufreq { + status = "okay"; + }; + thermal@801573c0 { num-trips = <4>; -- cgit v1.2.3 From 385d61ce267ce5ff09dec17bff2ef03098aaf725 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 15 Sep 2013 12:01:07 +0200 Subject: ARM: ux500: add default trigger on HREF LED This adds a heartbeat on the first LED on the ux500 HREF boards. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index f88a659aea3b..5e7cf4bf5afb 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -72,6 +72,7 @@ chan0 { led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; + linux,default-trigger = "heartbeat"; }; chan1 { led-cur = /bits/ 8 <0x2f>; -- cgit v1.2.3 From c90c36e4bceed4cb61853c3382abbc765ad46ef5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 26 Sep 2013 15:09:14 +0200 Subject: ARM: ux500 enable the AB8500 gpio for all HREFs The AB8500 GPIO was only registered for the pre-v60 HREF but should be made available on all HREF variants, move the DT entry to the common file. Cc: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href.dtsi | 4 ++++ arch/arm/boot/dts/ste-hrefprev60.dts | 8 -------- 2 files changed, 4 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 5e7cf4bf5afb..d6753261796b 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -169,6 +169,10 @@ prcmu@80157000 { ab8500 { + ab8500-gpio { + compatible = "stericsson,ab8500-gpio"; + }; + ab8500-regulators { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dts b/arch/arm/boot/dts/ste-hrefprev60.dts index d8d3b99ab007..767fa21e4881 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dts +++ b/arch/arm/boot/dts/ste-hrefprev60.dts @@ -25,14 +25,6 @@ }; soc { - prcmu@80157000 { - ab8500@5 { - ab8500-gpio { - compatible = "stericsson,ab8500-gpio"; - }; - }; - }; - i2c@80004000 { tps61052@33 { compatible = "tps61052"; -- cgit v1.2.3 From 5550e8e9cde86a665ba04b26cc910676ce228094 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 26 Sep 2013 13:16:16 +0200 Subject: ARM: dts: mxs: Add muxing options for the SSP2 MMC Add pinmux for 4-bit SD card connected to SSP2. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 918d419772dd..1c5ed9dbebb5 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -473,6 +473,37 @@ fsl,pull-up = ; }; + mmc2_4bit_pins_a: mmc2-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA4__SSP2_D0 + MX28_PAD_SSP1_SCK__SSP2_D1 + MX28_PAD_SSP1_CMD__SSP2_D2 + MX28_PAD_SSP0_DATA5__SSP2_D3 + MX28_PAD_SSP0_DATA6__SSP2_CMD + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT + MX28_PAD_SSP0_DATA7__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc2_cd_cfg: mmc2-cd-cfg { + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT + >; + fsl,pull-up = ; + }; + + mmc2_sck_cfg: mmc2-sck-cfg { + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA7__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,pull-up = ; + }; + i2c0_pins_a: i2c0@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v1.2.3 From 40cdaa542cf0c570600c29b006b782631d07d052 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 26 Sep 2013 17:43:52 -0300 Subject: ARM: dts: imx6q-udoo: Add initial board support For more information about the Udoo board: http://www.udoo.org/ Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6q-udoo.dts | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-udoo.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c703da2581cf..909561081711 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -140,6 +140,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ imx6q-sbc6x.dtb \ + imx6q-udoo.dtb \ imx6q-wandboard.dtb \ imx6sl-evk.dtb \ vf610-cosmic.dtb \ diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts new file mode 100644 index 000000000000..6e1ccdc019a7 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-udoo.dts @@ -0,0 +1,39 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/dts-v1/; +#include "imx6q.dtsi" + +/ { + model = "Udoo i.MX6 Quad Board"; + compatible = "udoo,imx6q-udoo", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x40000000>; + }; +}; + +&sata { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_2>; + non-removable; + status = "okay"; +}; -- cgit v1.2.3 From 3a57291fa4ca7f7647d826f5b47082ef306d839f Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Thu, 26 Sep 2013 10:51:09 +0800 Subject: ARM: dts: imx6qdl: add pcie device node Add pcie device node for imx6qdl. Signed-off-by: Sean Cross Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index ef51342be314..59154dc15fe4 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -116,6 +116,22 @@ arm,data-latency = <4 2 3>; }; + pcie: pcie@0x01000000 { + compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; + reg = <0x01ffc000 0x4000>; /* DBI */ + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ + 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <0 123 0x04>; + clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; + clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; + status = "disabled"; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 94 0x04>; -- cgit v1.2.3 From c986d35e9149295b1f28ea1410b2d84315374fd3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 27 Sep 2013 11:12:40 -0300 Subject: ARM: dts: imx6q-sabrelite: Add ethernet phy reset pin into hog MX6QDL_PAD_EIM_D23__GPIO3_IO23 pin is used to reset the ethernet phy. Add it to the 'hog' group. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabrelite.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index e1c1777a80d5..f004913f7d80 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -123,6 +123,7 @@ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 >; }; }; -- cgit v1.2.3 From c5f592d1cb64cb46b2bb1ac54734c1247fd1331b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 27 Sep 2013 11:12:41 -0300 Subject: ARM: dts: imx6qdl-sabresd: Provide phy-reset-gpios GPIO1_25 is used to reset the ethernet phy. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 64e454bcc4a3..2035d6698ec5 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -108,6 +108,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet_1>; phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 25 0>; status = "okay"; }; @@ -172,6 +173,7 @@ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 >; }; }; -- cgit v1.2.3 From 80121372ec26eb1871e62688f74316f4fd838beb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 27 Sep 2013 11:12:42 -0300 Subject: ARM: dts: imx6qdl-wandboard: Provide phy-reset-gpios GPIO3_29 is used to reset the ethernet phy. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index df42d3ccb70e..35f547929167 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -88,6 +88,7 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 >; }; }; @@ -97,6 +98,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet_1>; phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 29 0>; status = "okay"; }; -- cgit v1.2.3 From c1f95979baa9c33c5e6c280d7a8742fad0d20326 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 29 Aug 2013 08:22:17 +0900 Subject: ARM: shmobile: Add r8a7790 CA15 CPU cores Add CA15 CPU cores to r8a7790 for a total of 4 x CA15. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 3b879e7c697c..388f49f675bb 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -24,6 +24,27 @@ reg = <0>; clock-frequency = <1300000000>; }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1300000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + clock-frequency = <1300000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + clock-frequency = <1300000000>; + }; }; gic: interrupt-controller@f1001000 { -- cgit v1.2.3 From 2007e74ca3769fd353fe87a7a105c14102d7980c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Sun, 15 Sep 2013 00:28:58 +0900 Subject: ARM: shmobile: Add r8a7790 CA7 CPU cores to DTSI Add r8a7790 Cortex-A7 CPU information to DTSI. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 388f49f675bb..a0cfb6618884 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -45,6 +45,34 @@ reg = <3>; clock-frequency = <1300000000>; }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <780000000>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <780000000>; + }; + + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <780000000>; + }; + + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <780000000>; + }; }; gic: interrupt-controller@f1001000 { -- cgit v1.2.3 From 86178f862defd293c7ac3eb2073759a52ba2518c Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 9 Aug 2013 22:27:13 +0200 Subject: ARM: mvebu: the MPIC now provides MSI controller features Adds the 'msi-controller' property to the main interrupt controller Device Tree node, to indicate that it can now behave as a MSI controller. Signed-off-by: Thomas Petazzoni Reviewed-by: Thierry Reding Tested-by: Daniel Price Acked-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 57dbc5dbc360..534e1be80df2 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -113,6 +113,7 @@ #interrupt-cells = <1>; #size-cells = <1>; interrupt-controller; + msi-controller; }; coherency-fabric@20200 { -- cgit v1.2.3 From d4fa99417a0701c7aebe2d53ff65b3048985b310 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 9 Aug 2013 22:27:15 +0200 Subject: ARM: mvebu: link PCIe controllers to the MSI controller This commit adjusts the Armada 370 and Armada XP PCIe controllers Device Tree informations to reference their MSI controller. In the case of this platform, the MSI controller is implemented by the MPIC. Signed-off-by: Thomas Petazzoni Tested-by: Daniel Price Acked-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 1 + 4 files changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index b8d376170959..7a4b82e71aaf 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -44,6 +44,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 0358a33cba48..3f5e6121c730 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -57,6 +57,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 0e82c5062243..3e9fd1353f89 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -58,6 +58,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index e82c1b80af17..31ba6d8fbadf 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -74,6 +74,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = -- cgit v1.2.3 From fbd99d51a7a7fd8344bf285f64200d72d4e6d2eb Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Mon, 29 Jul 2013 14:31:50 +0200 Subject: ARM: dove: use preprocessor on device tree files This coverts Dove DT board files to preprocessor includes instead of dtc includes. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove-cm-a510.dts | 2 +- arch/arm/boot/dts/dove-cubox.dts | 2 +- arch/arm/boot/dts/dove-d2plug.dts | 2 +- arch/arm/boot/dts/dove-dove-db.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts index 61a8062e56de..50c0d6904497 100644 --- a/arch/arm/boot/dts/dove-cm-a510.dts +++ b/arch/arm/boot/dts/dove-cm-a510.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "dove.dtsi" +#include "dove.dtsi" / { model = "Compulab CM-A510"; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 022646ef4b38..4af59b6dce0f 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "dove.dtsi" +#include "dove.dtsi" / { model = "SolidRun CuBox"; diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts index e2222ce94f2f..c11d3636c8e5 100644 --- a/arch/arm/boot/dts/dove-d2plug.dts +++ b/arch/arm/boot/dts/dove-d2plug.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "dove.dtsi" +#include "dove.dtsi" / { model = "Globalscale D2Plug"; diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts index e5a920beab45..bb725dca3a10 100644 --- a/arch/arm/boot/dts/dove-dove-db.dts +++ b/arch/arm/boot/dts/dove-dove-db.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "dove.dtsi" +#include "dove.dtsi" / { model = "Marvell DB-MV88AP510-BP Development Board"; -- cgit v1.2.3 From 6953af7749cd023770b948865cb8efa738cc6473 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Mon, 29 Jul 2013 14:31:51 +0200 Subject: ARM: dove: add MBUS_ID macro to Dove DT This adds a macro used for defining address window's target ID and attribute cells for the MBus ranges entry. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index cc279166646f..0b4b8ec966c4 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -1,5 +1,7 @@ /include/ "skeleton.dtsi" +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + / { compatible = "marvell,dove"; model = "Marvell Armada 88AP510 SoC"; -- cgit v1.2.3 From 960ee4e7967f0d0bdebae439e79f94cec78e23f7 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Mon, 29 Jul 2013 14:31:52 +0200 Subject: ARM: dove: add MBus DT node This adds a MBus node including ranges and pcie apertures required later. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 0b4b8ec966c4..d312290edfc1 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -29,6 +29,21 @@ marvell,tauros2-cache-features = <0>; }; + mbus { + compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ + pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ + + ranges = ; /* PMU SRAM 1M */ + }; + soc@f1000000 { compatible = "simple-bus"; #address-cells = <1>; @@ -44,6 +59,11 @@ 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */ 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */ + mbusc: mbus-ctrl@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x80>, <0x800100 0x8>; + }; + timer: timer@20300 { compatible = "marvell,orion-timer"; reg = <0x20300 0x20>; -- cgit v1.2.3 From 0ad44659355d5c2efdd5b6c1de165ca31cb34fa8 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Mon, 29 Jul 2013 14:31:53 +0200 Subject: ARM: dove: relocate internal registers device nodes With mbus node in place, now relocate all internal device nodes to internal-regs node with proper address ranges. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 955 ++++++++++++++++++++++---------------------- 1 file changed, 474 insertions(+), 481 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index d312290edfc1..d42b323e7593 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -5,6 +5,7 @@ / { compatible = "marvell,dove"; model = "Marvell Armada 88AP510 SoC"; + interrupt-parent = <&intc>; aliases { gpio0 = &gpio0; @@ -42,489 +43,481 @@ MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */ MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ - }; - - soc@f1000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */ - 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */ - 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */ - 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */ - 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */ - 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */ - 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */ - 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */ - - mbusc: mbus-ctrl@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x800100 0x8>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - intc: main-interrupt-ctrl@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - marvell,#interrupts = <5>; - }; - - core_clk: core-clocks@d0214 { - compatible = "marvell,dove-core-clock"; - reg = <0xd0214 0x4>; - #clock-cells = <1>; - }; - - gate_clk: clock-gating-ctrl@d0038 { - compatible = "marvell,dove-gating-clock"; - reg = <0xd0038 0x4>; - clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - thermal: thermal-diode@d001c { - compatible = "marvell,dove-thermal"; - reg = <0xd001c 0x0c>, <0xd005c 0x08>; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <7>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <8>; - clocks = <&core_clk 0>; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart2: serial@12200 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart3: serial@12300 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - gpio0: gpio-ctrl@d0400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xd0400 0x20>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <12>, <13>, <14>, <60>; - }; - - gpio1: gpio-ctrl@d0420 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xd0420 0x20>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <61>; - }; - - gpio2: gpio-ctrl@e8400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xe8400 0x0c>; - ngpios = <8>; - }; - - pinctrl: pin-ctrl@d0200 { - compatible = "marvell,dove-pinctrl"; - reg = <0xd0200 0x10>; - clocks = <&gate_clk 22>; - - pmx_gpio_0: pmx-gpio-0 { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_gpio_1: pmx-gpio-1 { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_gpio_2: pmx-gpio-2 { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_gpio_3: pmx-gpio-3 { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_gpio_4: pmx-gpio-4 { - marvell,pins = "mpp4"; - marvell,function = "gpio"; - }; - - pmx_gpio_5: pmx-gpio-5 { - marvell,pins = "mpp5"; - marvell,function = "gpio"; - }; - - pmx_gpio_6: pmx-gpio-6 { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - pmx_gpio_7: pmx-gpio-7 { - marvell,pins = "mpp7"; - marvell,function = "gpio"; - }; - - pmx_gpio_8: pmx-gpio-8 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - - pmx_gpio_9: pmx-gpio-9 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_gpio_10: pmx-gpio-10 { - marvell,pins = "mpp10"; - marvell,function = "gpio"; - }; - - pmx_gpio_11: pmx-gpio-11 { - marvell,pins = "mpp11"; - marvell,function = "gpio"; - }; - - pmx_gpio_12: pmx-gpio-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_gpio_13: pmx-gpio-13 { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_gpio_14: pmx-gpio-14 { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_gpio_15: pmx-gpio-15 { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_gpio_16: pmx-gpio-16 { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_gpio_17: pmx-gpio-17 { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_gpio_18: pmx-gpio-18 { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - pmx_gpio_19: pmx-gpio-19 { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; - - pmx_gpio_20: pmx-gpio-20 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_gpio_21: pmx-gpio-21 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_camera: pmx-camera { - marvell,pins = "mpp_camera"; - marvell,function = "camera"; - }; - - pmx_camera_gpio: pmx-camera-gpio { - marvell,pins = "mpp_camera"; - marvell,function = "gpio"; - }; - - pmx_sdio0: pmx-sdio0 { - marvell,pins = "mpp_sdio0"; - marvell,function = "sdio0"; - }; - - pmx_sdio0_gpio: pmx-sdio0-gpio { - marvell,pins = "mpp_sdio0"; - marvell,function = "gpio"; - }; - - pmx_sdio1: pmx-sdio1 { - marvell,pins = "mpp_sdio1"; - marvell,function = "sdio1"; - }; - - pmx_sdio1_gpio: pmx-sdio1-gpio { - marvell,pins = "mpp_sdio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_gpio: pmx-audio1-gpio { - marvell,pins = "mpp_audio1"; - marvell,function = "gpio"; - }; - - pmx_spi0: pmx-spi0 { - marvell,pins = "mpp_spi0"; - marvell,function = "spi0"; - }; - - pmx_spi0_gpio: pmx-spi0-gpio { - marvell,pins = "mpp_spi0"; - marvell,function = "gpio"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp_uart1"; - marvell,function = "uart1"; - }; - - pmx_uart1_gpio: pmx-uart1-gpio { - marvell,pins = "mpp_uart1"; - marvell,function = "gpio"; - }; - - pmx_nand: pmx-nand { - marvell,pins = "mpp_nand"; - marvell,function = "nand"; - }; - - pmx_nand_gpo: pmx-nand-gpo { - marvell,pins = "mpp_nand"; - marvell,function = "gpo"; - }; - }; - - spi0: spi-ctrl@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <6>; - reg = <0x10600 0x28>; - clocks = <&core_clk 0>; - pinctrl-0 = <&pmx_spi0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - spi1: spi-ctrl@14600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <5>; - reg = <0x14600 0x28>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - i2c0: i2c-ctrl@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <11>; - clock-frequency = <400000>; - timeout-ms = <1000>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - ehci0: usb-host@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <24>; - clocks = <&gate_clk 0>; - status = "okay"; - }; - - ehci1: usb-host@51000 { - compatible = "marvell,orion-ehci"; - reg = <0x51000 0x1000>; - interrupts = <25>; - clocks = <&gate_clk 1>; - status = "okay"; - }; - - sdio0: sdio-host@92000 { - compatible = "marvell,dove-sdhci"; - reg = <0x92000 0x100>; - interrupts = <35>, <37>; - clocks = <&gate_clk 8>; - pinctrl-0 = <&pmx_sdio0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sdio1: sdio-host@90000 { - compatible = "marvell,dove-sdhci"; - reg = <0x90000 0x100>; - interrupts = <36>, <38>; - clocks = <&gate_clk 9>; - pinctrl-0 = <&pmx_sdio1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sata0: sata-host@a0000 { - compatible = "marvell,orion-sata"; - reg = <0xa0000 0x2400>; - interrupts = <62>; - clocks = <&gate_clk 3>; - nr-ports = <1>; - status = "disabled"; - }; - - rtc: real-time-clock@d8500 { - compatible = "marvell,orion-rtc"; - reg = <0xd8500 0x20>; - }; - - crypto: crypto-engine@30000 { - compatible = "marvell,orion-crypto"; - reg = <0x30000 0x10000>, - <0xc8000000 0x800>; - reg-names = "regs", "sram"; - interrupts = <31>; - clocks = <&gate_clk 15>; - status = "okay"; - }; - - xor0: dma-engine@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gate_clk 23>; - status = "okay"; - - channel0 { - interrupts = <39>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <40>; - dmacap,memset; - dmacap,memcpy; - dmacap,xor; - }; - }; - - xor1: dma-engine@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gate_clk 24>; - status = "okay"; - - channel0 { - interrupts = <42>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <43>; - dmacap,memset; - dmacap,memcpy; - dmacap,xor; - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <30>; - clocks = <&gate_clk 2>; - status = "disabled"; - - ethphy: ethernet-phy { - device-type = "ethernet-phy"; - /* set phy address in board file */ - }; - }; - eth: ethernet-controller@72000 { - compatible = "marvell,orion-eth"; + internal-regs { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - clocks = <&gate_clk 2>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - ethernet-port@0 { - device_type = "network"; - compatible = "marvell,orion-eth-port"; - reg = <0>; - interrupts = <29>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - phy-handle = <ðphy>; + #size-cells = <1>; + ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */ + 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */ + 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ + 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ + + mbusc: mbus-ctrl@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x80>, <0x800100 0x8>; + }; + + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; + + intc: main-interrupt-ctrl@20200 { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20200 0x10>, <0x20210 0x10>; + }; + + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <0>; + marvell,#interrupts = <5>; + }; + + core_clk: core-clocks@d0214 { + compatible = "marvell,dove-core-clock"; + reg = <0xd0214 0x4>; + #clock-cells = <1>; + }; + + gate_clk: clock-gating-ctrl@d0038 { + compatible = "marvell,dove-gating-clock"; + reg = <0xd0038 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + + thermal: thermal-diode@d001c { + compatible = "marvell,dove-thermal"; + reg = <0xd001c 0x0c>, <0xd005c 0x08>; + }; + + uart0: serial@12000 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <7>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&core_clk 0>; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart2: serial@12200 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + uart3: serial@12300 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + gpio0: gpio-ctrl@d0400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xd0400 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <12>, <13>, <14>, <60>; + }; + + gpio1: gpio-ctrl@d0420 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xd0420 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <61>; + }; + + gpio2: gpio-ctrl@e8400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xe8400 0x0c>; + ngpios = <8>; + }; + + pinctrl: pin-ctrl@d0200 { + compatible = "marvell,dove-pinctrl"; + reg = <0xd0200 0x10>; + clocks = <&gate_clk 22>; + + pmx_gpio_0: pmx-gpio-0 { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_gpio_1: pmx-gpio-1 { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_gpio_2: pmx-gpio-2 { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_gpio_3: pmx-gpio-3 { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_gpio_4: pmx-gpio-4 { + marvell,pins = "mpp4"; + marvell,function = "gpio"; + }; + + pmx_gpio_5: pmx-gpio-5 { + marvell,pins = "mpp5"; + marvell,function = "gpio"; + }; + + pmx_gpio_6: pmx-gpio-6 { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + pmx_gpio_7: pmx-gpio-7 { + marvell,pins = "mpp7"; + marvell,function = "gpio"; + }; + + pmx_gpio_8: pmx-gpio-8 { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + pmx_gpio_9: pmx-gpio-9 { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_gpio_10: pmx-gpio-10 { + marvell,pins = "mpp10"; + marvell,function = "gpio"; + }; + + pmx_gpio_11: pmx-gpio-11 { + marvell,pins = "mpp11"; + marvell,function = "gpio"; + }; + + pmx_gpio_12: pmx-gpio-12 { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_gpio_13: pmx-gpio-13 { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_gpio_14: pmx-gpio-14 { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_gpio_15: pmx-gpio-15 { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_gpio_16: pmx-gpio-16 { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_gpio_17: pmx-gpio-17 { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_gpio_18: pmx-gpio-18 { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + + pmx_gpio_19: pmx-gpio-19 { + marvell,pins = "mpp19"; + marvell,function = "gpio"; + }; + + pmx_gpio_20: pmx-gpio-20 { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + + pmx_gpio_21: pmx-gpio-21 { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_camera: pmx-camera { + marvell,pins = "mpp_camera"; + marvell,function = "camera"; + }; + + pmx_camera_gpio: pmx-camera-gpio { + marvell,pins = "mpp_camera"; + marvell,function = "gpio"; + }; + + pmx_sdio0: pmx-sdio0 { + marvell,pins = "mpp_sdio0"; + marvell,function = "sdio0"; + }; + + pmx_sdio0_gpio: pmx-sdio0-gpio { + marvell,pins = "mpp_sdio0"; + marvell,function = "gpio"; + }; + + pmx_sdio1: pmx-sdio1 { + marvell,pins = "mpp_sdio1"; + marvell,function = "sdio1"; + }; + + pmx_sdio1_gpio: pmx-sdio1-gpio { + marvell,pins = "mpp_sdio1"; + marvell,function = "gpio"; + }; + + pmx_audio1_gpio: pmx-audio1-gpio { + marvell,pins = "mpp_audio1"; + marvell,function = "gpio"; + }; + + pmx_spi0: pmx-spi0 { + marvell,pins = "mpp_spi0"; + marvell,function = "spi0"; + }; + + pmx_spi0_gpio: pmx-spi0-gpio { + marvell,pins = "mpp_spi0"; + marvell,function = "gpio"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp_uart1"; + marvell,function = "uart1"; + }; + + pmx_uart1_gpio: pmx-uart1-gpio { + marvell,pins = "mpp_uart1"; + marvell,function = "gpio"; + }; + + pmx_nand: pmx-nand { + marvell,pins = "mpp_nand"; + marvell,function = "nand"; + }; + + pmx_nand_gpo: pmx-nand-gpo { + marvell,pins = "mpp_nand"; + marvell,function = "gpo"; + }; + }; + + spi0: spi-ctrl@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <6>; + reg = <0x10600 0x28>; + clocks = <&core_clk 0>; + pinctrl-0 = <&pmx_spi0>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi1: spi-ctrl@14600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <5>; + reg = <0x14600 0x28>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + i2c0: i2c-ctrl@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <11>; + clock-frequency = <400000>; + timeout-ms = <1000>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + ehci0: usb-host@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <24>; + clocks = <&gate_clk 0>; + status = "okay"; + }; + + ehci1: usb-host@51000 { + compatible = "marvell,orion-ehci"; + reg = <0x51000 0x1000>; + interrupts = <25>; + clocks = <&gate_clk 1>; + status = "okay"; + }; + + sdio0: sdio-host@92000 { + compatible = "marvell,dove-sdhci"; + reg = <0x92000 0x100>; + interrupts = <35>, <37>; + clocks = <&gate_clk 8>; + pinctrl-0 = <&pmx_sdio0>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sdio1: sdio-host@90000 { + compatible = "marvell,dove-sdhci"; + reg = <0x90000 0x100>; + interrupts = <36>, <38>; + clocks = <&gate_clk 9>; + pinctrl-0 = <&pmx_sdio1>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sata0: sata-host@a0000 { + compatible = "marvell,orion-sata"; + reg = <0xa0000 0x2400>; + interrupts = <62>; + clocks = <&gate_clk 3>; + nr-ports = <1>; + status = "disabled"; + }; + + rtc: real-time-clock@d8500 { + compatible = "marvell,orion-rtc"; + reg = <0xd8500 0x20>; + }; + + crypto: crypto-engine@30000 { + compatible = "marvell,orion-crypto"; + reg = <0x30000 0x10000>, + <0xffffe000 0x800>; + reg-names = "regs", "sram"; + interrupts = <31>; + clocks = <&gate_clk 15>; + status = "okay"; + }; + + xor0: dma-engine@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gate_clk 23>; + status = "okay"; + + channel0 { + interrupts = <39>; + dmacap,memcpy; + dmacap,xor; + }; + + channel1 { + interrupts = <40>; + dmacap,memcpy; + dmacap,xor; + }; + }; + + xor1: dma-engine@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gate_clk 24>; + status = "okay"; + + channel0 { + interrupts = <42>; + dmacap,memcpy; + dmacap,xor; + }; + + channel1 { + interrupts = <43>; + dmacap,memcpy; + dmacap,xor; + }; + }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <30>; + clocks = <&gate_clk 2>; + status = "disabled"; + + ethphy: ethernet-phy { + device-type = "ethernet-phy"; + /* set phy address in board file */ + }; + }; + + eth: ethernet-ctrl@72000 { + compatible = "marvell,orion-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72000 0x4000>; + clocks = <&gate_clk 2>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + ethernet-port@0 { + device_type = "network"; + compatible = "marvell,orion-eth-port"; + reg = <0>; + interrupts = <29>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <ðphy>; + }; }; }; }; -- cgit v1.2.3 From 74ecaa403a742b2c614a60e5ffef04a704d84071 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Mon, 12 Aug 2013 20:46:53 +0200 Subject: ARM: dove: add PCIe controllers to SoC DT This adds a node for the pcie controllers found on Dove SoCs to the SoC DT include. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 54 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index d42b323e7593..499abadf86f0 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -44,6 +44,60 @@ MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ + pcie: pcie-controller { + compatible = "marvell,dove-pcie"; + status = "disabled"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&intc>; + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 + 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 + 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ + 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ + 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ + 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ + + pcie-port@0 { + device_type = "pci"; + status = "disabled"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + clocks = <&gate_clk 4>; + marvell,pcie-port = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 16>; + }; + + pcie-port@1 { + device_type = "pci"; + status = "disabled"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + clocks = <&gate_clk 5>; + marvell,pcie-port = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 18>; + }; + }; + internal-regs { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From 37078732998e51c2645db99e7434ccc6774dafed Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Mon, 12 Aug 2013 20:46:54 +0200 Subject: ARM: dove: add initial DT file for Globalscale D3Plug This adds an initial DT file for the Globalscale D3Plug with Dove SoC. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/dove-d3plug.dts | 103 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 arch/arm/boot/dts/dove-d3plug.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index cc0f1fb61753..69193bedc88c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ dove-cubox.dtb \ dove-d2plug.dtb \ + dove-d3plug.dtb \ dove-dove-db.dtb dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/dove-d3plug.dts new file mode 100644 index 000000000000..f5f59bb5a534 --- /dev/null +++ b/arch/arm/boot/dts/dove-d3plug.dts @@ -0,0 +1,103 @@ +/dts-v1/; + +#include "dove.dtsi" + +/ { + model = "Globalscale D3Plug"; + compatible = "globalscale,d3plug", "marvell,dove"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p2 rw rootwait"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; + pinctrl-names = "default"; + + wlan-act { + label = "wlan-act"; + gpios = <&gpio0 0 1>; + }; + + wlan-ap { + label = "wlan-ap"; + gpios = <&gpio0 1 1>; + }; + + status { + label = "status"; + gpios = <&gpio0 2 1>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 8 0>; + pinctrl-0 = <&pmx_gpio_8>; + pinctrl-names = "default"; + }; + }; +}; + +&uart0 { status = "okay"; }; +&sata0 { status = "okay"; }; +&i2c0 { status = "okay"; }; + +/* Samsung M8G2F eMMC */ +&sdio0 { + status = "okay"; + non-removable; + bus-width = <4>; +}; + +/* Marvell SD8787 WLAN/BT */ +&sdio1 { + status = "okay"; + non-removable; +}; + +&spi0 { + status = "okay"; + + /* spi0.0: 2M Flash Macronix MX25L1605D */ + spi-flash@0 { + compatible = "st,m25l1605d"; + spi-max-frequency = <86000000>; + reg = <0>; + }; +}; + +&pcie { + status = "okay"; + /* Fresco Logic USB3.0 xHCI controller */ + pcie-port@0 { + status = "okay"; + reset-gpios = <&gpio0 26 1>; + reset-delay-us = <20000>; + pinctrl-0 = <&pmx_camera_gpio>; + pinctrl-names = "default"; + }; + /* Mini-PCIe slot */ + pcie-port@1 { + status = "okay"; + reset-gpios = <&gpio0 25 1>; + }; +}; -- cgit v1.2.3 From 7f69f8a4997ad12e062ddac8d6f996a50b26ebc2 Mon Sep 17 00:00:00 2001 From: Jason Gunthorpe Date: Tue, 17 Sep 2013 12:41:46 -0600 Subject: ARM: kirkwood: Remove kirkwood_setup_wins and rely on the DT binding kirkwood_setup_wins is the last manual caller of mbus in kirkwood, don't call it for DT boards and rely on the DT having a mbus node with a proper ranges property to setup these windows. Move all the mbus ranges properties for all boards into kirkwood.dtsi, since they are currently all the same. This makes the DT self consistent, since the physical address of the NAND and CRYPTO are both referenced internally. The arbitary Linux constants KIRKWOOD_NAND_MEM_PHYS_BASE and KIRKWOOD_SRAM_PHYS_BASE no longer have to match the DT values. Signed-off-by: Jason Gunthorpe Acked-by: Ezequiel Garcia Tested-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-db-88f6281.dts | 1 - arch/arm/boot/dts/kirkwood-db-88f6282.dts | 1 - arch/arm/boot/dts/kirkwood-iconnect.dts | 1 - arch/arm/boot/dts/kirkwood-mplcec4.dts | 1 - arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 1 - arch/arm/boot/dts/kirkwood-nsa310.dts | 1 - arch/arm/boot/dts/kirkwood-ts219-6282.dts | 1 - arch/arm/boot/dts/kirkwood.dtsi | 5 +++++ arch/arm/mach-kirkwood/board-dt.c | 1 - 9 files changed, 5 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts index 72c4b0a0366f..c39dd766c75a 100644 --- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts +++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts @@ -19,7 +19,6 @@ compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; mbus { - ranges = ; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts index 36c411d34926..701c6b6cdaa2 100644 --- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts +++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts @@ -19,7 +19,6 @@ compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; mbus { - ranges = ; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 0323f017eeed..b8150a768547 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -19,7 +19,6 @@ }; mbus { - ranges = ; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index ce2b94b513db..26ae24055d85 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -17,7 +17,6 @@ }; mbus { - ranges = ; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index 874857ea9cb8..d3a5a0fe4821 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -17,7 +17,6 @@ }; mbus { - ranges = ; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index 7aeae0c2c1f4..b5418bcaecce 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -15,7 +15,6 @@ }; mbus { - ranges = ; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index 9efcd2dc79d3..345562f75891 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -6,7 +6,6 @@ / { mbus { - ranges = ; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index cf7aeaf89e9c..d1bbe955b439 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -27,6 +27,11 @@ compatible = "marvell,kirkwood-mbus", "simple-bus"; #address-cells = <2>; #size-cells = <1>; + /* If a board file needs to change this ranges it must replace it completely */ + ranges = ; controller = <&mbusc>; pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 82d3ad8e87cf..f087b5f22425 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -92,7 +92,6 @@ static void __init kirkwood_dt_init(void) writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); BUG_ON(mvebu_mbus_dt_init()); - kirkwood_setup_wins(); kirkwood_l2_init(); -- cgit v1.2.3 From 34a300909e5e795500fcf7d3b971751fc65ed67b Mon Sep 17 00:00:00 2001 From: Jason Gunthorpe Date: Tue, 17 Sep 2013 12:43:09 -0600 Subject: ARM: kirkwood: Move the crypto node under the mbus node There should be no nodes that are not children of the mbus. Move the crypto node under the mbus. Signed-off-by: Jason Gunthorpe Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood.dtsi | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index d1bbe955b439..76b16271362a 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -35,13 +35,22 @@ controller = <&mbusc>; pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ + + crypto@0301 { + compatible = "marvell,orion-crypto"; + reg = , + ; + reg-names = "regs", "sram"; + interrupts = <22>; + clocks = <&gate_clk 17>; + status = "okay"; + }; }; ocp@f1000000 { compatible = "simple-bus"; ranges = <0x00000000 0xf1000000 0x0100000 - 0xf4000000 0xf4000000 0x0000400 - 0xf5000000 0xf5000000 0x0000400>; + 0xf4000000 0xf4000000 0x0000400>; #address-cells = <1>; #size-cells = <1>; @@ -222,16 +231,6 @@ status = "disabled"; }; - crypto@30000 { - compatible = "marvell,orion-crypto"; - reg = <0x30000 0x10000>, - <0xf5000000 0x800>; - reg-names = "regs", "sram"; - interrupts = <22>; - clocks = <&gate_clk 17>; - status = "okay"; - }; - mdio: mdio-bus@72004 { compatible = "marvell,orion-mdio"; #address-cells = <1>; -- cgit v1.2.3 From 7045ff5a5322fa7461d7255c15ad1896bd659440 Mon Sep 17 00:00:00 2001 From: Jason Gunthorpe Date: Tue, 17 Sep 2013 12:44:33 -0600 Subject: ARM: kirkwood: Move the nand node under the mbus node There should be no nodes that are not children of the mbus. Move the nand node under the mbus, and rework the board .dts files to use an & reference to the nand node. Signed-off-by: Jason Gunthorpe Acked-by: Ezequiel Garcia Tested-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-db.dtsi | 44 +++++------ arch/arm/boot/dts/kirkwood-dnskw.dtsi | 76 +++++++++---------- arch/arm/boot/dts/kirkwood-dockstar.dts | 40 +++++----- arch/arm/boot/dts/kirkwood-goflexnet.dts | 51 ++++++------- .../arm/boot/dts/kirkwood-guruplug-server-plus.dts | 40 +++++----- arch/arm/boot/dts/kirkwood-ib62x0.dts | 44 +++++------ arch/arm/boot/dts/kirkwood-iconnect.dts | 58 +++++++-------- arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 51 ++++++------- arch/arm/boot/dts/kirkwood-km_kirkwood.dts | 14 ++-- arch/arm/boot/dts/kirkwood-mplcec4.dts | 62 ++++++++-------- .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 60 +++++++-------- arch/arm/boot/dts/kirkwood-nsa310-common.dtsi | 86 +++++++++++----------- arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 74 +++++++++---------- arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi | 42 +++++------ arch/arm/boot/dts/kirkwood-topkick.dts | 62 ++++++++-------- arch/arm/boot/dts/kirkwood.dtsi | 31 ++++---- 16 files changed, 418 insertions(+), 417 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index c0e2a5879174..053aa20fb30f 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -39,28 +39,6 @@ status = "ok"; }; - nand@3000000 { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - chip-delay = <25>; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x500000 0x1fb00000>; - }; - }; - sata@80000 { nr-ports = <2>; status = "okay"; @@ -80,6 +58,28 @@ }; }; +&nand { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + chip-delay = <25>; + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x1fb00000>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index d544f77a4ca4..aefa375a550d 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -148,44 +148,6 @@ status = "okay"; nr-ports = <2>; }; - - nand@3000000 { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x500000>; - }; - - partition@600000 { - label = "ramdisk"; - reg = <0x0600000 0x500000>; - }; - - partition@b00000 { - label = "image"; - reg = <0x0b00000 0x6600000>; - }; - - partition@7100000 { - label = "mini firmware"; - reg = <0x7100000 0xa00000>; - }; - - partition@7b00000 { - label = "config"; - reg = <0x7b00000 0x500000>; - }; - }; }; regulators { @@ -220,6 +182,44 @@ }; }; +&nand { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + status = "okay"; + chip-delay = <35>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x500000>; + }; + + partition@600000 { + label = "ramdisk"; + reg = <0x0600000 0x500000>; + }; + + partition@b00000 { + label = "image"; + reg = <0x0b00000 0x6600000>; + }; + + partition@7100000 { + label = "mini firmware"; + reg = <0x7100000 0xa00000>; + }; + + partition@7b00000 { + label = "config"; + reg = <0x7b00000 0x500000>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index 59a2117c35a7..33ff368fbfa5 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -34,26 +34,6 @@ serial@12000 { status = "ok"; }; - - nand@3000000 { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x0500000 0xfb00000>; - }; - }; }; gpio-leds { compatible = "gpio-leds"; @@ -91,6 +71,26 @@ }; }; +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "data"; + reg = <0x0500000 0xfb00000>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index 6f7c7d7ecf2a..a43bebb25110 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -67,31 +67,6 @@ status = "ok"; }; - nand@3000000 { - chip-delay = <40>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "pogoplug"; - reg = <0x0500000 0x2000000>; - }; - - partition@2500000 { - label = "root"; - reg = <0x02500000 0xd800000>; - }; - }; sata@80000 { status = "okay"; nr-ports = <2>; @@ -171,6 +146,32 @@ }; }; +&nand { + chip-delay = <40>; + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "pogoplug"; + reg = <0x0500000 0x2000000>; + }; + + partition@2500000 { + label = "root"; + reg = <0x02500000 0xd800000>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 6548b9dc6855..d30a91a5047d 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -40,26 +40,6 @@ status = "ok"; }; - nand@3000000 { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x00100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x00100000 0x00400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x00500000 0x1fb00000>; - }; - }; - sata@80000 { status = "okay"; nr-ports = <1>; @@ -97,6 +77,26 @@ }; }; +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x00100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x00100000 0x00400000>; + }; + + partition@500000 { + label = "data"; + reg = <0x00500000 0x1fb00000>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index cb711a3bd983..066f40f99816 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -51,28 +51,6 @@ status = "okay"; nr-ports = <2>; }; - - nand@3000000 { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x600000>; - }; - - partition@700000 { - label = "root"; - reg = <0x0700000 0xf900000>; - }; - - }; }; gpio_keys { @@ -123,6 +101,28 @@ }; +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x600000>; + }; + + partition@700000 { + label = "root"; + reg = <0x0700000 0xf900000>; + }; + +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index b8150a768547..4a62b206f680 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -82,35 +82,6 @@ serial@12000 { status = "ok"; }; - - nand@3000000 { - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0xc0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0xa0000 0x20000>; - }; - - partition@100000 { - label = "zImage"; - reg = <0x100000 0x300000>; - }; - - partition@540000 { - label = "initrd"; - reg = <0x540000 0x300000>; - }; - - partition@980000 { - label = "boot"; - reg = <0x980000 0x1f400000>; - }; - }; }; gpio-leds { @@ -179,6 +150,35 @@ }; }; +&nand { + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0xc0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0xa0000 0x20000>; + }; + + partition@100000 { + label = "zImage"; + reg = <0x100000 0x300000>; + }; + + partition@540000 { + label = "initrd"; + reg = <0x540000 0x300000>; + }; + + partition@980000 { + label = "boot"; + reg = <0x980000 0x1f400000>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index df8447442b37..d15395d671ed 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -113,31 +113,6 @@ status = "ok"; }; - nand@3000000 { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@a0000 { - label = "env"; - reg = <0xa0000 0x20000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x300000>; - }; - - partition@400000 { - label = "uInitrd"; - reg = <0x540000 0x1000000>; - }; - }; sata@80000 { status = "okay"; nr-ports = <2>; @@ -195,6 +170,32 @@ }; }; +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@a0000 { + label = "env"; + reg = <0xa0000 0x20000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x300000>; + }; + + partition@400000 { + label = "uInitrd"; + reg = <0x540000 0x1000000>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index 6899408482d2..cd44f37e54b5 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -34,13 +34,6 @@ serial@12000 { status = "ok"; }; - - nand@3000000 { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "ok"; - chip-delay = <25>; - }; }; i2c@0 { @@ -51,6 +44,13 @@ }; }; +&nand { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + status = "ok"; + chip-delay = <25>; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 26ae24055d85..6c1ec2786e6e 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -95,37 +95,6 @@ pinctrl-names = "default"; }; - nand@3000000 { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "env"; - reg = <0x100000 0x80000>; - }; - - partition@180000 { - label = "fdt"; - reg = <0x180000 0x80000>; - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x400000>; - }; - - partition@600000 { - label = "rootfs"; - reg = <0x600000 0x1fa00000>; - }; - }; - rtc@10300 { status = "disabled"; }; @@ -193,6 +162,37 @@ }; }; +&nand { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "env"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "fdt"; + reg = <0x180000 0x80000>; + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x400000>; + }; + + partition@600000 { + label = "rootfs"; + reg = <0x600000 0x1fa00000>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index d3a5a0fe4821..e6a102cf424c 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -97,36 +97,6 @@ status = "okay"; }; - nand@3000000 { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "jffs2"; - reg = <0x1800000 0x6800000>; - }; - }; - sata@80000 { status = "okay"; nr-ports = <2>; @@ -207,6 +177,36 @@ }; }; +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x1000000>; + }; + + partition@1800000 { + label = "jffs2"; + reg = <0x1800000 0x6800000>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi index 06267a91de38..e3f915defd3d 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi @@ -27,49 +27,6 @@ nr-ports = <2>; }; - nand@3000000 { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x0100000>; - read-only; - }; - partition@100000 { - label = "uboot_env"; - reg = <0x0100000 0x0080000>; - }; - partition@180000 { - label = "key_store"; - reg = <0x0180000 0x0080000>; - }; - partition@200000 { - label = "info"; - reg = <0x0200000 0x0080000>; - }; - partition@280000 { - label = "etc"; - reg = <0x0280000 0x0a00000>; - }; - partition@c80000 { - label = "kernel_1"; - reg = <0x0c80000 0x0a00000>; - }; - partition@1680000 { - label = "rootfs1"; - reg = <0x1680000 0x2fc0000>; - }; - partition@4640000 { - label = "kernel_2"; - reg = <0x4640000 0x0a00000>; - }; - partition@5040000 { - label = "rootfs2"; - reg = <0x5040000 0x2fc0000>; - }; - }; - pcie-controller { status = "okay"; @@ -105,3 +62,46 @@ }; }; }; + +&nand { + status = "okay"; + chip-delay = <35>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x0100000>; + read-only; + }; + partition@100000 { + label = "uboot_env"; + reg = <0x0100000 0x0080000>; + }; + partition@180000 { + label = "key_store"; + reg = <0x0180000 0x0080000>; + }; + partition@200000 { + label = "info"; + reg = <0x0200000 0x0080000>; + }; + partition@280000 { + label = "etc"; + reg = <0x0280000 0x0a00000>; + }; + partition@c80000 { + label = "kernel_1"; + reg = <0x0c80000 0x0a00000>; + }; + partition@1680000 { + label = "rootfs1"; + reg = <0x1680000 0x2fc0000>; + }; + partition@4640000 { + label = "kernel_2"; + reg = <0x4640000 0x0a00000>; + }; + partition@5040000 { + label = "rootfs2"; + reg = <0x5040000 0x2fc0000>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index 85ccf8d8abb1..f0e3d213604c 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -29,43 +29,6 @@ pinctrl-names = "default"; }; - nand@3000000 { - chip-delay = <25>; - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x90000>; - }; - - partition@90000 { - label = "env"; - reg = <0x90000 0x44000>; - }; - - partition@d4000 { - label = "test"; - reg = <0xd4000 0x24000>; - }; - - partition@f4000 { - label = "conf"; - reg = <0xf4000 0x400000>; - }; - - partition@4f4000 { - label = "linux"; - reg = <0x4f4000 0x1d20000>; - }; - - partition@2214000 { - label = "user"; - reg = <0x2214000 0x1dec000>; - }; - }; - sata@80000 { nr-ports = <1>; status = "okay"; @@ -167,6 +130,43 @@ }; }; +&nand { + chip-delay = <25>; + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x90000>; + }; + + partition@90000 { + label = "env"; + reg = <0x90000 0x44000>; + }; + + partition@d4000 { + label = "test"; + reg = <0xd4000 0x24000>; + }; + + partition@f4000 { + label = "conf"; + reg = <0xf4000 0x400000>; + }; + + partition@4f4000 { + label = "linux"; + reg = <0x4f4000 0x1d20000>; + }; + + partition@2214000 { + label = "user"; + reg = <0x2214000 0x1dec000>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi index 5696b630b70b..1173d7fb31b2 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi @@ -48,27 +48,6 @@ pinctrl-names = "default"; status = "okay"; }; - - nand@3000000 { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x0500000 0x1fb00000>; - }; - }; }; regulators { @@ -92,6 +71,27 @@ }; }; +&nand { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x0500000 0x1fb00000>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 30842b4ff293..320da677b984 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -90,37 +90,6 @@ pinctrl-names = "default"; }; - nand@3000000 { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - }; - - partition@180000 { - label = "u-boot env"; - reg = <0x0180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "uInitrd"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "rootfs"; - reg = <0x1800000 0xe800000>; - }; - }; - sata@80000 { status = "okay"; nr-ports = <1>; @@ -204,6 +173,37 @@ }; }; +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; + }; + + partition@180000 { + label = "u-boot env"; + reg = <0x0180000 0x20000>; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; + }; + + partition@800000 { + label = "uInitrd"; + reg = <0x0800000 0x1000000>; + }; + + partition@1800000 { + label = "rootfs"; + reg = <0x1800000 0xe800000>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 76b16271362a..632b64701ecd 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -45,12 +45,25 @@ clocks = <&gate_clk 17>; status = "okay"; }; + + nand: nand@012f { + #address-cells = <1>; + #size-cells = <1>; + cle = <0>; + ale = <1>; + bank-width = <1>; + compatible = "marvell,orion-nand"; + reg = ; + chip-delay = <25>; + /* set partition map and/or chip-delay in board dts */ + clocks = <&gate_clk 7>; + status = "disabled"; + }; }; ocp@f1000000 { compatible = "simple-bus"; - ranges = <0x00000000 0xf1000000 0x0100000 - 0xf4000000 0xf4000000 0x0000400>; + ranges = <0x00000000 0xf1000000 0x0100000>; #address-cells = <1>; #size-cells = <1>; @@ -206,20 +219,6 @@ status = "okay"; }; - nand@3000000 { - #address-cells = <1>; - #size-cells = <1>; - cle = <0>; - ale = <1>; - bank-width = <1>; - compatible = "marvell,orion-nand"; - reg = <0xf4000000 0x400>; - chip-delay = <25>; - /* set partition map and/or chip-delay in board dts */ - clocks = <&gate_clk 7>; - status = "disabled"; - }; - i2c@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; -- cgit v1.2.3 From 7e9dee0ca27f0bcedb4fad728bb0dc86da0863c7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 2 Oct 2013 13:40:09 +0200 Subject: ARM: ux500: correct I2C address of ambient light sensor The ambient light sensor is places at address 0x29 nothing else. This patch makes the ambient light sensor probe again. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index d6753261796b..a561bc39e6ab 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -103,7 +103,7 @@ }; bh1780@29 { compatible = "rohm,bh1780gli"; - reg = <0x33>; + reg = <0x29>; }; }; -- cgit v1.2.3 From 0ca3399fc822ff65120f6a59f6d4b82ff462559f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 2 Oct 2013 14:56:49 +0200 Subject: ARM: ux500: fix proximity sensor button The proximity sensor is connected to pin AH12 on newer HREFs, that corresponds to pin offset 25 on gpio5, not gpio6. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-hrefv60plus.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dts b/arch/arm/boot/dts/ste-hrefv60plus.dts index bb3cfc7280e8..111546802667 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dts +++ b/arch/arm/boot/dts/ste-hrefv60plus.dts @@ -20,7 +20,7 @@ gpio_keys { button@1 { - gpios = <&gpio6 25 0x4>; + gpios = <&gpio5 25 0x4>; }; }; -- cgit v1.2.3 From bf7a9b6f2fd31745e6ba532da37f68416312a688 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 2 Oct 2013 16:12:52 +0200 Subject: ARM: ux500: correct CD for micro SD on hrev60plus This correct the card detect line for the HREF v60 and later reference designs. This is connected directly to the Nomadik GPIO block, line 95 at offset 31 on the third instance. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-hrefv60plus.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dts b/arch/arm/boot/dts/ste-hrefv60plus.dts index 111546802667..b82ae5015121 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dts +++ b/arch/arm/boot/dts/ste-hrefv60plus.dts @@ -40,7 +40,7 @@ mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; - cd-gpios = <&tc3589x_gpio 3 0x4>; + cd-gpios = <&gpio2 31 0x4>; // 95 status = "okay"; }; -- cgit v1.2.3 From d62407b0a68370c0eef9f4a508d846570ff6d38e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 2 Oct 2013 16:03:31 +0200 Subject: ARM: ux500: move TC35892 at 0x42 to hrefprev60 The TC35892 was mounted as a GPIO expander on the HREF prior to v60 and not in later versions, which instead use the Nomadik GPIO directly, so move it over to the hrefprev60 DTS file. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href.dtsi | 22 ---------------------- arch/arm/boot/dts/ste-hrefprev60.dts | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 22 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index a561bc39e6ab..aa3f02060fdd 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -41,28 +41,6 @@ status = "okay"; }; - i2c@80004000 { - tc3589x@42 { - compatible = "tc3589x"; - reg = <0x42>; - interrupt-parent = <&gpio6>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - - tc3589x_gpio: tc3589x_gpio { - compatible = "tc3589x-gpio"; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; - i2c@80128000 { lp5521@33 { compatible = "national,lp5521"; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dts b/arch/arm/boot/dts/ste-hrefprev60.dts index 767fa21e4881..5016dc93d98e 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dts +++ b/arch/arm/boot/dts/ste-hrefprev60.dts @@ -30,6 +30,26 @@ compatible = "tps61052"; reg = <0x33>; }; + + tc3589x@42 { + compatible = "tc3589x"; + reg = <0x42>; + interrupt-parent = <&gpio6>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + + tc3589x_gpio: tc3589x_gpio { + compatible = "tc3589x-gpio"; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + }; }; i2c@80110000 { -- cgit v1.2.3 From 9c19cfa93a43803c5f40054f96bca28d439e0847 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 26 Sep 2013 15:34:02 +0200 Subject: ARM: ux500: split HREF UIB files Create two different UIB (User Interface Board) include files: one per UIB simply. The include files now only handle the devices on that very UIB. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-stuib.dtsi | 80 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/ste-href-tvk1281618.dtsi | 20 ++++++++ arch/arm/boot/dts/ste-hrefprev60.dts | 3 +- arch/arm/boot/dts/ste-hrefv60plus.dts | 3 +- arch/arm/boot/dts/ste-stuib.dtsi | 80 ------------------------------ 5 files changed, 104 insertions(+), 82 deletions(-) create mode 100644 arch/arm/boot/dts/ste-href-stuib.dtsi create mode 100644 arch/arm/boot/dts/ste-href-tvk1281618.dtsi delete mode 100644 arch/arm/boot/dts/ste-stuib.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi new file mode 100644 index 000000000000..524e33240ad4 --- /dev/null +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -0,0 +1,80 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include + +/ { + soc { + i2c@80004000 { + stmpe1601: stmpe1601@40 { + compatible = "st,stmpe1601"; + reg = <0x40>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio6>; + interrupt-controller; + + wakeup-source; + st,autosleep-timeout = <1024>; + + stmpe_keypad { + compatible = "st,stmpe-keypad"; + + debounce-interval = <64>; + st,scan-count = <8>; + st,no-autorepeat; + + linux,keymap = <0x205006b + 0x4010074 + 0x3050072 + 0x1030004 + 0x502006a + 0x500000a + 0x5008b + 0x706001c + 0x405000b + 0x6070003 + 0x3040067 + 0x303006c + 0x60400e7 + 0x602009e + 0x4020073 + 0x5050002 + 0x4030069 + 0x3020008>; + }; + }; + }; + + i2c@80110000 { + bu21013_tp@5c { + compatible = "rohm,bu21013_tp"; + reg = <0x5c>; + touch-gpio = <&gpio2 20 0x4>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + + rohm,touch-max-x = <384>; + rohm,touch-max-y = <704>; + rohm,flip-y; + }; + + bu21013_tp@5d { + compatible = "rohm,bu21013_tp"; + reg = <0x5d>; + touch-gpio = <&gpio2 20 0x4>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + + rohm,touch-max-x = <384>; + rohm,touch-max-y = <704>; + rohm,flip-y; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi new file mode 100644 index 000000000000..89e1485a3850 --- /dev/null +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -0,0 +1,20 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * Device Tree for the TVK1281618 UIB + */ + +#include + +/ { + soc { + /* Add Synaptics touch screen, TC35892 keypad etc here */ + }; +}; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dts b/arch/arm/boot/dts/ste-hrefprev60.dts index 5016dc93d98e..85c6dd4ab37e 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dts +++ b/arch/arm/boot/dts/ste-hrefprev60.dts @@ -12,7 +12,8 @@ /dts-v1/; #include "ste-dbx5x0.dtsi" #include "ste-href.dtsi" -#include "ste-stuib.dtsi" +#include "ste-href-stuib.dtsi" +#include "ste-href-tvk1281618.dtsi" / { model = "ST-Ericsson HREF (pre-v60) platform with Device Tree"; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dts b/arch/arm/boot/dts/ste-hrefv60plus.dts index b82ae5015121..0f222e16f0b3 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dts +++ b/arch/arm/boot/dts/ste-hrefv60plus.dts @@ -12,7 +12,8 @@ /dts-v1/; #include "ste-dbx5x0.dtsi" #include "ste-href.dtsi" -#include "ste-stuib.dtsi" +#include "ste-href-stuib.dtsi" +#include "ste-href-tvk1281618.dtsi" / { model = "ST-Ericsson HREF (v60+) platform with Device Tree"; diff --git a/arch/arm/boot/dts/ste-stuib.dtsi b/arch/arm/boot/dts/ste-stuib.dtsi deleted file mode 100644 index 524e33240ad4..000000000000 --- a/arch/arm/boot/dts/ste-stuib.dtsi +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include - -/ { - soc { - i2c@80004000 { - stmpe1601: stmpe1601@40 { - compatible = "st,stmpe1601"; - reg = <0x40>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpio6>; - interrupt-controller; - - wakeup-source; - st,autosleep-timeout = <1024>; - - stmpe_keypad { - compatible = "st,stmpe-keypad"; - - debounce-interval = <64>; - st,scan-count = <8>; - st,no-autorepeat; - - linux,keymap = <0x205006b - 0x4010074 - 0x3050072 - 0x1030004 - 0x502006a - 0x500000a - 0x5008b - 0x706001c - 0x405000b - 0x6070003 - 0x3040067 - 0x303006c - 0x60400e7 - 0x602009e - 0x4020073 - 0x5050002 - 0x4030069 - 0x3020008>; - }; - }; - }; - - i2c@80110000 { - bu21013_tp@5c { - compatible = "rohm,bu21013_tp"; - reg = <0x5c>; - touch-gpio = <&gpio2 20 0x4>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - - rohm,touch-max-x = <384>; - rohm,touch-max-y = <704>; - rohm,flip-y; - }; - - bu21013_tp@5d { - compatible = "rohm,bu21013_tp"; - reg = <0x5d>; - touch-gpio = <&gpio2 20 0x4>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - - rohm,touch-max-x = <384>; - rohm,touch-max-y = <704>; - rohm,flip-y; - }; - }; - }; -}; -- cgit v1.2.3 From 01dc909fa1be6259cdbbc9fd6933df4fbe26ea5a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 2 Oct 2013 15:42:59 +0200 Subject: ARM: ux500: split the HREF DTS files from two to four As the device tree conversion did away with the ability to auto-detect the UIB (User Interface Board) version from attempting to read an I2C address, we now have to pass the knowledge of what UIB is mounted through the device tree. This gives rise to four possible board permutations: - HREF prior to v60, ST UIB (hrefprev60-stuib) - HREF prior to v60, TVK1281618 UIB (hrefprev60-tvk) - HREF v60 and later, ST UIB (href60plus-stuib) - HREF v60 and later, TVK1281618 UIB (hrefv60plus-tvk) Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 6 ++- arch/arm/boot/dts/ste-hrefprev60-stuib.dts | 28 ++++++++++ arch/arm/boot/dts/ste-hrefprev60-tvk.dts | 19 +++++++ arch/arm/boot/dts/ste-hrefprev60.dts | 69 ------------------------- arch/arm/boot/dts/ste-hrefprev60.dtsi | 65 ++++++++++++++++++++++++ arch/arm/boot/dts/ste-hrefv60plus-stuib.dts | 30 +++++++++++ arch/arm/boot/dts/ste-hrefv60plus-tvk.dts | 21 ++++++++ arch/arm/boot/dts/ste-hrefv60plus.dts | 79 ----------------------------- arch/arm/boot/dts/ste-hrefv60plus.dtsi | 76 +++++++++++++++++++++++++++ 9 files changed, 243 insertions(+), 150 deletions(-) create mode 100644 arch/arm/boot/dts/ste-hrefprev60-stuib.dts create mode 100644 arch/arm/boot/dts/ste-hrefprev60-tvk.dts delete mode 100644 arch/arm/boot/dts/ste-hrefprev60.dts create mode 100644 arch/arm/boot/dts/ste-hrefprev60.dtsi create mode 100644 arch/arm/boot/dts/ste-hrefv60plus-stuib.dts create mode 100644 arch/arm/boot/dts/ste-hrefv60plus-tvk.dts delete mode 100644 arch/arm/boot/dts/ste-hrefv60plus.dts create mode 100644 arch/arm/boot/dts/ste-hrefv60plus.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index cc0f1fb61753..f1163a4c55d3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -189,8 +189,10 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ - ste-hrefprev60.dtb \ - ste-hrefv60plus.dtb \ + ste-hrefprev60-stuib.dtb \ + ste-hrefprev60-tvk.dtb \ + ste-hrefv60plus-stuib.dtb \ + ste-hrefv60plus-tvk.dtb \ ste-ccu8540.dtb \ ste-ccu9540.dtb dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb diff --git a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts b/arch/arm/boot/dts/ste-hrefprev60-stuib.dts new file mode 100644 index 000000000000..3e1b974b43a1 --- /dev/null +++ b/arch/arm/boot/dts/ste-hrefprev60-stuib.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "ste-hrefprev60.dtsi" +#include "ste-href-stuib.dtsi" + +/ { + model = "ST-Ericsson HREF (pre-v60) and ST UIB"; + compatible = "st-ericsson,mop500", "st-ericsson,u8500"; + + soc { + /* Reset line for the BU21013 touchscreen */ + i2c@80110000 { + bu21013_tp@5c { + reset-gpio = <&tc3589x_gpio 13 0x4>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-hrefprev60-tvk.dts b/arch/arm/boot/dts/ste-hrefprev60-tvk.dts new file mode 100644 index 000000000000..59523f866812 --- /dev/null +++ b/arch/arm/boot/dts/ste-hrefprev60-tvk.dts @@ -0,0 +1,19 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "ste-hrefprev60.dtsi" +#include "ste-href-tvk1281618.dtsi" + +/ { + model = "ST-Ericsson HREF (pre-v60) and TVK1281618 UIB"; + compatible = "st-ericsson,mop500", "st-ericsson,u8500"; +}; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dts b/arch/arm/boot/dts/ste-hrefprev60.dts deleted file mode 100644 index 85c6dd4ab37e..000000000000 --- a/arch/arm/boot/dts/ste-hrefprev60.dts +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "ste-dbx5x0.dtsi" -#include "ste-href.dtsi" -#include "ste-href-stuib.dtsi" -#include "ste-href-tvk1281618.dtsi" - -/ { - model = "ST-Ericsson HREF (pre-v60) platform with Device Tree"; - compatible = "st-ericsson,mop500", "st-ericsson,u8500"; - - gpio_keys { - button@1 { - gpios = <&tc3589x_gpio 7 0x4>; - }; - }; - - soc { - i2c@80004000 { - tps61052@33 { - compatible = "tps61052"; - reg = <0x33>; - }; - - tc3589x@42 { - compatible = "tc3589x"; - reg = <0x42>; - interrupt-parent = <&gpio6>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - - tc3589x_gpio: tc3589x_gpio { - compatible = "tc3589x-gpio"; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; - - i2c@80110000 { - bu21013_tp@5c { - reset-gpio = <&tc3589x_gpio 13 0x4>; - }; - }; - - vmmci: regulator-gpio { - gpios = <&tc3589x_gpio 18 0x4>; - enable-gpio = <&tc3589x_gpio 17 0x4>; - - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi new file mode 100644 index 000000000000..de6b0a0c5a54 --- /dev/null +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -0,0 +1,65 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * Device Tree for the HREF+ prior to the v60 variant. + */ + +#include "ste-dbx5x0.dtsi" +#include "ste-href.dtsi" + +/ { + gpio_keys { + button@1 { + gpios = <&tc3589x_gpio 7 0x4>; + }; + }; + + soc { + i2c@80004000 { + tps61052@33 { + compatible = "tps61052"; + reg = <0x33>; + }; + + tc3589x@42 { + compatible = "tc3589x"; + reg = <0x42>; + interrupt-parent = <&gpio6>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + + tc3589x_gpio: tc3589x_gpio { + compatible = "tc3589x-gpio"; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + + i2c@80110000 { + bu21013_tp@5c { + reset-gpio = <&tc3589x_gpio 13 0x4>; + }; + }; + + vmmci: regulator-gpio { + gpios = <&tc3589x_gpio 18 0x4>; + enable-gpio = <&tc3589x_gpio 17 0x4>; + + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts b/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts new file mode 100644 index 000000000000..4da49e7988e9 --- /dev/null +++ b/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * Device Tree for the HREF version 60 or later with the ST UIB + */ + +/dts-v1/; +#include "ste-hrefv60plus.dtsi" +#include "ste-href-stuib.dtsi" + +/ { + model = "ST-Ericsson HREF (v60+) and ST UIB"; + compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; + + soc { + /* Reset line for the BU21013 touchscreen */ + i2c@80110000 { + bu21013_tp@0x5c { + reset-gpio = <&gpio4 15 0x4>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts b/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts new file mode 100644 index 000000000000..d53cccdce776 --- /dev/null +++ b/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * Device Tree for the HREF version 60 or later with the TVK1281618 UIB + */ + +/dts-v1/; +#include "ste-hrefv60plus.dtsi" +#include "ste-href-tvk1281618.dtsi" + +/ { + model = "ST-Ericsson HREF (v60+) and TVK1281618 UIB"; + compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; +}; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dts b/arch/arm/boot/dts/ste-hrefv60plus.dts deleted file mode 100644 index 0f222e16f0b3..000000000000 --- a/arch/arm/boot/dts/ste-hrefv60plus.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "ste-dbx5x0.dtsi" -#include "ste-href.dtsi" -#include "ste-href-stuib.dtsi" -#include "ste-href-tvk1281618.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) platform with Device Tree"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - - gpio_keys { - button@1 { - gpios = <&gpio5 25 0x4>; - }; - }; - - soc { - i2c@80110000 { - bu21013_tp@0x5c { - reset-gpio = <&gpio4 15 0x4>; - }; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - mmc-cap-sd-highspeed; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - - cd-gpios = <&gpio2 31 0x4>; // 95 - - status = "okay"; - }; - - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - - status = "okay"; - }; - - // PoP:ed eMMC - sdi2_per3@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - mmc-cap-mmc-highspeed; - - status = "okay"; - }; - - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi new file mode 100644 index 000000000000..d0f116555c0e --- /dev/null +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -0,0 +1,76 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "ste-dbx5x0.dtsi" +#include "ste-href.dtsi" + +/ { + model = "ST-Ericsson HREF (v60+) platform with Device Tree"; + compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; + + gpio_keys { + button@1 { + gpios = <&gpio5 25 0x4>; + }; + }; + + soc { + i2c@80110000 { + bu21013_tp@0x5c { + reset-gpio = <&gpio4 15 0x4>; + }; + }; + + // External Micro SD slot + sdi0_per1@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + mmc-cap-sd-highspeed; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + + cd-gpios = <&gpio2 31 0x4>; // 95 + + status = "okay"; + }; + + // WLAN SDIO channel + sdi1_per2@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + + status = "okay"; + }; + + // PoP:ed eMMC + sdi2_per3@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + + status = "okay"; + }; + + // On-board eMMC + sdi4_per2@80114000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux2_reg>; + + status = "okay"; + }; + }; +}; -- cgit v1.2.3 From 84919b96feebaf95f1739232c2984d69c2ee0802 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 3 Oct 2013 10:18:36 +0200 Subject: ARM: ux500: register the tc35892 GPIO on the TVK UIB The TVK1281618 UIB has a TC35892 GPIO expander on it, which has in the past probably been confused with the GPIO expander on the older HREF plus previous to v60, which is on an entirely different part of the system with another I2C address. Register the expander in the right place. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-tvk1281618.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi index 89e1485a3850..76d3ef13175f 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -16,5 +16,26 @@ / { soc { /* Add Synaptics touch screen, TC35892 keypad etc here */ + i2c@80004000 { + tc3589x@44 { + compatible = "tc3589x"; + reg = <0x44>; + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + + tc3589x_gpio { + compatible = "tc3589x-gpio"; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; }; }; -- cgit v1.2.3 From 741a6c4c59cfa1266bc75aca9f66bdc6e421b0d5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 3 Oct 2013 10:29:24 +0200 Subject: ARM: ux500: move BU21013 touchpad GPIOs into top-level DTS The BU21013 touchscreen GPIOs have been pretty confused, correct them per board, and move the GPIO assignments up to the top level DTS file so we can control it from there, and avoid defining the GPIO assignments for non-ST UIB equipped boards. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-stuib.dtsi | 2 -- arch/arm/boot/dts/ste-hrefprev60-stuib.dts | 6 ++++++ arch/arm/boot/dts/ste-hrefprev60.dtsi | 6 ------ arch/arm/boot/dts/ste-hrefv60plus-stuib.dts | 10 ++++++++-- arch/arm/boot/dts/ste-hrefv60plus.dtsi | 6 ------ 5 files changed, 14 insertions(+), 16 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index 524e33240ad4..76704ec0ffcc 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -57,7 +57,6 @@ bu21013_tp@5c { compatible = "rohm,bu21013_tp"; reg = <0x5c>; - touch-gpio = <&gpio2 20 0x4>; avdd-supply = <&ab8500_ldo_aux1_reg>; rohm,touch-max-x = <384>; @@ -68,7 +67,6 @@ bu21013_tp@5d { compatible = "rohm,bu21013_tp"; reg = <0x5d>; - touch-gpio = <&gpio2 20 0x4>; avdd-supply = <&ab8500_ldo_aux1_reg>; rohm,touch-max-x = <384>; diff --git a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts b/arch/arm/boot/dts/ste-hrefprev60-stuib.dts index 3e1b974b43a1..2b1cb5b584b6 100644 --- a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts +++ b/arch/arm/boot/dts/ste-hrefprev60-stuib.dts @@ -20,7 +20,13 @@ soc { /* Reset line for the BU21013 touchscreen */ i2c@80110000 { + /* Only one of these will be used */ bu21013_tp@5c { + touch-gpio = <&gpio2 12 0x4>; + reset-gpio = <&tc3589x_gpio 13 0x4>; + }; + bu21013_tp@5d { + touch-gpio = <&gpio2 12 0x4>; reset-gpio = <&tc3589x_gpio 13 0x4>; }; }; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index de6b0a0c5a54..b2cd7bc2752f 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -49,12 +49,6 @@ }; }; - i2c@80110000 { - bu21013_tp@5c { - reset-gpio = <&tc3589x_gpio 13 0x4>; - }; - }; - vmmci: regulator-gpio { gpios = <&tc3589x_gpio 18 0x4>; enable-gpio = <&tc3589x_gpio 17 0x4>; diff --git a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts b/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts index 4da49e7988e9..8c6a2de56cf1 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts +++ b/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts @@ -22,8 +22,14 @@ soc { /* Reset line for the BU21013 touchscreen */ i2c@80110000 { - bu21013_tp@0x5c { - reset-gpio = <&gpio4 15 0x4>; + /* Only one of these will be used */ + bu21013_tp@5c { + touch-gpio = <&gpio2 20 0x4>; + reset-gpio = <&gpio4 17 0x4>; + }; + bu21013_tp@5d { + touch-gpio = <&gpio2 20 0x4>; + reset-gpio = <&gpio4 17 0x4>; }; }; }; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index d0f116555c0e..aed511b47a9e 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -23,12 +23,6 @@ }; soc { - i2c@80110000 { - bu21013_tp@0x5c { - reset-gpio = <&gpio4 15 0x4>; - }; - }; - // External Micro SD slot sdi0_per1@80126000 { arm,primecell-periphid = <0x10480180>; -- cgit v1.2.3 From 148c274ea64448673c4294e32cfd0d60b524ca9a Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Thu, 3 Oct 2013 05:06:45 +0200 Subject: ARM: kirkwood: ib62x0: add u-boot environment partition Also, add some trivial whitespace cleanup. Signed-off-by: Luka Perkov Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-ib62x0.dts | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index 066f40f99816..c5fb02f7ebc3 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -5,7 +5,7 @@ / { model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; - compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; memory { device_type = "memory"; @@ -43,6 +43,7 @@ marvell,function = "gpio"; }; }; + serial@12000 { status = "okay"; }; @@ -71,6 +72,7 @@ gpios = <&gpio0 28 1>; }; }; + gpio-leds { compatible = "gpio-leds"; pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green @@ -91,14 +93,13 @@ gpios = <&gpio0 27 0>; }; }; + gpio_poweroff { compatible = "gpio-poweroff"; pinctrl-0 = <&pmx_power_off>; pinctrl-names = "default"; gpios = <&gpio0 24 0>; }; - - }; &nand { @@ -108,7 +109,12 @@ partition@0 { label = "u-boot"; - reg = <0x0000000 0x100000>; + reg = <0x0000000 0xe0000>; + }; + + partition@e0000 { + label = "u-boot environment"; + reg = <0xe0000 0x100000>; }; partition@100000 { @@ -134,6 +140,7 @@ ð0 { status = "okay"; + ethernet0-port@0 { phy-handle = <ðphy0>; }; -- cgit v1.2.3 From 7837feff0d881835309fced7a7c4b5f32866d632 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 3 Oct 2013 16:35:26 +0200 Subject: arm: mvebu: add support for the Armada XP Matrix board The Armada XP Matrix board is the mother board of a more complex system. The mother board uses an Armada XP MV78460, 4 serial ports, 2 SATA ports, one Ethernet connection, a PCIe port and a USB port. All those devices are enabled in the Device Tree added by this patch. Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/armada-xp-matrix.dts | 75 ++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 arch/arm/boot/dts/armada-xp-matrix.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 69193bedc88c..5b832744a0bb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -111,6 +111,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ armada-xp-gp.dtb \ + armada-xp-matrix.dtb \ armada-xp-openblocks-ax3-4.dtb dtb-$(CONFIG_ARCH_MXC) += \ imx25-karo-tx25.dtb \ diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts new file mode 100644 index 000000000000..e47c49ecd55c --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-matrix.dts @@ -0,0 +1,75 @@ +/* + * Device Tree file for Marvell Armada XP Matrix board + * + * Copyright (C) 2013 Marvell + * + * Lior Amsalem + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +#include "armada-xp-mv78460.dtsi" + +/ { + model = "Marvell Armada XP Matrix Board"; + compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = ; + + internal-regs { + serial@12000 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@12100 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@12200 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@12300 { + clock-frequency = <250000000>; + status = "okay"; + }; + + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + ethernet@30000 { + status = "okay"; + phy-mode = "sgmii"; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + }; + + usb@50000 { + status = "okay"; + }; + }; + }; +}; -- cgit v1.2.3 From 159c7f89494fb64ccd435b7ef5861ecdb64bc379 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 1 Oct 2013 14:42:27 -0500 Subject: arm: socfpga: Add clock for smp_twd timer Assign a clock for the twd-timer. Signed-off-by: Dinh Nguyen Acked-by: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: Ian Campbell CC: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/socfpga.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index e273fa993b8c..e7260ca9eaf1 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -473,6 +473,7 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xfffec600 0x100>; interrupts = <1 13 0xf04>; + clocks = <&mpu_periph_clk>; }; timer0: timer0@ffc08000 { -- cgit v1.2.3 From e0ec2f39ef9905a24d5d88238eda3dabb8d591e0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 Sep 2013 00:41:29 +0200 Subject: ARM: dts: mxs: Add MSR M28CU3 board This board is based on the M28 SoM with custom baseboard. Supported are LEDs, ethernet, PWM, LCD, SD slots. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx28-m28cu3.dts | 266 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-mxs/mach-mxs.c | 7 + 3 files changed, 274 insertions(+) create mode 100644 arch/arm/boot/dts/imx28-m28cu3.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 909561081711..3043e6cd101e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -159,6 +159,7 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx28-cfa10057.dtb \ imx28-cfa10058.dtb \ imx28-evk.dtb \ + imx28-m28cu3.dtb \ imx28-m28evk.dtb \ imx28-sps1.dtb \ imx28-tx28.dtb diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts new file mode 100644 index 000000000000..d3958da60bd7 --- /dev/null +++ b/arch/arm/boot/dts/imx28-m28cu3.dts @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2013 Marek Vasut + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx28.dtsi" + +/ { + model = "MSR M28CU3"; + compatible = "msr,m28cu3", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + gpmi-nand@8000c000 { + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + + partition@0 { + label = "gpmi-nfc-0-boot"; + reg = <0x00000000 0x01400000>; + read-only; + }; + + partition@1 { + label = "gpmi-nfc-general-use"; + reg = <0x01400000 0x0ec00000>; + }; + }; + + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <4>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; + }; + + ssp2: ssp@80014000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pins_a + &mmc2_cd_cfg + &mmc2_sck_cfg>; + bus-width = <4>; + vmmc-supply = <®_vddio_sd1>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SS0__GPIO_2_19 + MX28_PAD_PWM4__GPIO_3_29 + MX28_PAD_AUART2_RX__GPIO_3_8 + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_m28: lcdif-m28@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_VSYNC__LCD_VSYNC + MX28_PAD_LCD_HSYNC__LCD_HSYNC + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK + MX28_PAD_LCD_RESET__LCD_RESET + MX28_PAD_LCD_CS__LCD_ENABLE + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pins_gpio: leds-m28@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP3_MISO__GPIO_2_26 + MX28_PAD_SSP3_SCK__GPIO_2_24 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + }; + + ocotp@8002c000 { + status = "okay"; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_m28>; + display = <&display>; + reset-active-high; + status = "okay"; + + display: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <6410256>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hfront-porch = <20>; + vback-porch = <15>; + vfront-porch = <5>; + hsync-len = <30>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + }; + }; + + apbx@80040000 { + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_b>; + status = "okay"; + }; + + usbphy1: usbphy@8007e000 { + status = "okay"; + }; + + auart0: serial@8006a000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; + }; + + auart3: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_2pins_b>; + status = "okay"; + }; + + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_a>; + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb1: usb@80090000 { + vbus-supply = <®_usb1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usbphy1_pins_a>; + disable-over-current; + status = "okay"; + }; + + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio4 13 0>; + phy-reset-duration = <100>; + status = "okay"; + }; + + mac1: ethernet@800f4000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 3 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_gpio>; + + user1 { + label = "sd0-led"; + gpios = <&gpio2 26 0>; + linux,default-trigger = "mmc0"; + }; + + user2 { + label = "sd1-led"; + gpios = <&gpio2 24 0>; + linux,default-trigger = "mmc2"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 29 0>; + }; + + reg_vddio_sd1: vddio-sd1 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 0>; + }; + + reg_usb1_vbus: usb1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 8 0>; + enable-active-high; + }; + }; +}; diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 98f6e2adb53e..c0ceb17649fa 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -332,6 +332,11 @@ static void __init crystalfontz_init(void) update_fec_mac_prop(OUI_CRYSTALFONTZ); } +static void __init m28cu3_init(void) +{ + update_fec_mac_prop(OUI_DENX); +} + static const char __init *mxs_get_soc_id(void) { struct device_node *np; @@ -459,6 +464,8 @@ static void __init mxs_machine_init(void) apx4devkit_init(); else if (of_machine_is_compatible("crystalfontz,cfa10036")) crystalfontz_init(); + else if (of_machine_is_compatible("msr,m28cu3")) + m28cu3_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); -- cgit v1.2.3 From 439d9f58017af96f0375d9443ff957c19056d6ec Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 24 Sep 2013 16:30:05 +0300 Subject: ARM: sun6i: Fix the APB2 clock gates register size The APB2 clocks gates are only a 32 bits register wide, and not 2 as set currently in the DTSI. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index f244f5f02365..c1751a64889a 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -175,7 +175,7 @@ apb2_gates: apb2_gates@01c2006c { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-apb2-gates-clk"; - reg = <0x01c2006c 0x8>; + reg = <0x01c2006c 0x4>; clocks = <&apb2>; clock-output-names = "apb2_i2c0", "apb2_i2c1", "apb2_i2c2", "apb2_i2c3", "apb2_uart0", -- cgit v1.2.3 From 21b190d2499057b5deafbf11d577494db43b80db Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Sun, 6 Oct 2013 09:14:39 +0900 Subject: ARM: dts: Add MIPI PHY node to exynos4.dtsi Add PHY provider node for the MIPI CSIS and MIPI DSIM PHYs. Signed-off-by: Sylwester Nawrocki Signed-off-by: Kyungmin Park Acked-by: Felipe Balbi Acked-by: Kishon Vijay Abraham I Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index caadc0257342..a73eeb5f258f 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -49,6 +49,12 @@ reg = <0x10000000 0x100>; }; + mipi_phy: video-phy@10020710 { + compatible = "samsung,s5pv210-mipi-video-phy"; + reg = <0x10020710 8>; + #phy-cells = <1>; + }; + pd_mfc: mfc-power-domain@10023C40 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C40 0x20>; @@ -161,6 +167,8 @@ clock-names = "csis", "sclk_csis"; bus-width = <4>; samsung,power-domain = <&pd_cam>; + phys = <&mipi_phy 0>; + phy-names = "csis"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -174,6 +182,8 @@ clock-names = "csis", "sclk_csis"; bus-width = <2>; samsung,power-domain = <&pd_cam>; + phys = <&mipi_phy 2>; + phy-names = "csis"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From af617c93b3975ff5b9e9a0922851dce47766da15 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Sun, 6 Oct 2013 09:20:59 +0900 Subject: ARM: dts: Add fixed voltage regulator to simple bus for origen This has been done for Arndale board vide commit aa3edb65 ("ARM: dts: Put Arndale fixed voltage regulators on a simple-bus"). Replicate here for consistency and correctness. Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4210-origen.dts | 21 ++++++++++++++------- arch/arm/boot/dts/exynos4412-origen.dts | 21 ++++++++++++++------- 2 files changed, 28 insertions(+), 14 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 382d8c7e2906..d3340db03000 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -32,13 +32,20 @@ bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; - mmc_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 0>; - enable-active-high; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + mmc_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpx1 1 0>; + enable-active-high; + }; }; tmu@100C0000 { diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 8768b03702e5..d65984c440f6 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -32,13 +32,20 @@ reg = <0x0203F000 0x1000>; }; - mmc_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 0>; - enable-active-high; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + mmc_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpx1 1 0>; + enable-active-high; + }; }; pinctrl@11000000 { -- cgit v1.2.3 From 8365f763a7816f0b5d04f6cabd359de14b378e52 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Sun, 6 Oct 2013 09:21:10 +0900 Subject: ARM: dts: Add reg property to regulator nodes in exynos5250-arndale For consistency and correctness, since this is a bus, even if not physical, it is worth to add 'reg' property and unit-address to subnodes. The 'reg' property would merely be an index. Also for consistency, use "regulator" as node name as used most commonly across other dts files. Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-arndale.dts | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index cee55fa33731..0c425476d4db 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -482,13 +482,15 @@ #address-cells = <1>; #size-cells = <0>; - main_dc_reg: fixedregulator@1 { + main_dc_reg: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "MAIN_DC"; }; - mmc_reg: voltage-regulator { + mmc_reg: regulator@1 { compatible = "regulator-fixed"; + reg = <1>; regulator-name = "VDD_33ON_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -496,8 +498,9 @@ enable-active-high; }; - reg_hdmi_en: fixedregulator@0 { + reg_hdmi_en: regulator@2 { compatible = "regulator-fixed"; + reg = <2>; regulator-name = "hdmi-en"; }; }; -- cgit v1.2.3 From 8d4a54af47ce7a71fd049a942cb2ea0041b18ecb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 4 Oct 2013 13:15:26 -0300 Subject: ARM: dts: imx53-qsb: SDHC3 is connected in 8-bit mode SDHC3 is 8 bit-wide, so pass the bus-width property to reflect that. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-qsb.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 94597c3c2eb6..b646ef1617d5 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -136,6 +136,7 @@ pinctrl-0 = <&pinctrl_esdhc3_1>; cd-gpios = <&gpio3 11 0>; wp-gpios = <&gpio3 12 0>; + bus-width = <8>; status = "okay"; }; -- cgit v1.2.3 From 71686dda2b14e5afca013f7d61653ea155e1e390 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 4 Oct 2013 13:15:27 -0300 Subject: ARM: dts: imx53-qsb: SDHC1 does not have cd-gpios SDHC1 does not have any GPIO for reading the card detection status, so remove 'cd-gpios'. After this change card detection works via the internal SD controller mechanism. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-qsb.dts | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index b646ef1617d5..029ae42357fb 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -122,7 +122,6 @@ &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1_1>; - cd-gpios = <&gpio3 13 0>; status = "okay"; }; @@ -153,7 +152,6 @@ MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 - MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 MX53_PAD_GPIO_16__GPIO7_11 0x80000000 -- cgit v1.2.3 From ecccab3c5f84f7377bd09c094faa8cafa48dc55d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 4 Oct 2013 13:15:28 -0300 Subject: ARM: dts: imx53-qsb: Do not use GPIO1_8 as wakeup source On the mx53qsb board with mc34708 PMIC, GPIO1_8 resets the system, so better not to use it as a wakeup source. Use GPIO 2_14 and 2_15 for wakeup sources instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-qsb.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 029ae42357fb..91a5935a4aac 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -55,19 +55,20 @@ label = "Power Button"; gpios = <&gpio1 8 0>; linux,code = <116>; /* KEY_POWER */ - gpio-key,wakeup; }; volume-up { label = "Volume Up"; gpios = <&gpio2 14 0>; linux,code = <115>; /* KEY_VOLUMEUP */ + gpio-key,wakeup; }; volume-down { label = "Volume Down"; gpios = <&gpio2 15 0>; linux,code = <114>; /* KEY_VOLUMEDOWN */ + gpio-key,wakeup; }; }; -- cgit v1.2.3 From 328aee4b5103fe071ace03cd2ab425fc2186d28b Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 7 Oct 2013 23:13:47 +0900 Subject: ARM: dts: Disable Exynos5250 I2S controllers by default Rather than requiring each board to explicitly disable the I2S controllers it is not using instead require boards to enable those that they are using. This is required for audio operation on Arndale, one of the unused I2S controllers is pinmuxed with the LDO enable GPIOs for the WM1811A. Signed-off-by: Mark Brown Acked-by: Mark Rutland Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-arndale.dts | 4 ++++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 8 -------- arch/arm/boot/dts/exynos5250.dtsi | 3 +++ 3 files changed, 7 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 0c425476d4db..b0dbea8f0286 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -412,6 +412,10 @@ status = "disabled"; }; + i2s0: i2s@03830000 { + status = "okay"; + }; + spi_0: spi@12d20000 { status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 2538b329f2ce..f86d56760a45 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -231,14 +231,6 @@ status = "okay"; }; - i2s1: i2s@12D60000 { - status = "disabled"; - }; - - i2s2: i2s@12D70000 { - status = "disabled"; - }; - sound { compatible = "samsung,smdk-wm8994"; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 7d7cc777ff7b..c863113eed3f 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -417,6 +417,7 @@ i2s0: i2s@03830000 { compatible = "samsung,s5pv210-i2s"; + status = "disabled"; reg = <0x03830000 0x100>; dmas = <&pdma0 10 &pdma0 9 @@ -433,6 +434,7 @@ i2s1: i2s@12D60000 { compatible = "samsung,s3c6410-i2s"; + status = "disabled"; reg = <0x12D60000 0x100>; dmas = <&pdma1 12 &pdma1 11>; @@ -445,6 +447,7 @@ i2s2: i2s@12D70000 { compatible = "samsung,s3c6410-i2s"; + status = "disabled"; reg = <0x12D70000 0x100>; dmas = <&pdma0 12 &pdma0 11>; -- cgit v1.2.3 From 99bda7b901e36ada545656ba40acdcdc091b83d2 Mon Sep 17 00:00:00 2001 From: Wei Ni Date: Mon, 7 Oct 2013 17:28:28 +0800 Subject: ARM: tegra: add DT entry for nct1008 to Dalmore Enable thermal sensor nct1008 for Tegra114 dalmore. Signed-off-by: Wei Ni Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-dalmore.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 871aff5e2b87..cb5ec23b03a7 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -739,6 +739,14 @@ realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; }; + + temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&palmas_ldo6_reg>; + interrupt-parent = <&gpio>; + interrupts = ; + }; }; i2c@7000d000 { @@ -948,7 +956,7 @@ regulator-max-microvolt = <1800000>; }; - ldo6 { + palmas_ldo6_reg: ldo6 { regulator-name = "vdd-sensor-2v85"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; -- cgit v1.2.3 From 7c7de6b03a2ad8a6f429e5a01c94cdf3289d47d1 Mon Sep 17 00:00:00 2001 From: Wei Ni Date: Mon, 7 Oct 2013 17:28:29 +0800 Subject: ARM: tegra: add vcc supply for nct1008 to Cardhu Add vcc-supply property in the nct1008 node, and set it as sys_3v3_reg. change the name of this node to temp-sensor. Signed-off-by: Wei Ni Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-cardhu.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index e19dbf238e5c..5ea7dfa4d9fa 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -294,9 +294,10 @@ }; }; - nct1008 { + temperature-sensor@4c { compatible = "onnn,nct1008"; reg = <0x4c>; + vcc-supply = <&sys_3v3_reg>; interrupt-parent = <&gpio>; interrupts = ; }; -- cgit v1.2.3 From 18fe6ef0b1b1396a4ff991664fbf926d72004859 Mon Sep 17 00:00:00 2001 From: Sean Paul Date: Tue, 8 Oct 2013 06:49:45 +0900 Subject: ARM: dts: add mixer clocks to mixer node for Exynos5250 This patch adds the mixer clocks to the mixer node in the exynos 5250 dts file. Signed-off-by: Sean Paul Signed-off-by: Rahul Sharma Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index c863113eed3f..80a6d08e5044 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -623,6 +623,8 @@ compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; interrupts = <0 94 0>; + clocks = <&clock 343>, <&clock 136>; + clock-names = "mixer", "sclk_hdmi"; }; dp_phy: video-phy@10040720 { -- cgit v1.2.3 From 27c16d19e2ac723fb037c9f6f7994291f8eb3226 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Tue, 8 Oct 2013 06:49:46 +0900 Subject: ARM: dts: add clocks to hdmi dt node for exynos5250 Fix wrong clock numbers in hdmi dt node. Removed hdmiphy clock which was a dummy clock earlier and not required now. Also added mux clock to change the clock parent. Signed-off-by: Rahul Sharma Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 80a6d08e5044..7cb5c4b491c8 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -613,10 +613,10 @@ compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; interrupts = <0 95 0>; - clocks = <&clock 333>, <&clock 136>, <&clock 137>, - <&clock 333>, <&clock 333>; + clocks = <&clock 344>, <&clock 136>, <&clock 137>, + <&clock 159>, <&clock 1024>; clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "hdmiphy"; + "sclk_hdmiphy", "mout_hdmi"; }; mixer { -- cgit v1.2.3 From f49e347b5a6b790a4486301c5b8ce2c2c48bca4e Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Tue, 8 Oct 2013 06:49:46 +0900 Subject: ARM: dts: add i2c device nodes for Exynos5420 This adds device-tree nodes for the i2c busses on Exynos 5420 platforms. Signed-off-by: Andrew Bresticker Signed-off-by: Rahul Sharma Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 56 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index d537cd704e19..77805a56d2c7 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -27,6 +27,10 @@ pinctrl2 = &pinctrl_2; pinctrl3 = &pinctrl_3; pinctrl4 = &pinctrl_4; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; }; cpus { @@ -235,4 +239,56 @@ io-channel-ranges; status = "disabled"; }; + + i2c_0: i2c@12C60000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C60000 0x100>; + interrupts = <0 56 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock 261>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + status = "disabled"; + }; + + i2c_1: i2c@12C70000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C70000 0x100>; + interrupts = <0 57 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock 262>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + status = "disabled"; + }; + + i2c_2: i2c@12C80000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C80000 0x100>; + interrupts = <0 58 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock 263>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; + status = "disabled"; + }; + + i2c_3: i2c@12C90000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C90000 0x100>; + interrupts = <0 59 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock 264>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; + status = "disabled"; + }; }; -- cgit v1.2.3 From b0e505ceea7e20aa25ea70eaf4cef98e71708944 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Tue, 8 Oct 2013 06:49:46 +0900 Subject: ARM: dts: add dt nodes for hdmi subsystem for exynos5420 Add hdmi and mixer device tree nodes for Exynos 5420 SoC. Signed-off-by: Rahul Sharma Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 77805a56d2c7..09aa06cb3d3a 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -291,4 +291,23 @@ pinctrl-0 = <&i2c3_bus>; status = "disabled"; }; + + hdmi@14530000 { + compatible = "samsung,exynos4212-hdmi"; + reg = <0x14530000 0x70000>; + interrupts = <0 95 0>; + clocks = <&clock 413>, <&clock 143>, <&clock 768>, + <&clock 158>, <&clock 640>; + clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", + "sclk_hdmiphy", "mout_hdmi"; + status = "disabled"; + }; + + mixer@14450000 { + compatible = "samsung,exynos5420-mixer"; + reg = <0x14450000 0x10000>; + interrupts = <0 94 0>; + clocks = <&clock 431>, <&clock 143>; + clock-names = "mixer", "sclk_hdmi"; + }; }; -- cgit v1.2.3 From 29f8666109064a400bf6807508209a08b28cf3cd Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Tue, 8 Oct 2013 06:49:46 +0900 Subject: ARM: dts: enable hdmi subsystem for exynos5420 smdk board Add pinctrl node for hdmi hpd gpio pin to exynos5420 smdk board file. hpd Gpio property is added to the hdmi node. This patch also adds hdmi ddc node. Both hdmi device and ddc i2c channel are enabled in exynos5420-smdk5420.dts Signed-off-by: Rahul Sharma Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420-smdk5420.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index bafba25ba7c2..79524c74c603 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -61,4 +61,30 @@ }; }; + pinctrl@13400000 { + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + }; + + hdmi@14530000 { + status = "okay"; + hpd-gpio = <&gpx3 7 0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + }; + + i2c_2: i2c@12C80000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + status = "okay"; + + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; + }; + }; }; -- cgit v1.2.3 From 93457b9cb980ffeeef020c3bcd99065c3807619b Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Tue, 8 Oct 2013 06:53:12 +0900 Subject: ARM: dts: Add HDMI related I2C nodes for Arndale board Updated I2C nodes for HDMI-DDC and HDMI-PHY for Arndale board. Signed-off-by: Sachin Kamat Signed-off-by: Tushar Behera Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-arndale.dts | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index b0dbea8f0286..684527087aa4 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -324,7 +324,14 @@ }; i2c@12C80000 { - status = "disabled"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + samsung,i2c-slave-addr = <0x50>; + + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; + }; }; i2c@12C90000 { @@ -362,6 +369,17 @@ status = "disabled"; }; + i2c@12CE0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + samsung,i2c-slave-addr = <0x38>; + + hdmiphy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; + }; + }; + i2c@121D0000 { status = "disabled"; }; -- cgit v1.2.3 From eda3a4fa9529341f2ce23374e5f295764d0b5838 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 26 Sep 2013 13:06:01 +0200 Subject: ARM: shmobile: only enable used I2C interfaces in DT on all Renesas boards Currently all I2C interfaces in all *.dtsi files for various Renesas SoCs are enabled by default. Switch them all off and only enable populated I2C interfaces in board-specific *.dts files. Signed-off-by: Guennadi Liakhovetski Acked-by: Mark Rutland Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 1 + arch/arm/boot/dts/r8a73a4-ape6evm.dts | 1 + arch/arm/boot/dts/r8a73a4.dtsi | 9 +++++++++ arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 1 + arch/arm/boot/dts/r8a7740.dtsi | 2 ++ arch/arm/boot/dts/r8a7779.dtsi | 4 ++++ arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 2 ++ arch/arm/boot/dts/sh73a0.dtsi | 5 +++++ 8 files changed, 25 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts index 2b49b05ae2f4..9443e93d3cac 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts @@ -62,6 +62,7 @@ }; &i2c5 { + status = "okay"; vdd_dvfs: max8973@1b { compatible = "maxim,max8973"; reg = <0x1b>; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 72f867e65791..91436b58016f 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -52,6 +52,7 @@ }; &i2c5 { + status = "okay"; vdd_dvfs: max8973@1b { compatible = "maxim,max8973"; reg = <0x1b>; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 6c26caa880f2..a2c945670460 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -93,6 +93,7 @@ reg = <0 0xe6500000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 174 0x4>; + status = "disabled"; }; i2c1: i2c@e6510000 { @@ -102,6 +103,7 @@ reg = <0 0xe6510000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 175 0x4>; + status = "disabled"; }; i2c2: i2c@e6520000 { @@ -111,6 +113,7 @@ reg = <0 0xe6520000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 176 0x4>; + status = "disabled"; }; i2c3: i2c@e6530000 { @@ -120,6 +123,7 @@ reg = <0 0xe6530000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 177 0x4>; + status = "disabled"; }; i2c4: i2c@e6540000 { @@ -129,6 +133,7 @@ reg = <0 0xe6540000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 178 0x4>; + status = "disabled"; }; i2c5: i2c@e60b0000 { @@ -138,6 +143,7 @@ reg = <0 0xe60b0000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 179 0x4>; + status = "disabled"; }; i2c6: i2c@e6550000 { @@ -147,6 +153,7 @@ reg = <0 0xe6550000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 184 0x4>; + status = "disabled"; }; i2c7: i2c@e6560000 { @@ -156,6 +163,7 @@ reg = <0 0xe6560000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 185 0x4>; + status = "disabled"; }; i2c8: i2c@e6570000 { @@ -165,6 +173,7 @@ reg = <0 0xe6570000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 173 0x4>; + status = "disabled"; }; mmcif0: mmcif@ee200000 { diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index c638e4ab91b8..9fcffc175da2 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -52,6 +52,7 @@ }; &i2c0 { + status = "okay"; touchscreen: st1232@55 { compatible = "sitronix,st1232"; reg = <0x55>; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 44d3d520e01f..868bdded237c 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -131,6 +131,7 @@ 0 202 0x4 0 203 0x4 0 204 0x4>; + status = "disabled"; }; i2c1: i2c@e6c20000 { @@ -143,6 +144,7 @@ 0 71 0x4 0 72 0x4 0 73 0x4>; + status = "disabled"; }; pfc: pfc@e6050000 { diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 23a62447359c..65dc6528bc85 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -156,6 +156,7 @@ reg = <0xffc70000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 0x4>; + status = "disabled"; }; i2c1: i2c@ffc71000 { @@ -165,6 +166,7 @@ reg = <0xffc71000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 0x4>; + status = "disabled"; }; i2c2: i2c@ffc72000 { @@ -174,6 +176,7 @@ reg = <0xffc72000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 0x4>; + status = "disabled"; }; i2c3: i2c@ffc73000 { @@ -183,6 +186,7 @@ reg = <0xffc73000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 0x4>; + status = "disabled"; }; pfc: pfc@fffc0000 { diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 212230629f27..8ee06dd81799 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -108,6 +108,7 @@ }; &i2c0 { + status = "okay"; as3711@40 { compatible = "ams,as3711"; reg = <0x40>; @@ -183,6 +184,7 @@ &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; + status = "okay"; }; &mmcif { diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index ba59a5875a10..f56665af1e42 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -135,6 +135,7 @@ 0 168 0x4 0 169 0x4 0 170 0x4>; + status = "disabled"; }; i2c1: i2c@e6822000 { @@ -147,6 +148,7 @@ 0 52 0x4 0 53 0x4 0 54 0x4>; + status = "disabled"; }; i2c2: i2c@e6824000 { @@ -159,6 +161,7 @@ 0 172 0x4 0 173 0x4 0 174 0x4>; + status = "disabled"; }; i2c3: i2c@e6826000 { @@ -171,6 +174,7 @@ 0 184 0x4 0 185 0x4 0 186 0x4>; + status = "disabled"; }; i2c4: i2c@e6828000 { @@ -183,6 +187,7 @@ 0 188 0x4 0 189 0x4 0 190 0x4>; + status = "disabled"; }; mmcif: mmcif@e6bd0000 { -- cgit v1.2.3 From edd2b9f4e6ed39032ffe9793e262c8a4b62c2152 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 26 Sep 2013 19:20:58 +0200 Subject: ARM: shmobile: r8a7790: add I2C DT nodes Add DT nodes for the four I2C interfacces on r8a7790. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index a0cfb6618884..47bc1cbfd075 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -176,6 +176,46 @@ interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; }; + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790"; + reg = <0 0xe6508000 0 0x40>; + interrupt-parent = <&gic>; + interrupts = <0 287 0x4>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790"; + reg = <0 0xe6518000 0 0x40>; + interrupt-parent = <&gic>; + interrupts = <0 288 0x4>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790"; + reg = <0 0xe6530000 0 0x40>; + interrupt-parent = <&gic>; + interrupts = <0 286 0x4>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7790"; + reg = <0 0xe6540000 0 0x40>; + interrupt-parent = <&gic>; + interrupts = <0 290 0x4>; + status = "disabled"; + }; + mmcif0: mmcif@ee200000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; -- cgit v1.2.3 From 734e2ce38c6aa3e88f0a339f001d272196f26dfa Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 26 Sep 2013 19:30:03 +0200 Subject: ARM: shmobile: r8a73a4: add a DT node for the DMAC Add a DT node for the only system DMAC instance on r8a73a4. The RT DMAC can be added later under the same multiplexer, because they can serve the same slaves and use the same MID-RID values. Configuration data is supplied to the driver, using a compatibility match string. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 43 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index a2c945670460..8c81a0c21178 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -78,6 +78,49 @@ <0 56 4>, <0 57 4>; }; + dmac: dma-multiplexer@0 { + compatible = "renesas,shdma-mux"; + #dma-cells = <1>; + dma-channels = <20>; + dma-requests = <256>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dma0: dma-controller@e6700020 { + compatible = "renesas,shdma-r8a73a4"; + reg = <0 0xe6700020 0 0x89e0>; + interrupt-parent = <&gic>; + interrupts = <0 220 4 + 0 200 4 + 0 201 4 + 0 202 4 + 0 203 4 + 0 204 4 + 0 205 4 + 0 206 4 + 0 207 4 + 0 208 4 + 0 209 4 + 0 210 4 + 0 211 4 + 0 212 4 + 0 213 4 + 0 214 4 + 0 215 4 + 0 216 4 + 0 217 4 + 0 218 4 + 0 219 4>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19"; + }; + }; + thermal@e61f0000 { compatible = "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, -- cgit v1.2.3 From 87b73d88723601636646a69445f89c0e498fff71 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Sep 2013 13:51:13 +0200 Subject: ARM: shmobile: armadillo-reference: Add PWM backlight node to DT Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- .../boot/dts/r8a7740-armadillo800eva-reference.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 9fcffc175da2..8b2aab5c1d3c 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -11,6 +11,7 @@ /dts-v1/; /include/ "r8a7740.dtsi" #include +#include / { model = "armadillo 800 eva reference"; @@ -49,6 +50,15 @@ gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; }; }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; + brightness-levels = <0 1 2 4 8 16 32 64 128 255>; + default-brightness-level = <9>; + pinctrl-0 = <&backlight_pins>; + pinctrl-names = "default"; + }; }; &i2c0 { @@ -77,4 +87,13 @@ renesas,groups = "intc_irq10"; renesas,function = "intc"; }; + + backlight_pins: backlight { + renesas,groups = "tpu0_to2_1"; + renesas,function = "tpu0"; + }; +}; + +&tpu { + status = "okay"; }; -- cgit v1.2.3 From e99d7963e0b9469f16f434a5a68a7cba3004a2df Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 27 Sep 2013 10:02:57 +0200 Subject: ARM: shmobile: armadillo800eva-reference: add SDHI and MMCIF interfaces Add SDHI0 and MMCIF interfaces to armadillo800eva-reference with regulators and pin configurations. SDHI1 is not added yet, because the switch, that connects the interface either to an SD slot or to a WiFi SDIO card cannot be described in DT yet. Signed-off-by: Guennadi Liakhovetski Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- .../boot/dts/r8a7740-armadillo800eva-reference.dts | 58 ++++++++++++++++++++++ arch/arm/boot/dts/r8a7740.dtsi | 33 ++++++++++++ 2 files changed, 91 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 8b2aab5c1d3c..1c56c5e56950 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -35,6 +35,33 @@ regulator-boot-on; }; + vcc_sdhi0: regulator@1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pfc 75 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator@2 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sdhi0>; + + enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>; + gpios = <&pfc 17 GPIO_ACTIVE_HIGH>; + states = <3300000 0 + 1800000 1>; + + enable-active-high; + }; + leds { compatible = "gpio-leds"; led1 { @@ -92,8 +119,39 @@ renesas,groups = "tpu0_to2_1"; renesas,function = "tpu0"; }; + + mmc0_pins: mmc0 { + renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1"; + renesas,function = "mmc0"; + }; + + sdhi0_pins: sdhi0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; + renesas,function = "sdhi0"; + }; }; &tpu { status = "okay"; }; + +&mmcif0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 868bdded237c..ae1e230f711d 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -161,4 +161,37 @@ status = "disabled"; #pwm-cells = <3>; }; + + mmcif0: mmcif@e6bd0000 { + compatible = "renesas,sh-mmcif"; + reg = <0xe6bd0000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 56 4 + 0 57 4>; + status = "disabled"; + }; + + sdhi0: sdhi@e6850000 { + compatible = "renesas,sdhi-r8a7740"; + reg = <0xe6850000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 117 4 + 0 118 4 + 0 119 4>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: sdhi@e6860000 { + compatible = "renesas,sdhi-r8a7740"; + reg = <0xe6860000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 121 4 + 0 122 4 + 0 123 4>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; }; -- cgit v1.2.3 From d77db73e260fe4b5cca4fa1e5253c21e2d755f58 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 1 Oct 2013 17:12:29 +0900 Subject: ARM: shmobile: r8a7791 IRQC device tree node Enable a r8a7791 IRQC block by adding a device tree node for the IRQC hardware and pins IRQ0 to IRQ9. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index bbed43bd9be9..b70141758de1 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -38,4 +38,22 @@ <0 0xf1006000 0 0x2000>; interrupts = <1 9 0xf04>; }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 0 4>, + <0 1 4>, + <0 2 4>, + <0 3 4>, + <0 12 4>, + <0 13 4>, + <0 14 4>, + <0 15 4>, + <0 16 4>, + <0 17 4>; + }; }; -- cgit v1.2.3 From 03586acf7808ed65963cd262188b059ff6951d40 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 1 Oct 2013 17:12:38 +0900 Subject: ARM: shmobile: r8a7791 Arch timer device tree node Add r8a7791 arch timer device tree information. This needs to be used together with r8a7791 support code that ties in the R-Car Gen2 arch timer workarounds. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index b70141758de1..a1a9e5c4813d 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -39,6 +39,14 @@ interrupts = <1 9 0xf04>; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + irqc0: interrupt-controller@e61c0000 { compatible = "renesas,irqc"; #interrupt-cells = <2>; -- cgit v1.2.3 From 15ab426c0f1935016ea52cfedf0d808f8c79dd1e Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 1 Oct 2013 17:13:07 +0900 Subject: ARM: shmobile: r8a7791 SMP device tree node Add a device node for the r8a7791 secondary CPU core. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index a1a9e5c4813d..fea5cfef4691 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -25,6 +25,13 @@ reg = <0>; clock-frequency = <1300000000>; }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1300000000>; + }; }; gic: interrupt-controller@f1001000 { -- cgit v1.2.3 From 87f1ba80179a75ae1e2e783b890adb39949c7c03 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 2 Oct 2013 01:32:12 -0700 Subject: ARM: shmobile: r8a7778: add renesas_intc_irqpin support on DTSI Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 45ac404ab6d8..5d08f1162e8c 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -33,6 +33,25 @@ <0xfe430000 0x100>; }; + /* irqpin: IRQ0 - IRQ3 */ + irqpin: irqpin@fe78001c { + compatible = "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + status = "disabled"; /* default off */ + reg = <0xfe78001c 4>, + <0xfe780010 4>, + <0xfe780024 4>, + <0xfe780044 4>, + <0xfe780064 4>; + interrupt-parent = <&gic>; + interrupts = <0 27 0x4 + 0 28 0x4 + 0 29 0x4 + 0 30 0x4>; + sense-bitfield-width = <2>; + }; + gpio0: gpio@ffc40000 { compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc40000 0x2c>; -- cgit v1.2.3 From 1e918e00ea2aa2d23a3e0552e907c1da104cdc39 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 2 Oct 2013 01:34:07 -0700 Subject: ARM: shmobile: bockw: add SMSC support on DTS This patch enables INTC IRQ and SMSC on BockW board via DT. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 9bb903a3230d..4425fd2e09f4 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -22,11 +22,36 @@ compatible = "renesas,bockw-reference", "renesas,r8a7778"; chosen { - bootargs = "console=ttySC0,115200 ignore_loglevel rw"; + bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; }; memory { device_type = "memory"; reg = <0x60000000 0x10000000>; }; + + fixedregulator3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + lan0@18300000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x18300000 0x1000>; + + phy-mode = "mii"; + interrupt-parent = <&irqpin>; + interrupts = <0 0>; /* IRQ0: hwirq 0 on irqpin */ + reg-io-width = <4>; + vddvario-supply = <&fixedregulator3v3>; + vdd33a-supply = <&fixedregulator3v3>; + }; +}; + +&irqpin { + status = "okay"; }; -- cgit v1.2.3 From bffdd7d1a4249dddf1ded81e412cf3c78d139e38 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 2 Oct 2013 01:40:20 -0700 Subject: ARM: shmobile: marzen: fixup SMSC IRQ number on DTS This patch fixup miss-setting of SMSC IRQ number. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779-marzen-reference.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index 6d5508392252..ab4110aa3c3b 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -42,8 +42,8 @@ pinctrl-names = "default"; phy-mode = "mii"; - interrupt-parent = <&gic>; - interrupts = <0 28 0x4>; + interrupt-parent = <&irqpin0>; + interrupts = <1 0>; /* IRQ1: hwirq 1 on irqpin0 */ reg-io-width = <4>; vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; @@ -63,6 +63,10 @@ }; }; +&irqpin0 { + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From 84b47dfc1b1638c40257382d2216d1668cfca3d0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 2 Oct 2013 01:39:13 -0700 Subject: ARM: shmobile: r8a7779: add irqpin default status on DTSI r8a7779 INTC needs IRL pin mode settings to determine behavior of IRQ0 - IRQ3. But it depends on platform. This patch adds status = "disabled" on r8a7779.dtsi as default Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 65dc6528bc85..c2fb49b54b4f 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -135,6 +135,7 @@ irqpin0: irqpin@fe780010 { compatible = "renesas,intc-irqpin"; #interrupt-cells = <2>; + status = "disabled"; interrupt-controller; reg = <0xfe78001c 4>, <0xfe780010 4>, -- cgit v1.2.3 From 73c79afa61cdee2553461ee714bb4716372bdd55 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Oct 2013 18:20:19 -0700 Subject: ARM: shmobile: bockw: fixup ether node naming According to the ePAPR spec, the node name should be "ethernet", not "lan0". Reported-by: Sergei Shtylyov Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 4425fd2e09f4..969e386e852c 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -39,7 +39,7 @@ regulator-always-on; }; - lan0@18300000 { + ethernet@18300000 { compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0x18300000 0x1000>; -- cgit v1.2.3 From 5d150eac17e1b8eb153c69939ad5f90e10ea2350 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sun, 6 Oct 2013 13:48:52 +0200 Subject: ARM: imx51-apf51dev: Add parallel display support Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-apf51dev.dts | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts index 123fe84e0e8c..5a7f552786a1 100644 --- a/arch/arm/boot/dts/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/imx51-apf51dev.dts @@ -16,6 +16,33 @@ model = "Armadeus Systems APF51Dev docking/development board"; compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; + display@di1 { + compatible = "fsl,imx-parallel-display"; + crtcs = <&ipu 0>; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp1_1>; + + display-timings { + lw700 { + native-mode; + clock-frequency = <33000033>; + hactive = <800>; + vactive = <480>; + hback-porch = <96>; + hfront-porch = <96>; + vback-porch = <20>; + vfront-porch = <21>; + hsync-len = <64>; + vsync-len = <4>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; -- cgit v1.2.3 From e724a2fc00609db1e4efae9e855fbc94fba915d2 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sun, 6 Oct 2013 16:07:54 +0200 Subject: ARM: imx27-apf27dev: Add framebuffer support Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-apf27dev.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 2a377ca1881a..47c8c26012e4 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts @@ -16,6 +16,26 @@ model = "Armadeus Systems APF27Dev docking/development board"; compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27"; + display: display { + model = "Chimei-LW700AT9003"; + native-mode = <&timing0>; + bits-per-pixel = <16>; /* non-standard but required */ + fsl,pcr = <0xfae80083>; /* non-standard but required */ + display-timings { + timing0: 640x480 { + clock-frequency = <33000033>; + hactive = <800>; + vactive = <640>; + hback-porch = <96>; + hfront-porch = <96>; + vback-porch = <20>; + vfront-porch = <21>; + hsync-len = <64>; + vsync-len = <4>; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -50,6 +70,12 @@ status = "okay"; }; +&fb { + display = <&display>; + fsl,dmacr = <0x00020010>; + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; status = "okay"; -- cgit v1.2.3 From 01ed6632a554dfdf4a9fc3c593ce4ff7255ed161 Mon Sep 17 00:00:00 2001 From: Oliver Schinagl Date: Tue, 8 Oct 2013 10:22:32 +0200 Subject: ARM: sunxi: dts: Add support for the cubieboard3, the CubieTruck Cubietech introduced a new cubieboard, the CubieTruck. This board added more output connectors and features 2 GiB of RAM and a Gigabit PHY. Tested are are uart0 and LEDS which both work as expected. Signed-off-by: Oliver Schinagl Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 63 ++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 arch/arm/boot/dts/sun7i-a20-cubietruck.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index cc0f1fb61753..171e6c7bb1f2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -232,6 +232,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ sun5i-a13-olinuxino.dtb \ sun6i-a31-colombus.dtb \ sun7i-a20-cubieboard2.dtb \ + sun7i-a20-cubietruck.dtb \ sun7i-a20-olinuxino-micro.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-iris-512.dtb \ diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts new file mode 100644 index 000000000000..8a1009d6c829 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -0,0 +1,63 @@ +/* + * Copyright 2013 Oliver Schinagl + * + * Oliver Schinagl + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" + +/ { + model = "Cubietech Cubietruck"; + compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; + + soc@01c00000 { + pinctrl@01c20800 { + led_pins_cubietruck: led_pins@0 { + allwinner,pins = "PH7", "PH11", "PH20", "PH21"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_cubietruck>; + + blue { + label = "cubietruck:blue:usr"; + gpios = <&pio 7 21 0>; + }; + + orange { + label = "cubietruck:orange:usr"; + gpios = <&pio 7 20 0>; + }; + + white { + label = "cubietruck:white:usr"; + gpios = <&pio 7 11 0>; + }; + + green { + label = "cubietruck:green:usr"; + gpios = <&pio 7 7 0>; + }; + }; +}; -- cgit v1.2.3 From a4d4b15363ea31236e557c471d9aa95202fed88a Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Tue, 13 Aug 2013 15:36:36 +0200 Subject: ARM: dts: N900: Add device tree This adds device tree with necessary support to boot with functional video (on both emulator and real N900 device). Signed-off-by: Pavel Machek Signed-off-by: Aaro Koskinen Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/omap3-n900.dts | 92 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 93 insertions(+) create mode 100644 arch/arm/boot/dts/omap3-n900.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 802720e3e8fd..a7cae5371489 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -172,6 +172,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap3-devkit8000.dtb \ omap3-beagle-xm.dtb \ omap3-evm.dtb \ + omap3-n900.dtb \ omap3-tobi.dtb \ omap3-igep0020.dtb \ omap3-igep0030.dtb \ diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts new file mode 100644 index 000000000000..d64fa04e83f6 --- /dev/null +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2013 Pavel Machek + * Copyright 2013 Aaro Koskinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 (or later) as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "omap34xx.dtsi" + +/ { + model = "Nokia N900"; + compatible = "nokia,omap3-n900", "ti,omap3"; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + +}; + +&i2c1 { + clock-frequency = <2200000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +#include "twl4030.dtsi" + +&twl_gpio { + ti,pullups = <0x0>; + ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <100000>; +}; + +&mmc1 { + status = "disabled"; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&mcspi1 { + /* + * For some reason, touchscreen is necessary for screen to work at + * all on real hw. It works well without it on emulator. + * + * Also... order in the device tree actually matters here. + */ + tsc2005@0 { + compatible = "tsc2005"; + spi-max-frequency = <6000000>; + reg = <0>; + }; + mipid@2 { + compatible = "acx565akm"; + spi-max-frequency = <6000000>; + reg = <2>; + }; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + mode = <2>; + power = <50>; +}; -- cgit v1.2.3 From 00964a90728d752abe61ad134dac8c13491c3595 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 20 Jun 2013 16:42:30 +0200 Subject: ARM: dts: omap3-igep: add pinmux node for GPIO LED configuration IGEP boards have a number of LED connected to OMAP or TWL GPIO lines. The actual wiring is different on each board so each board DT has need to configure the mux correctly. Even though it works with the current DT, the kernel complains with: [2.305023] leds-gpio leds.18: pins are not configured from the driver Add an empty pinmux_leds_pins pinctrl child node so boards can override with the correct mux configuration and not depend on default values for the GPIO LEDs to work. Signed-off-by: Javier Martinez Canillas Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-igep.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index 2326d11462a5..0f92224dc4fc 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -77,6 +77,8 @@ 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ >; }; + + leds_pins: pinmux_leds_pins { }; }; &i2c1 { -- cgit v1.2.3 From bd52e2d274d369182f38d9ddaf8ce910c2a7332f Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 20 Jun 2013 16:42:31 +0200 Subject: ARM: dts: omap3-igep0020: add mux conf for GPIO LEDs The IGEPv2 has a number of GPIO LED connected to OMAP pins. Configure these pins as output GPIO. Signed-off-by: Javier Martinez Canillas Tested-by: Enric Balletbo i Serra Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-igep0020.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index e8c48284587c..51c084eeb7bd 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -16,7 +16,10 @@ compatible = "isee,omap3-igep0020", "ti,omap3"; leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; compatible = "gpio-leds"; + boot { label = "omap3:green:boot"; gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; @@ -54,6 +57,14 @@ }; }; +&leds_pins { + pinctrl-single,pins = < + 0x5c4 (PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ + 0x5c6 (PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ + 0x5c8 (PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ + >; +}; + &i2c3 { clock-frequency = <100000>; -- cgit v1.2.3 From 78132036da5e11e9d54ef1d62d41255ccdae1c4f Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 20 Jun 2013 16:42:32 +0200 Subject: ARM: dts: omap3-igep0030: add mux conf for GPIO LED The IGEP COM MOdule has a GPIO LED connected to OMAP pins. Configure this pin as output GPIO. Signed-off-by: Javier Martinez Canillas Tested-by: Enric Balletbo i Serra Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-igep0030.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts index 644d05383836..eee3c632b260 100644 --- a/arch/arm/boot/dts/omap3-igep0030.dts +++ b/arch/arm/boot/dts/omap3-igep0030.dts @@ -16,7 +16,10 @@ compatible = "isee,omap3-igep0030", "ti,omap3"; leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; compatible = "gpio-leds"; + boot { label = "omap3:green:boot"; gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; @@ -43,6 +46,12 @@ }; }; +&leds_pins { + pinctrl-single,pins = < + 0x5b0 (PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ + >; +}; + &gpmc { ranges = <0 0 0x00000000 0x20000000>; -- cgit v1.2.3 From 6797cdbe14b262c3bcb5a65b1488ae46fdc6b4db Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 3 Aug 2013 20:00:54 +0200 Subject: ARM: dts: AM33XX: Add PMU support ARM Performance Monitor Units are available on the am33xx, add the support in the dtsi. Tested with perf and oprofile on a regular beaglebone. Signed-off-by: Alexandre Belloni Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index f9c5da9c7fe1..4d1c6321b252 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -57,6 +57,11 @@ }; }; + pmu { + compatible = "arm,cortex-a8-pmu"; + interrupts = <3>; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. -- cgit v1.2.3 From 5eac0eb7af0982afae4788441533cc208ede3ff4 Mon Sep 17 00:00:00 2001 From: Lars Poeschel Date: Wed, 7 Aug 2013 13:06:32 +0200 Subject: ARM: dts: AM33xx: Correct gpio #interrupt-cells property Following commit ff5c9059 and therefore other omap platforms using the gpio-omap driver correct the #interrupt-cells property on am33xx too. The omap gpio binding documentaion also states that the #interrupt-cells property should be 2. Signed-off-by: Lars Poeschel Reviewed-by: Javier Martinez Canillas Acked-by: Mark Rutland Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 4d1c6321b252..a7731ead0b91 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -111,7 +111,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; reg = <0x44e07000 0x1000>; interrupts = <96>; }; @@ -122,7 +122,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; reg = <0x4804c000 0x1000>; interrupts = <98>; }; @@ -133,7 +133,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; reg = <0x481ac000 0x1000>; interrupts = <32>; }; @@ -144,7 +144,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; reg = <0x481ae000 0x1000>; interrupts = <62>; }; -- cgit v1.2.3 From 9448996c09509dac80b97a1803bd31b2f99cbc5c Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 12 Aug 2013 15:07:01 +0530 Subject: ARM: dts: omap5-uevm: Split SMPS10 in two nodes SMPS10 has two outputs OUT1 and OUT2. Hence SMPS10 is modeled as two regulators. The DT node is split to reflect it. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-uevm.dts | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 65d7b601651c..05b9b126f084 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -334,9 +334,18 @@ ti,smps-range = <0x80>; }; - smps10_reg: smps10 { + smps10_out2_reg: smps10_out2 { /* VBUS_5V_OTG */ - regulator-name = "smps10"; + regulator-name = "smps10_out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps10_out1_reg: smps10_out1 { + /* VBUS_5V_OTG */ + regulator-name = "smps10_out1"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; -- cgit v1.2.3 From f1d6ed21944fedc6552e46d38a03127aeaef2d41 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 22 Jul 2013 11:52:31 +0100 Subject: ARM: dts: Remove '0x's from OMAP2420 H4 DTS file Cc: Tony Lindgren Signed-off-by: Lee Jones Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap2420-h4.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts index 224c08f472f4..34cdecb4fdda 100644 --- a/arch/arm/boot/dts/omap2420-h4.dts +++ b/arch/arm/boot/dts/omap2420-h4.dts @@ -50,15 +50,15 @@ label = "bootloader"; reg = <0 0x20000>; }; - partition@0x20000 { + partition@20000 { label = "params"; reg = <0x20000 0x20000>; }; - partition@0x40000 { + partition@40000 { label = "kernel"; reg = <0x40000 0x200000>; }; - partition@0x240000 { + partition@240000 { label = "file-system"; reg = <0x240000 0x3dc0000>; }; -- cgit v1.2.3 From 8771c9625b6eec65a2a503b1a48ea6d49fc0d5ca Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 22 Jul 2013 11:52:32 +0100 Subject: ARM: dts: Remove '0x's from OMAP3 IGEP0020 DTS file Cc: Tony Lindgren Signed-off-by: Lee Jones Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-igep0020.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index 51c084eeb7bd..eedf0d8b42d5 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -110,19 +110,19 @@ label = "SPL"; reg = <0 0x100000>; }; - partition@0x80000 { + partition@80000 { label = "U-Boot"; reg = <0x100000 0x180000>; }; - partition@0x1c0000 { + partition@1c0000 { label = "Environment"; reg = <0x280000 0x100000>; }; - partition@0x280000 { + partition@280000 { label = "Kernel"; reg = <0x380000 0x300000>; }; - partition@0x780000 { + partition@780000 { label = "Filesystem"; reg = <0x680000 0x1f980000>; }; -- cgit v1.2.3 From fa304a88e7664c32118dfb58fe44cfdffc323f59 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 22 Jul 2013 11:52:33 +0100 Subject: ARM: dts: Remove '0x's from OMAP3 IGEP0030 DTS file Cc: Tony Lindgren Signed-off-by: Lee Jones Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-igep0030.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts index eee3c632b260..525e6d9b0978 100644 --- a/arch/arm/boot/dts/omap3-igep0030.dts +++ b/arch/arm/boot/dts/omap3-igep0030.dts @@ -83,19 +83,19 @@ label = "SPL"; reg = <0 0x100000>; }; - partition@0x80000 { + partition@80000 { label = "U-Boot"; reg = <0x100000 0x180000>; }; - partition@0x1c0000 { + partition@1c0000 { label = "Environment"; reg = <0x280000 0x100000>; }; - partition@0x280000 { + partition@280000 { label = "Kernel"; reg = <0x380000 0x300000>; }; - partition@0x780000 { + partition@780000 { label = "Filesystem"; reg = <0x680000 0x1f980000>; }; -- cgit v1.2.3 From b7317777102e54472e747361a907314a8da1f4e0 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 22 Jul 2013 11:52:34 +0100 Subject: ARM: dts: Remove '0x's from OMAP3 DTS file Cc: Tony Lindgren Signed-off-by: Lee Jones Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 7d95cda1fae4..16420ae16004 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -111,7 +111,7 @@ pinctrl-single,function-mask = <0x7f1f>; }; - omap3_pmx_wkup: pinmux@0x48002a00 { + omap3_pmx_wkup: pinmux@48002a00 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x48002a00 0x5c>; #address-cells = <1>; -- cgit v1.2.3 From ee8530b41b42bea58e6c78744bc7a75db2781995 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 22 Jul 2013 11:52:35 +0100 Subject: ARM: dts: Remove '0x's from OMAP3430 SDP DTS file Cc: Tony Lindgren Signed-off-by: Lee Jones Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3430-sdp.dts | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index e2249bcc3e63..281914ed0151 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts @@ -84,15 +84,15 @@ label = "bootloader-nor"; reg = <0 0x40000>; }; - partition@0x40000 { + partition@40000 { label = "params-nor"; reg = <0x40000 0x40000>; }; - partition@0x80000 { + partition@80000 { label = "kernel-nor"; reg = <0x80000 0x200000>; }; - partition@0x280000 { + partition@280000 { label = "filesystem-nor"; reg = <0x240000 0x7d80000>; }; @@ -125,19 +125,19 @@ label = "xloader-nand"; reg = <0 0x80000>; }; - partition@0x80000 { + partition@80000 { label = "bootloader-nand"; reg = <0x80000 0x140000>; }; - partition@0x1c0000 { + partition@1c0000 { label = "params-nand"; reg = <0x1c0000 0xc0000>; }; - partition@0x280000 { + partition@280000 { label = "kernel-nand"; reg = <0x280000 0x500000>; }; - partition@0x780000 { + partition@780000 { label = "filesystem-nand"; reg = <0x780000 0x7880000>; }; @@ -170,19 +170,19 @@ label = "xloader-onenand"; reg = <0 0x80000>; }; - partition@0x80000 { + partition@80000 { label = "bootloader-onenand"; reg = <0x80000 0x40000>; }; - partition@0xc0000 { + partition@c0000 { label = "params-onenand"; reg = <0xc0000 0x20000>; }; - partition@0xe0000 { + partition@e0000 { label = "kernel-onenand"; reg = <0xe0000 0x200000>; }; - partition@0x2e0000 { + partition@2e0000 { label = "filesystem-onenand"; reg = <0x2e0000 0xfd20000>; }; -- cgit v1.2.3 From 75d71d46106b93d2e08de91347793cebf1132b95 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 22 Jul 2013 11:52:36 +0100 Subject: ARM: dts: Remove '0x's from OMAP4 DTS file Cc: Tony Lindgren Signed-off-by: Lee Jones Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 22d9f2b593d4..45708e1b7a74 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -56,7 +56,7 @@ cache-level = <2>; }; - local-timer@0x48240600 { + local-timer@48240600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x48240600 0x20>; interrupts = ; -- cgit v1.2.3 From 8906d654992b472ce270d056f523ec21dd06cd3c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 22 Jul 2013 11:52:37 +0100 Subject: ARM: dts: Remove '0x's from OMAP5 DTS file Cc: Tony Lindgren Signed-off-by: Lee Jones Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 7cdea1bfea09..ecc06a99fd4d 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -604,7 +604,7 @@ ti,hwmods = "wd_timer2"; }; - emif1: emif@0x4c000000 { + emif1: emif@4c000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif1"; phy-type = <2>; /* DDR PHY type: Intelli PHY */ @@ -615,7 +615,7 @@ hw-caps-temp-alert; }; - emif2: emif@0x4d000000 { + emif2: emif@4d000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif2"; phy-type = <2>; /* DDR PHY type: Intelli PHY */ -- cgit v1.2.3 From 06a9ea5d76fdff82d9792d8cc315de4c43086780 Mon Sep 17 00:00:00 2001 From: Ruslan Bilovol Date: Wed, 14 Aug 2013 11:35:47 +0300 Subject: ARM: dts: twl6030: Move common configuration for OMAP4 boards in a separate dtsi file The OMAP4 SoC family uses specially-designed PMIC (power management IC) companion chip for power management needs: TWL6030/TWL6032. Therefore there is a typical connection of PMIC to OMAP4 so we can move it into separate .dtsi file and do not duplicate over board-specific files. Tested on OMAP4 SDP board and Pandaboard ES2. Signed-off-by: Ruslan Bilovol Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4-panda-common.dtsi | 21 +---------------- arch/arm/boot/dts/omap4-sdp.dts | 21 +---------------- arch/arm/boot/dts/twl6030_omap4.dtsi | 38 +++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+), 40 deletions(-) create mode 100644 arch/arm/boot/dts/twl6030_omap4.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 814ab67c8c29..43b7661cfe24 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -122,23 +122,9 @@ }; }; -&omap4_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = < - &twl6030_wkup_pins - >; - - twl6030_wkup_pins: pinmux_twl6030_wkup_pins { - pinctrl-single,pins = < - 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ - >; - }; -}; - &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < - &twl6030_pins &twl6040_pins &mcpdm_pins &mcbsp1_pins @@ -147,12 +133,6 @@ &hsusbb1_pins >; - twl6030_pins: pinmux_twl6030_pins { - pinctrl-single,pins = < - 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ - >; - }; - twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ @@ -305,6 +285,7 @@ }; #include "twl6030.dtsi" +#include "twl6030_omap4.dtsi" &i2c2 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 4f78380ecdb8..5fc3f43c5a81 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -155,23 +155,9 @@ }; }; -&omap4_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = < - &twl6030_wkup_pins - >; - - twl6030_wkup_pins: pinmux_twl6030_wkup_pins { - pinctrl-single,pins = < - 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ - >; - }; -}; - &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < - &twl6030_pins &twl6040_pins &mcpdm_pins &dmic_pins @@ -206,12 +192,6 @@ >; }; - twl6030_pins: pinmux_twl6030_pins { - pinctrl-single,pins = < - 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ - >; - }; - twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ @@ -370,6 +350,7 @@ }; #include "twl6030.dtsi" +#include "twl6030_omap4.dtsi" &i2c2 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/twl6030_omap4.dtsi b/arch/arm/boot/dts/twl6030_omap4.dtsi new file mode 100644 index 000000000000..a4fa5703c42b --- /dev/null +++ b/arch/arm/boot/dts/twl6030_omap4.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&twl { + /* + * On most OMAP4 platforms, the twl6030 IRQ line is connected + * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is + * connected to the fref_clk0_out.sys_drm_msecure line. + * Therefore, configure the defaults for the SYS_NIRQ1 and + * fref_clk0_out.sys_drm_msecure pins here. + */ + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_pins + &twl6030_wkup_pins + >; +}; + +&omap4_pmx_wkup { + twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + pinctrl-single,pins = < + 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ + >; + }; +}; + +&omap4_pmx_core { + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ + >; + }; +}; -- cgit v1.2.3 From 6e58b8f1daaf1af340fb9309907e5ffa473c7aff Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Wed, 14 Aug 2013 19:08:20 +0530 Subject: ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board Add minimal device tree source needed for DRA7 based SoCs. Also add a board dts file for the dra7-evm (based on dra752) which contains 1.5G of memory with 1G interleaved and 512MB non-interleaved. Also added in the board file are pin configuration details for i2c, mcspi and uart devices on board. Signed-off-by: R Sricharan Signed-off-by: Rajendra Nayak Signed-off-by: Sourav Poddar Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/dra7-evm.dts | 140 ++++++++++ arch/arm/boot/dts/dra7.dtsi | 575 ++++++++++++++++++++++++++++++++++++++ include/dt-bindings/pinctrl/dra.h | 50 ++++ 4 files changed, 767 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/dra7-evm.dts create mode 100644 arch/arm/boot/dts/dra7.dtsi create mode 100644 include/dt-bindings/pinctrl/dra.h (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a7cae5371489..b057b0e12d7c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -189,7 +189,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ am335x-boneblack.dtb \ am3517-evm.dtb \ am3517_mt_ventoux.dtb \ - am43x-epos-evm.dtb + am43x-epos-evm.dtb \ + dra7-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts new file mode 100644 index 000000000000..ca5dab2214d5 --- /dev/null +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra7.dtsi" + +/ { + model = "TI DRA7"; + compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x60000000>; /* 1536 MB */ + }; +}; + +&dra7_pmx_core { + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ + 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + 0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */ + 0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + >; + }; + + mcspi1_pins: pinmux_mcspi1_pins { + pinctrl-single,pins = < + 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */ + 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */ + 0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */ + 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ + 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */ + 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */ + 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */ + >; + }; + + mcspi2_pins: pinmux_mcspi2_pins { + pinctrl-single,pins = < + 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */ + 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ + 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ + 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ + 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ + 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ + 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */ + 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */ + 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ + 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ + 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ + >; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <3400000>; +}; + +&mcspi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; +}; + +&mcspi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcspi2_pins>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi new file mode 100644 index 000000000000..c01ef769761f --- /dev/null +++ b/arch/arm/boot/dts/dra7.dtsi @@ -0,0 +1,575 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * Based on "omap4.dtsi" + */ + +#include +#include + +#include "skeleton.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "ti,dra7xx"; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + gic: interrupt-controller@48211000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48211000 0x1000>, + <0x48212000 0x1000>, + <0x48214000 0x2000>, + <0x48216000 0x2000>; + interrupts = ; + }; + + /* + * The soc node represents the soc top level view. It is uses for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap5-mpu"; + ti,hwmods = "mpu"; + }; + }; + + /* + * XXX: Use a flat representation of the SOC interconnect. + * The real OMAP interconnect network is quite complex. + * Since that will not bring real advantage to represent that in DT for + * the moment, just use a fake OCP bus entry to represent the whole bus + * hierarchy. + */ + ocp { + compatible = "ti,omap4-l3-noc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main_1", "l3_main_2"; + reg = <0x44000000 0x2000>, + <0x44800000 0x3000>; + interrupts = , + ; + + counter32k: counter@4ae04000 { + compatible = "ti,omap-counter32k"; + reg = <0x4ae04000 0x40>; + ti,hwmods = "counter_32k"; + }; + + dra7_pmx_core: pinmux@4a003400 { + compatible = "pinctrl-single"; + reg = <0x4a003400 0x0464>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x3fffffff>; + }; + + sdma: dma-controller@4a056000 { + compatible = "ti,omap4430-sdma"; + reg = <0x4a056000 0x1000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + #dma-channels = <32>; + #dma-requests = <127>; + }; + + gpio1: gpio@4ae10000 { + compatible = "ti,omap4-gpio"; + reg = <0x4ae10000 0x200>; + interrupts = ; + ti,hwmods = "gpio1"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@48055000 { + compatible = "ti,omap4-gpio"; + reg = <0x48055000 0x200>; + interrupts = ; + ti,hwmods = "gpio2"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@48057000 { + compatible = "ti,omap4-gpio"; + reg = <0x48057000 0x200>; + interrupts = ; + ti,hwmods = "gpio3"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio4: gpio@48059000 { + compatible = "ti,omap4-gpio"; + reg = <0x48059000 0x200>; + interrupts = ; + ti,hwmods = "gpio4"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio5: gpio@4805b000 { + compatible = "ti,omap4-gpio"; + reg = <0x4805b000 0x200>; + interrupts = ; + ti,hwmods = "gpio5"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio6: gpio@4805d000 { + compatible = "ti,omap4-gpio"; + reg = <0x4805d000 0x200>; + interrupts = ; + ti,hwmods = "gpio6"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio7: gpio@48051000 { + compatible = "ti,omap4-gpio"; + reg = <0x48051000 0x200>; + interrupts = ; + ti,hwmods = "gpio7"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio8: gpio@48053000 { + compatible = "ti,omap4-gpio"; + reg = <0x48053000 0x200>; + interrupts = ; + ti,hwmods = "gpio8"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart1: serial@4806a000 { + compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = ; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart2: serial@4806c000 { + compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = ; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart3: serial@48020000 { + compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = ; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart4: serial@4806e000 { + compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = ; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart5: serial@48066000 { + compatible = "ti,omap4-uart"; + reg = <0x48066000 0x100>; + interrupts = ; + ti,hwmods = "uart5"; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart6: serial@48068000 { + compatible = "ti,omap4-uart"; + reg = <0x48068000 0x100>; + interrupts = ; + ti,hwmods = "uart6"; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart7: serial@48420000 { + compatible = "ti,omap4-uart"; + reg = <0x48420000 0x100>; + ti,hwmods = "uart7"; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart8: serial@48422000 { + compatible = "ti,omap4-uart"; + reg = <0x48422000 0x100>; + ti,hwmods = "uart8"; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart9: serial@48424000 { + compatible = "ti,omap4-uart"; + reg = <0x48424000 0x100>; + ti,hwmods = "uart9"; + clock-frequency = <48000000>; + status = "disabled"; + }; + + uart10: serial@4ae2b000 { + compatible = "ti,omap4-uart"; + reg = <0x4ae2b000 0x100>; + ti,hwmods = "uart10"; + clock-frequency = <48000000>; + status = "disabled"; + }; + + timer1: timer@4ae18000 { + compatible = "ti,omap5430-timer"; + reg = <0x4ae18000 0x80>; + interrupts = ; + ti,hwmods = "timer1"; + ti,timer-alwon; + }; + + timer2: timer@48032000 { + compatible = "ti,omap5430-timer"; + reg = <0x48032000 0x80>; + interrupts = ; + ti,hwmods = "timer2"; + }; + + timer3: timer@48034000 { + compatible = "ti,omap5430-timer"; + reg = <0x48034000 0x80>; + interrupts = ; + ti,hwmods = "timer3"; + }; + + timer4: timer@48036000 { + compatible = "ti,omap5430-timer"; + reg = <0x48036000 0x80>; + interrupts = ; + ti,hwmods = "timer4"; + }; + + timer5: timer@48820000 { + compatible = "ti,omap5430-timer"; + reg = <0x48820000 0x80>; + interrupts = ; + ti,hwmods = "timer5"; + ti,timer-dsp; + }; + + timer6: timer@48822000 { + compatible = "ti,omap5430-timer"; + reg = <0x48822000 0x80>; + interrupts = ; + ti,hwmods = "timer6"; + ti,timer-dsp; + ti,timer-pwm; + }; + + timer7: timer@48824000 { + compatible = "ti,omap5430-timer"; + reg = <0x48824000 0x80>; + interrupts = ; + ti,hwmods = "timer7"; + ti,timer-dsp; + }; + + timer8: timer@48826000 { + compatible = "ti,omap5430-timer"; + reg = <0x48826000 0x80>; + interrupts = ; + ti,hwmods = "timer8"; + ti,timer-dsp; + ti,timer-pwm; + }; + + timer9: timer@4803e000 { + compatible = "ti,omap5430-timer"; + reg = <0x4803e000 0x80>; + interrupts = ; + ti,hwmods = "timer9"; + }; + + timer10: timer@48086000 { + compatible = "ti,omap5430-timer"; + reg = <0x48086000 0x80>; + interrupts = ; + ti,hwmods = "timer10"; + }; + + timer11: timer@48088000 { + compatible = "ti,omap5430-timer"; + reg = <0x48088000 0x80>; + interrupts = ; + ti,hwmods = "timer11"; + ti,timer-pwm; + }; + + timer13: timer@48828000 { + compatible = "ti,omap5430-timer"; + reg = <0x48828000 0x80>; + ti,hwmods = "timer13"; + status = "disabled"; + }; + + timer14: timer@4882a000 { + compatible = "ti,omap5430-timer"; + reg = <0x4882a000 0x80>; + ti,hwmods = "timer14"; + status = "disabled"; + }; + + timer15: timer@4882c000 { + compatible = "ti,omap5430-timer"; + reg = <0x4882c000 0x80>; + ti,hwmods = "timer15"; + status = "disabled"; + }; + + timer16: timer@4882e000 { + compatible = "ti,omap5430-timer"; + reg = <0x4882e000 0x80>; + ti,hwmods = "timer16"; + status = "disabled"; + }; + + wdt2: wdt@4ae14000 { + compatible = "ti,omap4-wdt"; + reg = <0x4ae14000 0x80>; + interrupts = ; + ti,hwmods = "wd_timer2"; + }; + + i2c1: i2c@48070000 { + compatible = "ti,omap4-i2c"; + reg = <0x48070000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + status = "disabled"; + }; + + i2c2: i2c@48072000 { + compatible = "ti,omap4-i2c"; + reg = <0x48072000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + status = "disabled"; + }; + + i2c3: i2c@48060000 { + compatible = "ti,omap4-i2c"; + reg = <0x48060000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + status = "disabled"; + }; + + i2c4: i2c@4807a000 { + compatible = "ti,omap4-i2c"; + reg = <0x4807a000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c4"; + status = "disabled"; + }; + + i2c5: i2c@4807c000 { + compatible = "ti,omap4-i2c"; + reg = <0x4807c000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c5"; + status = "disabled"; + }; + + mmc1: mmc@4809c000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x4809c000 0x400>; + interrupts = ; + ti,hwmods = "mmc1"; + ti,dual-volt; + ti,needs-special-reset; + dmas = <&sdma 61>, <&sdma 62>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mmc2: mmc@480b4000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x480b4000 0x400>; + interrupts = ; + ti,hwmods = "mmc2"; + ti,needs-special-reset; + dmas = <&sdma 47>, <&sdma 48>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mmc3: mmc@480ad000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x480ad000 0x400>; + interrupts = ; + ti,hwmods = "mmc3"; + ti,needs-special-reset; + dmas = <&sdma 77>, <&sdma 78>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mmc4: mmc@480d1000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x480d1000 0x400>; + interrupts = ; + ti,hwmods = "mmc4"; + ti,needs-special-reset; + dmas = <&sdma 57>, <&sdma 58>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mcspi1: spi@48098000 { + compatible = "ti,omap4-mcspi"; + reg = <0x48098000 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "mcspi1"; + ti,spi-num-cs = <4>; + dmas = <&sdma 35>, + <&sdma 36>, + <&sdma 37>, + <&sdma 38>, + <&sdma 39>, + <&sdma 40>, + <&sdma 41>, + <&sdma 42>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + status = "disabled"; + }; + + mcspi2: spi@4809a000 { + compatible = "ti,omap4-mcspi"; + reg = <0x4809a000 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "mcspi2"; + ti,spi-num-cs = <2>; + dmas = <&sdma 43>, + <&sdma 44>, + <&sdma 45>, + <&sdma 46>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + status = "disabled"; + }; + + mcspi3: spi@480b8000 { + compatible = "ti,omap4-mcspi"; + reg = <0x480b8000 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "mcspi3"; + ti,spi-num-cs = <2>; + dmas = <&sdma 15>, <&sdma 16>; + dma-names = "tx0", "rx0"; + status = "disabled"; + }; + + mcspi4: spi@480ba000 { + compatible = "ti,omap4-mcspi"; + reg = <0x480ba000 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "mcspi4"; + ti,spi-num-cs = <1>; + dmas = <&sdma 70>, <&sdma 71>; + dma-names = "tx0", "rx0"; + status = "disabled"; + }; + }; +}; diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h new file mode 100644 index 000000000000..002a2855c046 --- /dev/null +++ b/include/dt-bindings/pinctrl/dra.h @@ -0,0 +1,50 @@ +/* + * This header provides constants for DRA pinctrl bindings. + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Rajendra Nayak + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _DT_BINDINGS_PINCTRL_DRA_H +#define _DT_BINDINGS_PINCTRL_DRA_H + +/* DRA7 mux mode options for each pin. See TRM for options */ +#define MUX_MODE0 0x0 +#define MUX_MODE1 0x1 +#define MUX_MODE2 0x2 +#define MUX_MODE3 0x3 +#define MUX_MODE4 0x4 +#define MUX_MODE5 0x5 +#define MUX_MODE6 0x6 +#define MUX_MODE7 0x7 +#define MUX_MODE8 0x8 +#define MUX_MODE9 0x9 +#define MUX_MODE10 0xa +#define MUX_MODE11 0xb +#define MUX_MODE12 0xc +#define MUX_MODE13 0xd +#define MUX_MODE14 0xe +#define MUX_MODE15 0xf + +#define PULL_ENA (1 << 16) +#define PULL_UP (1 << 17) +#define INPUT_EN (1 << 18) +#define SLEWCONTROL (1 << 19) +#define WAKEUP_EN (1 << 24) +#define WAKEUP_EVENT (1 << 25) + +/* Active pin states */ +#define PIN_OUTPUT 0 +#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) +#define PIN_INPUT INPUT_EN +#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) +#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) + +#endif + -- cgit v1.2.3 From 738c74090e97854278827637297556e6ae0a7fab Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Fri, 2 Aug 2013 19:16:13 +0530 Subject: ARM: dts: AM4372: cpu(s) node per latest binding Update AM4372 cpu node to the latest cpus/cpu bindings for ARM. Signed-off-by: Afzal Mohammed Acked-by: Mark Rutland Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am4372.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index ddc1df77ac52..4635e7f3d129 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -22,8 +22,12 @@ }; cpus { + #address-cells = <1>; + #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; }; }; -- cgit v1.2.3 From 73456012734b80442b33916406cfd13bf1b73acb Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Fri, 2 Aug 2013 19:16:35 +0530 Subject: ARM: dts: AM4372: add few nodes Populate uarts, timers, rtc, wdt, gpio, i2c, spi, cpsw & pwm nodes. Reason for adding these nodes early - hwmod code required address space of peripherals corresponding to these nodes (as address space details are removed from hwmod database). uart0, timers - 1 & 2 and synctimer were already present, so here the remaining uarts & timers are added. All properties as per the existing binding has been added for uart, timer, rtc, wdt & gpio. Even though that was not the current scope of work, felt adding those would reduce or require no effort later to get these peripherals working. For i2c, spi, cpsw & pwm - only the properties that were sure to be correct has been added (main intention is to make hwmod happy and avoid any later modification to here added properties). While at it add "ti,hwmod" property to already existing nodes. Signed-off-by: Afzal Mohammed Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am4372.dtsi | 343 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 343 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 4635e7f3d129..0fe393ab8920 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -49,6 +49,47 @@ compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x44e09000 0x2000>; interrupts = ; + ti,hwmods = "uart1"; + }; + + uart1: serial@48022000 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x48022000 0x2000>; + interrupts = ; + ti,hwmods = "uart2"; + status = "disabled"; + }; + + uart2: serial@48024000 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x48024000 0x2000>; + interrupts = ; + ti,hwmods = "uart3"; + status = "disabled"; + }; + + uart3: serial@481a6000 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x481a6000 0x2000>; + interrupts = ; + ti,hwmods = "uart4"; + status = "disabled"; + }; + + uart4: serial@481a8000 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x481a8000 0x2000>; + interrupts = ; + ti,hwmods = "uart5"; + status = "disabled"; + }; + + uart5: serial@481aa000 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x481aa000 0x2000>; + interrupts = ; + ti,hwmods = "uart6"; + status = "disabled"; }; timer1: timer@44e31000 { @@ -56,17 +97,319 @@ reg = <0x44e31000 0x400>; interrupts = ; ti,timer-alwon; + ti,hwmods = "timer1"; }; timer2: timer@48040000 { compatible = "ti,am4372-timer","ti,am335x-timer"; reg = <0x48040000 0x400>; interrupts = ; + ti,hwmods = "timer2"; + }; + + timer3: timer@48042000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x48042000 0x400>; + interrupts = ; + ti,hwmods = "timer3"; + status = "disabled"; + }; + + timer4: timer@48044000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x48044000 0x400>; + interrupts = ; + ti,timer-pwm; + ti,hwmods = "timer4"; + status = "disabled"; + }; + + timer5: timer@48046000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x48046000 0x400>; + interrupts = ; + ti,timer-pwm; + ti,hwmods = "timer5"; + status = "disabled"; + }; + + timer6: timer@48048000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x48048000 0x400>; + interrupts = ; + ti,timer-pwm; + ti,hwmods = "timer6"; + status = "disabled"; + }; + + timer7: timer@4804a000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x4804a000 0x400>; + interrupts = ; + ti,timer-pwm; + ti,hwmods = "timer7"; + status = "disabled"; + }; + + timer8: timer@481c1000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x481c1000 0x400>; + interrupts = ; + ti,hwmods = "timer8"; + status = "disabled"; + }; + + timer9: timer@4833d000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x4833d000 0x400>; + interrupts = ; + ti,hwmods = "timer9"; + status = "disabled"; + }; + + timer10: timer@4833f000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x4833f000 0x400>; + interrupts = ; + ti,hwmods = "timer10"; + status = "disabled"; + }; + + timer11: timer@48341000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x48341000 0x400>; + interrupts = ; + ti,hwmods = "timer11"; + status = "disabled"; }; counter32k: counter@44e86000 { compatible = "ti,am4372-counter32k","ti,omap-counter32k"; reg = <0x44e86000 0x40>; + ti,hwmods = "counter_32k"; + }; + + rtc@44e3e000 { + compatible = "ti,am4372-rtc","ti,da830-rtc"; + reg = <0x44e3e000 0x1000>; + interrupts = ; + ti,hwmods = "rtc"; + status = "disabled"; + }; + + wdt@44e35000 { + compatible = "ti,am4372-wdt","ti,omap3-wdt"; + reg = <0x44e35000 0x1000>; + interrupts = ; + ti,hwmods = "wd_timer2"; + status = "disabled"; + }; + + gpio0: gpio@44e07000 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x44e07000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ti,hwmods = "gpio1"; + status = "disabled"; + }; + + gpio1: gpio@4804c000 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x4804c000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ti,hwmods = "gpio2"; + status = "disabled"; + }; + + gpio2: gpio@481ac000 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x481ac000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ti,hwmods = "gpio3"; + status = "disabled"; + }; + + gpio3: gpio@481ae000 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x481ae000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ti,hwmods = "gpio4"; + status = "disabled"; + }; + + gpio4: gpio@48320000 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x48320000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ti,hwmods = "gpio5"; + status = "disabled"; + }; + + gpio5: gpio@48322000 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x48322000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ti,hwmods = "gpio6"; + status = "disabled"; + }; + + i2c0: i2c@44e0b000 { + compatible = "ti,am4372-i2c","ti,omap4-i2c"; + reg = <0x44e0b000 0x1000>; + interrupts = ; + ti,hwmods = "i2c1"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4802a000 { + compatible = "ti,am4372-i2c","ti,omap4-i2c"; + reg = <0x4802a000 0x1000>; + interrupts = ; + ti,hwmods = "i2c2"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4819c000 { + compatible = "ti,am4372-i2c","ti,omap4-i2c"; + reg = <0x4819c000 0x1000>; + interrupts = ; + ti,hwmods = "i2c3"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@48030000 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x48030000 0x400>; + interrupts = ; + ti,hwmods = "spi0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@481a0000 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x481a0000 0x400>; + interrupts = ; + ti,hwmods = "spi1"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@481a2000 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x481a2000 0x400>; + interrupts = ; + ti,hwmods = "spi2"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@481a4000 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x481a4000 0x400>; + interrupts = ; + ti,hwmods = "spi3"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@48345000 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x48345000 0x400>; + interrupts = ; + ti,hwmods = "spi4"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mac: ethernet@4a100000 { + compatible = "ti,am4372-cpsw","ti,cpsw"; + reg = <0x4a100000 0x800 + 0x4a101200 0x100>; + interrupts = ; + ti,hwmods = "cpgmac0"; + status = "disabled"; + }; + + epwmss0: epwmss@48300000 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x48300000 0x10>; + ti,hwmods = "epwmss0"; + status = "disabled"; + }; + + epwmss1: epwmss@48302000 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x48302000 0x10>; + ti,hwmods = "epwmss1"; + status = "disabled"; + }; + + epwmss2: epwmss@48304000 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x48304000 0x10>; + ti,hwmods = "epwmss2"; + status = "disabled"; + }; + + epwmss3: epwmss@48306000 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x48306000 0x10>; + ti,hwmods = "epwmss3"; + status = "disabled"; + }; + + epwmss4: epwmss@48308000 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x48308000 0x10>; + ti,hwmods = "epwmss4"; + status = "disabled"; + }; + + epwmss5: epwmss@4830a000 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x4830a000 0x10>; + ti,hwmods = "epwmss5"; + status = "disabled"; }; }; }; -- cgit v1.2.3 From adfe1473bda5bfb8d344a94fb17c0a929fcbd852 Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Thu, 15 Aug 2013 22:43:05 +0200 Subject: ARM: dts: Add devicetree for gta04 board. This adds devicetree for gta04 (Openmoko next generation board) with necessary support for mmc, usb, leds and button. Signed-off-by: Marek Belisko Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/omap3-gta04.dts | 168 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 169 insertions(+) create mode 100644 arch/arm/boot/dts/omap3-gta04.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b057b0e12d7c..1be0c95391d7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -174,6 +174,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap3-evm.dtb \ omap3-n900.dtb \ omap3-tobi.dtb \ + omap3-gta04.dtb \ omap3-igep0020.dtb \ omap3-igep0030.dtb \ omap4-panda.dtb \ diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts new file mode 100644 index 000000000000..a84684a95891 --- /dev/null +++ b/arch/arm/boot/dts/omap3-gta04.dts @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2013 Marek Belisko + * + * Based on omap3-beagle-xm.dts + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap36xx.dtsi" + +/ { + model = "OMAP3 GTA04"; + compatible = "ti,omap3-gta04", "ti,omap3"; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + gpio-keys { + compatible = "gpio-keys"; + + aux-button { + label = "aux"; + linux,code = <169>; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + }; + }; +}; + +&omap3_pmx_core { + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c2 { + clock-frequency = <400000>; + + /* pressure sensor */ + bmp085@77 { + compatible = "bosch,bmp085"; + reg = <0x77>; + }; + + /* leds */ + tca6507@45 { + compatible = "ti,tca6507"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x45>; + + gta04_led0: red_aux@0 { + label = "gta04:red:aux"; + reg = <0x0>; + }; + + gta04_led1: green_aux@1 { + label = "gta04:green:aux"; + reg = <0x1>; + }; + + gta04_led3: red_power@3 { + label = "gta04:red:power"; + reg = <0x3>; + linux,default-trigger = "default-on"; + }; + + gta04_led4: green_power@4 { + label = "gta04:green:power"; + reg = <0x4>; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + mode = <3>; + power = <50>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + vmmc_aux-supply = <&vsim>; + bus-width = <4>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + -- cgit v1.2.3 From 36f496ac70cadaadc1b024a74c53013bb2461dd1 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Thu, 15 Aug 2013 13:18:28 +0300 Subject: ARM: dts: omap3-beagle: Make USB host pin naming consistent Use a common naming scheme "mode0name.modename flags" for the USB host pins to be consistent. Signed-off-by: Roger Quadros Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-beagle.dts | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index dfd83103657a..2e29e811dd42 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -101,18 +101,18 @@ hsusbb2_pins: pinmux_hsusbb2_pins { pinctrl-single,pins = < - 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */ - 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */ - 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */ - 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */ - 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */ - 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */ - 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */ - 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */ - 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */ - 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */ - 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */ - 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */ + 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ >; }; -- cgit v1.2.3 From e3a412c9eed08a246d9542645d102c194059cb2b Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Wed, 21 Aug 2013 20:01:32 +0530 Subject: ARM: dts: OMAP5: add palmas-usb node Without this node, there will be no palmas driver to notify dwc3 that a cable has been connected and, without that, dwc3 will never initialize. Signed-off-by: Felipe Balbi [kishon@ti.com: added dt properties for enabling vbus/id interrupts and fixed vbus-supply value after SMPS10 is modeled as 2 regulators] Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-uevm.dts | 12 ++++++++++++ arch/arm/boot/dts/omap5.dtsi | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 05b9b126f084..da25a14d919f 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -272,6 +272,13 @@ interrupt-controller; #interrupt-cells = <2>; + extcon_usb3: palmas_usb { + compatible = "ti,palmas-usb-vid"; + ti,enable-vbus-detection; + ti,enable-id-detection; + ti,wakeup; + }; + palmas_pmic { compatible = "ti,palmas-pmic"; interrupt-parent = <&palmas>; @@ -479,6 +486,11 @@ phys = <0 &hsusb2_phy &hsusb3_phy>; }; +&usb3 { + extcon = <&extcon_usb3>; + vbus-supply = <&smps10_out1_reg>; +}; + &mcspi1 { }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index ecc06a99fd4d..6192c458bea1 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -634,7 +634,7 @@ ti,type = <2>; }; - omap_dwc3@4a020000 { + usb3: omap_dwc3@4a020000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss"; reg = <0x4a020000 0x10000>; -- cgit v1.2.3 From ad03b1a768cab40799c07200dd6ec078d6bb49b9 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Tue, 8 Oct 2013 12:50:05 +0800 Subject: ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 132 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 arch/arm/boot/dts/tegra124.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi new file mode 100644 index 000000000000..905f14839947 --- /dev/null +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -0,0 +1,132 @@ +#include + +#include "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra124"; + interrupt-parent = <&gic>; + + gic: interrupt-controller@50041000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x50041000 0x1000>, + <0x50042000 0x1000>, + <0x50044000 0x2000>, + <0x50046000 0x2000>; + interrupts = ; + }; + + timer@60005000 { + compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; + reg = <0x60005000 0x400>; + interrupts = , + , + , + , + , + ; + }; + + /* + * There are two serial driver i.e. 8250 based simple serial + * driver and APB DMA based serial driver for higher baudrate + * and performace. To enable the 8250 based driver, the compatible + * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable + * the APB DMA based serial driver, the comptible is + * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". + */ + serial@70006000 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = ; + status = "disabled"; + }; + + serial@70006040 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = ; + status = "disabled"; + }; + + serial@70006200 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x40>; + reg-shift = <2>; + interrupts = ; + status = "disabled"; + }; + + serial@70006300 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x40>; + reg-shift = <2>; + interrupts = ; + status = "disabled"; + }; + + serial@70006400 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x40>; + reg-shift = <2>; + interrupts = ; + status = "disabled"; + }; + + rtc@7000e000 { + compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = ; + status = "disabled"; + }; + + pmc@7000e400 { + compatible = "nvidia,tegra124-pmc"; + reg = <0x7000e400 0x400>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; +}; -- cgit v1.2.3 From a1425d428f39e5b95663f3f8037f372e86f2676f Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Tue, 8 Oct 2013 12:50:06 +0800 Subject: ARM: tegra: add Venice2 board support Add support for the Tegra124 based Venice2 reference board. Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren --- arch/arm/boot/dts/Makefile | 3 ++- arch/arm/boot/dts/tegra124-venice2.dts | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/tegra124-venice2.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index cc0f1fb61753..817638b67070 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -246,7 +246,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ - tegra114-dalmore.dtb + tegra114-dalmore.dtb \ + tegra124-venice2.dtb dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ versatile-pb.dtb dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts new file mode 100644 index 000000000000..2bfc7abd26b2 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -0,0 +1,20 @@ +/dts-v1/; + +#include "tegra124.dtsi" + +/ { + model = "NVIDIA Tegra124 Venice2"; + compatible = "nvidia,venice2", "nvidia,tegra124"; + + memory { + reg = <0x80000000 0x80000000>; + }; + + serial@70006000 { + status = "okay"; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + }; +}; -- cgit v1.2.3 From 493a86365bebdae944a9f2bbf21e106a77c92928 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 8 Oct 2013 15:52:12 -0300 Subject: ARM: dts: imx51-babbage: Make DVI and WVGA panel functional Currently we get the following errors on imx51-babbage: /display@di0: could not find display-timings node /display@di0: no timings specified /display@di1: could not find display-timings node /display@di1: no timings specified imx-drm imx-drm: failed to allocate buffer with size 0 Provide timing values for IPU1, which is connected to a DVI bridge and to IPU2, which can be connected to the WVGA panel, so that both of them can be functional. While at it, disable the WVGA panel, so that DVI output becomes the default one. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index f13f33906dde..be1407cf5abd 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -27,6 +27,20 @@ interface-pix-fmt = "rgb24"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ipu_disp1_1>; + display-timings { + native-mode = <&timing0>; + timing0: dvi { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; }; display@di1 { @@ -35,6 +49,25 @@ interface-pix-fmt = "rgb565"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ipu_disp2_1>; + status = "disabled"; + display-timings { + native-mode = <&timing1>; + timing1: claawvga { + clock-frequency = <27000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <60>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; }; gpio-keys { -- cgit v1.2.3 From 080972aaff6f6634fe1a6195ecc25e4e0904348e Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Tue, 8 Oct 2013 19:41:19 +0200 Subject: ARM: Dove: Add the audio devices in DT This patch adds the nodes to instantiate the audio devices of the Dove boards. Signed-off-by: Jean-Francois Moine Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 499abadf86f0..1e60db1ae353 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -573,6 +573,24 @@ phy-handle = <ðphy>; }; }; + + audio0: audio-controller@b0000 { + compatible = "marvell,dove-audio"; + reg = <0xb0000 0x2210>; + interrupts = <19>, <20>; + clocks = <&gate_clk 12>; + clock-names = "internal"; + status = "disabled"; + }; + + audio1: audio-controller@b4000 { + compatible = "marvell,dove-audio"; + reg = <0xb4000 0x2210>; + interrupts = <21>, <22>; + clocks = <&gate_clk 13>; + clock-names = "internal"; + status = "disabled"; + }; }; }; }; -- cgit v1.2.3 From 34ea5342bd6da63f666215c4ef4b7b3948511c14 Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Tue, 8 Oct 2013 20:56:17 +0200 Subject: ARM: Dove: Add the audio device to the Cubox DT This patch activates the audio device of the Cubox. The audio flow (pin mpp_audio1) is output on both I2S and S/PDIF. The third si5351 clock (#2, pin mpp13) is used as the external clock. Signed-off-by: Jean-Francois Moine Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove-cubox.dts | 8 ++++++++ arch/arm/boot/dts/dove.dtsi | 10 ++++++++++ 2 files changed, 18 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 4af59b6dce0f..173d46304cd2 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -132,3 +132,11 @@ reg = <0>; }; }; + +&audio1 { + status = "okay"; + clocks = <&gate_clk 13>, <&si5351 2>; + clock-names = "internal", "extclk"; + pinctrl-0 = <&pmx_audio1_i2s1_spdifo &pmx_audio1_extclk>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 1e60db1ae353..113a8bc7bee7 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -297,6 +297,11 @@ marvell,function = "gpio"; }; + pmx_audio1_extclk: pmx-audio1-extclk { + marvell,pins = "mpp13"; + marvell,function = "audio1"; + }; + pmx_gpio_14: pmx-gpio-14 { marvell,pins = "mpp14"; marvell,function = "gpio"; @@ -372,6 +377,11 @@ marvell,function = "gpio"; }; + pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { + marvell,pins = "mpp_audio1"; + marvell,function = "i2s1/spdifo"; + }; + pmx_spi0: pmx-spi0 { marvell,pins = "mpp_spi0"; marvell,function = "spi0"; -- cgit v1.2.3 From 1deb122c724edfd799a4d7d0b88ff14c365c9e69 Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Tue, 8 Oct 2013 20:20:27 +0200 Subject: ARM: Dove: fix bad properties of the si5351 clkout2 used by Cubox audio As defined in the DT, clkout2 is not allowed to change the pll inside si5351. This patch extends the properties of clkout2 so that it works as the external clock of the audio device in the Cubox. Also, as the second si5351 clock is not used in the Cubox, its definition is removed. Signed-off-by: Jean-Francois Moine Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove-cubox.dts | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 173d46304cd2..8349a248ecea 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -99,18 +99,12 @@ silabs,pll-master; }; - clkout1 { - reg = <1>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <1>; - silabs,clock-source = <0>; - silabs,pll-master; - }; - clkout2 { reg = <2>; + silabs,drive-strength = <8>; silabs,multisynth-source = <1>; silabs,clock-source = <0>; + silabs,pll-master; }; }; }; -- cgit v1.2.3 From 071fb4cbe01cb418264143cf49612a8d23cfaf4e Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Mon, 7 Oct 2013 10:38:41 -0500 Subject: ARM: socfpga: dts: Move common nodes to cyclone5 dtsi The current socfpga_cyclone5.dts describes the Altera Cyclone5 SoC Development Kit. The Cyclone5 includes a SoCFPGA, which itself can be included in other SoC+FPGA combinations. Instead of having to describe all Cyclone5 common nodes in every board specific dts, move socfpga_cyclone5.dts to a dtsi and include this in a new dts for the Development Kit. [Dinh Nguyen] - Changed to 115200 for baudrate in dts bootargs Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/Makefile | 2 +- arch/arm/boot/dts/socfpga_cyclone5.dts | 85 ---------------------------- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 65 +++++++++++++++++++++ arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 40 +++++++++++++ 4 files changed, 106 insertions(+), 86 deletions(-) delete mode 100644 arch/arm/boot/dts/socfpga_cyclone5.dts create mode 100644 arch/arm/boot/dts/socfpga_cyclone5.dtsi create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_socdk.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e95af3f5433b..430ba19b2f87 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -211,7 +211,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a73a4-ape6evm-reference.dtb \ sh7372-mackerel.dtb dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb -dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ +dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_socdk.dtb \ socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ spear1340-evb.dtb diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts deleted file mode 100644 index 973999d2c697..000000000000 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/dts-v1/; -/include/ "socfpga.dtsi" - -/ { - model = "Altera SOCFPGA Cyclone V"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - - ethernet@ff702000 { - phy-mode = "rgmii"; - phy-addr = <0xffffffff>; /* probe for phy addr */ - status = "okay"; - }; - - timer0@ffc08000 { - clock-frequency = <100000000>; - }; - - timer1@ffc09000 { - clock-frequency = <100000000>; - }; - - timer2@ffd00000 { - clock-frequency = <25000000>; - }; - - timer3@ffd01000 { - clock-frequency = <25000000>; - }; - - serial0@ffc02000 { - clock-frequency = <100000000>; - }; - - serial1@ffc03000 { - clock-frequency = <100000000>; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd080c4>; - }; - }; -}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi new file mode 100644 index 000000000000..a8716f6dbe2e --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/dts-v1/; +/include/ "socfpga.dtsi" + +/ { + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + ethernet@ff702000 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + status = "okay"; + }; + + timer0@ffc08000 { + clock-frequency = <100000000>; + }; + + timer1@ffc09000 { + clock-frequency = <100000000>; + }; + + timer2@ffd00000 { + clock-frequency = <25000000>; + }; + + timer3@ffd01000 { + clock-frequency = <25000000>; + }; + + serial0@ffc02000 { + clock-frequency = <100000000>; + }; + + serial1@ffc03000 { + clock-frequency = <100000000>; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts new file mode 100644 index 000000000000..2ee52ab8cabb --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/include/ "socfpga_cyclone5.dtsi" + +/ { + model = "Altera SOCFPGA Cyclone V SoC Development Kit"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; +}; -- cgit v1.2.3 From 47ba5c815a341899035a35f7b58fbe1f1deee880 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Mon, 7 Oct 2013 10:41:32 -0500 Subject: ARM: socfpga: dts: Add support for terasic SoCkit This adds basic support for the terasic SoCkit board. The board includes an Altera Cyclone 5 SoC. [Dinh Nguyen] - Changed to 115200 for baudrate in dts bootargs Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 37 +++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_sockit.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 430ba19b2f87..9414342169b1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -212,6 +212,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ sh7372-mackerel.dtb dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_sockit.dtb \ socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ spear1340-evb.dtb diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts new file mode 100644 index 000000000000..50b99a2c12ae --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2013 Steffen Trumtrar + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/include/ "socfpga_cyclone5.dtsi" + +/ { + model = "Terasic SoCkit"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; +}; + +&gmac1 { + status = "okay"; +}; -- cgit v1.2.3 From 7857d560da4a8c9d14f64bb765f64d8150da5d3c Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Mon, 7 Oct 2013 10:44:07 -0500 Subject: ARM: socfpga: dts: cleanup indentation Some of the clock nodes and the rst-/sysmgr use wrong indentation. Fix it. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 290 ++++++++++++++++++++--------------------- 1 file changed, 145 insertions(+), 145 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index e7260ca9eaf1..0207a6af5fd2 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -243,197 +243,197 @@ }; }; - mpu_periph_clk: mpu_periph_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mpuclk>; - fixed-divider = <4>; + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mpuclk>; + fixed-divider = <4>; }; - mpu_l2_ram_clk: mpu_l2_ram_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mpuclk>; - fixed-divider = <2>; + mpu_l2_ram_clk: mpu_l2_ram_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mpuclk>; + fixed-divider = <2>; }; - l4_main_clk: l4_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - clk-gate = <0x60 0>; + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + clk-gate = <0x60 0>; }; - l3_main_clk: l3_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; + l3_main_clk: l3_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; }; - l3_mp_clk: l3_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - div-reg = <0x64 0 2>; - clk-gate = <0x60 1>; + l3_mp_clk: l3_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 0 2>; + clk-gate = <0x60 1>; }; - l3_sp_clk: l3_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - div-reg = <0x64 2 2>; - }; + l3_sp_clk: l3_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 2 2>; + }; - l4_mp_clk: l4_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>, <&per_base_clk>; - div-reg = <0x64 4 3>; - clk-gate = <0x60 2>; + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 4 3>; + clk-gate = <0x60 2>; }; - l4_sp_clk: l4_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>, <&per_base_clk>; - div-reg = <0x64 7 3>; - clk-gate = <0x60 3>; + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 7 3>; + clk-gate = <0x60 3>; }; - dbg_at_clk: dbg_at_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x68 0 2>; - clk-gate = <0x60 4>; + dbg_at_clk: dbg_at_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 0 2>; + clk-gate = <0x60 4>; }; - dbg_clk: dbg_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x68 2 2>; - clk-gate = <0x60 5>; + dbg_clk: dbg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 2 2>; + clk-gate = <0x60 5>; }; - dbg_trace_clk: dbg_trace_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x6C 0 3>; - clk-gate = <0x60 6>; + dbg_trace_clk: dbg_trace_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x6C 0 3>; + clk-gate = <0x60 6>; }; - dbg_timer_clk: dbg_timer_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - clk-gate = <0x60 7>; + dbg_timer_clk: dbg_timer_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + clk-gate = <0x60 7>; }; - cfg_clk: cfg_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_s2f_usr0_clk>; - clk-gate = <0x60 8>; + cfg_clk: cfg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_s2f_usr0_clk>; + clk-gate = <0x60 8>; }; - s2f_user0_clk: s2f_user0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_s2f_usr0_clk>; - clk-gate = <0x60 9>; + s2f_user0_clk: s2f_user0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_s2f_usr0_clk>; + clk-gate = <0x60 9>; }; - emac_0_clk: emac_0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&emac0_clk>; - clk-gate = <0xa0 0>; + emac_0_clk: emac_0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac0_clk>; + clk-gate = <0xa0 0>; }; - emac_1_clk: emac_1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&emac1_clk>; - clk-gate = <0xa0 1>; + emac_1_clk: emac_1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac1_clk>; + clk-gate = <0xa0 1>; }; - usb_mp_clk: usb_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 2>; - div-reg = <0xa4 0 3>; + usb_mp_clk: usb_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 2>; + div-reg = <0xa4 0 3>; }; - spi_m_clk: spi_m_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 3>; - div-reg = <0xa4 3 3>; + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 3>; + div-reg = <0xa4 3 3>; }; - can0_clk: can0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 4>; - div-reg = <0xa4 6 3>; + can0_clk: can0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 4>; + div-reg = <0xa4 6 3>; }; - can1_clk: can1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 5>; - div-reg = <0xa4 9 3>; + can1_clk: can1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 5>; + div-reg = <0xa4 9 3>; }; - gpio_db_clk: gpio_db_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 6>; - div-reg = <0xa8 0 24>; + gpio_db_clk: gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 6>; + div-reg = <0xa8 0 24>; }; - s2f_user1_clk: s2f_user1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&s2f_usr1_clk>; - clk-gate = <0xa0 7>; + s2f_user1_clk: s2f_user1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&s2f_usr1_clk>; + clk-gate = <0xa0 7>; }; - sdmmc_clk: sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 8>; + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 8>; }; - nand_x_clk: nand_x_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 9>; + nand_x_clk: nand_x_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 9>; }; - nand_clk: nand_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 10>; - fixed-divider = <4>; + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 10>; + fixed-divider = <4>; }; - qspi_clk: qspi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; - clk-gate = <0xa0 11>; + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; + clk-gate = <0xa0 11>; }; }; }; @@ -517,9 +517,9 @@ }; rstmgr@ffd05000 { - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - }; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x1000>; + }; sysmgr@ffd08000 { compatible = "altr,sys-mgr"; -- cgit v1.2.3 From 01ed80b07dadc8747468bd738c8cbfcaf0169866 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Mon, 7 Oct 2013 11:11:38 -0500 Subject: ARM: socfpga: dts: fix s2f_* clock name The s2f_* clocks are called h2f_* in the datasheets. Rename them accordingly in the socfpga.dtsi. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 0207a6af5fd2..6d09b8d42fdd 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -147,7 +147,7 @@ reg = <0x58>; }; - cfg_s2f_usr0_clk: cfg_s2f_usr0_clk { + cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; @@ -198,7 +198,7 @@ reg = <0x98>; }; - s2f_usr1_clk: s2f_usr1_clk { + h2f_usr1_clk: h2f_usr1_clk { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; @@ -235,7 +235,7 @@ reg = <0xD0>; }; - s2f_usr2_clk: s2f_usr2_clk { + h2f_usr2_clk: h2f_usr2_clk { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&sdram_pll>; @@ -335,14 +335,14 @@ cfg_clk: cfg_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_s2f_usr0_clk>; + clocks = <&cfg_h2f_usr0_clk>; clk-gate = <0x60 8>; }; - s2f_user0_clk: s2f_user0_clk { + h2f_user0_clk: h2f_user0_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_s2f_usr0_clk>; + clocks = <&cfg_h2f_usr0_clk>; clk-gate = <0x60 9>; }; @@ -400,10 +400,10 @@ div-reg = <0xa8 0 24>; }; - s2f_user1_clk: s2f_user1_clk { + h2f_user1_clk: h2f_user1_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&s2f_usr1_clk>; + clocks = <&h2f_usr1_clk>; clk-gate = <0xa0 7>; }; -- cgit v1.2.3 From 163a036468c2eb8f30658dff6c0de6c959f79b0d Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 25 Sep 2013 15:38:20 -0500 Subject: dts: socfpga: Add support for Altera's SOCFPGA Arria V board Add support for a new SOCFPGA board that has an Arria V FPGA along with dual ARM Cortex-A9 cores. Signed-off-by: Dinh Nguyen Cc: Pavel Machek Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: devicetree@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/socfpga_arria5.dtsi | 58 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/socfpga_arria5_socdk.dts | 40 +++++++++++++++++++++ 3 files changed, 100 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/socfpga_arria5.dtsi create mode 100644 arch/arm/boot/dts/socfpga_arria5_socdk.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9414342169b1..59c1616fe061 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -211,7 +211,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a73a4-ape6evm-reference.dtb \ sh7372-mackerel.dtb dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb -dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_socdk.dtb \ +dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ + socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi new file mode 100644 index 000000000000..a85b4043f888 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +/dts-v1/; +/include/ "socfpga.dtsi" + +/ { + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + serial0@ffc02000 { + clock-frequency = <100000000>; + }; + + serial1@ffc03000 { + clock-frequency = <100000000>; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; + + timer0@ffc08000 { + clock-frequency = <100000000>; + }; + + timer1@ffc09000 { + clock-frequency = <100000000>; + }; + + timer2@ffd00000 { + clock-frequency = <25000000>; + }; + + timer3@ffd01000 { + clock-frequency = <25000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts new file mode 100644 index 000000000000..5beffb2265f4 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/include/ "socfpga_arria5.dtsi" + +/ { + model = "Altera SOCFPGA Arria V SoC Development Kit"; + compatible = "altr,socfpga-arria5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; +}; -- cgit v1.2.3 From 30a69ef785e87c791aab0b4dae76709a7baa3e85 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 10 Oct 2013 15:45:13 -0700 Subject: ARM: OMAP: Move DT wake-up event handling over to use pinctrl-single-omap Now pinctrl-single-omap can handle the wake-up events for us now as long as the events are configured in the .dts files. Done in collaboration with Roger Quadros . Cc: Peter Ujfalusi Cc: Grygorii Strashko Cc: Prakash Manjunathappa Cc: Roger Quadros Cc: Haojian Zhuang Cc: Linus Walleij Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3.dtsi | 4 ++++ arch/arm/boot/dts/omap4.dtsi | 4 ++++ arch/arm/mach-omap2/mux.c | 8 ++++++-- arch/arm/mach-omap2/pdata-quirks.c | 18 ++++++++++++++++++ arch/arm/mach-omap2/prm3xxx.h | 8 +++++++- arch/arm/mach-omap2/prm44xx_54xx.h | 8 +++++++- arch/arm/mach-omap2/prm_common.c | 11 +++++++++++ 7 files changed, 57 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 7d95cda1fae4..695e2d34c9c6 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -107,6 +107,8 @@ reg = <0x48002030 0x05cc>; #address-cells = <1>; #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7f1f>; }; @@ -116,6 +118,8 @@ reg = <0x48002a00 0x5c>; #address-cells = <1>; #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7f1f>; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 22d9f2b593d4..0415d5ed6014 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -114,6 +114,8 @@ reg = <0x4a100040 0x0196>; #address-cells = <1>; #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; @@ -122,6 +124,8 @@ reg = <0x4a31e040 0x0038>; #address-cells = <1>; #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index f82cf878d6af..48094b58c88f 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -811,6 +811,12 @@ int __init omap_mux_late_init(void) } } + omap_mux_dbg_init(); + + /* see pinctrl-single-omap for the wake-up interrupt handling */ + if (of_have_populated_dt()) + return 0; + ret = request_irq(omap_prcm_event_to_irq("io"), omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND, "hwmod_io", omap_mux_late_init); @@ -818,8 +824,6 @@ int __init omap_mux_late_init(void) if (ret) pr_warning("mux: Failed to setup hwmod io irq %d\n", ret); - omap_mux_dbg_init(); - return 0; } diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 76abc5b63d6d..18afbde020f7 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -14,6 +14,8 @@ #include #include +#include + #include "common.h" #include "common-board-devices.h" #include "dss-common.h" @@ -105,7 +107,23 @@ static void __init omap5_uevm_legacy_init(void) } #endif +static struct pcs_pdata pcs_pdata; + +void omap_pcs_legacy_init(int irq, void (*rearm)(void)) +{ + pcs_pdata.irq = irq; + pcs_pdata.rearm = rearm; +} + struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { +#ifdef CONFIG_ARCH_OMAP3 + OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata), + OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata), +#endif +#ifdef CONFIG_ARCH_OMAP4 + OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata), + OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata), +#endif { /* sentinel */ }, }; diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h index 277f71794e61..f8eb83323b1a 100644 --- a/arch/arm/mach-omap2/prm3xxx.h +++ b/arch/arm/mach-omap2/prm3xxx.h @@ -144,7 +144,13 @@ extern u32 omap3_prm_vcvp_read(u8 offset); extern void omap3_prm_vcvp_write(u32 val, u8 offset); extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); -extern void omap3xxx_prm_reconfigure_io_chain(void); +#ifdef CONFIG_ARCH_OMAP3 +void omap3xxx_prm_reconfigure_io_chain(void); +#else +static inline void omap3xxx_prm_reconfigure_io_chain(void) +{ +} +#endif /* PRM interrupt-related functions */ extern void omap3xxx_prm_read_pending_irqs(unsigned long *events); diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h index 7cd22abb8f15..a085d9cc1f5d 100644 --- a/arch/arm/mach-omap2/prm44xx_54xx.h +++ b/arch/arm/mach-omap2/prm44xx_54xx.h @@ -42,7 +42,13 @@ extern u32 omap4_prm_vcvp_read(u8 offset); extern void omap4_prm_vcvp_write(u32 val, u8 offset); extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); -extern void omap44xx_prm_reconfigure_io_chain(void); +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) +void omap44xx_prm_reconfigure_io_chain(void); +#else +static inline void omap44xx_prm_reconfigure_io_chain(void) +{ +} +#endif /* PRM interrupt-related functions */ extern void omap44xx_prm_read_pending_irqs(unsigned long *events); diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 228b850e632f..a2e1174ad1b6 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -24,6 +24,7 @@ #include #include +#include "soc.h" #include "prm2xxx_3xxx.h" #include "prm2xxx.h" #include "prm3xxx.h" @@ -322,6 +323,16 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) prcm_irq_chips[i] = gc; } + if (of_have_populated_dt()) { + int irq = omap_prcm_event_to_irq("io"); + if (cpu_is_omap34xx()) + omap_pcs_legacy_init(irq, + omap3xxx_prm_reconfigure_io_chain); + else + omap_pcs_legacy_init(irq, + omap44xx_prm_reconfigure_io_chain); + } + return 0; err: -- cgit v1.2.3 From bd4e301bda41d525b2d40267f0bf89dadc2b2c4a Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 11 Oct 2013 17:57:05 +0800 Subject: ARM: tegra: enable Tegra RTC as default for Tegra124 This patch makes the Tegra RTC enabled as default for Tegra124 platform. Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 905f14839947..f8242488de53 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -81,7 +81,6 @@ compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = ; - status = "disabled"; }; pmc@7000e400 { -- cgit v1.2.3 From 6ec1d127eeeb7943106daf4ec69b612fff93df74 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 11 Oct 2013 17:58:39 +0800 Subject: ARM: tegra: enable LP1 suspend mode for Venice2 Enable LP1 suspend mode for Tegra124 Venice2 board. Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 2bfc7abd26b2..431d67a2b413 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -16,5 +16,12 @@ pmc@7000e400 { nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; }; }; -- cgit v1.2.3 From 505975d3802f8d3a3c0905f38056213d06997b36 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Tue, 10 Sep 2013 14:24:37 -0500 Subject: ARM: dts: AM33XX: Add EDMA support Adds AM33XX EDMA support to the am33xx.dtsi as documented in Documentation/devicetree/bindings/dma/ti-edma.txt [Joel Fernandes ] Drop DT entries that are non-hardware-description as discussed in [1] [1] https://patchwork.kernel.org/patch/2226761/ Signed-off-by: Matt Porter Signed-off-by: Joel A Fernandes Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index a7731ead0b91..7a53e07e5a7a 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -105,6 +105,18 @@ reg = <0x48200000 0x1000>; }; + edma: edma@49000000 { + compatible = "ti,edma3"; + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; + reg = <0x49000000 0x10000>, + <0x44e10f90 0x10>; + interrupts = <12 13 14>; + #dma-cells = <1>; + dma-channels = <64>; + ti,edma-regions = <4>; + ti,edma-slots = <256>; + }; + gpio0: gpio@44e07000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio1"; -- cgit v1.2.3 From f5e2f807b730fa7f0683e515fe7483a5ebff9095 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Tue, 10 Sep 2013 14:24:38 -0500 Subject: ARM: dts: AM33XX: Add SPI DMA support Adds DMA resources to the AM33XX SPI nodes. Signed-off-by: Matt Porter Signed-off-by: Joel A Fernandes Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 7a53e07e5a7a..9cd60bf5edb5 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -340,6 +340,11 @@ interrupts = <65>; ti,spi-num-cs = <2>; ti,hwmods = "spi0"; + dmas = <&edma 16 + &edma 17 + &edma 18 + &edma 19>; + dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -351,6 +356,11 @@ interrupts = <125>; ti,spi-num-cs = <2>; ti,hwmods = "spi1"; + dmas = <&edma 42 + &edma 43 + &edma 44 + &edma 45>; + dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; -- cgit v1.2.3 From 55b4452b4b7082ecf3cc2095bc21762a901a8ca2 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Tue, 10 Sep 2013 14:24:39 -0500 Subject: ARM: dts: AM33XX: Add MMC support and documentation Adds AM33XX MMC support for am335x-bone, am335x-evm and am335x-evmsk boards. Also added is the DMA binding definitions based on the generic DMA request binding. Additional changes made to DTS: * Interrupt, reg and compatible properties added * ti,needs-special-hs-handling added Signed-off-by: Matt Porter Acked-by: Tony Lindgren Signed-off-by: Joel Fernandes Signed-off-by: Benoit Cousson --- .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 26 ++++++++++++++- arch/arm/boot/dts/am335x-bone.dts | 11 +++++++ arch/arm/boot/dts/am335x-evm.dts | 7 ++++ arch/arm/boot/dts/am335x-evmsk.dts | 7 ++++ arch/arm/boot/dts/am33xx.dtsi | 38 ++++++++++++++++++++++ 5 files changed, 88 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt index ed271fc255b2..8c8908ab84ba 100644 --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt @@ -20,8 +20,29 @@ ti,dual-volt: boolean, supports dual voltage cards ti,non-removable: non-removable slot (like eMMC) ti,needs-special-reset: Requires a special softreset sequence ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed +dmas: List of DMA specifiers with the controller specific format +as described in the generic DMA client binding. A tx and rx +specifier is required. +dma-names: List of DMA request names. These strings correspond +1:1 with the DMA specifiers listed in dmas. The string naming is +to be "rx" and "tx" for RX and TX DMA requests, respectively. + +Examples: + +[hwmod populated DMA resources] + + mmc1: mmc@0x4809c000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x4809c000 0x400>; + ti,hwmods = "mmc1"; + ti,dual-volt; + bus-width = <4>; + vmmc-supply = <&vmmc>; /* phandle to regulator node */ + ti,non-removable; + }; + +[generic DMA request binding] -Example: mmc1: mmc@0x4809c000 { compatible = "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; @@ -30,4 +51,7 @@ Example: bus-width = <4>; vmmc-supply = <&vmmc>; /* phandle to regulator node */ ti,non-removable; + dmas = <&edma 24 + &edma 25>; + dma-names = "tx", "rx"; }; diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 7993c489982c..d5f43fe2bfe1 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -9,3 +9,14 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&ldo3_reg>; +}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index e8ec8756e498..bc4a69d80fd8 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -477,6 +477,8 @@ }; vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; regulator-always-on; }; }; @@ -517,3 +519,8 @@ ti,adc-channels = <4 5 6 7>; }; }; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; +}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 4f339fa91c57..55fd19487b8c 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -393,6 +393,8 @@ }; vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; regulator-always-on; }; }; @@ -419,3 +421,8 @@ phy_id = <&davinci_mdio>, <1>; phy-mode = "rgmii-txid"; }; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 9cd60bf5edb5..553adc6b535e 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -245,6 +245,44 @@ status = "disabled"; }; + mmc1: mmc@48060000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc1"; + ti,dual-volt; + ti,needs-special-reset; + ti,needs-special-hs-handling; + dmas = <&edma 24 + &edma 25>; + dma-names = "tx", "rx"; + interrupts = <64>; + interrupt-parent = <&intc>; + reg = <0x48060000 0x1000>; + status = "disabled"; + }; + + mmc2: mmc@481d8000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc2"; + ti,needs-special-reset; + dmas = <&edma 2 + &edma 3>; + dma-names = "tx", "rx"; + interrupts = <28>; + interrupt-parent = <&intc>; + reg = <0x481d8000 0x1000>; + status = "disabled"; + }; + + mmc3: mmc@47810000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc3"; + ti,needs-special-reset; + interrupts = <29>; + interrupt-parent = <&intc>; + reg = <0x47810000 0x1000>; + status = "disabled"; + }; + wdt2: wdt@44e35000 { compatible = "ti,omap3-wdt"; ti,hwmods = "wd_timer2"; -- cgit v1.2.3 From 3045ffffcf5f334216ccb80697ac1a2ee5db179e Mon Sep 17 00:00:00 2001 From: Alexander Holler Date: Thu, 12 Sep 2013 20:35:32 +0200 Subject: ARM: dts: am335x-bone: add CD for mmc1 This enables the use of MMC cards even when no card was inserted at boot. Signed-off-by: Alexander Holler Signed-off-by: Koen Kooi Tested-by: Kevin Hilman Reviewed-by: Nishanth Menon Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-bone-common.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/am335x-bone.dts | 1 - 2 files changed, 14 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 2f66deda9f5c..0d95d54b6ae9 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -107,6 +107,12 @@ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ + >; + }; }; ocp { @@ -260,3 +266,11 @@ pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; }; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + cd-inverted; +}; diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index d5f43fe2bfe1..0d6334875df8 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -17,6 +17,5 @@ }; &mmc1 { - status = "okay"; vmmc-supply = <&ldo3_reg>; }; -- cgit v1.2.3 From 1aac4a990373cd53f75691e0901b029e29eb8190 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Thu, 12 Sep 2013 20:35:33 +0200 Subject: ARM: dts: am335x-boneblack: add eMMC DT entry The pinmux is specified in am335x-bone-common.dtsi to be reused by the eMMC cape. Signed-off-by: Koen Kooi Tested-by: Kevin Hilman Reviewed-by: Nishanth Menon [bcousson@baylibre.com: Fix traling spaces and useless comments] Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-bone-common.dtsi | 22 ++++++++++++++++++++++ arch/arm/boot/dts/am335x-boneblack.dts | 13 +++++++++++++ 2 files changed, 35 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 0d95d54b6ae9..c560cb7d3175 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -113,6 +113,21 @@ 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ >; }; + + emmc_pins: pinmux_emmc_pins { + pinctrl-single,pins = < + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + 0x84 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_csn2.mmc1_cmd */ + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; }; ocp { @@ -242,6 +257,13 @@ regulator-always-on; }; }; + + vmmcsd_fixed: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &cpsw_emac0 { diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 197cadf72d2c..16b3bea61d46 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -15,3 +15,16 @@ regulator-max-microvolt = <1800000>; regulator-always-on; }; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; + ti,vcc-aux-disable-is-sleep; +}; -- cgit v1.2.3 From 757a90e66c4828ec60a13792c2774488a28ae98d Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Thu, 12 Sep 2013 20:35:34 +0200 Subject: ARM: dts: am335x-bone-common: switch mmc1 to 4-bit mode The micro-SD slot hooks up all four data pins so lets' use them. Signed-off-by: Koen Kooi Tested-by: Kevin Hilman Reviewed-by: Nishanth Menon Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-bone-common.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index c560cb7d3175..fbb11dd76f08 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -291,6 +291,7 @@ &mmc1 { status = "okay"; + bus-width = <0x4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; -- cgit v1.2.3 From ec8a75979f199fd6fdcf24f8d1c928a48c61483e Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Thu, 12 Sep 2013 20:35:35 +0200 Subject: ARM: dts: am335x-bone-common: add cpu0 and mmc1 triggers This matches the vendor 3.8.x configuration that is shipping with the boards. The LED layout is now: USR0: heartbeat USR1: mmc0 (micro-SD slot) USR2: cpu0 USR3: mmc1 (eMMC) The cpu0 triggers was put in between the mmc triggers to make is easier to see where the disk activity is. Signed-off-by: Koen Kooi Tested-by: Kevin Hilman Reviewed-by: Nishanth Menon Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-bone-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index fbb11dd76f08..56361ceb418b 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -204,12 +204,14 @@ led@4 { label = "beaglebone:green:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; default-state = "off"; }; led@5 { label = "beaglebone:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; default-state = "off"; }; }; -- cgit v1.2.3 From 82d75afcb718dc8fe9fcd71959bff7878df53076 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 20 Sep 2013 17:00:00 +0200 Subject: ARM: dts: AM33XX: use pinmux node defined in included file am33xx boards DTS include the am33xx.dtsi Device Tree source file that already define a pinmux device node for the AM33XX SoC Pin Multiplex. Redefining this for each board makes the Device Tree files harder to modify and maintain so let's just use what is already defined in the included .dtsi file. Signed-off-by: Javier Martinez Canillas Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-bone-common.dtsi | 218 ++++++++++++------------- arch/arm/boot/dts/am335x-evm.dts | 254 ++++++++++++++--------------- arch/arm/boot/dts/am335x-evmsk.dts | 258 +++++++++++++++--------------- 3 files changed, 365 insertions(+), 365 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 56361ceb418b..29799ac3423a 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -21,115 +21,6 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - am33xx_pinmux: pinmux@44e10800 { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ - >; - }; - - emmc_pins: pinmux_emmc_pins { - pinctrl-single,pins = < - 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - 0x84 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_csn2.mmc1_cmd */ - 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; - }; - ocp { uart0: serial@44e09000 { pinctrl-names = "default"; @@ -217,6 +108,115 @@ }; }; +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ + >; + }; + + emmc_pins: pinmux_emmc_pins { + pinctrl-single,pins = < + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + 0x84 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_csn2.mmc1_cmd */ + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; +}; + /include/ "tps65217.dtsi" &tps { diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index bc4a69d80fd8..1525cd6d4844 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -24,133 +24,6 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - am33xx_pinmux: pinmux@44e10800 { - pinctrl-names = "default"; - pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; - - matrix_keypad_s0: matrix_keypad_s0 { - pinctrl-single,pins = < - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ - 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ - 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ - >; - }; - - volume_keys_s0: volume_keys_s0 { - pinctrl-single,pins = < - 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ - 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ - 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - nandflash_pins_s0: nandflash_pins_s0 { - pinctrl-single,pins = < - 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; - - ecap0_pins: backlight_pins { - pinctrl-single,pins = < - 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - }; - ocp { uart0: serial@44e09000 { pinctrl-names = "default"; @@ -405,6 +278,133 @@ }; }; +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; + + matrix_keypad_s0: matrix_keypad_s0 { + pinctrl-single,pins = < + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ + >; + }; + + volume_keys_s0: volume_keys_s0 { + pinctrl-single,pins = < + 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ + 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ + 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + nandflash_pins_s0: nandflash_pins_s0 { + pinctrl-single,pins = < + 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; + + ecap0_pins: backlight_pins { + pinctrl-single,pins = < + 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; +}; + #include "tps65910.dtsi" &tps { diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 55fd19487b8c..f0066fe5d739 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -31,135 +31,6 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - am33xx_pinmux: pinmux@44e10800 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; - - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ - 0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ - 0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ - 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ - >; - }; - - gpio_keys_s0: gpio_keys_s0 { - pinctrl-single,pins = < - 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ - 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ - 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ - 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - ecap2_pins: backlight_pins { - pinctrl-single,pins = < - 0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - - /* Slave 2 */ - 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) - - /* Slave 2 reset value*/ - 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - }; - ocp { uart0: serial@44e09000 { pinctrl-names = "default"; @@ -321,6 +192,135 @@ }; }; +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; + + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ + 0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ + 0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ + 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ + >; + }; + + gpio_keys_s0: gpio_keys_s0 { + pinctrl-single,pins = < + 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ + 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + ecap2_pins: backlight_pins { + pinctrl-single,pins = < + 0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + + /* Slave 2 */ + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value*/ + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; +}; + #include "tps65910.dtsi" &tps { -- cgit v1.2.3 From e0efaafbb5ba9bffe44c0ae838e5fd81632868b7 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 20 Sep 2013 17:42:19 +0200 Subject: ARM: dts: AM33XX: don't redefine OCP bus and device nodes The On Chip Peripherals (OCP) device node is a simplified representation of the AM33XX SoC interconnect. An OCP dev node is already defined in the am33xx.dtsi Device Tree source file included by am33xx based boards so there is no need to redefine this on each board DT file. Also, the OCP and IP modules directly connected to it are SoC internal details that is better to keep outside of board files. Signed-off-by: Javier Martinez Canillas Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-bone-common.dtsi | 100 ++++---- arch/arm/boot/dts/am335x-evm.dts | 380 +++++++++++++++--------------- arch/arm/boot/dts/am335x-evmsk.dts | 148 ++++++------ 3 files changed, 311 insertions(+), 317 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 29799ac3423a..ff5c3cafbdff 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -21,57 +21,6 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - ocp { - uart0: serial@44e09000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; - }; - - musb: usb@47400000 { - status = "okay"; - - control@44e10000 { - status = "okay"; - }; - - usb-phy@47401300 { - status = "okay"; - }; - - usb-phy@47401b00 { - status = "okay"; - }; - - usb@47401000 { - status = "okay"; - }; - - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; - - dma-controller@07402000 { - status = "okay"; - }; - }; - - i2c0: i2c@44e0b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - }; - }; - leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_s0>; @@ -217,6 +166,55 @@ }; }; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&usb { + status = "okay"; + + control@44e10000 { + status = "okay"; + }; + + usb-phy@47401300 { + status = "okay"; + }; + + usb-phy@47401b00 { + status = "okay"; + }; + + usb@47401000 { + status = "okay"; + }; + + usb@47401800 { + status = "okay"; + dr_mode = "host"; + }; + + dma-controller@07402000 { + status = "okay"; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + +}; + /include/ "tps65217.dtsi" &tps { diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 1525cd6d4844..23b0a3e32f2e 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -24,197 +24,6 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - ocp { - uart0: serial@44e09000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; - }; - - i2c0: i2c@44e0b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; - }; - - musb: usb@47400000 { - status = "okay"; - - control@44e10000 { - status = "okay"; - }; - - usb-phy@47401300 { - status = "okay"; - }; - - usb-phy@47401b00 { - status = "okay"; - }; - - usb@47401000 { - status = "okay"; - }; - - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; - - dma-controller@07402000 { - status = "okay"; - }; - }; - - i2c1: i2c@4802a000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - - tsl2550: tsl2550@39 { - compatible = "taos,tsl2550"; - reg = <0x39>; - }; - - tmp275: tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - }; - - elm: elm@48080000 { - status = "okay"; - }; - - epwmss0: epwmss@48300000 { - status = "okay"; - - ecap0: ecap@48300100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; - }; - }; - - gpmc: gpmc@50000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins_s0>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ - nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - gpmc,device-nand = "true"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - elm_id = <&elm>; - - /* MTD partition table */ - partition@0 { - label = "SPL1"; - reg = <0x00000000 0x000020000>; - }; - - partition@1 { - label = "SPL2"; - reg = <0x00020000 0x00020000>; - }; - - partition@2 { - label = "SPL3"; - reg = <0x00040000 0x00020000>; - }; - - partition@3 { - label = "SPL4"; - reg = <0x00060000 0x00020000>; - }; - - partition@4 { - label = "U-boot"; - reg = <0x00080000 0x001e0000>; - }; - - partition@5 { - label = "environment"; - reg = <0x00260000 0x00020000>; - }; - - partition@6 { - label = "Kernel"; - reg = <0x00280000 0x00500000>; - }; - - partition@7 { - label = "File-System"; - reg = <0x00780000 0x0F880000>; - }; - }; - }; - }; - vbat: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "vbat"; @@ -405,6 +214,195 @@ }; }; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; +}; + +&usb { + status = "okay"; + + control@44e10000 { + status = "okay"; + }; + + usb-phy@47401300 { + status = "okay"; + }; + + usb-phy@47401b00 { + status = "okay"; + }; + + usb@47401000 { + status = "okay"; + }; + + usb@47401800 { + status = "okay"; + dr_mode = "host"; + }; + + dma-controller@07402000 { + status = "okay"; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <100000>; + + lis331dlh: lis331dlh@18 { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x18>; + Vdd-supply = <&lis3_reg>; + Vdd_IO-supply = <&lis3_reg>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <120>; + st,min-limit-y = <120>; + st,min-limit-z = <140>; + st,max-limit-x = <550>; + st,max-limit-y = <550>; + st,max-limit-z = <750>; + }; + + tsl2550: tsl2550@39 { + compatible = "taos,tsl2550"; + reg = <0x39>; + }; + + tmp275: tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; +}; + +&elm { + status = "okay"; +}; + +&epwmss0 { + status = "okay"; + + ecap0: ecap@48300100 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; + }; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins_s0>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + elm_id = <&elm>; + + /* MTD partition table */ + partition@0 { + label = "SPL1"; + reg = <0x00000000 0x000020000>; + }; + + partition@1 { + label = "SPL2"; + reg = <0x00020000 0x00020000>; + }; + + partition@2 { + label = "SPL3"; + reg = <0x00040000 0x00020000>; + }; + + partition@3 { + label = "SPL4"; + reg = <0x00060000 0x00020000>; + }; + + partition@4 { + label = "U-boot"; + reg = <0x00080000 0x001e0000>; + }; + + partition@5 { + label = "environment"; + reg = <0x00260000 0x00020000>; + }; + + partition@6 { + label = "Kernel"; + reg = <0x00280000 0x00500000>; + }; + + partition@7 { + label = "File-System"; + reg = <0x00780000 0x0F880000>; + }; + }; +}; + #include "tps65910.dtsi" &tps { diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index f0066fe5d739..bc93895a6eca 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -31,81 +31,6 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - ocp { - uart0: serial@44e09000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; - }; - - i2c0: i2c@44e0b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - }; - - musb: usb@47400000 { - status = "okay"; - - control@44e10000 { - status = "okay"; - }; - - usb-phy@47401300 { - status = "okay"; - }; - - usb@47401000 { - status = "okay"; - }; - }; - - epwmss2: epwmss@48304000 { - status = "okay"; - - ecap2: ecap@48304100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap2_pins>; - }; - }; - }; - vbat: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "vbat"; @@ -321,6 +246,79 @@ }; }; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; + + lis331dlh: lis331dlh@18 { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x18>; + Vdd-supply = <&lis3_reg>; + Vdd_IO-supply = <&lis3_reg>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <120>; + st,min-limit-y = <120>; + st,min-limit-z = <140>; + st,max-limit-x = <550>; + st,max-limit-y = <550>; + st,max-limit-z = <750>; + }; +}; + +&usb { + status = "okay"; + + control@44e10000 { + status = "okay"; + }; + + usb-phy@47401300 { + status = "okay"; + }; + + usb@47401000 { + status = "okay"; + }; +}; + +&epwmss2 { + status = "okay"; + + ecap2: ecap@48304100 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>; + }; +}; + #include "tps65910.dtsi" &tps { -- cgit v1.2.3 From 6283513b6ee9caa8e38f9c41fcf95f209d9aebfd Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sat, 21 Sep 2013 02:40:14 +0300 Subject: ARM: dts: omap3-devkit8000: fix a typo in GMPC node "gpmc,sync-clki-ps" is not defined/documented, it should be "gpmc,sync-clk-ps" instead. Signed-off-by: Aaro Koskinen Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-devkit8000.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index 7ef282795dd4..4665421bb7bc 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts @@ -125,7 +125,7 @@ nand-bus-width = <16>; gpmc,device-nand; - gpmc,sync-clki-ps = <0>; + gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; -- cgit v1.2.3 From c56a831ca47e16f54467abc14eb597da87a8614c Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 26 Aug 2013 11:06:51 +0530 Subject: ARM: dts: DRA7: Add TPS659038 PMIC nodes Add DT nodes for TPS659038 PMIC on DRA7 boards. It is based on top of: http://comments.gmane.org/gmane.linux.ports.arm.omap/102459. Documentation: - Documentation/devicetree/bindings/mfd/palmas.txt - Documentation/devicetree/bindings/regulator/palmas-pmic.txt Boot Tested on DRA7 d1 Board. Signed-off-by: Keerthy Acked-by: Nishanth Menon [bcousson@baylibre.com: Fix indentation and changelog] Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/dra7-evm.dts | 112 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index ca5dab2214d5..fbbe40625508 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -93,6 +93,118 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + regulators { + smps123_reg: smps123 { + /* VDD_MPU */ + regulator-name = "smps123"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_GPU - over VDD_SMPS6 */ + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <12500000>; + regulator-boot-on; + }; + + smps7_reg: smps7 { + /* CORE_VDD */ + regulator-name = "smps7"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1030000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8_reg: smps8 { + /* VDD_IVAHD */ + regulator-name = "smps8"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + }; + + smps9_reg: smps9 { + /* VDDS1V8 */ + regulator-name = "smps9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> SDIO */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + ldo2_reg: ldo2 { + /* VDD_RTCIO */ + /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + }; }; &i2c2 { -- cgit v1.2.3 From 8170056d3cc99ce6521841cd30c1d50847958f9f Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Wed, 2 Oct 2013 12:58:33 -0500 Subject: ARM: dts: AM33XX: add ethernet alias's for am33xx Set the alias for ethernet0 and ethernet1 so that uBoot can set the MAC address appropriately. Currently u-boot cannot find the alias and there for does not set the MAC address. Signed-off-by: Dan Murphy Tested-by: Mugunthan V N Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 553adc6b535e..8aabaa0eb264 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -30,6 +30,8 @@ usb1 = &usb1; phy0 = &usb0_phy; phy1 = &usb1_phy; + ethernet0 = &cpsw_emac0; + ethernet1 = &cpsw_emac1; }; cpus { -- cgit v1.2.3 From 633b940fc0226aa322d5e8f2464c43efe77aaf31 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 24 Sep 2013 11:53:51 +0300 Subject: ARM: dts: omap3-beagle: Use reset-gpios for hsusb2_reset We no longer need to model the RESET line as a regulator since the USB phy-nop driver accepts "reset-gpios" property. Signed-off-by: Roger Quadros Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-beagle.dts | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 2e29e811dd42..12378224e46f 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -44,17 +44,6 @@ }; }; - /* HS USB Port 2 RESET */ - hsusb2_reset: hsusb2_reset_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_reset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 19 0>; /* gpio_147 */ - startup-delay-us = <70000>; - enable-active-high; - }; - /* HS USB Port 2 Power */ hsusb2_power: hsusb2_power_reg { compatible = "regulator-fixed"; @@ -68,7 +57,7 @@ /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; - reset-supply = <&hsusb2_reset>; + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ vcc-supply = <&hsusb2_power>; }; -- cgit v1.2.3 From 4cbdc86d6386765345e0934db256e257c0ef853f Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 24 Sep 2013 11:53:52 +0300 Subject: ARM: dts: omap4-panda: Use reset-gpios for hsusb1_reset We no longer need to model the RESET line as a regulator since the USB phy-nop driver accepts "reset-gpios" property. Signed-off-by: Roger Quadros Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4-panda-common.dtsi | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 43b7661cfe24..3e6801cecd04 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -60,22 +60,6 @@ "AFMR", "Line In"; }; - /* - * Temp hack: Need to be replaced with the proper gpio-controlled - * reset driver as soon it will be merged. - * http://thread.gmane.org/gmane.linux.drivers.devicetree/36830 - */ - /* HS USB Port 1 RESET */ - hsusb1_reset: hsusb1_reset_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_reset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 30 0>; /* gpio_62 */ - startup-delay-us = <70000>; - enable-active-high; - }; - /* HS USB Port 1 Power */ hsusb1_power: hsusb1_power_reg { compatible = "regulator-fixed"; @@ -97,7 +81,7 @@ /* HS USB Host PHY on PORT 1 */ hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; - reset-supply = <&hsusb1_reset>; + reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ vcc-supply = <&hsusb1_power>; /** * FIXME: -- cgit v1.2.3 From 8ae9b5953c811ea733080194373e56d8a8ef559c Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 24 Sep 2013 11:53:53 +0300 Subject: ARM: dts: omap5-uevm: Use reset-gpios for hsusb2/3_reset We no longer need to model the RESET line as a regulator since the USB phy-nop driver accepts "reset-gpios" property. Signed-off-by: Roger Quadros Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-uevm.dts | 26 ++------------------------ 1 file changed, 2 insertions(+), 24 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index da25a14d919f..748f6bfbeef6 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -27,21 +27,10 @@ regulator-max-microvolt = <3000000>; }; - /* HS USB Port 2 RESET */ - hsusb2_reset: hsusb2_reset_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_reset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */ - startup-delay-us = <70000>; - enable-active-high; - }; - /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; - reset-supply = <&hsusb2_reset>; + reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ /** * FIXME * Put the right clock phandle here when available @@ -51,21 +40,10 @@ clock-frequency = <19200000>; }; - /* HS USB Port 3 RESET */ - hsusb3_reset: hsusb3_reset_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb3_reset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */ - startup-delay-us = <70000>; - enable-active-high; - }; - /* HS USB Host PHY on PORT 3 */ hsusb3_phy: hsusb3_phy { compatible = "usb-nop-xceiv"; - reset-supply = <&hsusb3_reset>; + reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ }; leds { -- cgit v1.2.3 From aaba94429ab3570b7abe4ef2254a75a3a305e358 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 24 Sep 2013 11:53:55 +0300 Subject: ARM: dts: omap3-beagle-xm: Add USB Host support Provide RESET GPIO and Power regulator for the USB PHY, the USB Host port mode and the PHY device for the controller. Also provide pin multiplexer information for USB host pins. We also relocate omap3_pmx_core pin definations so that they are close to omap3_pmx_wkup pin definations. Signed-off-by: Roger Quadros Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-beagle-xm.dts | 65 ++++++++++++++++++++++++++++++----- 1 file changed, 56 insertions(+), 9 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 0c514dc8460c..0f7cfc503bf9 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -69,6 +69,23 @@ }; }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 18 0>; /* GPIO LEDA */ + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ + vcc-supply = <&hsusb2_power>; + }; }; &omap3_pmx_wkup { @@ -79,6 +96,37 @@ }; }; +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb2_pins + >; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ + >; + }; + + hsusbb2_pins: pinmux_hsusbb2_pins { + pinctrl-single,pins = < + 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; +}; + &i2c1 { clock-frequency = <2600000>; @@ -148,15 +196,6 @@ power = <50>; }; -&omap3_pmx_core { - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ - >; - }; -}; - &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; @@ -166,3 +205,11 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio1_pins>; }; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; -- cgit v1.2.3 From 816602086b2559271b55af70f22c9fa103af2c20 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 24 Sep 2013 11:53:56 +0300 Subject: ARM: dts: omap3-beagle: Add USB OTG PHY details Add information about the USB OTG PHY. Without this the OTG port on beagle will not work. Signed-off-by: Roger Quadros Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-beagle.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 12378224e46f..7669c16259a5 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -169,3 +169,10 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio1_pins>; }; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + mode = <3>; + power = <50>; +}; -- cgit v1.2.3 From ea5b7c10d4dce969fe7cf30a087e30664ad7f6dc Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 30 Sep 2013 09:40:16 -0500 Subject: ARM: dts: am335x-boneblack: move fixed regulator to board level 3.3V fixed regulator does not belong to TPS node - as a result the fixed regulator is never probed and MMC is continually deferred due to lack of regulator. Move the fixed regulator to be at root of platform. Cc: Joel Fernandes Cc: Sekhar Nori Cc: Koen Kooi Signed-off-by: Nishanth Menon Tested-by: Felipe Balbi Tested-by: Balaji T K Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-bone-common.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index ff5c3cafbdff..b3e6fcf92a67 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -55,6 +55,13 @@ default-state = "off"; }; }; + + vmmcsd_fixed: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &am33xx_pinmux { @@ -257,13 +264,6 @@ regulator-always-on; }; }; - - vmmcsd_fixed: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; }; &cpsw_emac0 { -- cgit v1.2.3 From e415245c68754150429aa707075233d3069c8dd7 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Tue, 10 Sep 2013 16:55:48 +0200 Subject: ARM: dts: AM33XX: Add support for IGEP COM AQUILA The IGEP COM AQUILA is industrial processors SODIMM module with following highlights: o AM3352/AM3354/AM3358/AM3359 Texas Instruments processor o Cortex-A8 ARM CPU o 3.3 volts Inputs / Outputs use industrial o 256 MB DDR3 SDRAM / 128 Megabytes FLASH o MicroSD card reader on-board o Ethernet controller on-board o JTAG debug connector available o Designed for industrial range purposes Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-igep0033.dtsi | 265 +++++++++++++++++++++++++++++++++ 1 file changed, 265 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-igep0033.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi new file mode 100644 index 000000000000..06eba076bfcd --- /dev/null +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -0,0 +1,265 @@ +/* + * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x + * + * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + + compatible = "gpio-leds"; + + led@0 { + label = "com:green:user"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&am33xx_pinmux { + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + nandflash_pins: pinmux_nandflash_pins { + pinctrl-single,pins = < + 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + leds_pins: pinmux_leds_pins { + pinctrl-single,pins = < + 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + >; + }; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + elm_id = <&elm>; + + /* MTD partition table */ + partition@0 { + label = "SPL"; + reg = <0x00000000 0x000080000>; + }; + + partition@1 { + label = "U-boot"; + reg = <0x00080000 0x001e0000>; + }; + + partition@2 { + label = "U-Boot Env"; + reg = <0x00260000 0x00020000>; + }; + + partition@3 { + label = "Kernel"; + reg = <0x00280000 0x00500000>; + }; + + partition@4 { + label = "File System"; + reg = <0x00780000 0x007880000>; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-always-on; + }; + }; +}; + -- cgit v1.2.3 From 5cda1620f457459240176ab6abc9431a1ad6684a Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Tue, 10 Sep 2013 16:55:49 +0200 Subject: ARM: dts: AM33XX: Add support for IGEP AQUILA EXPANSION board. The IGEP AQUILA EXPANSION board is a development platform for the IGEP COM AQUILA AM335x boards. The board adds the following connectivity: o USB OTG o USB HOST o HDMI o Ethernet o Serial Debug (3.3V) o 2x46 pin headers o EEPROM Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am335x-base0033.dts | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-base0033.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1be0c95391d7..9df7d2c15e7d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -188,6 +188,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ am335x-evmsk.dtb \ am335x-bone.dtb \ am335x-boneblack.dtb \ + am335x-base0033.dtb \ am3517-evm.dtb \ am3517_mt_ventoux.dtb \ am43x-epos-evm.dtb \ diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/am335x-base0033.dts new file mode 100644 index 000000000000..b4f95c2bbf74 --- /dev/null +++ b/arch/arm/boot/dts/am335x-base0033.dts @@ -0,0 +1,16 @@ +/* + * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION + * + * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "am335x-igep0033.dtsi" + +/ { + model = "IGEP COM AM335x on AQUILA Expansion"; + compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; +}; -- cgit v1.2.3 From af905b2225fa8905f93cc5a6f24dd116e6e7ada1 Mon Sep 17 00:00:00 2001 From: Balaji T K Date: Fri, 27 Sep 2013 17:05:09 +0530 Subject: ARM: dts: am335x-bone-common: correct mux mode for cmd line Set pinmux_emmc_pins mux mode for cmd line to MODE2 in order to detect eMMC on BBB and BBW + eMMC cape. Signed-off-by: Balaji T K Tested-by: Felipe Balbi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-bone-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index b3e6fcf92a67..e3f27ec31718 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -160,7 +160,7 @@ emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - 0x84 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_csn2.mmc1_cmd */ + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ -- cgit v1.2.3 From 0d8d40fc66b3fc08b8cb0e5f241455a4f6465509 Mon Sep 17 00:00:00 2001 From: Balaji T K Date: Fri, 27 Sep 2013 17:05:10 +0530 Subject: ARM: dts: am335x-evm[sdk]: switch mmc1 to 4-bit mode Set bus-width to make SD card operate in 4 bit mode. Signed-off-by: Balaji T K Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evm.dts | 1 + arch/arm/boot/dts/am335x-evmsk.dts | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 23b0a3e32f2e..028ca096d18d 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -521,4 +521,5 @@ &mmc1 { status = "okay"; vmmc-supply = <&vmmc_reg>; + bus-width = <4>; }; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index bc93895a6eca..563a2b136e0e 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -423,4 +423,5 @@ &mmc1 { status = "okay"; vmmc-supply = <&vmmc_reg>; + bus-width = <4>; }; -- cgit v1.2.3 From dd6317dffc24568df0ce31e0ce4d64541b38d00b Mon Sep 17 00:00:00 2001 From: Joel Fernandes Date: Thu, 11 Jul 2013 18:20:05 -0500 Subject: ARM: dts: OMAP4: Add AES node OMAP4 has an AES module that uses the omap-aes crypto driver. Add DT entries for the same. Signed-off-by: Joel Fernandes Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 45708e1b7a74..16a44d60b30e 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -663,5 +663,14 @@ ram-bits = <12>; ti,has-mailbox; }; + + aes: aes@4b501000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes"; + reg = <0x4b501000 0xa0>; + interrupts = ; + dmas = <&sdma 111>, <&sdma 110>; + dma-names = "tx", "rx"; + }; }; }; -- cgit v1.2.3 From 806e943153c50a14f107d9a612af1fddc3ceb9da Mon Sep 17 00:00:00 2001 From: Joel Fernandes Date: Tue, 24 Sep 2013 15:23:33 -0500 Subject: ARM: dts: OMAP4: Add DES3DES node OMAP4 has an DES3DES module that uses the omap-des crypto driver. Add DT entries for the same. Signed-off-by: Joel Fernandes Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 16a44d60b30e..6be1f5678f1a 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -672,5 +672,14 @@ dmas = <&sdma 111>, <&sdma 110>; dma-names = "tx", "rx"; }; + + des: des@480a5000 { + compatible = "ti,omap4-des"; + ti,hwmods = "des"; + reg = <0x480a5000 0xa0>; + interrupts = ; + dmas = <&sdma 117>, <&sdma 116>; + dma-names = "tx", "rx"; + }; }; }; -- cgit v1.2.3 From f8302e1efa7972b0eb8beefb80d756ddf2f30631 Mon Sep 17 00:00:00 2001 From: "Mark A. Greer" Date: Fri, 23 Aug 2013 14:12:35 -0700 Subject: ARM: dts: AM33XX: Add SHAM data and documentation Add the generic AM33XX SHAM module's device tree data and enable it for the am335x-evm, am335x-evmsk, and am335x-bone platforms. Also add Documentation file describing the data for the SHAM module. Cc: Paul Walmsley Signed-off-by: Mark A. Greer Signed-off-by: Joel Fernandes [joelf@ti.com: Dropped interrupt-parent property, documentation fixups] Acked-by: Mark Rutland Signed-off-by: Benoit Cousson --- .../devicetree/bindings/crypto/omap-sham.txt | 28 ++++++++++++++++++++++ arch/arm/boot/dts/am335x-bone.dts | 4 ++++ arch/arm/boot/dts/am335x-evm.dts | 4 ++++ arch/arm/boot/dts/am335x-evmsk.dts | 4 ++++ arch/arm/boot/dts/am33xx.dtsi | 9 +++++++ 5 files changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/omap-sham.txt (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/crypto/omap-sham.txt b/Documentation/devicetree/bindings/crypto/omap-sham.txt new file mode 100644 index 000000000000..f839acd6f0ee --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/omap-sham.txt @@ -0,0 +1,28 @@ +OMAP SoC SHA crypto Module + +Required properties: + +- compatible : Should contain entries for this and backward compatible + SHAM versions: + - "ti,omap2-sham" for OMAP2 & OMAP3. + - "ti,omap4-sham" for OMAP4 and AM33XX. + Note that these two versions are incompatible. +- ti,hwmods: Name of the hwmod associated with the SHAM module +- reg : Offset and length of the register set for the module +- interrupts : the interrupt-specifier for the SHAM module. + +Optional properties: +- dmas: DMA specifiers for the rx dma. See the DMA client binding, + Documentation/devicetree/bindings/dma/dma.txt +- dma-names: DMA request name. Should be "rx" if a dma is present. + +Example: + /* AM335x */ + sham: sham@53100000 { + compatible = "ti,omap4-sham"; + ti,hwmods = "sham"; + reg = <0x53100000 0x200>; + interrupts = <109>; + dmas = <&edma 36>; + dma-names = "rx"; + }; diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 0d6334875df8..8a9802ee6380 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -19,3 +19,7 @@ &mmc1 { vmmc-supply = <&ldo3_reg>; }; + +&sham { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 028ca096d18d..09786efc25c1 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -523,3 +523,7 @@ vmmc-supply = <&vmmc_reg>; bus-width = <4>; }; + +&sham { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 563a2b136e0e..08d5cd9e6457 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -425,3 +425,7 @@ vmmc-supply = <&vmmc_reg>; bus-width = <4>; }; + +&sham { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 8aabaa0eb264..5f114a7f9484 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -712,5 +712,14 @@ #size-cells = <1>; status = "disabled"; }; + + sham: sham@53100000 { + compatible = "ti,omap4-sham"; + ti,hwmods = "sham"; + reg = <0x53100000 0x200>; + interrupts = <109>; + dmas = <&edma 36>; + dma-names = "rx"; + }; }; }; -- cgit v1.2.3 From 99919e5e1545d819023f44e5e97d2105af0ca613 Mon Sep 17 00:00:00 2001 From: "Mark A. Greer" Date: Fri, 23 Aug 2013 14:12:36 -0700 Subject: ARM: dts: AM33XX: Add AES data and documentation Add the generic AM33XX AES module's device tree data and enable it for the am335x-evm, am335x-evmsk, and am335x-bone platforms. Also add Documentation file describing the data for the AES module. Cc: Paul Walmsley Signed-off-by: Mark A. Greer Signed-off-by: Joel Fernandes [joelf@ti.com: Dropped interrupt-parent property, documentation fixups] Signed-off-by: Benoit Cousson --- .../devicetree/bindings/crypto/omap-aes.txt | 31 ++++++++++++++++++++++ arch/arm/boot/dts/am335x-bone.dts | 4 +++ arch/arm/boot/dts/am335x-evm.dts | 4 +++ arch/arm/boot/dts/am335x-evmsk.dts | 4 +++ arch/arm/boot/dts/am33xx.dtsi | 10 +++++++ 5 files changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/omap-aes.txt (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/crypto/omap-aes.txt b/Documentation/devicetree/bindings/crypto/omap-aes.txt new file mode 100644 index 000000000000..fd9717653cbb --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/omap-aes.txt @@ -0,0 +1,31 @@ +OMAP SoC AES crypto Module + +Required properties: + +- compatible : Should contain entries for this and backward compatible + AES versions: + - "ti,omap2-aes" for OMAP2. + - "ti,omap3-aes" for OMAP3. + - "ti,omap4-aes" for OMAP4 and AM33XX. + Note that the OMAP2 and 3 versions are compatible (OMAP3 supports + more algorithms) but they are incompatible with OMAP4. +- ti,hwmods: Name of the hwmod associated with the AES module +- reg : Offset and length of the register set for the module +- interrupts : the interrupt-specifier for the AES module. + +Optional properties: +- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, + Documentation/devicetree/bindings/dma/dma.txt +- dma-names: DMA request names should include "tx" and "rx" if present. + +Example: + /* AM335x */ + aes: aes@53500000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes"; + reg = <0x53500000 0xa0>; + interrupts = <102>; + dmas = <&edma 6>, + <&edma 5>; + dma-names = "tx", "rx"; + }; diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 8a9802ee6380..94ee427a6db1 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -23,3 +23,7 @@ &sham { status = "okay"; }; + +&aes { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 09786efc25c1..ff834add842d 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -527,3 +527,7 @@ &sham { status = "okay"; }; + +&aes { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 08d5cd9e6457..5f12b28dd593 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -429,3 +429,7 @@ &sham { status = "okay"; }; + +&aes { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 5f114a7f9484..e36aed69a363 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -721,5 +721,15 @@ dmas = <&edma 36>; dma-names = "rx"; }; + + aes: aes@53500000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes"; + reg = <0x53500000 0xa0>; + interrupts = <102>; + dmas = <&edma 6>, + <&edma 5>; + dma-names = "tx", "rx"; + }; }; }; -- cgit v1.2.3 From 7af8884a175b56851ece09e47c74948c3160c07c Mon Sep 17 00:00:00 2001 From: Joel Fernandes Date: Wed, 17 Jul 2013 19:07:52 -0500 Subject: ARM: dts: AM33XX: Fix AES interrupt number AES interrupts were previously not used, but after recent changes to omap-aes driver, its being used. Correct the interrupt number to have working PIO mode. Signed-off-by: Joel Fernandes Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index e36aed69a363..c87bf4b8acf2 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -726,7 +726,7 @@ compatible = "ti,omap4-aes"; ti,hwmods = "aes"; reg = <0x53500000 0xa0>; - interrupts = <102>; + interrupts = <103>; dmas = <&edma 6>, <&edma 5>; dma-names = "tx", "rx"; -- cgit v1.2.3 From 6e70a510b4fc7b3e275e29875bb076e1891663d7 Mon Sep 17 00:00:00 2001 From: Joel Fernandes Date: Tue, 24 Sep 2013 14:35:09 -0500 Subject: ARM: dts: AM437X: Add AES node AM437x SoC has AES module similar to the one on OMAP4. Add DT node for the same. Signed-off-by: Joel Fernandes Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am4372.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 0fe393ab8920..7e9ff75c28b2 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -411,5 +411,12 @@ ti,hwmods = "epwmss5"; status = "disabled"; }; + + aes: aes@53501000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes"; + reg = <0x53501000 0xa0>; + interrupts = ; + }; }; }; -- cgit v1.2.3 From 099f3a854832c5d30188783ad48ea9e302fba4f8 Mon Sep 17 00:00:00 2001 From: Joel Fernandes Date: Tue, 24 Sep 2013 14:37:33 -0500 Subject: ARM: dts: AM437X: Add DES node AM437x SoC has a DES3DES module similar to the one on OMAP4. Add DT node for the same. Signed-off-by: Joel Fernandes Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am4372.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 7e9ff75c28b2..a403172430bc 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -418,5 +418,12 @@ reg = <0x53501000 0xa0>; interrupts = ; }; + + des: des@53701000 { + compatible = "ti,omap4-des"; + ti,hwmods = "des"; + reg = <0x53701000 0xa0>; + interrupts = ; + }; }; }; -- cgit v1.2.3 From d6cfc1e266d34d5b1f8a26bb272d2d2c466d89b8 Mon Sep 17 00:00:00 2001 From: Benoit Parrot Date: Thu, 8 Aug 2013 18:28:14 -0500 Subject: ARM: dts: AM33XX: Add LCDC info into am335x-evm Add LCDC device node in DT for am33xx Add LCDC and Panel info in DT for am335x-evm Changes: - remove redundant/unnecessary SoC specific setting in the board dts - resolved conflicts on for_3.13/dts Signed-off-by: Benoit Parrot Signed-off-by: Joel Fernandes Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evm.dts | 71 ++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/am33xx.dtsi | 9 +++++ 2 files changed, 80 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index ff834add842d..eabacf9b8c31 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -85,6 +85,40 @@ brightness-levels = <0 51 53 56 62 75 101 152 255>; default-brightness-level = <8>; }; + + panel { + compatible = "ti,tilcdc,panel"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins_s0>; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + display-timings { + 800x480p62 { + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <39>; + hback-porch = <39>; + hsync-len = <47>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <2>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; }; &am33xx_pinmux { @@ -212,6 +246,39 @@ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; + + lcd_pins_s0: lcd_pins_s0 { + pinctrl-single,pins = < + 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ + 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */ + 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */ + 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */ + 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */ + 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */ + 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */ + 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */ + 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ + 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ + 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ + 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ + 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ + 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ + 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ + 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ + 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ + 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ + 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ + 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ + 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ + 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ + 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ + 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ + 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ + 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ + 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ + 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ + >; + }; }; &uart0 { @@ -308,6 +375,10 @@ }; }; +&lcdc { + status = "okay"; +}; + &elm { status = "okay"; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index c87bf4b8acf2..7db3c81d1563 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -684,6 +684,15 @@ status = "disabled"; }; + lcdc: lcdc@4830e000 { + compatible = "ti,am33xx-tilcdc"; + reg = <0x4830e000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <36>; + ti,hwmods = "lcdc"; + status = "disabled"; + }; + tscadc: tscadc@44e0d000 { compatible = "ti,am3359-tscadc"; reg = <0x44e0d000 0x1000>; -- cgit v1.2.3 From 559a08e89350e269a4bba93629f39da5dd8e4fef Mon Sep 17 00:00:00 2001 From: Darren Etheridge Date: Fri, 20 Sep 2013 15:01:42 -0500 Subject: ARM: dts: AM33XX beagle black: add pinmux and hdmi node to enable display Enable the hdmi output and the LCD Controller on BeagleBone Black. Also configure the correct pinmux for output of video data from the SoC to the HDMI encoder. Signed-off-by: Darren Etheridge Signed-off-by: Joel Fernandes Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-boneblack.dts | 48 ++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 16b3bea61d46..6b71ad95a5cf 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -28,3 +28,51 @@ status = "okay"; ti,vcc-aux-disable-is-sleep; }; + +&am33xx_pinmux { + nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { + pinctrl-single,pins = < + 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ + 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + >; + }; + nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { + pinctrl-single,pins = < + 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ + >; + }; +}; + +&lcdc { + status = "okay"; +}; + +/ { + hdmi { + compatible = "ti,tilcdc,slave"; + i2c = <&i2c0>; + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + status = "okay"; + }; +}; -- cgit v1.2.3 From aa496bde78b9e6d1124b69b9f49acf4ee7d6b282 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 7 Oct 2013 17:12:23 +0200 Subject: ARM: dts: omap3-igep: Add USB OTG support Commit ad871c10b ("ARM: dts: OMAP: Add usb_otg and glue data to O added USB OTG support for most OMAP boards but some OMAP3 boards such as IGEP boards were not updated. This patch adds an USB OTG device node to these board. Signed-off-by: Javier Martinez Canillas Tested-by: Enric Balletbo i Serra Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-igep.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index 0f92224dc4fc..ba1e58b7b7e3 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -143,3 +143,12 @@ &twl_gpio { ti,use-leds; }; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; -- cgit v1.2.3 From 339e834fe06a2367ab8dcc18e57e810997ac9750 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 7 Oct 2013 17:12:24 +0200 Subject: ARM: dts: omap3-igep0020: Add HS USB Host support Add device nodes for the HS USB Host port 1, USB PHY and its required regulator and also pin mux setup for HS USB1 pins. Signed-off-by: Javier Martinez Canillas Tested-by: Enric Balletbo i Serra Acked-by: Roger Quadros Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-igep0020.dts | 49 ++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index eedf0d8b42d5..35346f2473b6 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -55,6 +55,47 @@ regulator-name = "vdd33a"; regulator-always-on; }; + + /* HS USB Port 1 Power */ + hsusb1_power: hsusb1_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ + vcc-supply = <&hsusb1_power>; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb1_pins + >; + + hsusbb1_pins: pinmux_hsusbb1_pins { + pinctrl-single,pins = < + 0x5aa (PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ + 0x5a8 (PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ + 0x5bc (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ + 0x5be (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ + 0x5ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ + 0x5ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ + 0x5b0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ + 0x5b2 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ + 0x5b4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ + 0x5b6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ + 0x5b8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ + 0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ + >; + }; }; &leds_pins { @@ -166,3 +207,11 @@ smsc,save-mac-address; }; }; + +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; -- cgit v1.2.3 From 2892aef29f7a08240debbaae9706a29839fd8c03 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 7 Oct 2013 17:12:25 +0200 Subject: ARM: dts: omap3-igep0020: use standard constant for IRQ flags Commit 840ef8b7 ("ARM: dt: add header to define IRQ flags") added constants for IRQ edge/level triggered types so use it instead of a magic number to enhance the DT readability. Signed-off-by: Javier Martinez Canillas Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-igep0020.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index 35346f2473b6..750ce84fc195 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -199,7 +199,7 @@ gpmc,cycle2cycle-diffcsen; interrupt-parent = <&gpio6>; - interrupts = <16 8>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; vmmc-supply = <&vddvario>; vmmc_aux-supply = <&vdd33a>; reg-io-width = <4>; -- cgit v1.2.3 From 86583375aaf76fb2a03085100bbc3123c6ced559 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 19 Sep 2013 14:11:36 -0500 Subject: ARM: dts: omap5-uevm: mark TWL6037 as system-power-controller This allows the palmas pm_power_off to kick in on power off command and switch off the board. Signed-off-by: Nishanth Menon Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-uevm.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 748f6bfbeef6..d784b3a00410 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -249,6 +249,7 @@ reg = <0x48>; interrupt-controller; #interrupt-cells = <2>; + ti,system-power-controller; extcon_usb3: palmas_usb { compatible = "ti,palmas-usb-vid"; -- cgit v1.2.3 From bf1788df8f99e5bcd8e9e0bbdacaf193ca2cbb68 Mon Sep 17 00:00:00 2001 From: Balaji T K Date: Mon, 7 Oct 2013 21:55:03 +0530 Subject: ARM: dts: dra7-evm: Add mmc1 node for micro-sd support Add mmc1 dt node to dra7-evm board. Input for ldo1 regulator is controlled by gpio 5 of pcf8575 chip (0x21) on i2c1 bus. When dt support for gpio-pcf857x is available, input supply will be modelled as cascaded regulator. Signed-off-by: Balaji T K Acked-by: Sekhar Nori Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/dra7-evm.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index fbbe40625508..65cd15a92cb1 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -250,3 +250,9 @@ pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; + +&mmc1 { + status = "okay"; + vmmc-supply = <&ldo1_reg>; + bus-width = <4>; +}; -- cgit v1.2.3 From 6cf02dbb4b71f1c0c9acec89ae2df3b2318135f4 Mon Sep 17 00:00:00 2001 From: Balaji T K Date: Mon, 7 Oct 2013 21:55:04 +0530 Subject: ARM: dts: dra7-evm: Add mmc2 node for eMMC support Add mmc2 dt node to dra7-evm board and model eMMC vcc as fixed regulator. Signed-off-by: Balaji T K Acked-by: Sekhar Nori Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/dra7-evm.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 65cd15a92cb1..3abf5f41e5cc 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -17,6 +17,13 @@ device_type = "memory"; reg = <0x80000000 0x60000000>; /* 1536 MB */ }; + + mmc2_3v3: fixedregulator-mmc2 { + compatible = "regulator-fixed"; + regulator-name = "mmc2_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &dra7_pmx_core { @@ -256,3 +263,9 @@ vmmc-supply = <&ldo1_reg>; bus-width = <4>; }; + +&mmc2 { + status = "okay"; + vmmc-supply = <&mmc2_3v3>; + bus-width = <8>; +}; -- cgit v1.2.3 From 2f35c0c41f6b9a326574fcbcde3736309c51ffc3 Mon Sep 17 00:00:00 2001 From: Rogerio Pimentel Date: Fri, 11 Oct 2013 16:48:16 -0300 Subject: ARM: dts: imx6qdl-sabresd: Add backlight support for lvds This patch adds support for lvds backlight on boards i.MX6q-SabreSD and i.MX6dl-SabreSD Signed-off-by: Rogerio Pimentel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 2035d6698ec5..e75e11b36dff 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -80,6 +80,14 @@ mux-int-port = <2>; mux-ext-port = <3>; }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + status = "okay"; + }; }; &audmux { @@ -204,6 +212,12 @@ }; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_1>; + status = "okay"; +}; + &ssi2 { fsl,mode = "i2s-slave"; status = "okay"; -- cgit v1.2.3 From fa87dfd6d0b067bd962ab83754cf1991ee512c0c Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Wed, 9 Oct 2013 19:20:07 +0800 Subject: ARM: dts: imx6sl: add pinctrl uhs states for usdhc This is needed for SD3.0 cards working on UHS mode. Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-evk.dts | 12 +++++-- arch/arm/boot/dts/imx6sl.dtsi | 77 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 36ea01e308d3..c14195f6c5f9 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -89,8 +89,10 @@ }; &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1_1>; + pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>; bus-width = <8>; cd-gpios = <&gpio4 7 0>; wp-gpios = <&gpio4 6 0>; @@ -98,16 +100,20 @@ }; &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2_1>; + pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; cd-gpios = <&gpio5 0 0>; wp-gpios = <&gpio4 29 0>; status = "okay"; }; &usdhc3 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; cd-gpios = <&gpio3 22 0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index f295290d29fc..e4d6d1efb457 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -639,6 +639,38 @@ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 >; }; + + pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 + >; + }; + + }; usdhc2 { @@ -652,6 +684,29 @@ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 >; }; + + pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + }; usdhc3 { @@ -665,6 +720,28 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 >; }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; }; }; -- cgit v1.2.3 From ffcd77e27991dee0531903468d2b103c128aec3e Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 14 Oct 2013 13:38:30 +0800 Subject: ARM: at91: add ssc dma parameter for at91sam9n12 Add ssc dma parameter for at91sam9n12 Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9n12.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 9fb7ffd32af2..6224f9fe2f2b 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -437,6 +437,9 @@ compatible = "atmel,at91sam9g45-ssc"; reg = <0xf0010000 0x4000>; interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, + <&dma 0 AT91_DMA_CFG_PER_ID(22)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; -- cgit v1.2.3 From e6f79916606695b89bf3c7deee1307478b8d6b59 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 14 Oct 2013 13:38:31 +0800 Subject: ARM: at91: enable wm8904 on at91sam9n12ek board Enable wm8904 codec on at91sam9n12ek board, which is connect to i2c0 bus with 0x1a as address. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9n12ek.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 27a9352b9d7a..1ba8defae672 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -41,6 +41,11 @@ i2c0: i2c@f8010000 { status = "okay"; + wm8904: codec@1a { + compatible = "wm8904"; + reg = <0x1a>; + }; + qt1070: keyboard@1b { compatible = "qt1070"; reg = <0x1b>; -- cgit v1.2.3 From 476090661a03f1ee1dcab9a3b669bfeb57875d0c Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 14 Oct 2013 13:38:32 +0800 Subject: ARM: at91: enable ssc on at91sam9n12ek board Enable ssc on at91sam9n12ek board Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9n12ek.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 1ba8defae672..391c5322248e 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -38,6 +38,10 @@ status = "okay"; }; + ssc0: ssc@f0010000 { + status = "okay"; + }; + i2c0: i2c@f8010000 { status = "okay"; -- cgit v1.2.3 From 551a409ca6b6285367669883186f84ea3bc88ecf Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 14 Oct 2013 13:38:33 +0800 Subject: ARM: at91: add sound support on at91sam9n12ek board Add sound support on at91sam9n12ek board with wm8904 as codec. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9n12ek.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 391c5322248e..e9487f6f0166 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -91,6 +91,13 @@ ; }; }; + + sound { + pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { + atmel,pins = + ; + }; + }; }; spi0: spi@f0000000 { @@ -151,4 +158,22 @@ gpio-key,wakeup; }; }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; + + atmel,model = "wm8904 @ AT91SAM9N12"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + }; }; -- cgit v1.2.3 From 6b2978ac40e414f984904fd53f6599d9eaf56407 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 14 Oct 2013 11:31:42 -0700 Subject: ARM: dts: Shared file for omap GPMC connected smsc911x Looks like at least Igep, Zoom and EVM boards can use a common file for the GPMC connected smsc911x. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi | 52 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap3-igep0020.dts | 45 ++------------------------ 2 files changed, 54 insertions(+), 43 deletions(-) create mode 100644 arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi new file mode 100644 index 000000000000..9c18adf788f7 --- /dev/null +++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi @@ -0,0 +1,52 @@ +/* + * Common file for GPMC connected smsc911x on omaps + * + * Note that the board specifc DTS file needs to specify + * ranges, pinctrl, reg, interrupt parent and interrupts. + */ + +/ { + vddvario: regulator-vddvario { + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; + }; + + vdd33a: regulator-vdd33a { + compatible = "regulator-fixed"; + regulator-name = "vdd33a"; + regulator-always-on; + }; +}; + +&gpmc { + ethernet@gpmc { + compatible = "smsc,lan9221", "smsc,lan9115"; + bank-width = <2>; + gpmc,mux-add-data; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <186>; + gpmc,cs-wr-off-ns = <186>; + gpmc,adv-on-ns = <12>; + gpmc,adv-rd-off-ns = <48>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <54>; + gpmc,oe-off-ns = <168>; + gpmc,we-on-ns = <54>; + gpmc,we-off-ns = <168>; + gpmc,rd-cycle-ns = <186>; + gpmc,wr-cycle-ns = <186>; + gpmc,access-ns = <114>; + gpmc,page-burst-access-ns = <6>; + gpmc,bus-turnaround-ns = <12>; + gpmc,cycle2cycle-delay-ns = <18>; + gpmc,wr-data-mux-bus-ns = <90>; + gpmc,wr-access-ns = <186>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + vmmc-supply = <&vddvario>; + vmmc_aux-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + }; +}; diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index 750ce84fc195..d5cc79267250 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -10,6 +10,7 @@ */ #include "omap3-igep.dtsi" +#include "omap-gpmc-smsc911x.dtsi" / { model = "IGEPv2"; @@ -44,18 +45,6 @@ }; }; - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; - /* HS USB Port 1 Power */ hsusb1_power: hsusb1_power_reg { compatible = "regulator-fixed"; @@ -169,42 +158,12 @@ }; }; - ethernet@5,0 { + ethernet@gpmc { pinctrl-names = "default"; pinctrl-0 = <&smsc911x_pins>; - compatible = "smsc,lan9221", "smsc,lan9115"; reg = <5 0 0xff>; - bank-width = <2>; - - gpmc,mux-add-data; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <186>; - gpmc,cs-wr-off-ns = <186>; - gpmc,adv-on-ns = <12>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <114>; - gpmc,page-burst-access-ns = <6>; - gpmc,bus-turnaround-ns = <12>; - gpmc,cycle2cycle-delay-ns = <18>; - gpmc,wr-data-mux-bus-ns = <90>; - gpmc,wr-access-ns = <186>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - interrupt-parent = <&gpio6>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - vmmc-supply = <&vddvario>; - vmmc_aux-supply = <&vdd33a>; - reg-io-width = <4>; - - smsc,save-mac-address; }; }; -- cgit v1.2.3 From 465ce68b467e5e47d699564432dff8cb60204433 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 14 Oct 2013 11:31:42 -0700 Subject: ARM: dts: Add common support for omap3-evm Looks like the main difference between the TMDSEVM3530 and TMDSEVM3730 is just the omap processor: http://www.ti.com/tool/tmdsevm3530 http://www.ti.com/tool/tmdsevm3730 So let's add a common file for the EVMs, and fix the description for the omap3-evm.dst as that's clearly for the TMDSEVM3530 since it includes omap34xx.dtsi. It cannot support the TMDSEVM3730 properly, and we need a separate file for that in the following patch. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-evm-common.dtsi | 60 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap3-evm.dts | 58 ++----------------------------- 2 files changed, 62 insertions(+), 56 deletions(-) create mode 100644 arch/arm/boot/dts/omap3-evm-common.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi new file mode 100644 index 000000000000..75753bb28535 --- /dev/null +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -0,0 +1,60 @@ +/* + * Common support for omap3 EVM boards + */ + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + leds { + compatible = "gpio-leds"; + ledb { + label = "omap3evm::ledb"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ + linux,default-trigger = "default-on"; + }; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; + + /* + * TVP5146 Video decoder-in for analog input support. + */ + tvp5146@5c { + compatible = "ti,tvp5146m2"; + reg = <0x5c>; + }; +}; + +&twl_gpio { + ti,use-leds; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + mode = <3>; + power = <50>; +}; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index 7d4329d179c4..e10dcd0fa539 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -8,68 +8,14 @@ /dts-v1/; #include "omap34xx.dtsi" +#include "omap3-evm-common.dtsi" / { - model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)"; + model = "TI OMAP35XX EVM (TMDSEVM3530)"; compatible = "ti,omap3-evm", "ti,omap3"; - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; - - leds { - compatible = "gpio-leds"; - ledb { - label = "omap3evm::ledb"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ - linux,default-trigger = "default-on"; - }; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - /* - * TVP5146 Video decoder-in for analog input support. - */ - tvp5146@5c { - compatible = "ti,tvp5146m2"; - reg = <0x5c>; - }; -}; - -&twl_gpio { - ti,use-leds; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - mode = <3>; - power = <50>; }; -- cgit v1.2.3 From 5992234bc5f34f3069d0457090d87865ec31fe13 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 14 Oct 2013 11:31:43 -0700 Subject: ARM: dts: Add basic support for TMDSEVM3730 (Mistral AM/DM37x EVM) I've tested the serial, MMC, smsc911x, wl12xx, and off-idle support with the pinctrl patches, so it probably works better than the board-*.c files ever did. Also the board-omap3evm.c file is broken for the DSS, and has been for a while. Patches are welcome to fix it in this .dts file, let's just drop the board-*.c file for this. Note that off-idle currently requires doing request_irq() on the wake-up pin from pinctrl-single IRQ domain until we can handle that in some Linux generic way. [tony@atomide.com: updated for make dtbs build fix] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/omap3-evm-37xx.dts | 151 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap3-evm-common.dtsi | 34 +++++++ 3 files changed, 186 insertions(+) create mode 100644 arch/arm/boot/dts/omap3-evm-37xx.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9df7d2c15e7d..96d8f1f50430 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -172,6 +172,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap3-devkit8000.dtb \ omap3-beagle-xm.dtb \ omap3-evm.dtb \ + omap3-evm-37xx.dtb \ omap3-n900.dtb \ omap3-tobi.dtb \ omap3-gta04.dtb \ diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts new file mode 100644 index 000000000000..4df68ad3736a --- /dev/null +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap36xx.dtsi" +#include "omap3-evm-common.dtsi" + + +/ { + model = "TI OMAP37XX EVM (TMDSEVM3730)"; + compatible = "ti,omap3-evm-37xx", "ti,omap36xx"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + wl12xx_vmmc: wl12xx_vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + }; +}; + +&omap3_pmx_core { + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + 0x120 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ + 0x122 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ + 0x124 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ + 0x126 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ + >; + }; + + /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + 0x12e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x16e (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + wl12xx_gpio: pinmux_wl12xx_gpio { + pinctrl-single,pins = < + 0x150 (PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ + 0x14e (PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ + >; + }; + + smsc911x_pins: pinmux_smsc911x_pins { + pinctrl-single,pins = < + 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ + >; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; +}; + +&mmc3 { + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&gpmc { + ranges = <0 0 0x00000000 0x20000000>, + <5 0 0x2c000000 0x01000000>; + + nand@0,0 { + linux,mtd-name= "hynix,h8kds0un0mer-4em"; + reg = <0 0 0>; + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@0x80000 { + label = "U-Boot"; + reg = <0x80000 0x1c0000>; + }; + partition@0x1c0000 { + label = "Environment"; + reg = <0x240000 0x40000>; + }; + partition@0x280000 { + label = "Kernel"; + reg = <0x280000 0x500000>; + }; + partition@0x780000 { + label = "Filesystem"; + reg = <0x780000 0x1f880000>; + }; + }; + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&smsc911x_pins>; + }; +}; diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index 75753bb28535..b5493296d103 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -2,6 +2,8 @@ * Common support for omap3 EVM boards */ +#include "omap-gpmc-smsc911x.dtsi" + / { cpus { cpu@0 { @@ -17,6 +19,17 @@ linux,default-trigger = "default-on"; }; }; + + wl12xx_vmmc: wl12xx_vmmc { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio5 22 0>; /* gpio150 */ + startup-delay-us = <70000>; + enable-active-high; + vin-supply = <&vmmc2>; + }; }; &i2c1 { @@ -48,6 +61,19 @@ }; }; +&mmc1 { + vmmc-supply = <&vmmc1>; + vmmc_aux-supply = <&vsim>; + bus-width = <8>; +}; + +&mmc2 { + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; +}; + &twl_gpio { ti,use-leds; }; @@ -58,3 +84,11 @@ mode = <3>; power = <50>; }; + +&gpmc { + ethernet@gpmc { + interrupt-parent = <&gpio6>; + interrupts = <16 8>; + reg = <5 0 0xff>; + }; +}; -- cgit v1.2.3 From 0a9375d129d4367883a9914c04cecbd31df1361a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 5 Aug 2013 16:10:02 -0700 Subject: ARM: tegra: add GPIO controller to tegra124.dtsi The Tegra124 GPIO controller is identical to Tegra30, so copy the DT node from tegra30.dtsi to tegra124.dtsi. Signed-off-by: Stephen Warren Reviewed-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index f8242488de53..b7413004ee77 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1,3 +1,4 @@ +#include #include #include "skeleton.dtsi" @@ -29,6 +30,23 @@ ; }; + gpio: gpio@6000d000 { + compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; + reg = <0x6000d000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + /* * There are two serial driver i.e. 8250 based simple serial * driver and APB DMA based serial driver for higher baudrate -- cgit v1.2.3 From 05465f4e25c0c37a01a22894220611c58922bb29 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 15 Oct 2013 17:27:51 +0200 Subject: ARM: tegra: Mark Tegra30 display controller compatible with Tegra20 The display controller found on Tegra30 SoCs is backwards-compatible with the one on Tegra20 SoCs. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 0022c127e1d9..d3d71ab7216a 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -141,7 +141,7 @@ }; dc@54200000 { - compatible = "nvidia,tegra30-dc"; + compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; reg = <0x54200000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_DISP1>, -- cgit v1.2.3 From c71d39090eae67c324a870f3c0d26347db504705 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 15 Oct 2013 17:28:02 +0200 Subject: ARM: tegra: Use symbolic names for gr3d clocks Commit 05849c9381354be4bd4a2a878b5ecb12d375a1a0 (ARM: tegra30: convert device tree files to use CLK defines) updated the Tegra30 device tree to use symbolic clock names but forgot to update this node. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d3d71ab7216a..2bd55cfd88ad 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -136,7 +136,8 @@ gr3d { compatible = "nvidia,tegra30-gr3d"; reg = <0x54180000 0x00040000>; - clocks = <&tegra_car 24 &tegra_car 98>; + clocks = <&tegra_car TEGRA30_CLK_GR3D + &tegra_car TEGRA30_CLK_GR3D2>; clock-names = "3d", "3d2"; }; -- cgit v1.2.3 From 443b6585acf70bd9a695fe4fc9325c29c96d7fde Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Thu, 17 Oct 2013 15:03:16 +0200 Subject: ARM: imx27: add missing #pwm-cells property The pwm-node is missing its #pwm-cells property. The pwm-framework will complain about this. Add the missing property. Signed-off-by: Steffen Trumtrar Acked-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index b7a1c6d950b9..826231eb4446 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -123,6 +123,7 @@ }; pwm: pwm@10006000 { + #pwm-cells = <2>; compatible = "fsl,imx27-pwm"; reg = <0x10006000 0x1000>; interrupts = <23>; -- cgit v1.2.3 From dc1089206d1f85fa1b3bd84ea633cbcb12a63956 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Fri, 18 Oct 2013 10:32:52 +0800 Subject: ARM: dts: imx6sl: add a pinctrl for ECSPI1 add a pinctrl for ECSPI1. This pinctrl can be used in the imx6sl-evk board. Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index e4d6d1efb457..0a2d614bc206 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -541,6 +541,16 @@ compatible = "fsl,imx6sl-iomuxc"; reg = <0x020e0000 0x4000>; + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 + MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 + MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 + >; + }; + }; + fec { pinctrl_fec_1: fecgrp-1 { fsl,pins = < -- cgit v1.2.3 From d1b539758ab228bff379ff3049304b0eff15fea9 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Fri, 18 Oct 2013 10:32:53 +0800 Subject: ARM: dts: imx6sl-evk: enable the SPI NOR enable the spi nor for imx6sl-evk boards. Signed-off-by: Huang Shijie Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-evk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index c14195f6c5f9..cc68e19c5163 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -41,6 +41,22 @@ }; }; +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 11 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec_1>; -- cgit v1.2.3 From 84873cb77344b9af7c57586c9c144573ebcf0fd1 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 18 Oct 2013 09:45:07 +0200 Subject: ARM: ux500: fix clock for GPIO block 8 The clock assignment in the device tree for GPIO block 8 was incorrect, indicating this was managed by bit 1 on PRCC 6 while it was in fact bit 1 on PRCC 5. Acked-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 2ef30c1c1997..55abf1292ddd 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -227,7 +227,7 @@ #gpio-cells = <2>; gpio-bank = <8>; - clocks = <&prcc_pclk 6 1>; + clocks = <&prcc_pclk 5 1>; }; pinctrl { -- cgit v1.2.3 From d591640adc7beaf816c2ffc0952d25b836cb3fcf Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 18 Oct 2013 09:49:21 +0200 Subject: ARM: ux500: fix clock for GPIO blocks 6 and 7 The clock assignment in the device tree for GPIO blocks 6 and 7 was incorrect, indicating this was managed by bit 1 on PRCC 2 while it was in fact bit 11 on PRCC 2. Acked-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 55abf1292ddd..5112f4cd8bce 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -197,7 +197,7 @@ #gpio-cells = <2>; gpio-bank = <6>; - clocks = <&prcc_pclk 2 1>; + clocks = <&prcc_pclk 2 11>; }; gpio7: gpio@8011e080 { @@ -212,7 +212,7 @@ #gpio-cells = <2>; gpio-bank = <7>; - clocks = <&prcc_pclk 2 1>; + clocks = <&prcc_pclk 2 11>; }; gpio8: gpio@a03fe000 { -- cgit v1.2.3 From 72b3e249ce5fb298e69bec698f9fdae7cc3f4ceb Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 18 Oct 2013 10:39:58 +0200 Subject: ARM: ux500: fix I2C4 clock bit The PCLK for I2C4 is controlled by bit 10 in the PCKEN registers while the KCLK is controlled by bit 9 on the KCKEN, it's one of these odd assymetric things. Correct the PCLK bit to 10. Acked-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 5112f4cd8bce..0fc634b1b50e 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -694,7 +694,7 @@ clock-frequency = <400000>; - clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 9>; + clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; clock-names = "i2cclk", "apb_pclk"; }; -- cgit v1.2.3 From 6e1484c2761e56bb98ec95ccdd1d98d2f67852ae Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 18 Oct 2013 10:25:52 +0200 Subject: ARM: ux500: register all SSP and SPI blocks This adds the SSP and SPI blocks to the device tree and makes them active. Only this way can their clocks be properly gated off at boot. Acked-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 75 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 0fc634b1b50e..7da99fe497e1 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -704,7 +704,80 @@ interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; + clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; + clock-names = "ssp0clk", "apb_pclk"; + dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ + <&dma 8 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + }; + + ssp@80003000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80003000 0x1000>; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; + clock-names = "ssp1clk", "apb_pclk"; + dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ + <&dma 9 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + }; + + spi@8011a000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x8011a000 0x1000>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; + clock-names = "spi0clk", "apb_pclk"; + dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ + <&dma 0 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + }; + + spi@80112000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80112000 0x1000>; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; + clock-names = "spi1clk", "apb_pclk"; + dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ + <&dma 35 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + }; + + spi@80111000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80111000 0x1000>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; + clock-names = "spi2clk", "apb_pclk"; + dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ + <&dma 33 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; + }; + + spi@80129000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x80129000 0x1000>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* Same clock wired to kernel and pclk */ + clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; + clock-names = "spi3clk", "apb_pclk"; + dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ + <&dma 40 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "tx"; }; uart@80120000 { -- cgit v1.2.3 From e483341ce82750a1b526b65b7178213dcf967a7a Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 18 Oct 2013 16:23:23 +0200 Subject: ARM: at91: remove pinctrl conflict between mmc and SPI for at91sam9g20ek These MMC and SPI buses can't be configured at the same time because they share the same traces on the EK board. Reported-by: Mark Brown Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index 137354689ad0..cb2c010e08e2 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -96,7 +96,6 @@ }; spi0: spi@fffc8000 { - status = "okay"; cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; mtd_dataflash@0 { compatible = "atmel,at45", "atmel,dataflash"; -- cgit v1.2.3 From 5f7adc9762a33c4aa534f575532f55804ff50609 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 18 Oct 2013 23:27:37 +0800 Subject: ARM: imx: imx6sl iomuxc syscon is compatible to imx6q The imx6sl iomuxc syscon is compatible to imx6q, so let's add compatible string 'fsl,imx6q-iomuxc-gpr' for imx6sl iomuxc syscon node. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 0a2d614bc206..6eabfa12e8c5 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -533,7 +533,8 @@ }; gpr: iomuxc-gpr@020e0000 { - compatible = "fsl,imx6sl-iomuxc-gpr", "syscon"; + compatible = "fsl,imx6sl-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e0000 0x38>; }; -- cgit v1.2.3 From c482525659effc9fadc0cef88cffdb6f8c63d2b6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 14 Oct 2013 11:31:43 -0700 Subject: ARM: dts: Add basic support for zoom3 I've tested serial, MMC, smsc911x and wl12xx on zoom3. As my omap is an early ES revision, I have not been able to test off-idle on this one. But anyways, I'd say we have enough device tree support for the zoom to be able to drop the board-zoom files. Patches are welcome to add further features to this .dts file. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/omap-zoom-common.dtsi | 33 +++++ arch/arm/boot/dts/omap3-zoom3.dts | 217 ++++++++++++++++++++++++++++++++ 3 files changed, 251 insertions(+) create mode 100644 arch/arm/boot/dts/omap-zoom-common.dtsi create mode 100644 arch/arm/boot/dts/omap3-zoom3.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 96d8f1f50430..841cd634d95d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -178,6 +178,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap3-gta04.dtb \ omap3-igep0020.dtb \ omap3-igep0030.dtb \ + omap3-zoom3.dtb \ omap4-panda.dtb \ omap4-panda-a4.dtb \ omap4-panda-es.dtb \ diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi new file mode 100644 index 000000000000..b0ee342598f0 --- /dev/null +++ b/arch/arm/boot/dts/omap-zoom-common.dtsi @@ -0,0 +1,33 @@ +/* + * Common features on the Zoom debug board + */ + +#include "omap-gpmc-smsc911x.dtsi" + +&gpmc { + ranges = <3 0 0x10000000 0x00000400>, + <7 0 0x2c000000 0x01000000>; + + /* + * Four port TL16CP754C serial port on GPMC, + * they probably share the same GPIO IRQ + * REVISIT: Add timing support from slls644g.pdf + */ + 8250@3,0 { + compatible = "ns16550a"; + reg = <3 0 0x100>; + bank-width = <2>; + reg-shift = <1>; + reg-io-width = <1>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ + clock-frequency = <1843200>; + current-speed = <115200>; + }; + + ethernet@gpmc { + reg = <7 0 0xff>; + interrupt-parent = <&gpio5>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; /* gpio158 */ + }; +}; diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts new file mode 100644 index 000000000000..15eb9fe5169c --- /dev/null +++ b/arch/arm/boot/dts/omap3-zoom3.dts @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap36xx.dtsi" +#include "omap-zoom-common.dtsi" + +/ { + model = "TI Zoom3"; + compatible = "ti,omap3-zoom3", "ti,omap36xx", "ti,omap3"; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + vddvario: regulator-vddvario { + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; + }; + + vdd33a: regulator-vdd33a { + compatible = "regulator-fixed"; + regulator-name = "vdd33a"; + regulator-always-on; + }; + + wl12xx_vmmc: wl12xx_vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio4 5 0>; /* gpio101 */ + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&omap3_pmx_core { + /* REVISIT: twl gpio0 is mmc0_cd */ + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + 0x116 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + 0x12c (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + 0x12e (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + 0x130 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + 0x132 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + 0x134 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ + 0x136 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ + 0x138 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ + 0x13a (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ + >; + }; + + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + 0x168 (PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ + 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ + 0x5a8 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + 0x5b4 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ + 0x5b6 (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ + 0x5b8 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ + 0x5b2 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x150 (PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ + 0x14e (PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ + 0x152 (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + 0x14c (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x144 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ + 0x146 (PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + 0x14a (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x16a (PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ + 0x16c (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ + 0x16e (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + /* wl12xx GPIO output for WLAN_EN */ + wl12xx_gpio: pinmux_wl12xx_gpio { + pinctrl-single,pins = < + 0xea (PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ + >; + }; +}; + +&omap3_pmx_wkup { + wlan_host_wkup: pinmux_wlan_host_wkup_pins { + pinctrl-single,pins = < + 0x1a (PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */ + >; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +#include "twl4030.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; + + /* + * TVP5146 Video decoder-in for analog input support. + */ + tvp5146@5c { + compatible = "ti,tvp5146m2"; + reg = <0x5c>; + }; +}; + +&twl_gpio { + ti,use-leds; +}; + +&mmc1 { + vmmc-supply = <&vmmc1>; + vmmc_aux-supply = <&vsim>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +}; +/* +&mmc2 { + vmmc-supply = <&vmmc2>; + ti,non-removable; + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; +}; +*/ +&mmc3 { + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&uart4 { + status = "disabled"; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + mode = <3>; + power = <50>; +}; -- cgit v1.2.3 From df01318850d5c687533c6e2460d1df65944d0d4b Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Tue, 15 Oct 2013 23:36:09 +0300 Subject: ARM: dts: add minimal DT support for Nokia N950 & N9 phones Add minimal DT support for Nokia N950 & N9 phones. The same functionality that is provided by the current board file should work: serial console, USB, OneNAND and MMC. Signed-off-by: Aaro Koskinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/omap3-n9.dts | 18 ++++ arch/arm/boot/dts/omap3-n950-n9.dtsi | 174 +++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap3-n950.dts | 18 ++++ 4 files changed, 212 insertions(+) create mode 100644 arch/arm/boot/dts/omap3-n9.dts create mode 100644 arch/arm/boot/dts/omap3-n950-n9.dtsi create mode 100644 arch/arm/boot/dts/omap3-n950.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 841cd634d95d..e3a8f226bf52 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -174,6 +174,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap3-evm.dtb \ omap3-evm-37xx.dtb \ omap3-n900.dtb \ + omap3-n9.dtb \ + omap3-n950.dtb \ omap3-tobi.dtb \ omap3-gta04.dtb \ omap3-igep0020.dtb \ diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts new file mode 100644 index 000000000000..39828ce464ee --- /dev/null +++ b/arch/arm/boot/dts/omap3-n9.dts @@ -0,0 +1,18 @@ +/* + * omap3-n9.dts - Device Tree file for Nokia N9 + * + * Written by: Aaro Koskinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "omap3-n950-n9.dtsi" + +/ { + model = "Nokia N9"; + compatible = "nokia,omap3-n9", "ti,omap3"; +}; diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi new file mode 100644 index 000000000000..94eb77d3b9dd --- /dev/null +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -0,0 +1,174 @@ +/* + * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff) + * + * Written by: Aaro Koskinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap36xx.dtsi" + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + vemmc: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VEMMC"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + gpio = <&gpio5 29 0>; /* gpio line 157 */ + startup-delay-us = <150>; + enable-active-high; + }; +}; + +&omap3_pmx_core { + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ + 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ + 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ + 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ + >; + }; +}; + +&i2c1 { + clock-frequency = <2900000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +/include/ "twl4030.dtsi" + +&twl { + compatible = "ti,twl5031"; +}; + +&twl_gpio { + ti,pullups = <0x000001>; /* BIT(0) */ + ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; +}; + +&mmc1 { + status = "disabled"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vemmc>; + bus-width = <4>; + ti,non-removable; +}; + +&mmc3 { + status = "disabled"; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&gpmc { + ranges = <0 0 0x04000000 0x20000000>; + + onenand@0,0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x20000000>; + + gpmc,sync-read; + gpmc,sync-write; + gpmc,burst-length = <16>; + gpmc,burst-read; + gpmc,burst-wrap; + gpmc,burst-write; + gpmc,device-width = <2>; + gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <87>; + gpmc,cs-wr-off-ns = <87>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <10>; + gpmc,adv-wr-off-ns = <10>; + gpmc,oe-on-ns = <15>; + gpmc,oe-off-ns = <87>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <87>; + gpmc,rd-cycle-ns = <112>; + gpmc,wr-cycle-ns = <112>; + gpmc,access-ns = <81>; + gpmc,page-burst-access-ns = <15>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <5>; + gpmc,wr-data-mux-bus-ns = <30>; + gpmc,wr-access-ns = <81>; + gpmc,sync-clk-ps = <15000>; + + /* + * MTD partition table corresponding to Nokia's MeeGo 1.2 + * Harmattan release. + */ + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x00100000>; + }; + partition@1 { + label = "config"; + reg = <0x00100000 0x002c0000>; + }; + partition@2 { + label = "kernel"; + reg = <0x003c0000 0x01000000>; + }; + partition@3 { + label = "log"; + reg = <0x013c0000 0x00200000>; + }; + partition@4 { + label = "var"; + reg = <0x015c0000 0x1ca40000>; + }; + partition@5 { + label = "moslo"; + reg = <0x1e000000 0x02000000>; + }; + partition@6 { + label = "omap2-onenand"; + reg = <0x00000000 0x20000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts new file mode 100644 index 000000000000..b076a526b999 --- /dev/null +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -0,0 +1,18 @@ +/* + * omap3-n950.dts - Device Tree file for Nokia N950 + * + * Written by: Aaro Koskinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "omap3-n950-n9.dtsi" + +/ { + model = "Nokia N950"; + compatible = "nokia,omap3-n950", "ti,omap3"; +}; -- cgit v1.2.3 From 5b025848e17a8659e2ebac21935daaa01799834b Mon Sep 17 00:00:00 2001 From: Sricharan R Date: Thu, 10 Oct 2013 13:20:13 +0530 Subject: ARM: dts: OMAP5: Remove clock-frequency field for cpu timers The arm arch timers frequency are now programmed in the CNTFREQ per-cpu register by the timer code using the secure API [1]. So remove the redundant entry from the dts. [1] http://marc.info/?l=linux-omap&m=138139106312786&w=2 Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 6192c458bea1..6a558cedffd6 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -52,7 +52,6 @@ , , ; - clock-frequency = <6144000>; }; gic: interrupt-controller@48211000 { -- cgit v1.2.3 From d2afcf09e6450e41b8987cf282ffde79c40ab401 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 7 Oct 2013 16:28:13 +0300 Subject: ARM: dts: omap3: Adapt USB OTG to generic PHY framework The generic PHY framewrok expects different properties than the old USB PHY framework. Supply those properties. Fixes USB OTG port on GAT04 and N900 after the Generic PHY framework was merged in greg/usb-next. [1] [1] - https://lkml.org/lkml/2013/9/27/581 Signed-off-by: Roger Quadros Acked-by: Felipe Balbi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-gta04.dts | 2 ++ arch/arm/boot/dts/omap3-n900.dts | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts index a84684a95891..b9b55c95a566 100644 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ b/arch/arm/boot/dts/omap3-gta04.dts @@ -131,6 +131,8 @@ &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; mode = <3>; power = <50>; }; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index d64fa04e83f6..e13b697f8bce 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -87,6 +87,8 @@ &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; mode = <2>; power = <50>; }; -- cgit v1.2.3 From f12ecbe2ea3c01b61e93af815723939a27511abc Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 15 Oct 2013 12:37:50 +0530 Subject: ARM: dts: omap: Add reset/idle on init bindings for OMAP On OMAP we have co-processor IPs, memory controllers, GPIOs which control regulators and power switches to PMIC, and SoC internal Bus IPs, some or most of which should either not be reset or idled or both at init. (In some cases there are erratas which prevent an IP from being reset) Have a way to pass this information from DT. Update the am33xx/omap4 and omap5 dtsi files with the new bindings for modules which either should not be idled. reset or both. A later patch would cleanup the same information that exists today as part of the hwmod data files. Signed-off-by: Rajendra Nayak Signed-off-by: Benoit Cousson --- Documentation/devicetree/bindings/arm/omap/omap.txt | 3 ++- arch/arm/boot/dts/am33xx.dtsi | 2 ++ arch/arm/boot/dts/omap4.dtsi | 3 +++ arch/arm/boot/dts/omap5.dtsi | 2 ++ 4 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index 91b7049affa1..808c1543b0f8 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -21,7 +21,8 @@ Required properties: Optional properties: - ti,no_idle_on_suspend: When present, it prevents the PM to idle the module during suspend. - +- ti,no-reset-on-init: When present, the module should not be reset at init +- ti,no-idle-on-init: When present, the module should not be idled at init Example: diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 7db3c81d1563..58cf5b91a118 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -674,6 +674,7 @@ reg = <0x44d00000 0x4000 /* M3 UMEM */ 0x44d80000 0x2000>; /* M3 DMEM */ ti,hwmods = "wkup_m3"; + ti,no-reset-on-init; }; elm: elm@48080000 { @@ -713,6 +714,7 @@ gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; + ti,no-idle-on-init; reg = <0x50000000 0x2000>; interrupts = <100>; gpmc,num-cs = <7>; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 6be1f5678f1a..6ca45b0d346b 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -214,6 +214,7 @@ gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; + ti,no-idle-on-init; }; uart1: serial@4806a000 { @@ -492,6 +493,7 @@ reg = <0x4c000000 0x100>; interrupts = ; ti,hwmods = "emif1"; + ti,no-idle-on-init; phy-type = <1>; hw-caps-read-idle-ctrl; hw-caps-ll-interface; @@ -503,6 +505,7 @@ reg = <0x4d000000 0x100>; interrupts = ; ti,hwmods = "emif2"; + ti,no-idle-on-init; phy-type = <1>; hw-caps-read-idle-ctrl; hw-caps-ll-interface; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 6a558cedffd6..f518ec6b6e49 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -606,6 +606,7 @@ emif1: emif@4c000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif1"; + ti,no-idle-on-init; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4c000000 0x400>; interrupts = ; @@ -617,6 +618,7 @@ emif2: emif@4d000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif2"; + ti,no-idle-on-init; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4d000000 0x400>; interrupts = ; -- cgit v1.2.3 From 6046adb6ad701026c10adeac8d6a4138895f12e5 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 9 Oct 2013 15:42:01 +0530 Subject: ARM: dts: am335x-evmsk: Do not reset gpio0 Do not reset GPIO0 at boot-up because GPIO0 is used on AM335x EVM-SK to control VTT regulators on DDR3. Without this EVM-SK boards fail to boot-up because of DDR3 corruption. Signed-off-by: Rajendra Nayak Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evmsk.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 5f12b28dd593..1a7e0d925965 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -433,3 +433,7 @@ &aes { status = "okay"; }; + +&gpio0 { + ti,no-reset-on-init; +}; -- cgit v1.2.3 From c1bac171c4f203101611110869bd2511c8153974 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 10 Oct 2013 11:44:41 -0500 Subject: ARM: dts: omap4-panda-es: Do not reset gpio1 Do not reset GPIO1 at boot-up because GPIO 7 in GPIO1 block is used on OMAP4460 PandaBoard-ES to select voltage register in TPS62361 which supplies VDD_MPU. Without this, OMAP4460 PandaBoard-ES boards fail to boot-up because MPU voltage switches over to VSET0 voltage value (boot voltage) which is not sufficient to operate the device at OPP100. Signed-off-by: Nishanth Menon Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4-panda-es.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index 56c435468e94..816d1c95b592 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -62,3 +62,7 @@ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; }; + +&gpio1 { + ti,no-reset-on-init; +}; -- cgit v1.2.3 From 46a25f1283aba55182cf5684fe217b0d5ca4e5f6 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 10 Oct 2013 16:19:53 +0530 Subject: ARM: dts: omap5-uevm: remove always_on, boot_on from smps10_out1 smps10 should be enabled only in the case of host mode. So stop doing always_on, boot_on from smps10_out1. The driver will enable it in host mode. Signed-off-by: Kishon Vijay Abraham I Acked-by: Nishanth Menon Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-uevm.dts | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index d784b3a00410..e06a04a63664 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -334,8 +334,6 @@ regulator-name = "smps10_out1"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; }; ldo1_reg: ldo1 { -- cgit v1.2.3 From c47ee6ee8b93a41428846f86fa36dc80cee432ce Mon Sep 17 00:00:00 2001 From: George Cherian Date: Thu, 10 Oct 2013 16:19:54 +0530 Subject: ARM: dts: OMAP5: Add dr_mode for dwc3 Added dr_mode property in dwc3 and set its default mode to device. Signed-off-by: George Cherian Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index f518ec6b6e49..53686e46f482 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -649,6 +649,7 @@ reg = <0x4a030000 0x10000>; interrupts = ; usb-phy = <&usb2_phy>, <&usb3_phy>; + dr_mode = "peripheral"; tx-fifo-resize; }; }; -- cgit v1.2.3 From 9e3269b8c68cef55a35146d32b2adde1009ce075 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Fri, 11 Oct 2013 00:44:53 +0530 Subject: ARM: dts: AM4372: Add L2, EDMA, mailbox, MMC and SHAM nodes Populate nodes for l2-cache-controller, EDMA, mailbox, mmc, sham. Update as well DT properties for epwmss, aes, des. Signed-off-by: Suman Anna Signed-off-by: Balaji T K Signed-off-by: Mugunthan V N Signed-off-by: Lokesh Vutla Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am4372.dtsi | 210 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 209 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index a403172430bc..c328d5cd8145 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -19,6 +19,8 @@ aliases { serial0 = &uart0; + ethernet0 = &cpsw_emac0; + ethernet1 = &cpsw_emac1; }; cpus { @@ -39,11 +41,42 @@ <0x48240100 0x0100>; }; + l2-cache-controller@48242000 { + compatible = "arm,pl310-cache"; + reg = <0x48242000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + am43xx_pinmux: pinmux@44e10800 { + compatible = "pinctrl-single"; + reg = <0x44e10800 0x31c>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + ocp { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + ti,hwmods = "l3_main"; + + edma: edma@49000000 { + compatible = "ti,edma3"; + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; + reg = <0x49000000 0x10000>, + <0x44e10f90 0x10>; + interrupts = , + , + ; + #dma-cells = <1>; + dma-channels = <64>; + ti,edma-regions = <4>; + ti,edma-slots = <256>; + }; uart0: serial@44e09000 { compatible = "ti,am4372-uart","ti,omap2-uart"; @@ -92,6 +125,18 @@ status = "disabled"; }; + mailbox: mailbox@480C8000 { + compatible = "ti,omap4-mailbox"; + reg = <0x480C8000 0x200>; + interrupts = ; + ti,hwmods = "mailbox"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <8>; + ti,mbox-names = "wkup_m3"; + ti,mbox-data = <0 0 0 0>; + status = "disabled"; + }; + timer1: timer@44e31000 { compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; reg = <0x44e31000 0x400>; @@ -203,7 +248,6 @@ reg = <0x44e35000 0x1000>; interrupts = ; ti,hwmods = "wd_timer2"; - status = "disabled"; }; gpio0: gpio@44e07000 { @@ -318,6 +362,40 @@ status = "disabled"; }; + mmc1: mmc@48060000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x48060000 0x1000>; + ti,hwmods = "mmc1"; + ti,dual-volt; + ti,needs-special-reset; + dmas = <&edma 24 + &edma 25>; + dma-names = "tx", "rx"; + interrupts = ; + status = "disabled"; + }; + + mmc2: mmc@481d8000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x481d8000 0x1000>; + ti,hwmods = "mmc2"; + ti,needs-special-reset; + dmas = <&edma 2 + &edma 3>; + dma-names = "tx", "rx"; + interrupts = ; + status = "disabled"; + }; + + mmc3: mmc@47810000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x47810000 0x1000>; + ti,hwmods = "mmc3"; + ti,needs-special-reset; + interrupts = ; + status = "disabled"; + }; + spi1: spi@481a0000 { compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; reg = <0x481a0000 0x400>; @@ -366,50 +444,173 @@ GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; ti,hwmods = "cpgmac0"; status = "disabled"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + no_bd_ram = <0>; + rx_descs = <64>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + ranges; + + davinci_mdio: mdio@4a101000 { + compatible = "ti,am4372-mdio","ti,davinci_mdio"; + reg = <0x4a101000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpsw_emac0: slave@4a100200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + cpsw_emac1: slave@4a100300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; }; epwmss0: epwmss@48300000 { compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; reg = <0x48300000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; ti,hwmods = "epwmss0"; status = "disabled"; + + ecap0: ecap@48300100 { + compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + reg = <0x48300100 0x80>; + ti,hwmods = "ecap0"; + status = "disabled"; + }; + + ehrpwm0: ehrpwm@48300200 { + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + reg = <0x48300200 0x80>; + ti,hwmods = "ehrpwm0"; + status = "disabled"; + }; }; epwmss1: epwmss@48302000 { compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; reg = <0x48302000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; ti,hwmods = "epwmss1"; status = "disabled"; + + ecap1: ecap@48302100 { + compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + reg = <0x48302100 0x80>; + ti,hwmods = "ecap1"; + status = "disabled"; + }; + + ehrpwm1: ehrpwm@48302200 { + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + reg = <0x48302200 0x80>; + ti,hwmods = "ehrpwm1"; + status = "disabled"; + }; }; epwmss2: epwmss@48304000 { compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; reg = <0x48304000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; ti,hwmods = "epwmss2"; status = "disabled"; + + ecap2: ecap@48304100 { + compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + reg = <0x48304100 0x80>; + ti,hwmods = "ecap2"; + status = "disabled"; + }; + + ehrpwm2: ehrpwm@48304200 { + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + reg = <0x48304200 0x80>; + ti,hwmods = "ehrpwm2"; + status = "disabled"; + }; }; epwmss3: epwmss@48306000 { compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; reg = <0x48306000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; ti,hwmods = "epwmss3"; status = "disabled"; + + ehrpwm3: ehrpwm@48306200 { + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + reg = <0x48306200 0x80>; + ti,hwmods = "ehrpwm3"; + status = "disabled"; + }; }; epwmss4: epwmss@48308000 { compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; reg = <0x48308000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; ti,hwmods = "epwmss4"; status = "disabled"; + + ehrpwm4: ehrpwm@48308200 { + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + reg = <0x48308200 0x80>; + ti,hwmods = "ehrpwm4"; + status = "disabled"; + }; }; epwmss5: epwmss@4830a000 { compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; reg = <0x4830a000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; ti,hwmods = "epwmss5"; status = "disabled"; + + ehrpwm5: ehrpwm@4830a200 { + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + reg = <0x4830a200 0x80>; + ti,hwmods = "ehrpwm5"; + status = "disabled"; + }; + }; + + sham: sham@53100000 { + compatible = "ti,omap5-sham"; + ti,hwmods = "sham"; + reg = <0x53100000 0x300>; + dmas = <&edma 36>; + dma-names = "rx"; + interrupts = ; }; aes: aes@53501000 { @@ -417,6 +618,9 @@ ti,hwmods = "aes"; reg = <0x53501000 0xa0>; interrupts = ; + dmas = <&edma 6 + &edma 5>; + dma-names = "tx", "rx"; }; des: des@53701000 { @@ -424,6 +628,10 @@ ti,hwmods = "des"; reg = <0x53701000 0xa0>; interrupts = ; + dmas = <&edma 34 + &edma 33>; + dma-names = "tx", "rx"; }; + }; }; -- cgit v1.2.3 From e54686e4c79a5b2e8d8c77317ac8ab08d3040935 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Fri, 11 Oct 2013 00:44:54 +0530 Subject: ARM: dts: AM4372: Update Support for EPOS EVM -> Adding pinmux for cpsw, i2c0. -> Enabling the modules that are present in AM4372 EPOS EVM These modules are tested on AM4372 EPOS EVM. Signed-off-by: Lokesh Vutla Signed-off-by: Sourav Poddar Signed-off-by: Mugunthan V N Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am43x-epos-evm.dts | 168 +++++++++++++++++++++++++++++++++++ include/dt-bindings/pinctrl/am43xx.h | 31 +++++++ 2 files changed, 199 insertions(+) create mode 100644 include/dt-bindings/pinctrl/am43xx.h (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 74174d48f476..fbf9c4c7a94f 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -11,8 +11,176 @@ /dts-v1/; #include "am4372.dtsi" +#include +#include / { model = "TI AM43x EPOS EVM"; compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43"; + + vmmcsd_fixed: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + am43xx_pinmux: pinmux@44e10800 { + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + }; + + matrix_keypad: matrix_keypad@0 { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + + row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ + &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ + &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ + &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ + + col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ + &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ + &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ + &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ + + linux,keymap = <0x00000201 /* P1 */ + 0x01000204 /* P4 */ + 0x02000207 /* P7 */ + 0x0300020a /* NUMERIC_STAR */ + 0x00010202 /* P2 */ + 0x01010205 /* P5 */ + 0x02010208 /* P8 */ + 0x03010200 /* P0 */ + 0x00020203 /* P3 */ + 0x01020206 /* P6 */ + 0x02020209 /* P9 */ + 0x0302020b /* NUMERIC_POUND */ + 0x00030067 /* UP */ + 0x0103006a /* RIGHT */ + 0x0203006c /* DOWN */ + 0x03030069>; /* LEFT */ + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <16>; + phy-mode = "rmii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rmii"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + at24@50 { + compatible = "at24,24c256"; + pagesize = <64>; + reg = <0x50>; + }; + + pixcir_ts@5c { + compatible = "pixcir,pixcir_ts"; + reg = <0x5c>; + interrupt-parent = <&gpio1>; + interrupts = <17 0>; + + attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; + + x-size = <1024>; + y-size = <768>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; }; diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h new file mode 100644 index 000000000000..eb6c366adfba --- /dev/null +++ b/include/dt-bindings/pinctrl/am43xx.h @@ -0,0 +1,31 @@ +/* + * This header provides constants specific to AM43XX pinctrl bindings. + */ + +#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H +#define _DT_BINDINGS_PINCTRL_AM43XX_H + +#define MUX_MODE0 0 +#define MUX_MODE1 1 +#define MUX_MODE2 2 +#define MUX_MODE3 3 +#define MUX_MODE4 4 +#define MUX_MODE5 5 +#define MUX_MODE6 6 +#define MUX_MODE7 7 + +#define PULL_DISABLE (1 << 16) +#define PULL_UP (1 << 17) +#define INPUT_EN (1 << 18) +#define SLEWCTRL_FAST (1 << 19) +#define DS0_PULL_UP_DOWN_EN (1 << 27) + +#define PIN_OUTPUT (PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN 0 +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN) + +#endif + -- cgit v1.2.3 From 3f72f87566e84d79201dc5f71f68f06cb0fcf0da Mon Sep 17 00:00:00 2001 From: Pantelis Antoniou Date: Sun, 20 Oct 2013 20:04:08 +0300 Subject: ARM: dts: AM33XX: Add mcasp0 and mcasp1 device tree entries Add missing mcasp entries in the am33xx.dtsi include file. Signed-off-by: Pantelis Antoniou Signed-off-by: Darren Etheridge Signed-off-by: Jyri Sarha Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 58cf5b91a118..861382ffa557 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -742,5 +742,29 @@ <&edma 5>; dma-names = "tx", "rx"; }; + + mcasp0: mcasp@48038000 { + compatible = "ti,am33xx-mcasp-audio"; + ti,hwmods = "mcasp0"; + reg = <0x48038000 0x2000>; + interrupts = <80>, <81>; + interrupts-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 8>, + <&edma 9>; + dma-names = "tx", "rx"; + }; + + mcasp1: mcasp@4803C000 { + compatible = "ti,am33xx-mcasp-audio"; + ti,hwmods = "mcasp1"; + reg = <0x4803C000 0x2000>; + interrupts = <82>, <83>; + interrupts-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 10>, + <&edma 11>; + dma-names = "tx", "rx"; + }; }; }; -- cgit v1.2.3 From 0bee55ab78a4450e5879c537097e97f3066dc14f Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Sun, 20 Oct 2013 20:04:09 +0300 Subject: ARM: dts: AM33XX: mcasp: Add location for data port registers to reg-property This patch adds a second tuple to reg property. The new property tuple describes the memory location for data port registers mapped trough L3 bus on am33xx. The both property tuples are named accordingly in the reg-names property. Signed-off-by: Hebbar, Gururaja Signed-off-by: Darren Etheridge Signed-off-by: Jyri Sarha Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 861382ffa557..3465d4b116af 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -746,7 +746,9 @@ mcasp0: mcasp@48038000 { compatible = "ti,am33xx-mcasp-audio"; ti,hwmods = "mcasp0"; - reg = <0x48038000 0x2000>; + reg = <0x48038000 0x2000>, + <0x46000000 0x400000>; + reg-names = "mpu", "dat"; interrupts = <80>, <81>; interrupts-names = "tx", "rx"; status = "disabled"; @@ -758,7 +760,9 @@ mcasp1: mcasp@4803C000 { compatible = "ti,am33xx-mcasp-audio"; ti,hwmods = "mcasp1"; - reg = <0x4803C000 0x2000>; + reg = <0x4803C000 0x2000>, + <0x46400000 0x400000>; + reg-names = "mpu", "dat"; interrupts = <82>, <83>; interrupts-names = "tx", "rx"; status = "disabled"; -- cgit v1.2.3 From f608f8dd31d2b5dc749e91e0f33fdfe44df4347d Mon Sep 17 00:00:00 2001 From: Darren Etheridge Date: Sun, 20 Oct 2013 20:04:10 +0300 Subject: ARM: dts: am335x-evm: Add audio support for am335x-evm.dts Adds sound, tlv320aic3106, mcasp1, and am335x_evm_audio_pin nodes. Signed-off-by: Darren Etheridge Signed-off-by: Peter Ujfalusi Signed-off-by: Jyri Sarha Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evm.dts | 50 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index eabacf9b8c31..987429436171 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -119,6 +119,19 @@ }; }; }; + + sound { + compatible = "ti,da830-evm-audio"; + ti,model = "AM335x-EVM"; + ti,audio-codec = <&tlv320aic3106>; + ti,mcasp-controller = <&mcasp1>; + ti,codec-clock-rate = <12000000>; + ti,audio-routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + }; }; &am33xx_pinmux { @@ -279,6 +292,15 @@ 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ >; }; + + am335x_evm_audio_pins: am335x_evm_audio_pins { + pinctrl-single,pins = < + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */ + 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + >; + }; }; &uart0 { @@ -373,6 +395,18 @@ compatible = "ti,tmp275"; reg = <0x48>; }; + + tlv320aic3106: tlv320aic3106@1b { + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&vaux2_reg>; + IOVDD-supply = <&vaux2_reg>; + DRVDD-supply = <&vaux2_reg>; + DVDD-supply = <&vbat>; + }; }; &lcdc { @@ -476,6 +510,22 @@ #include "tps65910.dtsi" +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&am335x_evm_audio_pins>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 + >; + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; -- cgit v1.2.3 From b452985bfa39be27f1eb836cd336f60324eb0be9 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 20 Oct 2013 20:04:11 +0300 Subject: ARM: dts: am335x-evmsk: Audio support AM335x EVM-SK have only support for audio playback (stereo jack on the board) via tlv320aic3106 codec connected to McASP1. Enable the support for audio playback on the board: - McASP1 configuration - tlv320aic3106 configuration - Machine driver. Signed-off-by: Peter Ujfalusi Signed-off-by: Jyri Sarha Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-evmsk.dts | 48 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 1a7e0d925965..03febf85fd2f 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -115,6 +115,17 @@ brightness-levels = <0 58 61 66 75 90 125 170 255>; default-brightness-level = <8>; }; + + sound { + compatible = "ti,da830-evm-audio"; + ti,model = "AM335x-EVMSK"; + ti,audio-codec = <&tlv320aic3106>; + ti,mcasp-controller = <&mcasp1>; + ti,codec-clock-rate = <24576000>; + ti,audio-routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT"; + }; }; &am33xx_pinmux { @@ -244,6 +255,15 @@ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; + + mcasp1_pins: mcasp1_pins { + pinctrl-single,pins = < + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + >; + }; }; &uart0 { @@ -291,6 +311,18 @@ st,max-limit-y = <550>; st,max-limit-z = <750>; }; + + tlv320aic3106: tlv320aic3106@1b { + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&vaux2_reg>; + IOVDD-supply = <&vaux2_reg>; + DRVDD-supply = <&vaux2_reg>; + DVDD-supply = <&vbat>; + }; }; &usb { @@ -437,3 +469,19 @@ &gpio0 { ti,no-reset-on-init; }; + +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp1_pins>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 + >; + tx-num-evt = <1>; + rx-num-evt = <1>; +}; -- cgit v1.2.3 From b462b05ab6f3b1b6121446beb87a9eac5a37fd55 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 7 Oct 2013 13:46:50 +0300 Subject: ARM: dts: omap3-beagle: Adapt USB OTG to generic PHY framework The generic PHY framewrok expects different properties than the old USB PHY framework. Supply those properties. Fixes USB OTG port on beagle after the Generic PHY framework was merged in greg/usb-next. [1] [1] - https://lkml.org/lkml/2013/9/27/581 Signed-off-by: Roger Quadros Acked-by: Felipe Balbi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-beagle.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 7669c16259a5..fa532aaacc68 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -173,6 +173,8 @@ &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; mode = <3>; power = <50>; }; -- cgit v1.2.3 From b9c95bf4e07757b525aefe39136a7f5050077531 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 21 Oct 2013 12:45:58 +0300 Subject: ARM: dts: AM4372: Add McASP nodes Add nodes for McASP0 and McASP1 for AM43xx. Signed-off-by: Peter Ujfalusi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am4372.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index c328d5cd8145..defaad16cdf1 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -633,5 +633,32 @@ dma-names = "tx", "rx"; }; + mcasp0: mcasp@48038000 { + compatible = "ti,am33xx-mcasp-audio"; + ti,hwmods = "mcasp0"; + reg = <0x48038000 0x2000>, + <0x46000000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <80>, <81>; + interrupts-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 8>, + <&edma 9>; + dma-names = "tx", "rx"; + }; + + mcasp1: mcasp@4803C000 { + compatible = "ti,am33xx-mcasp-audio"; + ti,hwmods = "mcasp1"; + reg = <0x4803C000 0x2000>, + <0x46400000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <82>, <83>; + interrupts-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 10>, + <&edma 11>; + dma-names = "tx", "rx"; + }; }; }; -- cgit v1.2.3 From 0ae6f9ee55aa54dcae465ad7fafea639848a601c Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Sat, 19 Oct 2013 22:55:19 +0200 Subject: ARM: dts: igep0033: Add mmc1 node for SDCARD support. Add mmc1 dt node to IGEP COM AQUILA board. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-igep0033.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index 06eba076bfcd..619624479311 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -44,6 +44,13 @@ regulator-max-microvolt = <5000000>; regulator-boot-on; }; + + vmmc: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &am33xx_pinmux { @@ -180,6 +187,12 @@ }; }; +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc>; + bus-width = <4>; +}; + &uart0 { status = "okay"; pinctrl-names = "default"; -- cgit v1.2.3 From 20b80942ef4e3156a1c4aa5628d1bcb3479812da Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 16 Oct 2013 15:21:03 -0500 Subject: ARM: dts: OMAP3+: Add i2c aliases Currently, on OMAP5, i2c1 and i2c5 defer probe due to pinctrl dependencies. This changes the i2c ID each bus is registered with in i2c-dev interface. As a result of this, many userspace tools break and there is no consistent manner to fix the same if the i2c dev interface have no consistent numbering. Since this could happen for other OMAP derivatives, provide i2c alias for all OMAP3+ SoCs to allow ordering the i2c devices correctly. Signed-off-by: Nishanth Menon Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/dra7.dtsi | 5 +++++ arch/arm/boot/dts/omap3.dtsi | 3 +++ arch/arm/boot/dts/omap4.dtsi | 4 ++++ arch/arm/boot/dts/omap5.dtsi | 5 +++++ 4 files changed, 17 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c01ef769761f..98ff6553edbc 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -20,6 +20,11 @@ interrupt-parent = <&gic>; aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + i2c4 = &i2c5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 16420ae16004..493b6d4373d1 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -19,6 +19,9 @@ interrupt-parent = <&intc>; aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 6ca45b0d346b..0d8fdbad43fa 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -17,6 +17,10 @@ interrupt-parent = <&gic>; aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 53686e46f482..2cb72ba1dd05 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -21,6 +21,11 @@ interrupt-parent = <&gic>; aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + i2c4 = &i2c5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; -- cgit v1.2.3 From 6a96867844895008558810853c7838af39dd317c Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 16 Oct 2013 15:21:04 -0500 Subject: ARM: dts: AM33xx+: Add i2c aliases Provide alias to allow ordering the i2c devices correctly. Signed-off-by: Nishanth Menon Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 3 +++ arch/arm/boot/dts/am4372.dtsi | 3 +++ 2 files changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 3465d4b116af..97f501951564 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -18,6 +18,9 @@ interrupt-parent = <&intc>; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index defaad16cdf1..974d103ab3b1 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -18,6 +18,9 @@ aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; serial0 = &uart0; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; -- cgit v1.2.3 From d7c8f25965b6931de93f2b55b00f0f3fca995a21 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 17 Oct 2013 15:15:22 -0700 Subject: ARM: dts: Add missing reg, interrupt and dma entries for omap3 Looks like omap3 is still relying on hwmod data for some basic device tree information. Let's add the information to omap3.dtsi so we can remove the related hwmod data once omap3 is DT only. Acked-by: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap36xx.dtsi | 4 ++++ 2 files changed, 53 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 493b6d4373d1..27e0eb9a3cc7 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -40,6 +40,7 @@ pmu { compatible = "arm,cortex-a8-pmu"; + reg = <0x54000000 0x800000>; interrupts = <3>; ti,hwmods = "debugss"; }; @@ -74,6 +75,8 @@ */ ocp { compatible = "simple-bus"; + reg = <0x68000000 0x10000>; + interrupts = <9 10>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -192,24 +195,40 @@ uart1: serial@4806a000 { compatible = "ti,omap3-uart"; + reg = <0x4806a000 0x2000>; + interrupts = <72>; + dmas = <&sdma 49 &sdma 50>; + dma-names = "tx", "rx"; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap3-uart"; + reg = <0x4806c000 0x400>; + interrupts = <73>; + dmas = <&sdma 51 &sdma 52>; + dma-names = "tx", "rx"; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@49020000 { compatible = "ti,omap3-uart"; + reg = <0x49020000 0x400>; + interrupts = <74>; + dmas = <&sdma 53 &sdma 54>; + dma-names = "tx", "rx"; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; i2c1: i2c@48070000 { compatible = "ti,omap3-i2c"; + reg = <0x48070000 0x80>; + interrupts = <56>; + dmas = <&sdma 27 &sdma 28>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -217,6 +236,10 @@ i2c2: i2c@48072000 { compatible = "ti,omap3-i2c"; + reg = <0x48072000 0x80>; + interrupts = <57>; + dmas = <&sdma 29 &sdma 30>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -224,6 +247,10 @@ i2c3: i2c@48060000 { compatible = "ti,omap3-i2c"; + reg = <0x48060000 0x80>; + interrupts = <61>; + dmas = <&sdma 25 &sdma 26>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; @@ -231,6 +258,8 @@ mcspi1: spi@48098000 { compatible = "ti,omap2-mcspi"; + reg = <0x48098000 0x100>; + interrupts = <65>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; @@ -249,6 +278,8 @@ mcspi2: spi@4809a000 { compatible = "ti,omap2-mcspi"; + reg = <0x4809a000 0x100>; + interrupts = <66>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi2"; @@ -262,6 +293,8 @@ mcspi3: spi@480b8000 { compatible = "ti,omap2-mcspi"; + reg = <0x480b8000 0x100>; + interrupts = <91>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi3"; @@ -275,6 +308,8 @@ mcspi4: spi@480ba000 { compatible = "ti,omap2-mcspi"; + reg = <0x480ba000 0x100>; + interrupts = <48>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi4"; @@ -283,8 +318,17 @@ dma-names = "tx0", "rx0"; }; + hdqw1w: 1w@480b2000 { + compatible = "ti,omap3-1w"; + reg = <0x480b2000 0x1000>; + interrupts = <58>; + ti,hwmods = "hdq1w"; + }; + mmc1: mmc@4809c000 { compatible = "ti,omap3-hsmmc"; + reg = <0x4809c000 0x200>; + interrupts = <83>; ti,hwmods = "mmc1"; ti,dual-volt; dmas = <&sdma 61>, <&sdma 62>; @@ -293,6 +337,8 @@ mmc2: mmc@480b4000 { compatible = "ti,omap3-hsmmc"; + reg = <0x480b4000 0x200>; + interrupts = <86>; ti,hwmods = "mmc2"; dmas = <&sdma 47>, <&sdma 48>; dma-names = "tx", "rx"; @@ -300,6 +346,8 @@ mmc3: mmc@480ad000 { compatible = "ti,omap3-hsmmc"; + reg = <0x480ad000 0x200>; + interrupts = <94>; ti,hwmods = "mmc3"; dmas = <&sdma 77>, <&sdma 78>; dma-names = "tx", "rx"; @@ -307,6 +355,7 @@ wdt2: wdt@48314000 { compatible = "ti,omap3-wdt"; + reg = <0x48314000 0x80>; ti,hwmods = "wd_timer2"; }; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index f8b3765eb9be..380c22eb468e 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -31,6 +31,10 @@ ocp { uart4: serial@49042000 { compatible = "ti,omap3-uart"; + reg = <0x49042000 0x400>; + interrupts = <80>; + dmas = <&sdma 81 &sdma 82>; + dma-names = "tx", "rx"; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; -- cgit v1.2.3 From c351e29018eeb2fa3151e09a9102e223519c34d5 Mon Sep 17 00:00:00 2001 From: Mark Jackson Date: Fri, 4 Oct 2013 09:15:01 +0100 Subject: ARM: dts: Add support for Newflow NanoBone board NanoBone Specification: ----------------------- CPU: TI AM335x Memory: 256MB DDR3 128MB NOR flash 128KB FRAM Ethernet: 2 x 10/100 connected to SMSC LAN8710 PHY USB: 1 x USB2.0 Type A I2C: 2Kbit EEPROM (Microchip 24AA02) RTC (Maxim DS1338) GPIO Expander (Microchip MCP23017) Expansion connector: 6 x UART 1 x MMC/SD 1 x USB2.0 Signed-off-by: Mark Jackson Reviewed-by: Javier Martinez Canillas Signed-off-by: Benoit Cousson --- MAINTAINERS | 6 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am335x-nano.dts | 431 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 438 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-nano.dts (limited to 'arch/arm/boot/dts') diff --git a/MAINTAINERS b/MAINTAINERS index 8a0cbf3cf2c8..ba09af9391a0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6088,6 +6088,12 @@ L: linux-omap@vger.kernel.org S: Maintained F: drivers/gpio/gpio-omap.c +OMAP/NEWFLOW NANOBONE MACHINE SUPPORT +M: Mark Jackson +L: linux-omap@vger.kernel.org +S: Maintained +F: arch/arm/boot/dts/am335x-nano.dts + OMFS FILESYSTEM M: Bob Copeland L: linux-karma-devel@lists.sourceforge.net diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9df7d2c15e7d..37c6ec974134 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -188,6 +188,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ am335x-evmsk.dtb \ am335x-bone.dtb \ am335x-boneblack.dtb \ + am335x-nano.dtb \ am335x-base0033.dtb \ am3517-evm.dtb \ am3517_mt_ventoux.dtb \ diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts new file mode 100644 index 000000000000..9907b494b99c --- /dev/null +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -0,0 +1,431 @@ +/* + * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "Newflow AM335x NanoBone"; + compatible = "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + leds { + compatible = "gpio-leds"; + + led@0 { + label = "nanobone:green:usr1"; + gpios = <&gpio1 5 0>; + default-state = "off"; + }; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&misc_pins>; + + misc_pins: misc_pins { + pinctrl-single,pins = < + 0x15c (PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */ + >; + }; + + gpmc_pins: gpmc_pins { + pinctrl-single,pins = < + 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x20 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */ + 0x24 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */ + 0x28 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */ + 0x2c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */ + 0x30 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */ + 0x34 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */ + 0x38 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */ + 0x3c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */ + + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x80 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */ + 0x84 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */ + 0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */ + + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */ + + 0xa4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */ + 0xa8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */ + 0xac (PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */ + 0xb0 (PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */ + 0xb4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */ + 0xb8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */ + 0xbc (PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */ + + 0xe0 (PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */ + 0xe4 (PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */ + 0xe8 (PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */ + >; + }; + + i2c0_pins: i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart1_pins: uart1_pins { + pinctrl-single,pins = < + 0x178 (PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */ + 0x17c (PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */ + 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ + 0x184 (PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */ + >; + }; + + uart2_pins: uart2_pins { + pinctrl-single,pins = < + 0xc0 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */ + 0xc4 (PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */ + 0x150 (PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */ + 0x154 (PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */ + >; + }; + + uart3_pins: uart3_pins { + pinctrl-single,pins = < + 0xc8 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */ + 0xcc (PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */ + 0x160 (PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */ + 0x164 (PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ + >; + }; + + uart4_pins: uart4_pins { + pinctrl-single,pins = < + 0xd0 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */ + 0xd4 (PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */ + 0x168 (PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */ + 0x16c (PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */ + >; + }; + + uart5_pins: uart5_pins { + pinctrl-single,pins = < + 0xd8 (PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */ + 0x144 (PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */ + >; + }; + + mmc1_pins: mmc1_pins { + pinctrl-single,pins = < + 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + 0x1e8 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */ + 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; + rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rx-during-tx; + rs485-rts-delay = <1 1>; + linux,rs485-enabled-at-boot-time; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; + rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rts-delay = <1 1>; + linux,rs485-enabled-at-boot-time; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + gpio@20 { + compatible = "mcp,mcp23017"; + reg = <0x20>; + }; + + tps: tps@24 { + reg = <0x24>; + }; + + eeprom@53 { + compatible = "mcp,24c02"; + reg = <0x53>; + pagesize = <8>; + }; + + rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + status = "okay"; + gpmc,num-waitpins = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&gpmc_pins>; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x08000000>; /* CS0: NOR 128M */ + + nor@0,0 { + reg = <0 0x00000000 0x08000000>; + compatible = "cfi-flash"; + linux,mtd-name = "spansion,s29gl010p11t"; + bank-width = <2>; + + gpmc,mux-add-data = <2>; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <160>; + gpmc,cs-wr-off-ns = <160>; + gpmc,adv-on-ns = <10>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; + gpmc,oe-on-ns = <40>; + gpmc,oe-off-ns = <160>; + gpmc,we-on-ns = <40>; + gpmc,we-off-ns = <160>; + gpmc,rd-cycle-ns = <160>; + gpmc,wr-cycle-ns = <160>; + gpmc,access-ns = <150>; + gpmc,page-burst-access-ns = <10>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-delay-ns = <20>; + gpmc,wr-data-mux-bus-ns = <70>; + gpmc,wr-access-ns = <80>; + + #address-cells = <1>; + #size-cells = <1>; + + /* + MTD partition table + =================== + +------------+-->0x00000000-> U-Boot start + | | + | |-->0x000BFFFF-> U-Boot end + | |-->0x000C0000-> ENV1 start + | | + | |-->0x000DFFFF-> ENV1 end + | |-->0x000E0000-> ENV2 start + | | + | |-->0x000FFFFF-> ENV2 end + | |-->0x00100000-> Kernel start + | | + | |-->0x004FFFFF-> Kernel end + | |-->0x00500000-> File system start + | | + | |-->0x014FFFFF-> File system end + | |-->0x01500000-> User data start + | | + | |-->0x03FFFFFF-> User data end + | |-->0x04000000-> Data storage start + | | + +------------+-->0x08000000-> NOR end (Free end) + */ + partition@0 { + label = "boot"; + reg = <0x00000000 0x000c0000>; /* 768KB */ + }; + + partition@1 { + label = "env1"; + reg = <0x000c0000 0x00020000>; /* 128KB */ + }; + + partition@2 { + label = "env2"; + reg = <0x000e0000 0x00020000>; /* 128KB */ + }; + + partition@3 { + label = "kernel"; + reg = <0x00100000 0x00400000>; /* 4MB */ + }; + + partition@4 { + label = "rootfs"; + reg = <0x00500000 0x01000000>; /* 16MB */ + }; + + partition@5 { + label = "user"; + reg = <0x01500000 0x02b00000>; /* 43MB */ + }; + + partition@6 { + label = "data"; + reg = <0x04000000 0x04000000>; /* 64MB */ + }; + }; +}; + +&mac { + dual_emac = <1>; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + dual_emac_res_vlan = <2>; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&ldo4_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + bus-width = <4>; + cd-gpios = <&gpio3 8 0>; + wp-gpios = <&gpio3 18 0>; +}; + +#include "tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + /* +1.5V voltage with ±4% tolerance */ + regulator-min-microvolt = <1450000>; + regulator-max-microvolt = <1550000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <915000>; + regulator-max-microvolt = <1140000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <915000>; + regulator-max-microvolt = <1140000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + /* +1.8V voltage with ±4% tolerance */ + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1870000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + /* +3.3V voltage with ±4% tolerance */ + regulator-min-microvolt = <3175000>; + regulator-max-microvolt = <3430000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + /* +1.8V voltage with ±4% tolerance */ + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1870000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + /* +3.3V voltage with ±4% tolerance */ + regulator-min-microvolt = <3175000>; + regulator-max-microvolt = <3430000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; -- cgit v1.2.3 From e7243b7673a20ac28cfdc78c8862587ea8173a39 Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Mon, 14 Oct 2013 14:49:21 +0200 Subject: ARM: dts: am33xx, change usb ctrl module label Control module is not usb specific. Changes the label to usb_ctrl_mod. Signed-off-by: Markus Pargmann Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 97f501951564..0ca13ad92fa6 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -416,7 +416,7 @@ ti,hwmods = "usb_otg_hs"; status = "disabled"; - ctrl_mod: control@44e10000 { + usb_ctrl_mod: control@44e10000 { compatible = "ti,am335x-usb-ctrl-module"; reg = <0x44e10620 0x10 0x44e10648 0x4>; @@ -429,7 +429,7 @@ reg = <0x47401300 0x100>; reg-names = "phy"; status = "disabled"; - ti,ctrl_mod = <&ctrl_mod>; + ti,ctrl_mod = <&usb_ctrl_mod>; }; usb0: usb@47401000 { @@ -477,7 +477,7 @@ reg = <0x47401b00 0x100>; reg-names = "phy"; status = "disabled"; - ti,ctrl_mod = <&ctrl_mod>; + ti,ctrl_mod = <&usb_ctrl_mod>; }; usb1: usb@47401800 { -- cgit v1.2.3 From 05bc85d1b52d8a9cc0faa7692747dcee05dd8bc9 Mon Sep 17 00:00:00 2001 From: Eric Witcher Date: Fri, 18 Oct 2013 02:42:34 -0400 Subject: ARM: dts: omap5-uevm: fix mcspi node pin descriptions Correct mcspi pin descriptions to match corresponding node name and add chip select number to be consistent with OMAP5 TRM. Signed-off-by: Eric Witcher Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-uevm.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index e06a04a63664..8d8030569378 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -131,25 +131,25 @@ 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ - 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs */ + 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ >; }; mcspi3_pins: pinmux_mcspi3_pins { pinctrl-single,pins = < - 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ - 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ - 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ - 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ + 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ + 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ + 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi3_simo */ + 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ >; }; mcspi4_pins: pinmux_mcspi4_pins { pinctrl-single,pins = < - 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ - 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ - 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ - 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ + 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi4_clk */ + 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi4_simo */ + 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi4_somi */ + 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi4_cs0 */ >; }; -- cgit v1.2.3 From b8981d71b59a42af614c231b3e3df4858c18a75e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 16 Oct 2013 10:39:04 -0500 Subject: ARM: dts: omap5-uevm: add smps123 supply for CPU regulator smps123 supply from Palmas PMIC powers CPU0 on OMAP5uEVM. Based on a patch by J Keerthy Signed-off-by: Nishanth Menon Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-uevm.dts | 4 ++++ arch/arm/boot/dts/omap5.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 8d8030569378..22d9b51dbd16 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -501,3 +501,7 @@ pinctrl-names = "default"; pinctrl-0 = <&uart5_pins>; }; + +&cpu0 { + cpu0-supply = <&smps123_reg>; +}; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 2cb72ba1dd05..b3158738991a 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -38,7 +38,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; -- cgit v1.2.3 From 22f1e7ef814d2ceace28a36edb4febbd0daab7d1 Mon Sep 17 00:00:00 2001 From: J Keerthy Date: Wed, 16 Oct 2013 10:39:05 -0500 Subject: ARM: dts: dra7-evm: add smps123 supply for CPU regulator smps123 supply from Palmas PMIC powers CPU0 on DRA7 EVM. [nm@ti.com: rebase to latest] Signed-off-by: Nishanth Menon Signed-off-by: J Keerthy Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/dra7-evm.dts | 4 ++++ arch/arm/boot/dts/dra7.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 3abf5f41e5cc..5babba0a3a75 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -269,3 +269,7 @@ vmmc-supply = <&mmc2_3v3>; bus-width = <8>; }; + +&cpu0 { + cpu0-supply = <&smps123_reg>; +}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 98ff6553edbc..c4fb401a086a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -37,7 +37,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; -- cgit v1.2.3 From 6c24894d9f1319fd23644e1c9f9b2b675fc20b1a Mon Sep 17 00:00:00 2001 From: J Keerthy Date: Wed, 16 Oct 2013 10:39:06 -0500 Subject: ARM: dts: OMAP5: Add CPU OPP table Add DT OPP table for OMAP54xx family of devices. This data is decoded by OF with of_init_opp_table() helper function. The data is based on OMAP543x ES2.0 DM Operating Condition Addendum Version 0.6(April 2013) NOTE: The voltage and frequency values work well only on NOM samples and are supposed to work properly only with ABB/AVS for ALL OPPs. TODO: Add SPEED BIN OPP after ABB and AVS support so the cpufreq works on all samples seamlessly. Clock node is pending alignment for clock dts conversion [nm@ti.com: sync to latest and fixes] Signed-off-by: Nishanth Menon Signed-off-by: J Keerthy Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index b3158738991a..154d92fae1d5 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -42,6 +42,13 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; + + operating-points = < + /* kHz uV */ + 500000 880000 + 1000000 1060000 + 1500000 1250000 + >; }; cpu@1 { device_type = "cpu"; -- cgit v1.2.3 From 620c516898f105a838c4f3bdd14742068d60e437 Mon Sep 17 00:00:00 2001 From: J Keerthy Date: Wed, 16 Oct 2013 10:39:07 -0500 Subject: ARM: dts: DRA7: Add CPU OPP table Add DT OPP table for DRA7xx family of devices. This data is decoded by OF with of_init_opp_table() helper function. The data is based on DRA75x, DRA74x Data Manual revision F (Sept 2013). TODO: add OPP_HIGH after AVS-Class0 is functional NOTE: The voltage and frequency values work well only on NOM samples and it is mandatory to use ABB/AVS Class 0 support for all OPPs. Clock nodes are pending clock node alignment. [nm@ti.com: cleanups and rebase to latest] Signed-off-by: Nishanth Menon Signed-off-by: J Keerthy Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/dra7.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c4fb401a086a..d0df4c4e8b0a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -41,6 +41,12 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1176000 1160000 + >; }; cpu@1 { device_type = "cpu"; -- cgit v1.2.3 From ac888a8895b1b4c4aa6c7df70ecc0056b1e96787 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:30 +0200 Subject: ARM: dts: omap3-n900: Add pinctrl for i2c devices Add pin muxing support for the Nokia N900 i2c controllers. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-n900.dts | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index e13b697f8bce..ad4edd95b5b1 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -28,7 +28,35 @@ }; +&omap3_pmx_core { + pinctrl-names = "default"; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x18a (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + 0x18e (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + 0x190 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + 0x192 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + 0x194 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; +}; + &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <2200000>; twl: twl@48 { @@ -39,6 +67,7 @@ }; #include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" &twl_gpio { ti,pullups = <0x0>; @@ -46,10 +75,16 @@ }; &i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; }; &i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; }; -- cgit v1.2.3 From 48fc98645062b459a8d136483ee7ebbc2087185f Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:31 +0200 Subject: ARM: dts: omap3-n900: Fix i2c bus speed Fix the bus speed of i2c bus 2 and 3. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-n900.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index ad4edd95b5b1..7dd6fb6488e0 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -78,14 +78,14 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; + clock-frequency = <100000>; }; &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; - clock-frequency = <100000>; + clock-frequency = <400000>; }; &mmc1 { -- cgit v1.2.3 From 7a89eecfdf745bcc3d39cbd5088ad821c4fc62c4 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:32 +0200 Subject: ARM: dts: omap3-n900: Add UART support Add UART support to Nokia N900. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-n900.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 7dd6fb6488e0..92262680cb85 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -31,6 +31,20 @@ &omap3_pmx_core { pinctrl-names = "default"; + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx */ + 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx */ + >; + }; + i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < 0x18a (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ @@ -127,3 +141,17 @@ mode = <2>; power = <50>; }; + +&uart1 { + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; -- cgit v1.2.3 From f1751cff82b8e568fb2197f1f74dbf59aa86f9b0 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:33 +0200 Subject: ARM: dts: omap3-n900: Add support for SD cards Add support for external SD card slot. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-n900.dts | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 92262680cb85..01a437edf93c 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -65,6 +65,17 @@ 0x194 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ + 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */ + 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ + 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ + 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ + >; + }; }; &i2c1 { @@ -103,7 +114,11 @@ }; &mmc1 { - status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + bus-width = <4>; + cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */ }; &mmc2 { -- cgit v1.2.3 From 3931c839e8886b47e37969b85edc8db25a48dc5a Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:34 +0200 Subject: ARM: dts: omap3-n900: GPIO key definitions Add device tree node for the GPIO keys provided by the N900 board. This is a simple conversion of the existing board code. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-n900.dts | 48 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 01a437edf93c..5082cb6ab160 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -26,6 +26,54 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; + gpio_keys { + compatible = "gpio-keys"; + + camera_lens_cover { + label = "Camera Lens Cover"; + gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x09>; /* SW_CAMERA_LENS_COVER */ + gpio-key,wakeup; + }; + + camera_focus { + label = "Camera Focus"; + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */ + linux,code = <0x210>; /* KEY_CAMERA_FOCUS */ + gpio-key,wakeup; + }; + + camera_capture { + label = "Camera Capture"; + gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */ + linux,code = <0xd4>; /* KEY_CAMERA */ + gpio-key,wakeup; + }; + + lock_button { + label = "Lock Button"; + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */ + linux,code = <0x98>; /* KEY_SCREENLOCK */ + gpio-key,wakeup; + }; + + keypad_slide { + label = "Keypad Slide"; + gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0a>; /* SW_KEYPAD_SLIDE */ + gpio-key,wakeup; + }; + + proximity_sensor { + label = "Proximity Sensor"; + gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0b>; /* SW_FRONT_PROXIMITY */ + }; + }; + }; &omap3_pmx_core { -- cgit v1.2.3 From 06ba7a61331c1e5fc908c3acf06006da73d32ed4 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:35 +0200 Subject: ARM: dts: omap3-n900: Add vibrator device Add support for Nokia N900's vibrator. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-n900.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 5082cb6ab160..a02f64f65fae 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -142,6 +142,13 @@ #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" +&twl { + twl_audio: audio { + compatible = "ti,twl4030-audio"; + ti,enable-vibra = <1>; + }; +}; + &twl_gpio { ti,pullups = <0x0>; ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ -- cgit v1.2.3 From b2b9b258042f23fcfeb4f4b8878aa58664168f26 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:36 +0200 Subject: ARM: dts: omap3-n900: Add LP5523 support Add support for LP5523 device. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-n900.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index a02f64f65fae..c7e0d2d668ba 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -159,6 +159,11 @@ pinctrl-0 = <&i2c2_pins>; clock-frequency = <100000>; + + bq27200: bq27200@55 { + compatible = "ti,bq27200"; + reg = <0x55>; + }; }; &i2c3 { -- cgit v1.2.3 From b86684d70f1e45cae4a85686e6f78d5db341fa85 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:37 +0200 Subject: ARM: dts: TWL4030: Add missing regulators The twl4030.dtsi is missing some regulators. This patch adds the missing ones and orders the regulators alphabetically. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/twl4030.dtsi | 44 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index ae6a17aed9ee..cb5afcdb5d35 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi @@ -23,6 +23,22 @@ compatible = "ti,twl4030-wdt"; }; + vaux1: regulator-vaux1 { + compatible = "ti,twl4030-vaux1"; + }; + + vaux2: regulator-vaux2 { + compatible = "ti,twl4030-vaux2"; + }; + + vaux3: regulator-vaux3 { + compatible = "ti,twl4030-vaux3"; + }; + + vaux4: regulator-vaux4 { + compatible = "ti,twl4030-vaux4"; + }; + vcc: regulator-vdd1 { compatible = "ti,twl4030-vdd1"; regulator-min-microvolt = <600000>; @@ -35,10 +51,20 @@ regulator-max-microvolt = <1800000>; }; - vpll2: regulator-vpll2 { - compatible = "ti,twl4030-vpll2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + vio: regulator-vio { + compatible = "ti,twl4030-vio"; + }; + + vintana1: regulator-vintana1 { + compatible = "ti,twl4030-vintana1"; + }; + + vintana2: regulator-vintana2 { + compatible = "ti,twl4030-vintana2"; + }; + + vintdig: regulator-vintdig { + compatible = "ti,twl4030-vintdig"; }; vmmc1: regulator-vmmc1 { @@ -65,6 +91,16 @@ compatible = "ti,twl4030-vusb3v1"; }; + vpll1: regulator-vpll1 { + compatible = "ti,twl4030-vpll1"; + }; + + vpll2: regulator-vpll2 { + compatible = "ti,twl4030-vpll2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vsim: regulator-vsim { compatible = "ti,twl4030-vsim"; regulator-min-microvolt = <1800000>; -- cgit v1.2.3 From 9cdbbadd11643778f9a6b5df9aa05e365daf9ad1 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:38 +0200 Subject: ARM: dts: omap3-n900: Specify regulator info Add regulator names and voltage information to the Nokia N900 DTS file. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-n900.dts | 84 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index c7e0d2d668ba..0a45af3ec97e 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -142,6 +142,90 @@ #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" +&vaux1 { + regulator-name = "V28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; /* due battery cover sensor */ +}; + +&vaux2 { + regulator-name = "VCSI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&vaux3 { + regulator-name = "VMMC2_30"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; +}; + +&vaux4 { + regulator-name = "VCAM_ANA_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&vmmc1 { + regulator-name = "VMMC1"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <3150000>; +}; + +&vmmc2 { + regulator-name = "V28_A"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; /* due VIO leak to AIC34 VDDs */ +}; + +&vpll1 { + regulator-name = "VPLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&vpll2 { + regulator-name = "VSDI_CSI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&vsim { + regulator-name = "VMMC2_IO_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&vio { + regulator-name = "VIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + +}; + +&vintana1 { + regulator-name = "VINTANA1"; + /* fixed to 1500000 */ + regulator-always-on; +}; + +&vintana2 { + regulator-name = "VINTANA2"; + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + regulator-always-on; +}; + +&vintdig { + regulator-name = "VINTDIG"; + /* fixed to 1500000 */ + regulator-always-on; +}; + &twl { twl_audio: audio { compatible = "ti,twl4030-audio"; -- cgit v1.2.3 From 8699d2dd21807bd8c8a6315060146b877675b58c Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:39 +0200 Subject: ARM: dts: omap3-n900: Add NAND support This patch adds supports for Nokia N900 NAND memory. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-n900.dts | 72 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 0a45af3ec97e..999a80c7a4c9 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -273,6 +273,78 @@ status = "disabled"; }; +&gpmc { + ranges = <0 0 0x04000000 0x10000000>; /* 256MB */ + + /* gpio-irq for dma: 65 */ + + onenand@0,0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x10000000>; + + gpmc,sync-read; + gpmc,sync-write; + gpmc,burst-length = <16>; + gpmc,burst-read; + gpmc,burst-wrap; + gpmc,burst-write; + gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ + gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <87>; + gpmc,cs-wr-off-ns = <87>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <10>; + gpmc,adv-wr-off-ns = <10>; + gpmc,oe-on-ns = <15>; + gpmc,oe-off-ns = <87>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <87>; + gpmc,rd-cycle-ns = <112>; + gpmc,wr-cycle-ns = <112>; + gpmc,access-ns = <81>; + gpmc,page-burst-access-ns = <15>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <5>; + gpmc,wr-data-mux-bus-ns = <30>; + gpmc,wr-access-ns = <81>; + gpmc,sync-clk-ps = <15000>; + + /* + * MTD partition table corresponding to Nokia's + * Maemo 5 (Fremantle) release. + */ + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x00020000>; + read-only; + }; + partition@1 { + label = "config"; + reg = <0x00020000 0x00060000>; + }; + partition@2 { + label = "log"; + reg = <0x00080000 0x00040000>; + }; + partition@3 { + label = "kernel"; + reg = <0x000c0000 0x00200000>; + }; + partition@4 { + label = "initfs"; + reg = <0x002c0000 0x00200000>; + }; + partition@5 { + label = "rootfs"; + reg = <0x004c0000 0x0fb40000>; + }; + }; +}; + &mcspi1 { /* * For some reason, touchscreen is necessary for screen to work at -- cgit v1.2.3 From d1e6f51646f2bed16826fd8e4fc1b5f4188d086e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:40 +0200 Subject: ARM: dts: omap3-n900:: Mux RX51_LCD_RESET_GPIO in DTS Add RX51_LCD_RESET_GPIO pin mux information to display. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-n900.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 999a80c7a4c9..5afbd2872e2f 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -124,6 +124,12 @@ 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ >; }; + + display_pins: pinmux_display_pins { + pinctrl-single,pins = < + 0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ + >; + }; }; &i2c1 { @@ -361,6 +367,9 @@ compatible = "acx565akm"; spi-max-frequency = <6000000>; reg = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&display_pins>; }; }; -- cgit v1.2.3 From 14e3e295b2b97724e0a9cb3b1ae7e693472769f8 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:41 +0200 Subject: ARM: dts: omap3-n900: Add TLV320AIC3X support This patch adds support for Nokia N900 TLV320AIC3X chips. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-n900.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 5afbd2872e2f..98797e521c58 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -250,6 +250,32 @@ clock-frequency = <100000>; + tlv320aic3x: tlv320aic3x@18 { + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */ + ai3x-gpio-func = < + 0 /* AIC3X_GPIO1_FUNC_DISABLED */ + 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ + >; + + AVDD-supply = <&vmmc2>; + DRVDD-supply = <&vmmc2>; + IOVDD-supply = <&vio>; + DVDD-supply = <&vio>; + }; + + tlv320aic3x_aux: tlv320aic3x@19 { + compatible = "ti,tlv320aic3x"; + reg = <0x19>; + gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */ + + AVDD-supply = <&vmmc2>; + DRVDD-supply = <&vmmc2>; + IOVDD-supply = <&vio>; + DVDD-supply = <&vio>; + }; + bq27200: bq27200@55 { compatible = "ti,bq27200"; reg = <0x55>; -- cgit v1.2.3 From a0bf1f3e455e629d1d453e69e7a8c9ca72871c84 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:42 +0200 Subject: ARM: dts: omap3-n900: Add LP5523 support Add support for LP5523 device. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-n900.dts | 61 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 98797e521c58..c4f20bfe4cce 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -276,6 +276,67 @@ DVDD-supply = <&vio>; }; + lp5523: lp5523@32 { + compatible = "national,lp5523"; + reg = <0x32>; + clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ + enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ + + chan0 { + chan-name = "lp5523:kb1"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + }; + + chan1 { + chan-name = "lp5523:kb2"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + }; + + chan2 { + chan-name = "lp5523:kb3"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + }; + + chan3 { + chan-name = "lp5523:kb4"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + }; + + chan4 { + chan-name = "lp5523:b"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + }; + + chan5 { + chan-name = "lp5523:g"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + }; + + chan6 { + chan-name = "lp5523:r"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + }; + + chan7 { + chan-name = "lp5523:kb5"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + }; + + chan8 { + chan-name = "lp5523:kb6"; + led-cur = /bits/ 8 <50>; + max-cur = /bits/ 8 <100>; + }; + }; + bq27200: bq27200@55 { compatible = "ti,bq27200"; reg = <0x55>; -- cgit v1.2.3 From a3317d4f2fcd064071bc188cbbc2769dda73e487 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 23 Oct 2013 00:49:43 +0200 Subject: ARM: dts: TWL4030: Add power button support Enable support for the power button. Signed-off-by: Sebastian Reichel Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/twl4030.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index cb5afcdb5d35..af7fa40fd216 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi @@ -133,4 +133,9 @@ compatible = "ti,twl4030-pwmled"; #pwm-cells = <2>; }; + + twl_pwrbutton: pwrbutton { + compatible = "ti,twl4030-pwrbutton"; + interrupts = <8>; + }; }; -- cgit v1.2.3 From 472e623db8d7ddc7fe15c44f1bba8f7772aede50 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 23 Oct 2013 12:32:19 +0300 Subject: ARM: dts: omap5-uevm: Correct twl6040 reset GPIO pinmux When the omap5-evm.dts file has been renamed to omap5-uevm.dts and the sEVM support got deprecated in favor of uEVM (or Panda5) the content was not validated. On uEVM the twl6040 reset GPIO is from gpio5_141 and not via gpio5_145, which was the case in sEVM. Signed-off-by: Peter Ujfalusi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-uevm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 22d9b51dbd16..4d79c7b0cb4e 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -71,7 +71,7 @@ twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < - 0x18a (PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ + 0x17e (PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ >; }; -- cgit v1.2.3 From b306e7b819edd0515e18f5ca7e0d1cb4b0e4e58a Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 23 Oct 2013 12:32:20 +0300 Subject: ARM: dts: omap5-uevm: Remove pinmux for dmic pins When the omap5-evm.dts file has been renamed to omap5-uevm.dts and the sEVM support got deprecated in favor of uEVM (or Panda5) the content was not validated. Panda5 does not have support for digital microphones so remove the pinmux section for it. Signed-off-by: Peter Ujfalusi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-uevm.dts | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 4d79c7b0cb4e..002fa70180a5 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -62,7 +62,6 @@ pinctrl-0 = < &twl6040_pins &mcpdm_pins - &dmic_pins &mcbsp1_pins &mcbsp2_pins &usbhost_pins @@ -85,15 +84,6 @@ >; }; - dmic_pins: pinmux_dmic_pins { - pinctrl-single,pins = < - 0x144 (PIN_INPUT | MUX_MODE0) /* abedmic_din1.abedmic_din1 */ - 0x146 (PIN_INPUT | MUX_MODE0) /* abedmic_din2.abedmic_din2 */ - 0x148 (PIN_INPUT | MUX_MODE0) /* abedmic_din3.abedmic_din3 */ - 0x14a (PIN_OUTPUT | MUX_MODE0) /* abedmic_clk1.abedmic_clk1 */ - >; - }; - mcbsp1_pins: pinmux_mcbsp1_pins { pinctrl-single,pins = < 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ -- cgit v1.2.3 From 4675cf577e4bbe179df1cf10a6fab8854333d99d Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 18 Oct 2013 20:02:30 -0300 Subject: ARM: mvebu: Add a 2 GHz fixed-clock Armada 370/XP Armada 370/XP SoCs have a 2 GHz fixed PLL that is used to feed other clocks. This commit adds a DT representation of this clock through a fixed-clock compatible node. Reviewed-by: Gregory CLEMENT Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 534e1be80df2..13efe05a8c9f 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -251,4 +251,13 @@ }; }; + + clocks { + /* 2 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + }; }; -- cgit v1.2.3 From f039dfb51b36a2d7e4ac25e65ffbd03e3ac77a0c Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 18 Oct 2013 20:02:31 -0300 Subject: ARM: mvebu: Add the core-divider clock to Armada 370/XP The Armada 370/XP SoC has a clock provider called "Core Divider", that is derived from a fixed 2 GHz PLL clock. Reviewed-by: Gregory CLEMENT Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 13efe05a8c9f..00d6a798c705 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -138,6 +138,14 @@ status = "disabled"; }; + coredivclk: corediv-clock@18740 { + compatible = "marvell,armada-370-corediv-clock"; + reg = <0x18740 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + timer@20300 { reg = <0x20300 0x30>, <0x21040 0x30>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>; -- cgit v1.2.3 From 5fadea22860d315330b51aa16569e05e4f1c610b Mon Sep 17 00:00:00 2001 From: Ye He Date: Sun, 22 Sep 2013 17:00:51 +0800 Subject: ARM: dts: sirf: add missed memcontrol-monitor node in prima2 and atlas6 dts memcontrol-monitor provides the ability of monitoring the memory bandwidth. Signed-off-by: Ye He Signed-off-by: Barry Song Signed-off-by: Olof Johansson --- arch/arm/boot/dts/atlas6.dtsi | 9 ++++++++- arch/arm/boot/dts/prima2.dtsi | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 6db4f81d4795..e53dc6d4eb26 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -75,10 +75,17 @@ memory-controller@90000000 { compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x10000>; + reg = <0x90000000 0x2000>; interrupts = <27>; clocks = <&clks 5>; }; + + memc-monitor { + compatible = "sirf,prima2-memcmon"; + reg = <0x90002000 0x200>; + interrupts = <4>; + clocks = <&clks 32>; + }; }; disp-iobg { diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 27ed9f5144bc..34e29b80f97f 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -86,10 +86,17 @@ memory-controller@90000000 { compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x10000>; + reg = <0x90000000 0x2000>; interrupts = <27>; clocks = <&clks 5>; }; + + memc-monitor { + compatible = "sirf,prima2-memcmon"; + reg = <0x90002000 0x200>; + interrupts = <4>; + clocks = <&clks 32>; + }; }; disp-iobg { -- cgit v1.2.3 From 0671840cce0cccc99d6a8b7ec8d6130589a875ac Mon Sep 17 00:00:00 2001 From: Barry Song Date: Sun, 22 Sep 2013 18:21:03 +0800 Subject: ARM: dts: sirf: add missed chhifbg node in prima2 and atlas6 dts CPHIF(Cell phone interface) is behind sys bridge, this patch adds the missed node. Signed-off-by: Barry Song Signed-off-by: Olof Johansson --- arch/arm/boot/dts/atlas6.dtsi | 5 +++++ arch/arm/boot/dts/prima2.dtsi | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index e53dc6d4eb26..22a5fa6fdedf 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -65,6 +65,11 @@ compatible = "sirf,prima2-rsc"; reg = <0x88020000 0x1000>; }; + + cphifbg@88030000 { + compatible = "sirf,prima2-cphifbg"; + reg = <0x88030000 0x1000>; + }; }; mem-iobg { diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 34e29b80f97f..030943085ca8 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -76,6 +76,11 @@ compatible = "sirf,prima2-rsc"; reg = <0x88020000 0x1000>; }; + + cphifbg@88030000 { + compatible = "sirf,prima2-cphifbg"; + reg = <0x88030000 0x1000>; + }; }; mem-iobg { -- cgit v1.2.3 From 304ec42fe9764e32a258125877b418e3f3d67b0a Mon Sep 17 00:00:00 2001 From: Jiansong Chen Date: Thu, 5 Sep 2013 18:33:17 +0800 Subject: ARM: dts: sirf: add missed graphics2d iobg in atlas6 dts there is a bus bridge for graphics 2D module lost in current dts, this patch takes it back. Signed-off-by: Jiansong Chen Signed-off-by: Barry Song Signed-off-by: Olof Johansson --- arch/arm/boot/dts/atlas6.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 22a5fa6fdedf..98e7afbd47bd 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -132,6 +132,20 @@ }; }; + graphics2d-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xa0000000 0xa0000000 0x8000000>; + + ble@a0000000 { + compatible = "sirf,atlas6-ble"; + reg = <0xa0000000 0x2000>; + interrupts = <5>; + clocks = <&clks 33>; + }; + }; + dsp-iobg { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From 6f4251158a6a748a50ba2f3c9928090fd497d1cf Mon Sep 17 00:00:00 2001 From: Barry Song Date: Mon, 23 Sep 2013 23:29:56 +0800 Subject: ARM: dts: sirf: add missed cell, cs and dma channel for SPI nodes here we need to add missed cell, cs and dma channels prop in SPI nodes to match with drivers. Signed-off-by: Barry Song Signed-off-by: Olof Johansson --- arch/arm/boot/dts/atlas6.dtsi | 5 +++++ arch/arm/boot/dts/prima2.dtsi | 12 ++++++++++++ 2 files changed, 17 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 98e7afbd47bd..a49032c6e199 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -297,6 +297,11 @@ compatible = "sirf,prima2-spi"; reg = <0xb0170000 0x10000>; interrupts = <16>; + sirf,spi-num-chipselects = <1>; + sirf,spi-dma-rx-channel = <12>; + sirf,spi-dma-tx-channel = <13>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&clks 20>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 030943085ca8..afe309f6e854 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -299,7 +299,13 @@ compatible = "sirf,prima2-spi"; reg = <0xb00d0000 0x10000>; interrupts = <15>; + sirf,spi-num-chipselects = <1>; + sirf,spi-dma-rx-channel = <25>; + sirf,spi-dma-tx-channel = <20>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&clks 19>; + status = "disabled"; }; spi1: spi@b0170000 { @@ -307,7 +313,13 @@ compatible = "sirf,prima2-spi"; reg = <0xb0170000 0x10000>; interrupts = <16>; + sirf,spi-num-chipselects = <1>; + sirf,spi-dma-rx-channel = <12>; + sirf,spi-dma-tx-channel = <13>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&clks 20>; + status = "disabled"; }; i2c0: i2c@b00e0000 { -- cgit v1.2.3 From 7a54a4baf0a319ccf7796f54f7848d207b84c553 Mon Sep 17 00:00:00 2001 From: Renwei Wu Date: Mon, 23 Sep 2013 23:37:42 +0800 Subject: ARM: dts: sirf: add missed address-cells and size-cells for prima2 I2C here prima2 i2c node is lacking of address-cells and size-cells. Signed-off-by: Renwei Wu Signed-off-by: Barry Song Signed-off-by: Olof Johansson --- arch/arm/boot/dts/prima2.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index afe309f6e854..7cf78afee7b1 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -328,6 +328,8 @@ reg = <0xb00e0000 0x10000>; interrupts = <24>; clocks = <&clks 17>; + #address-cells = <1>; + #size-cells = <0>; }; i2c1: i2c@b00f0000 { @@ -336,6 +338,8 @@ reg = <0xb00f0000 0x10000>; interrupts = <25>; clocks = <&clks 18>; + #address-cells = <1>; + #size-cells = <0>; }; tsc@b0110000 { -- cgit v1.2.3 From 331d7d6afe586477ba8804e653fd013b925bbeca Mon Sep 17 00:00:00 2001 From: Jingoo Han Date: Tue, 29 Oct 2013 15:12:34 +0900 Subject: ARM: dts: use 'status' property for PCIe nodes Set the default status for PCIe to disabled in the exynos5440.dtsi file and let the board dts files such as exynos5440-ssdk5440.dts enable the PCIe. However, keep the PCIe for SD5v1 board disabled, because there is no PCIe slot on SD5v1 board. Signed-off-by: Jingoo Han Acked-by: Kukjin Kim Signed-off-by: Olof Johansson --- arch/arm/boot/dts/exynos5440-ssdk5440.dts | 2 ++ arch/arm/boot/dts/exynos5440.dtsi | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index ede772741f81..4808a5af099b 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts @@ -68,9 +68,11 @@ pcie@290000 { reset-gpio = <&pin_ctrl 5 0>; + status = "okay"; }; pcie@2a0000 { reset-gpio = <&pin_ctrl 22 0>; + status = "okay"; }; }; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 5d6cf4965d6e..8da107088ce4 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -276,6 +276,7 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 53>; num-lanes = <4>; + status = "disabled"; }; pcie@2a0000 { @@ -296,5 +297,6 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 56>; num-lanes = <4>; + status = "disabled"; }; }; -- cgit v1.2.3 From 04c7d924eb676bd768765a598cea0f27fa1ca24b Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 10 Oct 2013 16:15:33 -0500 Subject: ARM: dts: OMAP4: Add hwspinlock node Add the hwspinlock device tree node for OMAP4 family of SoCs. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 0d8fdbad43fa..01caa89a8df1 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -253,6 +253,12 @@ clock-frequency = <48000000>; }; + hwspinlock: spinlock@4a0f6000 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x4a0f6000 0x1000>; + ti,hwmods = "spinlock"; + }; + i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; reg = <0x48070000 0x100>; -- cgit v1.2.3 From fe0e09e48cc3566b240a6b79e7e9cd54f7f48755 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 10 Oct 2013 16:15:34 -0500 Subject: ARM: dts: OMAP5: Add hwspinlock node Add the hwspinlock device tree node for OMAP5 SoCs. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 154d92fae1d5..a791846421d1 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -287,6 +287,12 @@ ti,hwmods = "i2c5"; }; + hwspinlock: spinlock@4a0f6000 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x4a0f6000 0x1000>; + ti,hwmods = "spinlock"; + }; + mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; reg = <0x48098000 0x200>; -- cgit v1.2.3 From d4cbe80db468dcfaa058f9f00a332784e5dff316 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 10 Oct 2013 16:15:35 -0500 Subject: ARM: dts: AM33XX: Add hwspinlock node Add the hwspinlock device tree node for AM33xx family of SoCs. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 0ca13ad92fa6..9ae258ebe1eb 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -288,6 +288,12 @@ status = "disabled"; }; + hwspinlock: spinlock@480ca000 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x480ca000 0x1000>; + ti,hwmods = "spinlock"; + }; + wdt2: wdt@44e35000 { compatible = "ti,omap3-wdt"; ti,hwmods = "wd_timer2"; -- cgit v1.2.3 From ed845d6b78bf32b396f7f1278eed0b87446934b1 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 29 Aug 2013 18:22:09 +0530 Subject: ARM: dts: AM33xx: Add RNG node Add the AM33xx RNG module's device tree data. Also add Documentation file describing the data for the RNG module. Signed-off-by: Lokesh Vutla Signed-off-by: Tony Lindgren --- .../devicetree/bindings/hwrng/omap_rng.txt | 22 ++++++++++++++++++++++ arch/arm/boot/dts/am33xx.dtsi | 7 +++++++ 2 files changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwrng/omap_rng.txt (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/hwrng/omap_rng.txt b/Documentation/devicetree/bindings/hwrng/omap_rng.txt new file mode 100644 index 000000000000..6a62acd86953 --- /dev/null +++ b/Documentation/devicetree/bindings/hwrng/omap_rng.txt @@ -0,0 +1,22 @@ +OMAP SoC HWRNG Module + +Required properties: + +- compatible : Should contain entries for this and backward compatible + RNG versions: + - "ti,omap2-rng" for OMAP2. + - "ti,omap4-rng" for OMAP4, OMAP5 and AM33XX. + Note that these two versions are incompatible. +- ti,hwmods: Name of the hwmod associated with the RNG module +- reg : Offset and length of the register set for the module +- interrupts : the interrupt number for the RNG module. + Only used for "ti,omap4-rng". + +Example: +/* AM335x */ +rng: rng@48310000 { + compatible = "ti,omap4-rng"; + ti,hwmods = "rng"; + reg = <0x48310000 0x2000>; + interrupts = <111>; +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 9ae258ebe1eb..fcb9c8e42ab7 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -779,5 +779,12 @@ <&edma 11>; dma-names = "tx", "rx"; }; + + rng: rng@48310000 { + compatible = "ti,omap4-rng"; + ti,hwmods = "rng"; + reg = <0x48310000 0x2000>; + interrupts = <111>; + }; }; }; -- cgit v1.2.3 From 0352bd1f04b706904b26d13f6d8792e7ff6b7eb6 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Fri, 25 Oct 2013 13:07:36 +0300 Subject: ARM: dts: omap4-panda: add DPI pinmuxing New u-boot versions no longer set the pinmuxing for Panda's DPI output, and the muxing has to be done in the .dts file. Add pinmuxing for DPI and TFP410. Without these, the DVI output on Panda does not work with recent u-boot. Signed-off-by: Tomi Valkeinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-panda-common.dtsi | 43 +++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 3e6801cecd04..298e85020e1b 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -112,6 +112,8 @@ &twl6040_pins &mcpdm_pins &mcbsp1_pins + &dss_dpi_pins + &tfp410_pins &dss_hdmi_pins &tpd12s015_pins &hsusbb1_pins @@ -143,6 +145,47 @@ >; }; + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + 0x122 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ + 0x124 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ + 0x126 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ + 0x128 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ + 0x12a (PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ + 0x12c (PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ + 0x12e (PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ + 0x130 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ + 0x132 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ + 0x134 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ + 0x136 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ + + 0x174 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ + 0x176 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ + 0x178 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ + 0x17a (PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ + 0x17c (PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ + 0x17e (PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ + 0x180 (PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ + 0x182 (PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ + 0x184 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ + 0x186 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ + 0x188 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ + 0x18a (PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ + 0x18c (PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ + 0x18e (PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ + + 0x190 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ + 0x192 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ + 0x194 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ + >; + }; + + tfp410_pins: pinmux_tfp410_pins { + pinctrl-single,pins = < + 0x144 (PIN_OUTPUT | MUX_MODE3) /* gpio_0 */ + >; + }; + dss_hdmi_pins: pinmux_dss_hdmi_pins { pinctrl-single,pins = < 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ -- cgit v1.2.3 From f24b56cbcd9d39cb2ed45b4b451f8614f9494c17 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 30 Oct 2013 17:55:09 +0100 Subject: ARM: kirkwood: add support for OpenBlocks A7 platform The OpenBlocks A7 board is designed and sold by PlatHome, and based on a Kirkwood 6283 Marvell SoC. It is quite similar to the OpenBlocks A6 already supported in the kernel, with the following main differences: - The A6 uses a RTC on I2C, while the A7 uses the internal SoC RTC. - The A6 has one Ethernet port, while the A7 has two Ethernet ports - The A6 has only one USB port, while the A7 integrates a USB hub, which provides two front-side USB port, and an internal USB port as well. - The A6 has 512 MB of RAM, while the A7 has 1 GB of RAM. - Slightly different GPIOs for some functions. Signed-off-by: Thomas Petazzoni Acked-by: Andrew Lunn Acked-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 5 +- arch/arm/boot/dts/kirkwood-openblocks_a7.dts | 223 +++++++++++++++++++++++++++ 2 files changed, 226 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/kirkwood-openblocks_a7.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5b832744a0bb..f2b1c33efbfc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -95,12 +95,13 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-ns2mini.dtb \ kirkwood-nsa310.dtb \ kirkwood-nsa310a.dtb \ + kirkwood-openblocks_a6.dtb \ + kirkwood-openblocks_a7.dtb \ kirkwood-sheevaplug.dtb \ kirkwood-sheevaplug-esata.dtb \ kirkwood-topkick.dtb \ kirkwood-ts219-6281.dtb \ - kirkwood-ts219-6282.dtb \ - kirkwood-openblocks_a6.dtb + kirkwood-ts219-6282.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ msm8960-cdp.dtb diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts new file mode 100644 index 000000000000..851fb2a60f20 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -0,0 +1,223 @@ +/* + * Device Tree file for OpenBlocks A7 board + * + * Copyright (C) 2013 Free Electrons + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Plat'Home OpenBlocksA7"; + compatible = "plathome,openblocks-a7", "marvell,kirkwood-88f6283", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + serial@12000 { + status = "ok"; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + }; + + serial@12100 { + status = "ok"; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; + }; + + sata@80000 { + nr-ports = <1>; + status = "okay"; + }; + + i2c@11100 { + status = "okay"; + pinctrl-0 = <&pmx_twsi1>; + pinctrl-names = "default"; + + s24c02: s24c02@50 { + compatible = "24c02"; + reg = <0x50>; + }; + }; + + pinctrl: pinctrl@10000 { + pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; + pinctrl-names = "default"; + + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11", "mpp15", + "mpp16"; + marvell,function = "uart0"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14", "mpp8", + "mpp9"; + marvell,function = "uart1"; + }; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_dip_switches: pmx-dip-switches { + marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47"; + marvell,function = "gpio"; + }; + + /* + * Accessible on connector J202. The MPP + * listed below are pin 1-7, pin 8 is unused, + * pin 9 is external reset input and pin 10 is + * ground. + */ + pmx_gpio_header: pmx-gpio-header { + marvell,pins = "mpp17", "mpp7", "mpp29", "mpp28", + "mpp35", "mpp34", "mpp40"; + marvell,function = "gpio"; + }; + + pmx_gpio_init: pmx-init { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + pmx_usb_oc: pmx-usb-oc { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_leds: pmx-leds { + marvell,pins = "mpp41", "mpp42", "mpp43"; + marvell,function = "gpio"; + }; + + pmx_ge1: pmx-ge1 { + marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", + "mpp24", "mpp25", "mpp26", "mpp27", + "mpp30", "mpp31", "mpp32", "mpp33"; + marvell,function = "ge1"; + }; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds>; + pinctrl-names = "default"; + + led-red { + label = "obsa7:red:stat"; + gpios = <&gpio1 9 1>; + }; + + led-green { + label = "obsa7:green:stat"; + gpios = <&gpio1 10 1>; + }; + + led-yellow { + label = "obsa7:yellow:stat"; + gpios = <&gpio1 11 1>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_gpio_init>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + label = "Init Button"; + linux,code = <116>; + gpios = <&gpio1 6 0>; + }; + }; +}; + +&nand { + chip-delay = <25>; + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x1c0000>; + }; + + partition@1c0000 { + label = "env"; + reg = <0x1c0000 0x2c0000>; + }; + + partition@480000 { + label = "test"; + reg = <0x480000 0x160000>; + }; + + partition@5e0000 { + label = "conf"; + reg = <0x5e0000 0x540000>; + }; + + partition@b20000 { + label = "linux"; + reg = <0xb20000 0x3d40000>; + }; + + partition@4860000 { + label = "user"; + reg = <0x4860000 0xb7a0000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + pinctrl-0 = <&pmx_ge1>; + pinctrl-names = "default"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; -- cgit v1.2.3 From 4cca9593266d70b741ae63618ed1657f69a9f389 Mon Sep 17 00:00:00 2001 From: Hiroshi Doyu Date: Wed, 30 Oct 2013 17:17:48 -0600 Subject: ARM: tegra: fix Tegra114 IOMMU register address The IOMMU node's reg property contains completely bogus values! Somehow, this had no practical effect, despite the fact the IOMMU driver appears to be writing to those registers. I suppose that since no HW modules is actually at that address, the writes simply had no effect. Note that I'm not CCing stable here, even though the problem exists as far back as v3.9, simply because this patch doesn't fix any observed issue, and I don't want to run the risk of suddenly writing to some registers and causing a regression. Signed-off-by: Hiroshi Doyu [swarren, wrote commit description] Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra114.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 2905145d8e59..8d42787c8ff1 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -318,9 +318,9 @@ iommu { compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; - reg = <0x7000f010 0x02c - 0x7000f1f0 0x010 - 0x7000f228 0x074>; + reg = <0x70019010 0x02c + 0x700191f0 0x010 + 0x70019228 0x074>; nvidia,#asids = <4>; dma-window = <0 0x40000000>; nvidia,swgroups = <0x18659fe>; -- cgit v1.2.3 From 45e8815fc1b7ed66729bbbc9464228ee1769b580 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Tue, 22 Oct 2013 20:56:13 +0200 Subject: ARM: mvebu: Add Netgear ReadyNAS 104 board Main hardware parts of the (Armada 370 based) NETGEAR ReadyNAS 104 are supported by mainline kernel (USB 3.0 rear ports, USB 2.0 front port, Gigabit controller and PHYs, serial port, LEDs, buttons, SATA ports, G762 fan controller) and referenced in provided .dts file. Some additonal work remains for: - Intersil ISL12057 I2C RTC and Alarm chip: working driver but needs to be splitted for submission of RTC part first; - Front LCD (Winstar 1602G): driver needs to be written - Armada NAND controller (to access onboard 128MB of NAND): support being pushed by @free-electrons people - 4 front SATA LEDs controlled via GPIO brought by NXP PCA9554: driver is available upstream. Not referenced/tested yet. but the device is usable w/o those. Signed-off-by: Arnaud Ebalard Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/armada-370-netgear-rn104.dts | 193 +++++++++++++++++++++++++ 2 files changed, 194 insertions(+) create mode 100644 arch/arm/boot/dts/armada-370-netgear-rn104.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f2b1c33efbfc..55fade67a629 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -108,6 +108,7 @@ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ armada-370-mirabox.dtb \ armada-370-netgear-rn102.dtb \ + armada-370-netgear-rn104.dtb \ armada-370-rd.dtb \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts new file mode 100644 index 000000000000..b0b32f5fbeb4 --- /dev/null +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -0,0 +1,193 @@ +/* + * Device Tree file for NETGEAR ReadyNAS 104 + * + * Copyright (C) 2013, Arnaud EBALARD + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "armada-370.dtsi" + +/ { + model = "NETGEAR ReadyNAS 104"; + compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = ; + + pcie-controller { + status = "okay"; + + /* Connected to FL1009 USB 3.0 controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to Marvell 88SE9215 SATA controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + serial@12000 { + clock-frequency = <200000000>; + status = "okay"; + }; + + pinctrl { + poweroff: poweroff { + marvell,pins = "mpp60"; + marvell,function = "gpio"; + }; + + backup_key_pin: backup-key-pin { + marvell,pins = "mpp52"; + marvell,function = "gpio"; + }; + + power_key_pin: power-key-pin { + marvell,pins = "mpp62"; + marvell,function = "gpio"; + }; + + backup_led_pin: backup-led-pin { + marvell,pins = "mpp63"; + marvell,function = "gpo"; + }; + + power_led_pin: power-led-pin { + marvell,pins = "mpp64"; + marvell,function = "gpio"; + }; + + reset_key_pin: reset-key-pin { + marvell,pins = "mpp65"; + marvell,function = "gpio"; + }; + }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + usb@50000 { + status = "okay"; + }; + + i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + clock-frequency = <100000>; + status = "okay"; + + g762: g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + }; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + g762_clk: fixedclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8192>; + }; + }; + + gpio_leds { + compatible = "gpio-leds"; + pinctrl-0 = <&backup_led_pin &power_led_pin>; + pinctrl-names = "default"; + + blue_backup_led { + label = "rn104:blue:backup"; + gpios = <&gpio1 31 0>; /* GPIO 63 Active High */ + default-state = "off"; + }; + + blue_power_led { + label = "rn104:blue:pwr"; + gpios = <&gpio2 0 1>; /* GPIO 64 Active Low */ + linux,default-trigger = "keep"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&backup_key_pin + &power_key_pin + &reset_key_pin>; + pinctrl-names = "default"; + + button@1 { + label = "Backup Button"; + linux,code = <133>; /* KEY_COPY */ + gpios = <&gpio1 20 1>; + }; + + button@2 { + label = "Power Button"; + linux,code = <116>; /* KEY_POWER */ + gpios = <&gpio1 30 0>; + }; + + button@3 { + label = "Reset Button"; + linux,code = <0x198>; /* KEY_RESTART */ + gpios = <&gpio2 1 1>; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&poweroff>; + pinctrl-names = "default"; + gpios = <&gpio1 28 1>; + }; +}; -- cgit v1.2.3 From d394c7bb660b6d595ff17a042f2b885e84dbf603 Mon Sep 17 00:00:00 2001 From: Markus Mayer Date: Tue, 10 Sep 2013 11:07:03 -0700 Subject: ARM: bcm281xx: Add device node for the GPIO controller Add the GPIO controller device node for the Broadcom bcm281xx family of mobile SoCs. Signed-off-by: Markus Mayer Reviewed-by: Tim Kryger Reviewed-by: Matt Porter Reviewed-by: Tomasz Figa Acked-by: Linus Walleij Signed-off-by: Christian Daudt Signed-off-by: Olof Johansson --- arch/arm/boot/dts/bcm11351.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 05a5aabe3b2c..77af39668090 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -68,6 +68,22 @@ clock-frequency = <32768>; }; + gpio: gpio@35003000 { + compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; + reg = <0x35003000 0x800>; + interrupts = + ; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + }; + sdio1: sdio@3f180000 { compatible = "brcm,kona-sdhci"; reg = <0x3f180000 0x10000>; -- cgit v1.2.3 From a4412050149fb314420ecec8f9b9f8b3c9515ecf Mon Sep 17 00:00:00 2001 From: Christian Daudt Date: Mon, 23 Sep 2013 10:20:36 -0700 Subject: ARM: dts: rename ARCH_BCM to ARCH_BCM_MOBILE (dt) Currently ARCH_BCM has been used for Broadcom Mobile V7 based SoCs. In order to allow other Broadcom SoCs to also use mach-bcm directory and files, this patch renames the original ARCH_BCM to ARCH_BCM_MOBILE, and uses ARCH_BCM to define any Broadcom chip residing in mach-bcm directory. Signed-off-by: Christian Daudt Signed-off-by: Olof Johansson --- arch/arm/boot/dts/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e95af3f5433b..b086aa28bd20 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -41,9 +41,9 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb -dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb -dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \ +dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \ bcm28155-ap.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ da850-evm.dtb dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ -- cgit v1.2.3 From 71469fe801082ca09f25d9b76c6bd8ab8ba02447 Mon Sep 17 00:00:00 2001 From: Markus Mayer Date: Wed, 2 Oct 2013 11:00:16 -0700 Subject: ARM: dts: bcm281xx: Add card detect GPIO Register GPIO 14 as card detect interrupt for the SD card slot. Signed-off-by: Markus Mayer Signed-off-by: Christian Daudt Signed-off-by: Olof Johansson --- arch/arm/boot/dts/bcm11351-brt.dts | 1 + arch/arm/boot/dts/bcm28155-ap.dts | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts index 9d36eb4e3c41..23cd16d736bf 100644 --- a/arch/arm/boot/dts/bcm11351-brt.dts +++ b/arch/arm/boot/dts/bcm11351-brt.dts @@ -40,6 +40,7 @@ sdio4: sdio@3f1b0000 { max-frequency = <48000000>; + cd-gpios = <&gpio 14 0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index 96ae67a2f0d3..08e47c285227 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -40,6 +40,7 @@ sdio4: sdio@3f1b0000 { max-frequency = <48000000>; + cd-gpios = <&gpio 14 0>; status = "okay"; }; }; -- cgit v1.2.3 From 84491c0fc5ecda6ae020179dd68b32d15dc14f36 Mon Sep 17 00:00:00 2001 From: Tim Kryger Date: Mon, 23 Sep 2013 10:49:57 -0700 Subject: ARM: dts: bcm: Add missing UARTs for bcm11351 (bcm281xx) This adds in three more UARTs that were not declared earlier. Signed-off-by: Tim Kryger Reviewed-by: Markus Mayer Reviewed-by: Matt Porter Signed-off-by: Christian Daudt Signed-off-by: Olof Johansson --- arch/arm/boot/dts/bcm11351.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 77af39668090..d2a89688716f 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -49,6 +49,36 @@ reg-io-width = <4>; }; + uart@3e001000 { + compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; + status = "disabled"; + reg = <0x3e001000 0x1000>; + clock-frequency = <13000000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart@3e002000 { + compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; + status = "disabled"; + reg = <0x3e002000 0x1000>; + clock-frequency = <13000000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart@3e003000 { + compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; + status = "disabled"; + reg = <0x3e003000 0x1000>; + clock-frequency = <13000000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + L2: l2-cache { compatible = "brcm,bcm11351-a2-pl310-cache"; reg = <0x3ff20000 0x1000>; -- cgit v1.2.3 From 9c0dae046caf01886608e24883d267ea60642a70 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Thu, 19 Sep 2013 13:18:26 -0400 Subject: ARM: dts: bcm11351: Use GIC/IRQ defines for sdio interrupts Trivial patch to make use of GIC/IRQ defines on the bcm11351 sdio interrupt properties. Signed-off-by: Matt Porter Signed-off-by: Christian Daudt Signed-off-by: Olof Johansson --- arch/arm/boot/dts/bcm11351.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index d2a89688716f..b0c0610d1395 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -117,28 +117,28 @@ sdio1: sdio@3f180000 { compatible = "brcm,kona-sdhci"; reg = <0x3f180000 0x10000>; - interrupts = <0x0 77 0x4>; + interrupts = ; status = "disabled"; }; sdio2: sdio@3f190000 { compatible = "brcm,kona-sdhci"; reg = <0x3f190000 0x10000>; - interrupts = <0x0 76 0x4>; + interrupts = ; status = "disabled"; }; sdio3: sdio@3f1a0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1a0000 0x10000>; - interrupts = <0x0 74 0x4>; + interrupts = ; status = "disabled"; }; sdio4: sdio@3f1b0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1b0000 0x10000>; - interrupts = <0x0 73 0x4>; + interrupts = ; status = "disabled"; }; -- cgit v1.2.3