From 949bdcc8a97c6078f21c8d4966436b117f2e4cd3 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 21 May 2018 13:08:32 -0700 Subject: ARM: dts: dra7: fix DCAN node addresses Fix the DT node addresses to match the reg property addresses, which were verified to match the TRM: http://www.ti.com/lit/pdf/sprui30 Cc: Roger Quadros Signed-off-by: Kevin Hilman Acked-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index f4ddd86f2c77..8b423eacf76b 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1895,7 +1895,7 @@ }; }; - dcan1: can@481cc000 { + dcan1: can@4ae3c000 { compatible = "ti,dra7-d_can"; ti,hwmods = "dcan1"; reg = <0x4ae3c000 0x2000>; @@ -1905,7 +1905,7 @@ status = "disabled"; }; - dcan2: can@481d0000 { + dcan2: can@48480000 { compatible = "ti,dra7-d_can"; ti,hwmods = "dcan2"; reg = <0x48480000 0x2000>; -- cgit v1.2.3 From bc1099d2b2519fa0f6c7613d8de398df8438a36b Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 8 May 2018 11:06:38 +1000 Subject: fsi/fsi-master-gpio: Add "no-gpio-delays" option This adds support for an optional device-tree property that makes the driver skip all the delays around clocking the GPIOs and set it in the device-tree of common POWER9 based OpenPower platforms. This useful on chips like the AST2500 where the GPIO block is running at a fairly low clock frequency (25Mhz typically). In this case, the delays are unnecessary and due to the low precision of the timers, actually quite harmful in terms of performance. Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Christopher Bostic Tested-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 1 + arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 1 + arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 1 + drivers/fsi/fsi-master-gpio.c | 20 ++++++++++++++++---- 4 files changed, 19 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 389f5f83bef9..0b9b37d4d6ef 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -52,6 +52,7 @@ compatible = "fsi-master-gpio", "fsi-master"; #address-cells = <2>; #size-cells = <0>; + no-gpio-delays; clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 78a511e6e482..656036106001 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -153,6 +153,7 @@ compatible = "fsi-master-gpio", "fsi-master"; #address-cells = <2>; #size-cells = <0>; + no-gpio-delays; clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index ccbf645ab84d..2c5aa90a546d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -91,6 +91,7 @@ compatible = "fsi-master-gpio", "fsi-master"; #address-cells = <2>; #size-cells = <0>; + no-gpio-delays; trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; diff --git a/drivers/fsi/fsi-master-gpio.c b/drivers/fsi/fsi-master-gpio.c index d6508bbad1fb..c82bbd35276e 100644 --- a/drivers/fsi/fsi-master-gpio.c +++ b/drivers/fsi/fsi-master-gpio.c @@ -62,6 +62,7 @@ struct fsi_master_gpio { struct gpio_desc *gpio_enable; /* FSI enable */ struct gpio_desc *gpio_mux; /* Mux control */ bool external_mode; + bool no_delays; }; #define CREATE_TRACE_POINTS @@ -79,9 +80,11 @@ static void clock_toggle(struct fsi_master_gpio *master, int count) int i; for (i = 0; i < count; i++) { - ndelay(FSI_GPIO_STD_DLY); + if (!master->no_delays) + ndelay(FSI_GPIO_STD_DLY); gpiod_set_value(master->gpio_clk, 0); - ndelay(FSI_GPIO_STD_DLY); + if (!master->no_delays) + ndelay(FSI_GPIO_STD_DLY); gpiod_set_value(master->gpio_clk, 1); } } @@ -90,10 +93,12 @@ static int sda_clock_in(struct fsi_master_gpio *master) { int in; - ndelay(FSI_GPIO_STD_DLY); + if (!master->no_delays) + ndelay(FSI_GPIO_STD_DLY); gpiod_set_value(master->gpio_clk, 0); in = gpiod_get_value(master->gpio_data); - ndelay(FSI_GPIO_STD_DLY); + if (!master->no_delays) + ndelay(FSI_GPIO_STD_DLY); gpiod_set_value(master->gpio_clk, 1); return in ? 1 : 0; } @@ -677,6 +682,13 @@ static int fsi_master_gpio_probe(struct platform_device *pdev) } master->gpio_mux = gpio; + /* + * Check if GPIO block is slow enought that no extra delays + * are necessary. This improves performance on ast2500 by + * an order of magnitude. + */ + master->no_delays = device_property_present(&pdev->dev, "no-gpio-delays"); + master->master.n_links = 1; master->master.flags = FSI_MASTER_FLAG_SWCLOCK; master->master.read = fsi_master_gpio_read; -- cgit v1.2.3 From 9f30b6b1a957b3d4cbfd97738ef2b02291aaf394 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Fri, 25 May 2018 15:42:06 +0800 Subject: ARM: dts: imx: Add basic dtsi file for imx6sll Add dtsi file for imx6sll. Signed-off-by: Bai Ping Reviewed-by: Rob Herring Acked-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-pinfunc.h | 880 ++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6sll.dtsi | 780 ++++++++++++++++++++++++++++++++ 2 files changed, 1660 insertions(+) create mode 100644 arch/arm/boot/dts/imx6sll-pinfunc.h create mode 100644 arch/arm/boot/dts/imx6sll.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sll-pinfunc.h b/arch/arm/boot/dts/imx6sll-pinfunc.h new file mode 100644 index 000000000000..b1c40dcdb42f --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-pinfunc.h @@ -0,0 +1,880 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +#ifndef __DTS_IMX6SLL_PINFUNC_H +#define __DTS_IMX6SLL_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0 +#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0 +#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0 +#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0 +#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0 +#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0 +#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0 +#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0 +#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0 +#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0 +#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0 +#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0 +#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0 +#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0 +#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0 +#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0 +#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0 +#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0 +#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0 +#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0 +#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0 +#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1 +#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1 +#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0 +#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1 +#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0 +#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0 +#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0 +#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0 +#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1 +#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0 +#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1 +#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0 +#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1 +#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0 +#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0 +#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1 +#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0 +#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1 +#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1 +#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2 +#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1 +#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1 +#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1 +#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1 +#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2 +#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1 +#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1 +#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0 +#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3 +#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2 +#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2 +#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1 +#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3 +#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2 +#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2 +#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1 +#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3 +#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3 +#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3 +#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1 +#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1 +#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4 +#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5 +#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4 +#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5 +#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1 +#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2 +#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1 +#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1 +#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0 +#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2 +#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2 +#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1 +#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4 +#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1 +#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5 +#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2 +#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3 +#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4 +#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1 +#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3 +#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1 +#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2 +#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2 +#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0 +#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1 +#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0 +#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1 +#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1 +#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2 +#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3 +#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2 +#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0 +#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1 +#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0 +#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1 +#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0 +#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0 +#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1 +#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1 +#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1 +#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0 +#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0 +#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0 +#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0 +#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1 +#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0 +#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0 +#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0 +#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1 +#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0 +#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0 +#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1 +#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0 +#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0 +#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0 +#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4 +#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0 +#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6 +#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0 +#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0 +#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0 +#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1 +#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0 +#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0 +#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5 +#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0 +#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7 +#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0 +#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0 +#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0 +#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0 +#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0 +#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0 +#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0 +#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0 +#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0 +#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0 +#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1 +#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0 +#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0 +#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0 +#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3 +#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2 +#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2 +#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3 +#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1 +#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3 +#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2 +#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0 +#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3 +#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2 +#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3 +#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2 +#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3 +#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2 +#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2 +#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2 +#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3 +#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2 +#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2 +#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2 +#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2 +#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6 +#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7 +#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4 +#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3 +#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5 +#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1 +#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1 +#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1 +#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1 +#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1 +#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1 +#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1 +#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4 +#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1 +#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5 +#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4 +#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5 +#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2 +#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3 +#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2 +#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3 +#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0 +#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0 +#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0 +#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0 +#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0 +#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0 +#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1 +#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1 +#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0 +#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2 +#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0 + +#endif /* __DTS_IMX6SLL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi new file mode 100644 index 000000000000..c9b0ccc0e2e2 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -0,0 +1,780 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +#include +#include +#include +#include "imx6sll-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6SLL_CLK_ARM>, + <&clks IMX6SLL_CLK_PLL2_PFD2>, + <&clks IMX6SLL_CLK_STEP>, + <&clks IMX6SLL_CLK_PLL1_SW>, + <&clks IMX6SLL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + }; + }; + + intc: interrupt-controller@a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + interrupt-parent = <&intc>; + }; + + ckil: clock-ckil { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock-ipp-di0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock-ipp-di1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + + tempmon: temperature-sensor { + compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; + interrupts = ; + interrupt-parent = <&gpc>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + }; + + L2: l2-cache@a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; + }; + + aips1: aips-bus@2000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba: spba-bus@2000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@2004000 { + compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = ; + dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, + <&clks IMX6SLL_CLK_OSC>, + <&clks IMX6SLL_CLK_SPDIF>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_IPG>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "dma"; + status = "disabled"; + }; + + ecspi1: spi@2008000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = ; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI1>, + <&clks IMX6SLL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: spi@200c000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = ; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI2>, + <&clks IMX6SLL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: spi@2010000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = ; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI3>, + <&clks IMX6SLL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: spi@2014000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = ; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI4>, + <&clks IMX6SLL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@2018000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02018000 0x4000>; + interrupts =; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART4_IPG>, + <&clks IMX6SLL_CLK_UART4_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@2020000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = ; + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART1_IPG>, + <&clks IMX6SLL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@2024000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02024000 0x4000>; + interrupts = ; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART2_IPG>, + <&clks IMX6SLL_CLK_UART2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi1: ssi-controller@2028000 { + compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; + reg = <0x02028000 0x4000>; + interrupts = ; + dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, + <&clks IMX6SLL_CLK_SSI1>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + ssi2: ssi-controller@202c000 { + compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; + reg = <0x0202c000 0x4000>; + interrupts = ; + dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, + <&clks IMX6SLL_CLK_SSI2>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + ssi3: ssi-controller@2030000 { + compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; + reg = <0x02030000 0x4000>; + interrupts = ; + dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, + <&clks IMX6SLL_CLK_SSI3>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + uart3: serial@2034000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02034000 0x4000>; + interrupts = ; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-name = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART3_IPG>, + <&clks IMX6SLL_CLK_UART3_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + pwm1: pwm@2080000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM1>, + <&clks IMX6SLL_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm2: pwm@2084000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM2>, + <&clks IMX6SLL_CLK_PWM2>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm3: pwm@2088000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM3>, + <&clks IMX6SLL_CLK_PWM3>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm4: pwm@208c000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM4>, + <&clks IMX6SLL_CLK_PWM4>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + gpt1: timer@2098000 { + compatible = "fsl,imx6sl-gpt"; + reg = <0x02098000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_GPT_BUS>, + <&clks IMX6SLL_CLK_GPT_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@209c000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@20a0000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@20a4000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@20a8000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@20ac000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@20b0000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020b0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + kpp: keypad@20b8000 { + compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_KPP>; + status = "disabled"; + }; + + wdog1: watchdog@20bc000 { + compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_WDOG1>; + }; + + wdog2: watchdog@20c0000 { + compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_WDOG2>; + status = "disabled"; + }; + + clks: clock-controller@20c4000 { + compatible = "fsl,imx6sll-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + + assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>; + assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>; + }; + + anatop: anatop@20c8000 { + compatible = "fsl,imx6sll-anatop", + "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x020c8000 0x4000>; + interrupts = , + , + ; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p0: regulator-3p0@20c8120 { + compatible = "fsl,anatop-regulator"; + reg = <0x20c8120>; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + }; + + usbphy1: usb-phy@20c9000 { + compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", + "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usb-phy@20ca000 { + compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", + "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBPHY2>; + phy-reg_3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@20cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = , + ; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x61>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + }; + }; + + src: reset-controller@20d8000 { + compatible = "fsl,imx6sll-src"; + reg = <0x020d8000 0x4000>; + interrupts = , + ; + #reset-cells = <1>; + }; + + gpc: interrupt-controller@20dc000 { + compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; + }; + + iomuxc: pinctrl@20e0000 { + compatible = "fsl,imx6sll-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@20e4000 { + compatible = "fsl,imx6sll-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + csi: csi@20e8000 { + compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; + reg = <0x020e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_CSI>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + sdma: dma-controller@20ec000 { + compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_SDMA>, + <&clks IMX6SLL_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + iram = <&ocram>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + + lcdif: lcd-controller@20f8000 { + compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; + reg = <0x020f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, + <&clks IMX6SLL_CLK_LCDIF_APB>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + dcp: dcp@20fc000 { + compatible = "fsl,imx28-dcp"; + reg = <0x020fc000 0x4000>; + interrupts = , + , + ; + clocks = <&clks IMX6SLL_CLK_DCP>; + clock-names = "dcp"; + }; + }; + + aips2: aips-bus@2100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@2184000 { + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbotg2: usb@2184200 { + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@2184800 { + #index-cells = <1>; + compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + }; + + usdhc1: mmc@2190000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC1>, + <&clks IMX6SLL_CLK_USDHC1>, + <&clks IMX6SLL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc2: mmc@2194000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC2>, + <&clks IMX6SLL_CLK_USDHC2>, + <&clks IMX6SLL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc3: mmc@2198000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC3>, + <&clks IMX6SLL_CLK_USDHC3>, + <&clks IMX6SLL_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + i2c1: i2c@21a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@21a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@21a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C3>; + status = "disabled"; + }; + + mmdc: memory-controller@21b0000 { + compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + ocotp: ocotp-ctrl@21bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx6sll-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SLL_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; + }; + + audmux: audmux@21d8000 { + compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + status = "disabled"; + }; + + uart5: serial@21f4000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts =; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART5_IPG>, + <&clks IMX6SLL_CLK_UART5_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; -- cgit v1.2.3 From 26bd0e5964deb4ee326689911a089889734bd409 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Fri, 25 May 2018 15:42:07 +0800 Subject: ARM: dts: imx: Add basic dts support for imx6sll EVK board Add dts file support for imx6sll EVK board. Signed-off-by: Bai Ping Reviewed-by: Rob Herring Acked-by: Dong Aisheng Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.txt | 4 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6sll-evk.dts | 315 ++++++++++++++++++++++++++ 3 files changed, 321 insertions(+) create mode 100644 arch/arm/boot/dts/imx6sll-evk.dts (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index cdb9dd705754..8a1baa2b9723 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board Required root node properties: - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; +i.MX6SLL EVK board +Required root node properties: + - compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; + Generic i.MX boards ------------------- diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..30379d342cd6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -521,6 +521,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ imx6sl-warp.dtb +dtb-$(CONFIG_SOC_IMX6SLL) += \ + imx6sll-evk.dtb dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-nitrogen6sx.dtb \ imx6sx-sabreauto.dtb \ diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts new file mode 100644 index 000000000000..4684ac4a816b --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +/dts-v1/; + +#include +#include +#include "imx6sll.dtsi" + +/ { + model = "Freescale i.MX6SLL EVK Board"; + compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; + + memory@80000000 { + reg = <0x80000000 0x80000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + reg_usb_otg1_vbus: regulator-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-otg2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_vbus>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_aud3v: regulator-aud3v { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply-3v15"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-boot-on; + }; + + reg_aud4v: regulator-aud4v { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply-4v2"; + regulator-min-microvolt = <4325000>; + regulator-max-microvolt = <4325000>; + regulator-boot-on; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd>; + regulator-name = "lcd-pwr"; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_sd1_vmmc>; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl_usb_otg1_vbus: vbus1grp { + fsl,pins = < + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 + >; + }; + + pinctrl_usb_otg2_vbus: vbus2grp { + fsl,pins = < + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 + >; + }; + + pinctrl_reg_lcd: reglcdgrp { + fsl,pins = < + MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x17059 + >; + }; + + pinctrl_reg_sd1_vmmc: sd1vmmcgrp { + fsl,pins = < + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 + >; + }; +}; -- cgit v1.2.3 From 5ebc384a15e4a315d7b50576799653e2ec5402f7 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Wed, 23 May 2018 10:30:12 +0200 Subject: ARM: dts: imx6: make edt-ft5x06 a wakeup source for imx6 boards The touchscreen driver no longer configures the device as wakeup source by default. A "wakeup-source" property is needed. Signed-off-by: Daniel Mack Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-var-dt6customboard.dts | 1 + arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 1 + arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 1 + arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 1 + arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 1 + 5 files changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts index f2368a073d07..c54362fcc508 100644 --- a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts +++ b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts @@ -177,6 +177,7 @@ touchscreen-size-y = <480>; touchscreen-inverted-x; touchscreen-inverted-y; + wakeup-source; }; rtc@68 { diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index aab088f318e8..aef4a756ca81 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -292,6 +292,7 @@ reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; rtc@6f { diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index 87ca6ead4098..9cb464b65be1 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -442,6 +442,7 @@ reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index f5b763d39285..5e4da6d6fcff 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -360,6 +360,7 @@ reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 596866b0a0d2..a14872436c5e 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -370,6 +370,7 @@ reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; }; -- cgit v1.2.3 From 52f2b531948db99c2dc5aaa8f81163c67921ed08 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 12 Jun 2018 15:32:08 +0200 Subject: ARM: dts: imx53: Add support for imx53 HSC/DDC boards from K+P This commit provides support for HSC and DDC boards from Kieback&Peter GmbH vendor. Signed-off-by: Lukasz Majewski Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx53-kp-ddc.dts | 146 ++++++++++++++++++++++++++++ arch/arm/boot/dts/imx53-kp-hsc.dts | 52 ++++++++++ arch/arm/boot/dts/imx53-kp.dtsi | 189 +++++++++++++++++++++++++++++++++++++ 4 files changed, 389 insertions(+) create mode 100644 arch/arm/boot/dts/imx53-kp-ddc.dts create mode 100644 arch/arm/boot/dts/imx53-kp-hsc.dts create mode 100644 arch/arm/boot/dts/imx53-kp.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 30379d342cd6..8b0e081b225d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -362,6 +362,8 @@ dtb-$(CONFIG_SOC_IMX51) += \ dtb-$(CONFIG_SOC_IMX53) += \ imx53-ard.dtb \ imx53-cx9020.dtb \ + imx53-kp-ddc.dtb \ + imx53-kp-hsc.dtb \ imx53-m53evk.dtb \ imx53-mba53.dtb \ imx53-ppd.dtb \ diff --git a/arch/arm/boot/dts/imx53-kp-ddc.dts b/arch/arm/boot/dts/imx53-kp-ddc.dts new file mode 100644 index 000000000000..0e7f071fd10e --- /dev/null +++ b/arch/arm/boot/dts/imx53-kp-ddc.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx53-kp.dtsi" + +/ { + model = "K+P imx53 DDC"; + compatible = "kiebackpeter,imx53-ddc", "fsl,imx53"; + + backlight_lcd: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000>; + power-supply = <®_backlight>; + brightness-levels = <0 24 28 32 36 + 40 44 48 52 56 + 60 64 68 72 76 + 80 84 88 92 96 100>; + default-brightness-level = <20>; + }; + + lcd_display: display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp>; + + port@0 { + reg = <0>; + + display1_in: endpoint { + remote-endpoint = <&ipu_di1_disp1>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + lcd_panel: lcd-panel { + compatible = "koe,tx14d24vm1bpa"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "backlight-supply"; + regulator-min-microvolt = <15000000>; + regulator-max-microvolt = <15000000>; + regulator-always-on; + }; +}; + +&fec { + status = "okay"; +}; + +&i2c3 { + adc@48 { + compatible = "ti,ads1015"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@6 { + reg = <6>; + ti,gain = <2>; + ti,datarate = <4>; + }; + }; + + gpio-expander2@21 { + compatible = "nxp,pcf8574"; + reg = <0x21>; + interrupts = <109>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&iomuxc { + imx53-kp-ddc { + pinctrl_disp: dispgrp { + fsl,pins = < + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4 + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4 + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4 + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4 + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4 + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4 + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4 + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4 + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4 + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4 + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4 + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4 + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4 + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4 + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4 + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4 + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4 + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4 + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4 + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4 + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4 + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4 + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4 + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4 + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4 + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4 + MX53_PAD_GPIO_1__PWM2_PWMO 0x4 + >; + }; + }; +}; + +&ipu_di1_disp1 { + remote-endpoint = <&display1_in>; +}; + +&pmic { + fsl,mc13xxx-uses-touch; +}; diff --git a/arch/arm/boot/dts/imx53-kp-hsc.dts b/arch/arm/boot/dts/imx53-kp-hsc.dts new file mode 100644 index 000000000000..6e3d71baac0f --- /dev/null +++ b/arch/arm/boot/dts/imx53-kp-hsc.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx53-kp.dtsi" + +/ { + model = "K+P imx53 HSC"; + compatible = "kiebackpeter,imx53-hsc", "fsl,imx53"; +}; + +&fec { + status = "okay"; + + fixed-link { /* RMII fixed link to LAN9303 */ + speed = <100>; + full-duplex; + }; +}; + +&i2c3 { + switch: switch@a { + compatible = "smsc,lan9303-i2c"; + reg = <0xa>; + reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + reset-duration = <400>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { /* RMII fixed link to master */ + reg = <0>; + label = "cpu"; + ethernet = <&fec>; + }; + + port@1 { /* external port 1 */ + reg = <1>; + label = "lan1"; + }; + + port@2 { /* external port 2 */ + reg = <2>; + label = "lan2"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx53-kp.dtsi b/arch/arm/boot/dts/imx53-kp.dtsi new file mode 100644 index 000000000000..8b25416a5303 --- /dev/null +++ b/arch/arm/boot/dts/imx53-kp.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx53-tqma53.dtsi" +#include + +/ { + buzzer { + compatible = "pwm-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_buzzer>; + pwms = <&pwm1 0 500000>; + }; + + gpio-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobuttons>; + + button-kalt { + label = "Kaltstart"; + linux,code = ; + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + }; + + button-pwr { + label = "PowerFailInterrupt"; + linux,code = ; + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-bus { + label = "bus"; + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + led-error { + label = "error"; + gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + led-flash { + label = "flash"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + gpio-expander1@22 { + compatible = "nxp,pcf8574"; + reg = <0x22>; + interrupts = <109>; + #gpio-cells = <2>; + gpio-controller; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kp_common>; + + imx53-kp-common { + pinctrl_buzzer: buzzergrp { + fsl,pins = < + MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4 + >; + }; + + pinctrl_gpiobuttons: gpiobuttonsgrp { + fsl,pins = < + MX53_PAD_EIM_RW__GPIO2_26 0x1e4 + MX53_PAD_EIM_D22__GPIO3_22 0x1e4 + >; + }; + + pinctrl_kp_common: kpcommongrp { + fsl,pins = < + MX53_PAD_EIM_CS0__GPIO2_23 0x1e4 + MX53_PAD_GPIO_19__GPIO4_5 0x1e4 + MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4 + MX53_PAD_PATA_DATA7__GPIO2_7 0xe0 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4 + MX53_PAD_EIM_D17__GPIO3_17 0x1e4 + MX53_PAD_EIM_D18__GPIO3_18 0x1e4 + MX53_PAD_EIM_D21__GPIO3_21 0x1e4 + MX53_PAD_EIM_D29__GPIO3_29 0x1e4 + MX53_PAD_EIM_DA11__GPIO3_11 0x1e4 + MX53_PAD_EIM_DA13__GPIO3_13 0x1e4 + MX53_PAD_EIM_DA14__GPIO3_14 0x1e4 + MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4 + MX53_PAD_SD1_CMD__GPIO1_18 0x1e4 + MX53_PAD_SD1_CLK__GPIO1_20 0x1e4 + >; + }; + + pinctrl_leds: ledgrp { + fsl,pins = < + MX53_PAD_EIM_EB2__GPIO2_30 0x1d4 + MX53_PAD_EIM_D28__GPIO3_28 0x1d4 + MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4 + >; + }; + }; +}; + +&pinctrl_uart1 { + fsl,pins = < + MX53_PAD_EIM_D23__GPIO3_23 0x1e4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 + MX53_PAD_EIM_D24__GPIO3_24 0x1e4 + MX53_PAD_EIM_D25__GPIO3_25 0x1e4 + MX53_PAD_EIM_D19__GPIO3_19 0x1e4 + MX53_PAD_EIM_D20__GPIO3_20 0x1e4 + >; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy0 { + status = "disabled"; +}; -- cgit v1.2.3 From 6e21e4c215a6e088c0d49fc107fd56361b1fdf22 Mon Sep 17 00:00:00 2001 From: Nikita Yushchenko Date: Thu, 17 May 2018 22:19:23 +0300 Subject: ARM: dts: imx51-zii-rdu1: add rave-sp subdevices This adds rave-sp powerbutton and backlight devices to RDU1 device tree. Signed-off-by: Nikita Yushchenko Tested-by: Chris Healy Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index df9eca94d812..ad2445dfa91d 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -582,6 +582,14 @@ watchdog { compatible = "zii,rave-sp-watchdog"; }; + + backlight { + compatible = "zii,rave-sp-backlight"; + }; + + pwrbutton { + compatible = "zii,rave-sp-pwrbutton"; + }; }; }; -- cgit v1.2.3 From bcf1477468143170ab98638a09162a3cac221367 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Fri, 25 May 2018 19:12:38 -0700 Subject: ARM: dts: imx51-zii-rdu1: Make sure SD1_WP is low Make sure that MX51_PAD_GPIO1_1 does not remain configure as ALT0/SD1_WP (it is out of reset). This is needed because of external pull-up resistor attached to that pad that, when left unchanged, will drive SD1_WP high preventing eSDHC1/eMMC from working correctly. To fix that add a pinmux configuration line configureing the pad to function as a GPIO. While we are at it, add a corresponding output-high GPIO hog in an effort to minimize current consumption. Cc: Nikita Yushchenko Cc: Fabio Estevam Cc: Lucas Stach Cc: Chris Healy Cc: Rob Herring Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Tested-By: Nikita Yushchenko Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index ad2445dfa91d..27ea581f7789 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -476,6 +476,17 @@ status = "okay"; }; +&gpio1 { + unused-sd3-wp-gpio { + /* + * See pinctrl_esdhc1 below for more details on this + */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; @@ -668,6 +679,23 @@ MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + /* + * GPIO1_1 is not directly used by eSDHC1 in + * any capacity, but earlier versions of RDU1 + * used that pin as WP GPIO for eSDHC3 and + * because of that that pad has an external + * pull-up resistor. This is problematic + * because out of reset the pad is configured + * as ALT0 which serves as SD1_WP, which, when + * pulled high by and external pull-up, will + * inhibit execution of any write request to + * attached eMMC device. + * + * To avoid this problem we configure the pad + * to ALT1/GPIO and avoid driving SD1_WP + * signal high. + */ + MX51_PAD_GPIO1_1__GPIO1_1 0x0000 >; }; -- cgit v1.2.3 From 9d1b8418b4773add2ec6ae29cfbd953cf07cc042 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Tue, 29 May 2018 06:20:18 +0000 Subject: ARM: dts: imx6qdl-wandboard: remove regulators bus node To match the convention, move all regulator-fixed nodes directly into the root node. Signed-off-by: Alexander Kurz Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 40 +++++++++++++------------------- 1 file changed, 16 insertions(+), 24 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index e1afa54404d0..52baf6d1a956 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -8,30 +8,6 @@ #include / { - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - sound { compatible = "fsl,imx6-wandboard-sgtl5000", "fsl,imx-audio-sgtl5000"; @@ -52,6 +28,22 @@ spdif-controller = <&spdif>; spdif-out; }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; &audmux { -- cgit v1.2.3 From d8d5f9dc40e7cf74a78f8e4164854b4eb5e45d8c Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Tue, 29 May 2018 06:20:19 +0000 Subject: ARM: dts: imx6dl-riotboard: remove regulators bus node To match the convention, move regulator-fixed nodes directly into the root node. Signed-off-by: Alexander Kurz Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-riotboard.dts | 55 ++++++++++++++-------------------- 1 file changed, 23 insertions(+), 32 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 2e98c92adff7..a6851bfebbdb 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -19,38 +19,6 @@ reg = <0x10000000 0x40000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - }; - leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -82,6 +50,29 @@ mux-int-port = <1>; mux-ext-port = <3>; }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &audmux { -- cgit v1.2.3 From e732f6d26eeab94a4988a556951bbc015b0c3d16 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Tue, 29 May 2018 06:20:20 +0000 Subject: ARM: dts: imx6qdl-wandboard: enable USB OTG Enable USB OTG (dual-role) on the Wandboard. Note, that the USB_OTG_VBUS current is quite limited due to a 22R resistor in the power line. Hence, the overcurrent signal of 1A will never be triggered on this board. Signed-off-by: Alexander Kurz Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 52baf6d1a956..381bf61fcd28 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -44,6 +44,16 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgvbus>; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + }; }; &audmux { @@ -166,6 +176,12 @@ >; }; + pinctrl_usbotgvbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 @@ -240,10 +256,11 @@ }; &usbotg { + vbus-supply = <®_usb_otg_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; }; -- cgit v1.2.3 From dcae11de22c9da83755d03f2631d7ddf4db00293 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Tue, 29 May 2018 06:20:21 +0000 Subject: ARM: dts: imx6dl-riotboard: fix OTG regulator polarity USB OTG power is switched on when the GPIO is pulled low. Signed-off-by: Alexander Kurz Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-riotboard.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index a6851bfebbdb..89b06e20480d 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -70,8 +70,7 @@ regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; }; }; -- cgit v1.2.3 From cddb86833615d9550d7b3a1b65b71071784dae70 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 16 Jun 2018 16:20:04 +0200 Subject: ARM: dts: rockchip: fix graph node unit address error from dtc The updated dtc emits a warning for the edp-panel of two rk3288 boards: Warning (graph_endpoint): /dp@ff970000/ports/port@1/endpoint: graph node unit address error, expected "0" Fix this by adding the necessary @0 to the endpoint node. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-evb.dtsi | 2 +- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 39b61dce97ad..1c4dfd94e555 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -232,7 +232,7 @@ #address-cells = <1>; #size-cells = <0>; - edp_out_panel: endpoint { + edp_out_panel: endpoint@0 { reg = <0>; remote-endpoint = <&panel_in_edp>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index b16d570ff029..acf5f8a2307d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -174,7 +174,7 @@ reg = <1>; #address-cells = <1>; #size-cells = <0>; - edp_out_panel: endpoint { + edp_out_panel: endpoint@0 { reg = <0>; remote-endpoint = <&panel_in_edp>; }; -- cgit v1.2.3 From fce152a63d9597c108c10a0eb7a71f1edfc9d42e Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Fri, 15 Dec 2017 12:44:27 +0100 Subject: ARM: dts: rockchip: use SPDX-License-Identifier Update all 32bit rockchip devicetree files to use SPDX-License-Identifiers. All files except rk3288-veyron-analog-audio.dtsi (which is GPL 2.0 only) claim to be GPL and X11 while the actual license text is MIT. Use the MIT SPDX tag for them. Signed-off-by: Klaus Goger Acked-by: Brian Norris Acked-by: Matthias Brugger Acked-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-evb.dts | 40 +---------------------- arch/arm/boot/dts/rk3036-kylin.dts | 40 +---------------------- arch/arm/boot/dts/rk3036.dtsi | 40 +---------------------- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 39 +--------------------- arch/arm/boot/dts/rk3066a-marsboard.dts | 39 +--------------------- arch/arm/boot/dts/rk3066a-mk808.dts | 39 +--------------------- arch/arm/boot/dts/rk3066a-rayeager.dts | 39 +--------------------- arch/arm/boot/dts/rk3066a.dtsi | 39 +--------------------- arch/arm/boot/dts/rk3188-px3-evb.dts | 39 +--------------------- arch/arm/boot/dts/rk3188-radxarock.dts | 39 +--------------------- arch/arm/boot/dts/rk3188.dtsi | 39 +--------------------- arch/arm/boot/dts/rk3228-evb.dts | 40 +---------------------- arch/arm/boot/dts/rk3229-evb.dts | 40 +---------------------- arch/arm/boot/dts/rk3229.dtsi | 39 +--------------------- arch/arm/boot/dts/rk322x.dtsi | 40 +---------------------- arch/arm/boot/dts/rk3288-evb-act8846.dts | 40 +---------------------- arch/arm/boot/dts/rk3288-evb-rk808.dts | 40 +---------------------- arch/arm/boot/dts/rk3288-evb.dtsi | 40 +---------------------- arch/arm/boot/dts/rk3288-fennec.dts | 40 +---------------------- arch/arm/boot/dts/rk3288-firefly-beta.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 39 +--------------------- arch/arm/boot/dts/rk3288-firefly-reload.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-firefly.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-firefly.dtsi | 39 +--------------------- arch/arm/boot/dts/rk3288-miqi.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-phycore-rdk.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-phycore-som.dtsi | 39 +--------------------- arch/arm/boot/dts/rk3288-popmetal.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-r89.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-rock2-som.dtsi | 40 +---------------------- arch/arm/boot/dts/rk3288-rock2-square.dts | 40 +---------------------- arch/arm/boot/dts/rk3288-tinker.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi | 5 +-- arch/arm/boot/dts/rk3288-veyron-brain.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 39 +--------------------- arch/arm/boot/dts/rk3288-veyron-jaq.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-veyron-jerry.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-veyron-mickey.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-veyron-minnie.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-veyron-pinky.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 39 +--------------------- arch/arm/boot/dts/rk3288-veyron-speedy.dts | 39 +--------------------- arch/arm/boot/dts/rk3288-veyron.dtsi | 39 +--------------------- arch/arm/boot/dts/rk3288-vyasa.dts | 39 +--------------------- arch/arm/boot/dts/rk3288.dtsi | 40 +---------------------- arch/arm/boot/dts/rk3xxx.dtsi | 39 +--------------------- arch/arm/boot/dts/rv1108-evb.dts | 40 +---------------------- arch/arm/boot/dts/rv1108.dtsi | 40 +---------------------- 48 files changed, 48 insertions(+), 1805 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts index c0953410121b..2a7e6624efb9 100644 --- a/arch/arm/boot/dts/rk3036-evb.dts +++ b/arch/arm/boot/dts/rk3036-evb.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index e2a0f576946f..0fd19f9723df 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 567a6a725f9c..67f57200d9a0 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include #include diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index ef1eabf2512c..1c925f20dba0 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index d23ee6d911ac..ce525b956ae5 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2014 Romain Perier - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index 13e285c53def..b6a8a82d219e 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 PaweÅ‚ Jarosz - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 4d7057a10a4c..cd126b927ba8 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2014, 2015 FUKAUMI Naoki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 06523caca27d..2ab3c4b32003 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts index 8ba9e06062f3..375129b62102 100644 --- a/arch/arm/boot/dts/rk3188-px3-evb.dts +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Andy Yan - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 00e05a6662ac..45fd2b302dda 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index aa10caae51c3..aa123f93f181 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts index 1be9daacc4f9..5670b33fd1bd 100644 --- a/arch/arm/boot/dts/rk3228-evb.dts +++ b/arch/arm/boot/dts/rk3228-evb.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index 73e384585755..4df7accc3ad7 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rk3229.dtsi index 6fe6c15fc13a..cb7d3fad8e60 100644 --- a/arch/arm/boot/dts/rk3229.dtsi +++ b/arch/arm/boot/dts/rk3229.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "rk322x.dtsi" diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index be80e9a2c9af..cdc08520de1d 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include #include diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts index b9418d170502..6592c809e2a5 100644 --- a/arch/arm/boot/dts/rk3288-evb-act8846.dts +++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; #include "rk3288-evb.dtsi" diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index 56c266df01c1..16788209625b 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; #include "rk3288-evb.dtsi" diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 39b61dce97ad..ced9d1584271 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include #include diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts index 41405974253a..b1b56dfdfdba 100644 --- a/arch/arm/boot/dts/rk3288-fennec.dts +++ b/arch/arm/boot/dts/rk3288-fennec.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-firefly-beta.dts b/arch/arm/boot/dts/rk3288-firefly-beta.dts index 0195d9721660..0f3c29d7fbab 100644 --- a/arch/arm/boot/dts/rk3288-firefly-beta.dts +++ b/arch/arm/boot/dts/rk3288-firefly-beta.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2014, 2015 FUKAUMI Naoki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi index 5f1e336dbaac..f57f286a93c3 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device tree file for Firefly Rockchip RK3288 Core board * Copyright (c) 2016 Randy Li - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index eab176e3dfc3..58ea8bed040a 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device tree file for Firefly Rockchip RK3288 Core board * Copyright (c) 2016 Randy Li - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-firefly.dts b/arch/arm/boot/dts/rk3288-firefly.dts index 14271be72f30..556ab42dd81c 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dts +++ b/arch/arm/boot/dts/rk3288-firefly.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2014, 2015 FUKAUMI Naoki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index b9e6f3a97240..a6ff7eac4aa8 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2014, 2015 FUKAUMI Naoki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index 4d923aa6ed11..504ab1177aa7 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts index 985743fa134c..7077c3403483 100644 --- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts +++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device tree file for Phytec PCM-947 carrier board * Copyright (C) 2017 PHYTEC Messtechnik GmbH * Author: Wadim Egorov - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi index aaab2d171ffe..c218dd54c9b5 100644 --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device tree file for Phytec phyCORE-RK3288 SoM * Copyright (C) 2017 PHYTEC Messtechnik GmbH * Author: Wadim Egorov - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index c06d0f4ceb81..596435e03132 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2014, 2015 Andy Yan - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index e95215c9788b..28972fb4e221 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2015 Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index 51f36a1b698e..50325489c0ce 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include #include "rk3288.dtsi" diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index 8ccc89dbdfaf..6a30cadad88a 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; #include diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts index 127488f9f174..ceade5962899 100644 --- a/arch/arm/boot/dts/rk3288-tinker.dts +++ b/arch/arm/boot/dts/rk3288-tinker.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi index 280aceae25d5..eaf921694e68 100644 --- a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Google Veyron (and derivatives) fragment for the max98090 audio * codec and analog headphone jack. * * Copyright 2016 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ / { diff --git a/arch/arm/boot/dts/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rk3288-veyron-brain.dts index ed4255294ad4..5c94a33d695d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-brain.dts +++ b/arch/arm/boot/dts/rk3288-veyron-brain.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Brain Rev 0 board device tree source * * Copyright 2014 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index b16d570ff029..cc11adf85fb3 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron (and derivatives) board device tree source * Chromebook specific parts * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index d33f5763c39c..9d6814c7f285 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Jaq Rev 1+ board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts index cdea751f2a8c..2ba89895c33a 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Jerry Rev 3+ board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts index f0994f0e5774..1e0158acf895 100644 --- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts +++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Mickey Rev 0 board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index 4c5307e62001..f95d0c5fcf71 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Minnie Rev 0+ board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts index 995cff42fa43..2950aadf49f0 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Pinky Rev 2 board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi index 95e9bee8bca2..a4570444cc79 100644 --- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron (and derivatives) fragment for sdmmc cards * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ &io_domains { diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts index cc0b78cefe34..e16421d80d22 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Speedy Rev 1+ board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 6e5bd8974f22..823c7ed47fcf 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron (and derivatives) board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index 14c896bfc639..4856a9fc0aea 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2017 Jagan Teki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index d7e49d29ace5..2a060c2dc383 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include #include diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 49584b6a4195..d752dc611fd7 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts index 70f0106d1252..203d83e3bbf5 100644 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 76ea24636feb..ed8f6ca52c5b 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include #include -- cgit v1.2.3 From 0bac06df36abb3b74e146091ca51c8c6d70d69a6 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:01:50 +0530 Subject: ARM: dts: rockchip: Add missing cooling device properties for CPUs on rk322x The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index cdc08520de1d..cd8f2a3b0e91 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -42,6 +42,7 @@ reg = <0xf01>; resets = <&cru SRST_CORE1>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ enable-method = "psci"; }; @@ -51,6 +52,7 @@ reg = <0xf02>; resets = <&cru SRST_CORE2>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ enable-method = "psci"; }; @@ -60,6 +62,7 @@ reg = <0xf03>; resets = <&cru SRST_CORE3>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ enable-method = "psci"; }; }; -- cgit v1.2.3 From e3b742026b92a141b43560858b089921953a63de Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Tue, 5 Jun 2018 10:17:49 +0530 Subject: ARM: dts: sunxi: Add missing cooling device properties for CPUs The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Fix other missing properties (clocks, OPP, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 30 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 13 +++++++++++++ arch/arm/boot/dts/sun8i-a33.dtsi | 9 +++++++++ 3 files changed, 52 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index c72992556a86..debc0bf22ea3 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -119,18 +119,48 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e529e4ff2174..35372a0cfc8d 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -122,6 +122,19 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 960000 1400000 + 912000 1400000 + 864000 1300000 + 720000 1200000 + 528000 1100000 + 312000 1000000 + 144000 1000000 + >; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 8d278ee001e9..4e92741b24a7 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -132,21 +132,30 @@ }; cpu@1 { + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; }; -- cgit v1.2.3 From 77ad0f2e34f849d4f85c30933c14ab742f617078 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Tue, 5 Jun 2018 10:17:48 +0530 Subject: ARM: dts: sun8i-h3: Add missing cooling device properties for CPUs The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Fix other missing properties (clocks, clock-names) as well to make it all work. Signed-off-by: Viresh Kumar Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 41d57c76f290..9dff6887923c 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -84,21 +84,30 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; }; -- cgit v1.2.3 From 5058a96cb7e8dca97629c48084537fe5def8344f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 23 May 2018 13:43:40 +0200 Subject: ARM: dts: porter: Add missing PMIC nodes Add PMIC nodes to Porter and connect CPU DVFS supply. There is one DA9063L and one DA9210 on Porter, the only difference from the other boards is that DA9063L is at I2C address 0x5a rather than 0x58 . Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-porter.dts | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index a01101b49d99..5f77d73d7462 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -375,10 +375,43 @@ clock-frequency = <400000>; }; +&i2c6 { + status = "okay"; + clock-frequency = <100000>; + + pmic@5a { + compatible = "dlg,da9063l"; + reg = <0x5a>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + }; + + vdd_dvfs: regulator@68 { + compatible = "dlg,da9210"; + reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + &sata0 { status = "okay"; }; +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; + /* composite video input */ &vin0 { status = "okay"; -- cgit v1.2.3 From ce76de984649bf85c81ee437eea282d10ba0dbb3 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 16 Jun 2018 16:55:17 +0200 Subject: ARM: dts: rockchip: convert rk3288 to operating-points-v2 Operating points need to be present in each cpu core using it, not only the first one. With operating-points-v1 this would require duplicating this table into each cpu node. With opp-v2 we can share the same table on all nodes. Signed-off-by: Heiko Stuebner Acked-by: Viresh Kumar --- arch/arm/boot/dts/rk3288-veyron.dtsi | 36 ++++++++++--------- arch/arm/boot/dts/rk3288.dtsi | 70 ++++++++++++++++++++++++++++-------- 2 files changed, 75 insertions(+), 31 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 823c7ed47fcf..2075120cfc4d 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -91,22 +91,26 @@ &cpu0 { cpu0-supply = <&vdd_cpu>; - operating-points = < - /* KHz uV */ - 1800000 1400000 - 1704000 1350000 - 1608000 1300000 - 1512000 1250000 - 1416000 1200000 - 1200000 1100000 - 1008000 1050000 - 816000 1000000 - 696000 950000 - 600000 900000 - 408000 900000 - 216000 900000 - 126000 900000 - >; +}; + +/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */ +&cpu_opp_table { + /delete-node/ opp-312000000; + + opp-1512000000 { + opp-microvolt = <1250000>; + }; + opp-1608000000 { + opp-microvolt = <1300000>; + }; + opp-1704000000 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <1350000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1400000>; + }; }; &emmc { diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 2a060c2dc383..7094f95b967f 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -60,21 +60,7 @@ compatible = "arm,cortex-a12"; reg = <0x500>; resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 1608000 1350000 - 1512000 1300000 - 1416000 1200000 - 1200000 1100000 - 1008000 1050000 - 816000 1000000 - 696000 950000 - 600000 900000 - 408000 900000 - 312000 900000 - 216000 900000 - 126000 900000 - >; + operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; @@ -99,6 +85,60 @@ }; }; + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-126000000 { + opp-hz = /bits/ 64 <126000000>; + opp-microvolt = <900000>; + }; + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <900000>; + }; + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <900000>; + }; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + }; + opp-696000000 { + opp-hz = /bits/ 64 <696000000>; + opp-microvolt = <950000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1050000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1200000>; + }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1300000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1350000>; + }; + }; + amba { compatible = "simple-bus"; #address-cells = <2>; -- cgit v1.2.3 From f999d76a0011abfd814c8513a5e60a7eb9b9dac0 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:01:56 +0530 Subject: ARM: dts: rockchip: Add missing cooling device properties for CPUs on rk3288 The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Fix other missing properties (clocks, OPP, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar [follow conversion to operating-points-v2] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 7094f95b967f..0840ffb3205c 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -70,18 +70,30 @@ compatible = "arm,cortex-a12"; reg = <0x501>; resets = <&cru SRST_CORE1>; + operating-points = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu2: cpu@502 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x502>; resets = <&cru SRST_CORE2>; + operating-points = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu3: cpu@503 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x503>; resets = <&cru SRST_CORE3>; + operating-points = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; }; -- cgit v1.2.3 From 4be9e673298fb4d204c6d4c782c800ec6d17d0c6 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 18 May 2018 15:43:39 -0500 Subject: ARM: dts: da850-evm: Enable SATA port The DA850-EVM from Logic PD has a SATA port and the module that went with the kit supports it as well. This patch enables SATA controller. Signed-off-by: Adam Ford Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-evm.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 0e82bb988fde..743af2b6a5ce 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -93,6 +93,10 @@ }; }; +&sata { + status = "okay"; +}; + &serial0 { status = "okay"; }; -- cgit v1.2.3 From 8ae024497b3d68165e692d6ad5ba149cd070dac2 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 18 May 2018 15:33:35 -0500 Subject: ARM: dts: da850-evm: Enable LCD and backlight When using the board files the LCD works, but not with the DT. This adds enables the original da850-evm to work with the same LCD in device tree mode. The EVM has a gpio for backlight regulator and a PWM for dimming the backlight. The LCD and the vpif display pins are mutually exclusive, so if using the LCD, do not load the vpif driver. Signed-off-by: Adam Ford Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-evm.dts | 83 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 743af2b6a5ce..e49d71100c15 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -27,6 +27,65 @@ spi0 = &spi1; }; + backlight: backlight-pwm { + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>; + power-supply = <&backlight_lcd>; + compatible = "pwm-backlight"; + /* + * The PWM here corresponds to production hardware. The + * schematic needs to be 1015171 (15 March 2010), Rev A + * or newer. + */ + pwms = <&ecap2 0 50000 0>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; + default-brightness-level = <7>; + }; + + panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + /* + * The vpif and the LCD are mutually exclusive. + * To enable VPIF, change the status below to 'disabled' then + * then change the status of the vpif below to 'okay' + */ + status = "okay"; + enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ + + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + display-timings { + native-mode = <&timing0>; + timing0: 480x272 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <3>; + hback-porch = <2>; + hsync-len = <42>; + vback-porch = <3>; + vfront-porch = <4>; + vsync-len = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; @@ -35,6 +94,15 @@ regulator-boot-on; }; + backlight_lcd: backlight-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_backlight_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */ + enable-active-high; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "DA850/OMAP-L138 EVM"; @@ -63,6 +131,10 @@ }; }; +&ecap2 { + status = "okay"; +}; + &pmx_core { status = "okay"; @@ -113,6 +185,10 @@ status = "okay"; }; +&lcdc { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <100000>; @@ -340,5 +416,10 @@ &vpif { pinctrl-names = "default"; pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>; - status = "okay"; + /* + * The vpif and the LCD are mutually exclusive. + * To enable VPIF, disable the ti,tilcdc,panel then + * change the status below to 'okay' + */ + status = "disabled"; }; -- cgit v1.2.3 From 39143301bed9cae5ce1c1c65b0c482ea650bf367 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Jun 2018 11:30:45 +0200 Subject: ARM: dts: imx6: RDU2: correct touchscreen axis inversion The RMI4 touchscreen driver applied inversion and axis swap in the wrong order, violating the DT binding for those properties. This is fixed now, so correct the RDU2 DT to apply the inversion to the correct axis. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 19a075aee19e..8e154c9bf814 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -569,14 +569,14 @@ rmi4-f11@11 { reg = <0x11>; - touchscreen-inverted-y; + touchscreen-inverted-x; touchscreen-swapped-x-y; syna,sensor-type = <1>; }; rmi4-f12@12 { reg = <0x12>; - touchscreen-inverted-y; + touchscreen-inverted-x; touchscreen-swapped-x-y; syna,sensor-type = <1>; }; -- cgit v1.2.3 From a8039f2dd0899a41d869ba2cc0f73a29b519d268 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 7 Jun 2018 19:21:31 +0530 Subject: ARM: dts: imx6dl: Add Engicam i.CoreM6 1.5 Quad/Dual MIPI starter kit support i.CoreM6 1.5 is an another i.CoreM6 QDL cpu modules which can be connected to EDIMM starter kit design with eMMC and MIPI-CSI interfaces suitable for Android and video capture application. notable features: CPU NXP i.MX6 S/DL/D/Q, Up to 4 x Cortex-A9@800MHz Memory Up to 2 GB DDR3-1066 Video Interfaces Up to 1 Parallel Up to 2 LVDS HDMI 1.4 port 8 bit CSI INPUT MIPI-CSI INPUT 1 x 10/100 Ethernet interface, 2 x USB, 1 x PCIe, 1 x I2S etc Signed-off-by: Jagan Teki Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-icore-mipi.dts | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-icore-mipi.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8b0e081b225d..bc63b4c81dfe 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -402,6 +402,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-hummingboard2-emmc-som-v15.dtb \ imx6dl-hummingboard2-som-v15.dtb \ imx6dl-icore.dtb \ + imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ imx6dl-mamoj.dtb \ imx6dl-nit6xlite.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-icore-mipi.dts b/arch/arm/boot/dts/imx6dl-icore-mipi.dts new file mode 100644 index 000000000000..bf53f0552aa1 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-icore-mipi.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Engicam S.r.l. + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6dl"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; -- cgit v1.2.3 From 3992516af3846bc2dcba002de5d7c908be5c06de Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 7 Jun 2018 19:21:32 +0530 Subject: ARM: dts: imx6q-icore-mipi: Add OV5640 Camera sensor OV5640 Camera sensor is connected in i.CoreM6 1.5 Quad/Dual MIPI starter kit. This patch also move MX6QDL_PAD_GPIO_0__CCM_CLKO1 pinctrl from i2c3 to ov5640 pinctrl. Signed-off-by: Jagan Teki Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-icore-mipi.dts | 8 ++++++ arch/arm/boot/dts/imx6qdl-icore.dtsi | 46 +++++++++++++++++++++++++++++++++- 2 files changed, 53 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6q-icore-mipi.dts b/arch/arm/boot/dts/imx6q-icore-mipi.dts index acd3d33476d4..95b2efda17b4 100644 --- a/arch/arm/boot/dts/imx6q-icore-mipi.dts +++ b/arch/arm/boot/dts/imx6q-icore-mipi.dts @@ -20,6 +20,14 @@ status = "okay"; }; +&mipi_csi { + status = "okay"; +}; + +&ov5640 { + status = "okay"; +}; + &usdhc3 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi index 0a1574998fc6..be8aa55c973e 100644 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -215,6 +215,29 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + ov5640: camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_3p3v>; + DVDD-supply = <®_3p3v>; + powerdown-gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; + status = "disabled"; + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + sgtl5000: codec@a { #sound-dai-cells = <0>; compatible = "fsl,sgtl5000"; @@ -226,6 +249,20 @@ }; }; +&mipi_csi { + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; @@ -353,7 +390,14 @@ fsl,pins = < MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 >; }; -- cgit v1.2.3 From f3af1e5c0c6fe20cd2cc3ae5512c79d8e2dfbfba Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 7 Jun 2018 19:21:33 +0530 Subject: ARM: dts: imx6qdl-icore: Fix wrong reg_2p5 regulator node name - in reg_2p5, fix regulator node name as regulator-2p5v - remove exctra line Signed-off-by: Jagan Teki Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-icore.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi index be8aa55c973e..9ce993776160 100644 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -65,8 +65,7 @@ regulator-always-on; }; - - reg_2p5v: regulator-3p3v { + reg_2p5v: regulator-2p5v { compatible = "regulator-fixed"; regulator-name = "2P5V"; regulator-min-microvolt = <2500000>; -- cgit v1.2.3 From a211b8c55f3ce54423bd1daf1bca82271b08ac2f Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Mon, 18 Jun 2018 11:15:44 +0300 Subject: ARM: dts: imx6qdl-sabreauto: Add sensors The following sensors are on I2C3 on the baseboard: * isil,isl29023 light sensor * fsl,mag3110 magnetometer * fsl,mma8451 accelerometer Added under i2cmux/i2c@1 because they're not otherwise accessible. These are all supported by iio with following configs: * CONFIG_SENSORS_ISL29018 * CONFIG_MAG3110 * CONFIG_MMA8452 Tested with raw reads from iio sysfs. Signed-off-by: Leonard Crestez Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 0e28e36ddbb2..a59a0fd1eb02 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -155,6 +155,27 @@ gpio-controller; #gpio-cells = <2>; }; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; + }; + + magnetometer@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + interrupt-parent = <&gpio2>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + }; + + accelerometer@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + }; }; }; }; -- cgit v1.2.3 From 13d8f1762bf64c564317695b573b0b2528a90af9 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Mon, 18 Jun 2018 16:11:09 +0300 Subject: ARM: dts: imx7d-sdb: Remove duplicate regulator-can2-3v3 Two different regulators are defined with the same name and label but distinct properties. The first definition was added with the first board dts and the second was added when upstream added flexcan support. Looking at schematics it is indeed gpio2 14 connected to the STB pin of the CAN transceiver so remove the first definition. The second definition entirely overrides the first so this already worked and this patch results in no DTB change, just a cleanup. Signed-off-by: Leonard Crestez Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 940849163104..9f9e6a1e3b72 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -71,14 +71,6 @@ enable-active-high; }; - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - reg_vref_1v8: regulator-vref-1v8 { compatible = "regulator-fixed"; regulator-name = "vref-1v8"; -- cgit v1.2.3 From 59ef2671a84732c96cb08a5060b7fcceaa44f4d9 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 7 Jun 2018 10:41:07 +0200 Subject: ARM: dts: fix PMC compatible Make each SoC dtsi use its soc specific PMc compatible string. This solves a potential issue on at91sam9261 and at91sam9263 when using suspend to RAM Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9261.dtsi | 2 +- arch/arm/boot/dts/at91sam9263.dtsi | 2 +- arch/arm/boot/dts/at91sam9rl.dtsi | 2 +- arch/arm/boot/dts/sama5d4.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 53c63d0a418a..33f09d5ea020 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -590,7 +590,7 @@ }; pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc", "syscon"; + compatible = "atmel,at91sam9261-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupt-controller; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 87fb0660ab5d..af68a86c9973 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -93,7 +93,7 @@ }; pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc", "syscon"; + compatible = "atmel,at91sam9263-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupt-controller; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index bd001cca25a4..8fb22030f00b 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -832,7 +832,7 @@ }; pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9g45-pmc", "syscon"; + compatible = "atmel,at91sam9rl-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupt-controller; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 0cf9beddd556..92a35a1942b6 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -392,7 +392,7 @@ }; pmc: pmc@f0018000 { - compatible = "atmel,sama5d3-pmc", "syscon"; + compatible = "atmel,sama5d4-pmc", "syscon"; reg = <0xf0018000 0x120>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupt-controller; -- cgit v1.2.3 From e9af481cbc21bba1d4447a5a4bd1674c40d619a1 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Thu, 14 Jun 2018 21:50:04 +0200 Subject: ARM: dts: add Raspberry Pi Compute Module and IO board The Raspberry Pi Compute Module (CM1) is a SoM which contains a BCM2835 processor, 512 MB RAM and a 4 GB eMMC. There is also a carrier board which is called Compute Module IO Board. Signed-off-by: Stefan Wahren Signed-off-by: Eric Anholt Reviewed-by: Eric Anholt --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts | 88 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi | 34 ++++++++++++ 3 files changed, 123 insertions(+) create mode 100644 arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts create mode 100644 arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..07b306f46715 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2835-rpi-b-rev2.dtb \ bcm2835-rpi-b-plus.dtb \ bcm2835-rpi-a-plus.dtb \ + bcm2835-rpi-cm1-io1.dtb \ bcm2836-rpi-2-b.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts new file mode 100644 index 000000000000..4764a25585ab --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835-rpi-cm1.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,compute-module", "brcm,bcm2835"; + model = "Raspberry Pi Compute Module IO board rev1"; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "GPIO0", + "GPIO1", + "GPIO2", + "GPIO3", + "GPIO4", + "GPIO5", + "GPIO6", + "GPIO7", + "GPIO8", + "GPIO9", + "GPIO10", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "GPIO15", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "GPIO32", + "GPIO33", + "GPIO34", + "GPIO35", + "GPIO36", + "GPIO37", + "GPIO38", + "GPIO39", + "GPIO40", + "GPIO41", + "GPIO42", + "GPIO43", + "GPIO44", + "GPIO45", + "HDMI_HPD_N", + /* Also used as ACT LED */ + "EMMC_EN_N", + /* Used by eMMC */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi new file mode 100644 index 000000000000..ef22c2da783a --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" + +/ { + leds { + act { + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; + }; + }; + + reg_3v3: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1v8: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&sdhost { + non-removable; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_1v8>; +}; -- cgit v1.2.3 From 3306657119ce673629be62dfa373f440eaf16cc9 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Wed, 9 May 2018 17:18:00 +0200 Subject: ARM: dts: stm32: update rtc st,syscfg property on stm32f429 To fit with latest rtc driver updates, rtc st,syscfg property must contain the control register offset of pwrcfg and the mask corresponding to the DBP (Disable Backup Protection) bit. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index ede77e0f1c41..309e7e335ab7 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -302,7 +302,7 @@ interrupt-parent = <&exti>; interrupts = <17 1>; interrupt-names = "alarm"; - st,syscfg = <&pwrcfg>; + st,syscfg = <&pwrcfg 0x00 0x100>; status = "disabled"; }; -- cgit v1.2.3 From 860f0d21a7ef6675f5566aeac3d754414f105894 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Wed, 9 May 2018 17:18:00 +0200 Subject: ARM: dts: stm32: update rtc st,syscfg property on stm32f746 To fit with latest rtc driver updates, rtc st,syscfg property must contain the control register offset of pwrcfg and the mask corresponding to the DBP (Disable Backup Protection) bit. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f746.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 1479e3eb05fa..f48d06a80d1d 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -297,7 +297,7 @@ interrupt-parent = <&exti>; interrupts = <17 1>; interrupt-names = "alarm"; - st,syscfg = <&pwrcfg>; + st,syscfg = <&pwrcfg 0x00 0x100>; status = "disabled"; }; -- cgit v1.2.3 From 1e726a40e067948ecf90b8ea876bb6038c0c495f Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Mon, 14 May 2018 12:00:00 +0200 Subject: ARM: dts: stm32: Add HASH support on stm32mp157c This patch add HASH instance of the stm32mp157c SoC Signed-off-by: Lionel Debieve Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 7d1753893453..db0e643c1638 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -709,6 +709,18 @@ status = "disabled"; }; + hash1: hash@54002000 { + compatible = "st,stm32f756-hash"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; + dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0 0x0>; + dma-names = "in"; + dma-maxburst = <2>; + status = "disabled"; + }; + rng1: rng@54003000 { compatible = "st,stm32-rng"; reg = <0x54003000 0x400>; -- cgit v1.2.3 From c322d96fccc4ab727c6df6394cb882836dad8292 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Tue, 15 May 2018 14:23:00 +0200 Subject: ARM: dts: stm32: m_can support to stm32mp157c Add support for the Controller Area Network m_can to STM32MP157C SoC. Signed-off-by: Bich Hemon Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index db0e643c1638..f9ca705d553f 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -556,6 +556,32 @@ }; }; + m_can1: can@4400e000 { + compatible = "bosch,m_can"; + reg = <0x4400e000 0x400>, <0x44011000 0x2800>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + status = "disabled"; + }; + + m_can2: can@4400f000 { + compatible = "bosch,m_can"; + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + status = "disabled"; + }; + dma1: dma@48000000 { compatible = "st,stm32-dma"; reg = <0x48000000 0x400>; -- cgit v1.2.3 From 41cc73c5568f148f9f7d3a1a53fb68c7da6086eb Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Mon, 25 Jun 2018 15:44:24 +0200 Subject: ARM: dts: stm32: m_can activation on stm32mp157c-ev1 Add activation of the Controller Area Network m_can on stm32mp157c-ev1 board. Signed-off-by: Bich Hemon Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 13 +++++++++++++ arch/arm/boot/dts/stm32mp157c-ev1.dts | 6 ++++++ 2 files changed, 19 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 4839db146890..a7125aecd1f7 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -187,6 +187,19 @@ }; }; + m_can1_pins_a: m-can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-disable; + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = ; /* TIM2_CH4 */ diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 9382d8063031..3be73d26fc62 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -42,6 +42,12 @@ status = "okay"; }; +&m_can1 { + pinctrl-names = "default"; + pinctrl-0 = <&m_can1_pins_a>; + status = "okay"; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; -- cgit v1.2.3 From 0c7f7a5150023f3c6f0b27c4d4940ce3dfaf62cc Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:01:49 +0530 Subject: arm: dts: mediatek: Add missing cooling device properties for CPUs The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index d1eb123bc73b..1cdc346a05e8 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -92,6 +92,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; clock-frequency = <1300000000>; }; @@ -103,6 +104,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; clock-frequency = <1300000000>; }; @@ -114,6 +116,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; clock-frequency = <1300000000>; }; }; -- cgit v1.2.3 From 672f33198bee21ee91e6af2cb8f67cfc8bc97ec1 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:01:53 +0530 Subject: arm: dts: exynos: Add missing cooling device properties for CPUs The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Fix other missing properties (clocks, OPP, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/exynos4210.dtsi | 13 +++++++++++++ arch/arm/boot/dts/exynos4412.dtsi | 9 +++++++++ arch/arm/boot/dts/exynos5250.dtsi | 23 +++++++++++++++++++++++ 4 files changed, 61 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 962af97c1883..aff5d66ae058 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -78,6 +78,22 @@ compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cmu CLK_ARM_CLK>; + clock-names = "cpu"; + #cooling-cells = <2>; + + operating-points = < + 1000000 1150000 + 900000 1112500 + 800000 1075000 + 700000 1037500 + 600000 1000000 + 500000 962500 + 400000 925000 + 300000 887500 + 200000 850000 + 100000 850000 + >; }; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 88fb47cef9a8..b6091c27f155 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -55,6 +55,19 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0x901>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <160000>; + + operating-points = < + 1200000 1250000 + 1000000 1150000 + 800000 1075000 + 500000 975000 + 400000 975000 + 200000 950000 + >; + #cooling-cells = <2>; /* min followed by max */ }; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7b43c10c510b..51f72f0327e5 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -49,21 +49,30 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA01>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; cpu@a02 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA02>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; cpu@a03 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA03>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 2daf505b3d08..69648f83b8b4 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -84,6 +84,29 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1700000000>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <140000>; + + operating-points = < + 1700000 1300000 + 1600000 1250000 + 1500000 1225000 + 1400000 1200000 + 1300000 1150000 + 1200000 1125000 + 1100000 1100000 + 1000000 1075000 + 900000 1050000 + 800000 1025000 + 700000 1012500 + 600000 1000000 + 500000 975000 + 400000 950000 + 300000 937500 + 200000 925000 + >; + #cooling-cells = <2>; /* min followed by max */ }; }; -- cgit v1.2.3 From 265e83d6cf97c54b73374c7447a6f26006ec6929 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 May 2018 18:49:22 +0200 Subject: ARM: dts: exynos: Add missing CPU clocks to secondary CPUs on Exynos542x Secondary CPUs should have the same information in DeviceTree as booting CPU from both correctness point of view and for possible hotplug scenarios. Suggested-by: Viresh Kumar Signed-off-by: Krzysztof Kozlowski Acked-by: Viresh Kumar Reviewed-by: Alim Akhtar Tested-by: Alim Akhtar --- arch/arm/boot/dts/exynos5420-cpus.dtsi | 6 ++++++ arch/arm/boot/dts/exynos5422-cpus.dtsi | 8 +++++++- 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi index a8e449471304..0ee6e92a3c29 100644 --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi @@ -38,6 +38,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -49,6 +50,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x2>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -60,6 +62,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x3>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -83,6 +86,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x101>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -94,6 +98,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x102>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -105,6 +110,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x103>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index 7c130a00d1a8..e4a5857c135f 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -37,6 +37,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x101>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -48,6 +49,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x102>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -59,6 +61,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x103>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -69,8 +72,8 @@ cpu4: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; - clocks = <&clock CLK_ARM_CLK>; reg = <0x0>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -82,6 +85,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -93,6 +97,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x2>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -104,6 +109,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x3>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; -- cgit v1.2.3 From c05b799ecc4b4363e57e23db401561a6fc51d054 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Thu, 21 Jun 2018 12:35:30 +0200 Subject: ARM: dts: exynos: remove no longer needed samsung thermal properties Remove no longer needed samsung thermal properties. There should be no functional changes caused by this patch. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 2 +- arch/arm/boot/dts/exynos4.dtsi | 2 +- arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi | 20 -------------------- arch/arm/boot/dts/exynos5250.dtsi | 2 +- arch/arm/boot/dts/exynos5410.dtsi | 8 ++++---- arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi | 21 --------------------- arch/arm/boot/dts/exynos5420.dtsi | 10 +++++----- 7 files changed, 12 insertions(+), 53 deletions(-) delete mode 100644 arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi delete mode 100644 arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index aff5d66ae058..27a1ee28c3bb 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -242,7 +242,7 @@ interrupts = ; clocks = <&cmu CLK_TMU_APBIF>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index dfe41b698745..6085e92ac2d7 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -735,7 +735,7 @@ reg = <0x100C0000 0x100>; interrupts = <2 4>; status = "disabled"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; jpeg_codec: jpeg-codec@11840000 { diff --git a/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi deleted file mode 100644 index 489b58c619ee..000000000000 --- a/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos4412 TMU sensor configuration - * - * Copyright (c) 2014 Lukasz Majewski - */ - -#include - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <8>; -samsung,tmu_reference_voltage = <16>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <55>; -samsung,tmu_min_efuse_value = <40>; -samsung,tmu_max_efuse_value = <100>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <85>; -samsung,tmu_default_temp_offset = <50>; -samsung,tmu_cal_type = ; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 69648f83b8b4..da163a40af15 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -301,7 +301,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; sata: sata@122f0000 { diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 20e789ea136f..57fc9c949e54 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -93,7 +93,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu1: tmu@10064000 { @@ -102,7 +102,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu2: tmu@10068000 { @@ -111,7 +111,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu3: tmu@1006c000 { @@ -120,7 +120,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; mmc_0: mmc@12200000 { diff --git a/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi deleted file mode 100644 index fbc77cb58473..000000000000 --- a/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos5420 TMU sensor configuration - * - * Copyright (c) 2014 Lukasz Majewski - * Copyright (c) 2017 Krzysztof Kozlowski - */ - -#include - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <8>; -samsung,tmu_reference_voltage = <16>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <55>; -samsung,tmu_min_efuse_value = <0>; -samsung,tmu_max_efuse_value = <100>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <85>; -samsung,tmu_default_temp_offset = <50>; -samsung,tmu_cal_type = ; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index f4e8c5823bc2..aaff15880761 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -738,7 +738,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu1: tmu@10064000 { @@ -747,7 +747,7 @@ interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu2: tmu@10068000 { @@ -756,7 +756,7 @@ interrupts = ; clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu3: tmu@1006c000 { @@ -765,7 +765,7 @@ interrupts = ; clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_gpu: tmu@100a0000 { @@ -774,7 +774,7 @@ interrupts = ; clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; sysmmu_g2dr: sysmmu@10a60000 { -- cgit v1.2.3 From 8499163a2e5b07561ffc9540844eceb366eeb4e2 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Thu, 17 May 2018 14:07:00 +0200 Subject: ARM: dts: stm32: add RTC support to stm32mp157c Add support for RTC (Real Time Clock) to STM32MP157C SoC. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index f9ca705d553f..d14c94034089 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -863,6 +863,15 @@ status = "disabled"; }; + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + clocks = <&rcc RTCAPB>, <&rcc RTC>; + clock-names = "pclk", "rtc_ck"; + interrupts = ; + status = "disabled"; + }; + i2c6: i2c@5c009000 { compatible = "st,stm32f7-i2c"; reg = <0x5c009000 0x400>; -- cgit v1.2.3 From 8905764a6aca1e1794e248ac680c6245b7aee406 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Thu, 17 May 2018 14:07:00 +0200 Subject: ARM: dts: stm32: enable RTC on stm32mp157c-ed1 Enable RTC (Real Time Clock) on stm32mp157c-ed1 board. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index ae336530b59b..050c30d327db 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -68,6 +68,10 @@ status = "okay"; }; +&rtc { + status = "okay"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; -- cgit v1.2.3 From 3652e2741f4297524d1b166c0ba19c390cea7c71 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 18 May 2018 11:48:29 -0500 Subject: ARM: dts: da850: Add clocks This adds clock provider nodes for da850 and wires them up to all of the devices. Signed-off-by: David Lechner Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-enbw-cmc.dts | 4 + arch/arm/boot/dts/da850-evm.dts | 4 + arch/arm/boot/dts/da850-lcdk.dts | 9 ++ arch/arm/boot/dts/da850-lego-ev3.dts | 4 + arch/arm/boot/dts/da850.dtsi | 168 +++++++++++++++++++++++++++++++++++ 5 files changed, 189 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts index 14dff3e188ed..0102ffc5aa53 100644 --- a/arch/arm/boot/dts/da850-enbw-cmc.dts +++ b/arch/arm/boot/dts/da850-enbw-cmc.dts @@ -35,6 +35,10 @@ }; }; +&ref_clk { + clock-frequency = <24000000>; +}; + &edma0 { ti,edma-reserved-slot-ranges = <32 50>; }; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index e49d71100c15..f9b757905845 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -135,6 +135,10 @@ status = "okay"; }; +&ref_clk { + clock-frequency = <24000000>; +}; + &pmx_core { status = "okay"; diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts index 0edf769ea95c..0177e3ed20fe 100644 --- a/arch/arm/boot/dts/da850-lcdk.dts +++ b/arch/arm/boot/dts/da850-lcdk.dts @@ -123,6 +123,10 @@ }; }; +&ref_clk { + clock-frequency = <24000000>; +}; + &pmx_core { status = "okay"; @@ -175,6 +179,11 @@ status = "okay"; }; +&sata_refclk { + status = "okay"; + clock-frequency = <100000000>; +}; + &sata { status = "okay"; }; diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts index ee3932475ce7..331362a6f01e 100644 --- a/arch/arm/boot/dts/da850-lego-ev3.dts +++ b/arch/arm/boot/dts/da850-lego-ev3.dts @@ -191,6 +191,10 @@ }; }; +&ref_clk { + clock-frequency = <24000000>; +}; + &pmx_core { status = "okay"; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index f6f1597b03df..de9a8bea100e 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -32,6 +32,25 @@ reg = <0xfffee000 0x2000>; }; }; + clocks: clocks { + ref_clk: ref_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "ref_clk"; + }; + sata_refclk: sata_refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "sata_refclk"; + status = "disabled"; + }; + usb_refclkin: usb_refclkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "usb_refclkin"; + status = "disabled"; + }; + }; dsp: dsp@11800000 { compatible = "ti,da850-dsp"; reg = <0x11800000 0x40000>, @@ -42,6 +61,7 @@ reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; interrupt-parent = <&intc>; interrupts = <28>; + clocks = <&psc0 15>; status = "disabled"; }; soc@1c00000 { @@ -52,6 +72,37 @@ ranges = <0x0 0x01c00000 0x400000>; interrupt-parent = <&intc>; + psc0: clock-controller@10000 { + compatible = "ti,da850-psc0"; + reg = <0x10000 0x1000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, + <&pll0_sysclk 4>, <&pll0_sysclk 6>, + <&async1_clk>; + clock-names = "pll0_sysclk1", "pll0_sysclk2", + "pll0_sysclk4", "pll0_sysclk6", + "async1"; + }; + pll0: clock-controller@11000 { + compatible = "ti,da850-pll0"; + reg = <0x11000 0x1000>; + clocks = <&ref_clk>, <&pll1_sysclk 3>; + clock-names = "clksrc", "extclksrc"; + + pll0_pllout: pllout { + #clock-cells = <0>; + }; + pll0_sysclk: sysclk { + #clock-cells = <1>; + }; + pll0_auxclk: auxclk { + #clock-cells = <0>; + }; + pll0_obsclk: obsclk { + #clock-cells = <0>; + }; + }; pmx_core: pinmux@14120 { compatible = "pinctrl-single"; reg = <0x14120 0x50>; @@ -281,8 +332,41 @@ usb_phy: usb-phy { compatible = "ti,da830-usb-phy"; #phy-cells = <1>; + clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>; + clock-names = "usb0_clk48", "usb1_clk48"; status = "disabled"; }; + usb_phy_clk: usb-phy-clocks { + compatible = "ti,da830-usb-phy-clocks"; + #clock-cells = <1>; + clocks = <&psc1 1>, <&usb_refclkin>, + <&pll0_auxclk>; + clock-names = "fck", "usb_refclkin", "auxclk"; + }; + ehrpwm_tbclk: ehrpwm_tbclk { + compatible = "ti,da830-tbclksync"; + #clock-cells = <0>; + clocks = <&psc1 17>; + clock-names = "fck"; + }; + div4p5_clk: div4.5 { + compatible = "ti,da830-div4p5ena"; + #clock-cells = <0>; + clocks = <&pll0_pllout>; + clock-names = "pll0_pllout"; + }; + async1_clk: async1 { + compatible = "ti,da850-async1-clksrc"; + #clock-cells = <0>; + clocks = <&pll0_sysclk 3>, <&div4p5_clk>; + clock-names = "pll0_sysclk3", "div4.5"; + }; + async3_clk: async3 { + compatible = "ti,da850-async3-clksrc"; + #clock-cells = <0>; + clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; + clock-names = "pll0_sysclk2", "pll1_sysclk2"; + }; }; edma0: edma@0 { compatible = "ti,edma3-tpcc"; @@ -294,18 +378,21 @@ #dma-cells = <2>; ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; + power-domains = <&psc0 0>; }; edma0_tptc0: tptc@8000 { compatible = "ti,edma3-tptc"; reg = <0x8000 0x400>; interrupts = <13>; interrupt-names = "edm3_tcerrint"; + power-domains = <&psc0 1>; }; edma0_tptc1: tptc@8400 { compatible = "ti,edma3-tptc"; reg = <0x8400 0x400>; interrupts = <32>; interrupt-names = "edm3_tcerrint"; + power-domains = <&psc0 2>; }; edma1: edma@230000 { compatible = "ti,edma3-tpcc"; @@ -317,12 +404,14 @@ #dma-cells = <2>; ti,tptcs = <&edma1_tptc0 7>; + power-domains = <&psc1 0>; }; edma1_tptc0: tptc@238000 { compatible = "ti,edma3-tptc"; reg = <0x238000 0x400>; interrupts = <95>; interrupt-names = "edm3_tcerrint"; + power-domains = <&psc1 21>; }; serial0: serial@42000 { compatible = "ti,da830-uart", "ns16550a"; @@ -330,6 +419,8 @@ reg-io-width = <4>; reg-shift = <2>; interrupts = <25>; + clocks = <&psc0 9>; + power-domains = <&psc0 9>; status = "disabled"; }; serial1: serial@10c000 { @@ -338,6 +429,8 @@ reg-io-width = <4>; reg-shift = <2>; interrupts = <53>; + clocks = <&psc1 12>; + power-domains = <&psc1 12>; status = "disabled"; }; serial2: serial@10d000 { @@ -346,6 +439,8 @@ reg-io-width = <4>; reg-shift = <2>; interrupts = <61>; + clocks = <&psc1 13>; + power-domains = <&psc1 13>; status = "disabled"; }; rtc0: rtc@23000 { @@ -353,6 +448,8 @@ reg = <0x23000 0x1000>; interrupts = <19 19>; + clocks = <&pll0_auxclk>; + clock-names = "int-clk"; status = "disabled"; }; i2c0: i2c@22000 { @@ -361,6 +458,7 @@ interrupts = <15>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pll0_auxclk>; status = "disabled"; }; i2c1: i2c@228000 { @@ -369,11 +467,21 @@ interrupts = <51>; #address-cells = <1>; #size-cells = <0>; + clocks = <&psc1 11>; + power-domains = <&psc1 11>; status = "disabled"; }; + clocksource: timer@20000 { + compatible = "ti,da830-timer"; + reg = <0x20000 0x1000>; + interrupts = <12>, <13>; + interrupt-names = "tint12", "tint34"; + clocks = <&pll0_auxclk>; + }; wdt: wdt@21000 { compatible = "ti,davinci-wdt"; reg = <0x21000 0x1000>; + clocks = <&pll0_auxclk>; status = "disabled"; }; mmc0: mmc@40000 { @@ -384,12 +492,14 @@ interrupts = <16>; dmas = <&edma0 16 0>, <&edma0 17 0>; dma-names = "rx", "tx"; + clocks = <&psc0 5>; status = "disabled"; }; vpif: video@217000 { compatible = "ti,da850-vpif"; reg = <0x217000 0x1000>; interrupts = <92>; + power-domains = <&psc1 9>; status = "disabled"; /* VPIF capture port */ @@ -412,6 +522,7 @@ interrupts = <72>; dmas = <&edma1 28 0>, <&edma1 29 0>; dma-names = "rx", "tx"; + clocks = <&psc1 18>; status = "disabled"; }; ehrpwm0: pwm@300000 { @@ -419,6 +530,8 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x300000 0x2000>; + clocks = <&psc1 17>, <&ehrpwm_tbclk>; + clock-names = "fck", "tbclk"; status = "disabled"; }; ehrpwm1: pwm@302000 { @@ -426,6 +539,8 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x302000 0x2000>; + clocks = <&psc1 17>, <&ehrpwm_tbclk>; + clock-names = "fck", "tbclk"; status = "disabled"; }; ecap0: ecap@306000 { @@ -433,6 +548,8 @@ "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x306000 0x80>; + clocks = <&psc1 20>; + clock-names = "fck"; status = "disabled"; }; ecap1: ecap@307000 { @@ -440,6 +557,8 @@ "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x307000 0x80>; + clocks = <&psc1 20>; + clock-names = "fck"; status = "disabled"; }; ecap2: ecap@308000 { @@ -447,6 +566,8 @@ "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x308000 0x80>; + clocks = <&psc1 20>; + clock-names = "fck"; status = "disabled"; }; spi0: spi@41000 { @@ -459,6 +580,8 @@ interrupts = <20>; dmas = <&edma0 14 0>, <&edma0 15 0>; dma-names = "rx", "tx"; + clocks = <&psc0 4>; + power-domains = <&psc0 4>; status = "disabled"; }; spi1: spi@30e000 { @@ -471,6 +594,8 @@ interrupts = <56>; dmas = <&edma0 18 0>, <&edma0 19 0>; dma-names = "rx", "tx"; + clocks = <&psc1 10>; + power-domains = <&psc1 10>; status = "disabled"; }; usb0: usb@200000 { @@ -482,6 +607,8 @@ dr_mode = "otg"; phys = <&usb_phy 0>; phy-names = "usb-phy"; + clocks = <&psc1 1>; + clock-ranges; status = "disabled"; #address-cells = <1>; @@ -512,13 +639,31 @@ compatible = "ti,da850-ahci"; reg = <0x218000 0x2000>, <0x22c018 0x4>; interrupts = <67>; + clocks = <&psc1 8>, <&sata_refclk>; + clock-names = "fck", "refclk"; status = "disabled"; }; + pll1: clock-controller@21a000 { + compatible = "ti,da850-pll1"; + reg = <0x21a000 0x1000>; + clocks = <&ref_clk>; + clock-names = "clksrc"; + + pll1_sysclk: sysclk { + #clock-cells = <1>; + }; + pll1_obsclk: obsclk { + #clock-cells = <0>; + }; + }; mdio: mdio@224000 { compatible = "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x224000 0x1000>; + clocks = <&psc1 5>; + clock-names = "fck"; + power-domains = <&psc1 5>; status = "disabled"; }; eth0: ethernet@220000 { @@ -534,6 +679,8 @@ 35 36 >; + clocks = <&psc1 5>; + power-domains = <&psc1 5>; status = "disabled"; }; usb1: usb@225000 { @@ -542,6 +689,7 @@ interrupts = <59>; phys = <&usb_phy 1>; phy-names = "usb-phy"; + clocks = <&psc1 2>; status = "disabled"; }; gpio: gpio@226000 { @@ -556,6 +704,8 @@ 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>; ti,ngpio = <144>; ti,davinci-gpio-unbanked = <0>; + clocks = <&psc1 3>; + clock-names = "gpio"; status = "disabled"; interrupt-controller; #interrupt-cells = <2>; @@ -704,6 +854,17 @@ <&pmx_core 142 147 1>, <&pmx_core 143 146 1>; }; + psc1: clock-controller@227000 { + compatible = "ti,da850-psc1"; + reg = <0x227000 0x1000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, + <&async3_clk>; + clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3"; + assigned-clocks = <&async3_clk>; + assigned-clock-parents = <&pll1_sysclk 2>; + }; pinconf: pin-controller@22c00c { compatible = "ti,da850-pupd"; reg = <0x22c00c 0x8>; @@ -717,6 +878,7 @@ reg-names = "mpu", "dat"; interrupts = <54>; interrupt-names = "common"; + power-domains = <&psc1 7>; status = "disabled"; dmas = <&edma0 1 1>, <&edma0 0 1>; @@ -728,6 +890,9 @@ reg = <0x213000 0x1000>; interrupts = <52>; max-pixelclock = <37500>; + clocks = <&psc1 16>; + clock-names = "fck"; + power-domains = <&psc1 16>; status = "disabled"; }; }; @@ -739,6 +904,9 @@ reg = <0x68000000 0x00008000>; ranges = <0 0 0x60000000 0x08000000 1 0 0x68000000 0x00008000>; + clocks = <&psc0 3>; + clock-names = "aemif"; + clock-ranges; status = "disabled"; }; memctrl: memory-controller@b0000000 { -- cgit v1.2.3 From ca8e26a72dd1e1c2ead65e00abe94e87772c851e Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Tue, 26 Jun 2018 10:02:56 -0700 Subject: ARM: dts: k2g: add dt bindings to support network driver This patch add dt bindings to support network driver based on Network Sub System (NSS) found on k2g SoC. This consists of bindings for netcp node, nss qmss , pktdma, cpsw 2u version of ethss and mdio. In order to support transitioning between non-promiscuous and promiscuous modes in K2G's ethernet switch, netcp ALE needs to be enabled. Therefore this patch enables K2G's netcp ALE for that purpose. Signed-off-by: Murali Karicheri Signed-off-by: WingMan Kwok Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g-netcp.dtsi | 147 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/keystone-k2g.dtsi | 13 +++ 2 files changed, 160 insertions(+) create mode 100644 arch/arm/boot/dts/keystone-k2g-netcp.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi new file mode 100644 index 000000000000..d0e6a9a43402 --- /dev/null +++ b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for K2G Netcp driver + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +qmss: qmss@4020000 { + compatible = "ti,66ak2g-navss-qm"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k2g_pds 0x0018>; + clocks = <&k2g_clks 0x0018 0>; + clock-names = "nss_vclk"; + ranges; + queue-range = <0 0x80>; + linkram0 = <0x4020000 0x7ff>; + status = "disabled"; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x80>; + reg = <0x4100000 0x800>, + <0x4040000 0x100>, + <0x4080000 0x800>, + <0x40c0000 0x800>; + reg-names = "peek", "config", + "region", "push"; + }; + + }; + queue-pools { + qpend { + qpend-0 { + qrange = <77 8>; + interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04 + 0 311 0xf04 0 312 0xf04 0 313 0xf04 + 0 314 0xf04 0 315 0xf04>; + qalloc-by-id; + }; + }; + general-purpose { + gp-0 { + qrange = <112 8>; + }; + netcp-tx { + qrange = <5 8>; + qalloc-by-id; + }; + }; + }; + + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <1023 128>; /* num_desc desc_size */ + link-index = <0x400>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + power-domains = <&k2g_pds 0x0018>; + clocks = <&k2g_clks 0x0018 0>; + clock-names = "nss_vclk"; + ranges; + ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>; + + dma_gbe: dma_gbe@0 { + reg = <0x4010000 0x100>, + <0x4011000 0x2a0>, /* 21 Tx channels */ + <0x4012000 0x400>, /* 32 Rx channels */ + <0x4010100 0x80>, + <0x4013000 0x400>; /* 32 Rx flows */ + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; + +}; + +netcp: netcp@4000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + power-domains = <&k2g_pds 0x0018>; + clocks = <&k2g_clks 0x0018 3>, <&k2g_clks 0x0018 8>; + clock-names = "ethss_clk", "cpts"; + + /* NetCP address range */ + ranges = <0 0x4000000 0x1000000>; + + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>; + ti,navigator-dma-names = "netrx0", "nettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe: gbe@200000 { + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-2"; + reg = <0x200000 0x20>, <0x220000 0x20000>; + enable-ale; + tx-queue = <5>; + tx-channel = "nettx"; + cpts-rftclk-sel = <0>; + cpts-ext-ts-inputs = <8>; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <5>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <512 12>; + tx-pool = <511 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <77>; + tx-completion-queue = <78>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index da78c0034427..a8324a7439da 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -609,5 +609,18 @@ reg = <0x21010000 0x200>; interrupts = ; }; + + mdio: mdio@4200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + reg = <0x04200f00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k2g_clks 0x0018 3>; + clock-names = "fck"; + power-domains = <&k2g_pds 0x0018>; + status = "disabled"; + bus_freq = <2500000>; + }; + #include "keystone-k2g-netcp.dtsi" }; }; -- cgit v1.2.3 From c95ca2c797b4604487128a4aa3d07a01d16a4664 Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Tue, 26 Jun 2018 10:02:56 -0700 Subject: ARM: dts: keystone-k2g-evm: Enable netcp network driver Add dt bindings to enable netcp network driver on K2G GP EVM. This consists of enabling bindings for nss qmss, pktdma, 2u ethss, mdio, pinmux and netcp devices. Signed-off-by: Murali Karicheri Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g-evm.dts | 53 ++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index 154fdd7a7022..f028a004ac38 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -128,6 +128,30 @@ K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */ >; }; + + emac_pins: pinmux_emac_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ + K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ + K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ + K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ + K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ + K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ + K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ + K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ + K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ + K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ + K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ + K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ + >; + }; + + mdio_pins: pinmux_mdio_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ + K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ + >; + }; }; &uart0 { @@ -294,3 +318,32 @@ pinctrl-0 = <&dcan1_pins>; status = "okay"; }; + +&qmss { + status = "okay"; +}; + +&knav_dmas { + status = "okay"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&gbe0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&netcp { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins>; + status = "okay"; +}; -- cgit v1.2.3 From 1fbaa958769458fee565703f3c2077b6e7c26093 Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Tue, 26 Jun 2018 10:02:56 -0700 Subject: ARM: dts: keystone-k2g-ice: Enable netcp network driver This patch adds dt bindings to enable netcp network driver on K2G ICE boards. This consists of enabling bindings for NSS qmss, pktdma, 2u ethss, mdio, pinmux and netcp devices as well as DP83867 phy. EVM hardware spec recommends to add 0.25 nsec delay in the tx direction and 2.25 nsec delay in the rx direction for internal delay in the clock path to be on the safer side. The board straps RX_DV/RX_CTRL pin of on board DP83867 phy in mode 1. The phy data manual disallows this. Add ti,dp83867-rxctrl-strap-quirk in the phy node to allow software to enable the workaround suggested for this incorrect strap setting. This ensures proper operation of this PHY. Signed-off-by: Murali Karicheri Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g-ice.dts | 59 ++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts index d820ed2474bb..2a2d38cf0fff 100644 --- a/arch/arm/boot/dts/keystone-k2g-ice.dts +++ b/arch/arm/boot/dts/keystone-k2g-ice.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "keystone-k2g.dtsi" +#include / { compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone"; @@ -281,6 +282,30 @@ K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.gpio0_102 */ >; }; + + emac_pins: pinmux_emac_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ + K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ + K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ + K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ + K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ + K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ + K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ + K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ + K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ + K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ + K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ + K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ + >; + }; + + mdio_pins: pinmux_mdio_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ + K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ + >; + }; }; &uart0 { @@ -386,3 +411,37 @@ vcc-supply = <&vdd_3v3>; }; }; + +&qmss { + status = "okay"; +}; + +&knav_dmas { + status = "okay"; +}; + +&netcp { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins>; + status = "okay"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + ethphy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + }; +}; + +&gbe0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; -- cgit v1.2.3 From 5653d72c72947ed69586d71e1e86d4a106e6af29 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Tue, 26 Jun 2018 10:02:56 -0700 Subject: ARM: dts: k2hk: add dts node for k2hk hw_rng driver This patch adds dts node for k2hk hw_random generator driver Signed-off-by: Vitaly Andrianov [t-kristo@ti.com: added missing addresses from node identifiers] Signed-off-by: Tero Kristo Signed-off-by: Murali Karicheri Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2hk-netcp.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi index b88c0689c285..e203145acbea 100644 --- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi @@ -228,3 +228,23 @@ netcp: netcp@2000000 { }; }; }; + +sa_subsys: subsys@20c0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x20c0000 0x40000>; + + sa_config: subsys@0 { + compatible = "syscon"; + reg = <0x0 0x100>; + }; + + rng@24000 { + compatible = "ti,keystone-rng"; + reg = <0x24000 0x1000>; + ti,syscon-sa-cfg = <&sa_config>; + clocks = <&clksa>; + clock-names = "fck"; + }; +}; -- cgit v1.2.3 From 3d0b6bd8717b5faa318ce0bd7ec6c048355f950f Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Tue, 26 Jun 2018 10:02:57 -0700 Subject: ARM: dts: k2l: add dts node for k2l hw_rng driver This patch adds dts node for k2l hw_random generator driver Signed-off-by: Vitaly Andrianov [t-kristo@ti.com: added missing addresses from node identifiers] Signed-off-by: Tero Kristo Signed-off-by: Murali Karicheri Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2l-netcp.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi index 9ec84228bc16..a2e47bad3307 100644 --- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi @@ -208,3 +208,23 @@ netcp: netcp@26000000 { }; }; }; + +sa_subsys: subsys@26080000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x26080000 0x40000>; + + sa_config: subsys@0 { + compatible = "syscon"; + reg = <0x0 0x100>; + }; + + rng@24000 { + compatible = "ti,keystone-rng"; + reg = <0x24000 0x1000>; + ti,syscon-sa-cfg = <&sa_config>; + clocks = <&clksa>; + clock-names = "fck"; + }; +}; -- cgit v1.2.3 From bf5ebea4812f01ef3aa73cdb8a01ca115797f43c Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Tue, 26 Jun 2018 10:02:57 -0700 Subject: ARM: dts: k2e: add dts node for k2e hw_rng driver This patch adds dts node for k2e hw_random generator driver Signed-off-by: Vitaly Andrianov Signed-off-by: Murali Karicheri Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2e-netcp.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi index a17311c602aa..1db17ec744b1 100644 --- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi @@ -225,3 +225,23 @@ netcp: netcp@24000000 { }; }; }; + +sa_subsys: subsys@24080000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x24080000 0x40000>; + + sa_config: subsys@0 { + compatible = "syscon"; + reg = <0x0 0x100>; + }; + + rng@24000 { + compatible = "ti,keystone-rng"; + reg = <0x24000 0x1000>; + ti,syscon-sa-cfg = <&sa_config>; + clocks = <&clksa>; + clock-names = "fck"; + }; +}; -- cgit v1.2.3 From ced8025b569e21c31b52cc80410ed49d0bf13368 Mon Sep 17 00:00:00 2001 From: Dennis Gilmore Date: Tue, 5 Jun 2018 17:15:45 -0500 Subject: ARM: dts: armada388-helios4 The helios4 is a Armada388 based nas board designed by SolidRun and based on their SOM. It is sold by kobol.io the dts file came from https://raw.githubusercontent.com/armbian/build/master/patch/kernel/mvebu-default/95-helios4-device-tree.patch I added a SPDX license line to match the clearfog it says it was based on and a compatible line for "kobol,helios4" Signed-off-by: Dennis Gilmore Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/armada-388-helios4.dts | 313 +++++++++++++++++++++++++++++++ 2 files changed, 314 insertions(+) create mode 100644 arch/arm/boot/dts/armada-388-helios4.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..55133fac83ab 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1138,6 +1138,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-388-clearfog-pro.dtb \ armada-388-db.dtb \ armada-388-gp.dtb \ + armada-388-helios4.dtb \ armada-388-rd.dtb dtb-$(CONFIG_MACH_ARMADA_39X) += \ armada-398-db.dtb diff --git a/arch/arm/boot/dts/armada-388-helios4.dts b/arch/arm/boot/dts/armada-388-helios4.dts new file mode 100644 index 000000000000..705adfa8c680 --- /dev/null +++ b/arch/arm/boot/dts/armada-388-helios4.dts @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Helios4 + * based on SolidRun Clearfog revision A1 rev 2.0 (88F6828) + * + * Copyright (C) 2017 Aditya Prayoga + * + */ + +/dts-v1/; +#include "armada-388.dtsi" +#include "armada-38x-solidrun-microsom.dtsi" + +/ { + model = "Helios4"; + compatible = "kobol,helios4", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + aliases { + /* So that mvebu u-boot can update the MAC addresses */ + ethernet1 = ð0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "power_brick_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_12v>; + }; + + reg_5p0v_hdd: regulator-5v-hdd { + compatible = "regulator-fixed"; + regulator-name = "5V_HDD"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_12v>; + }; + + reg_5p0v_usb: regulator-5v-usb { + compatible = "regulator-fixed"; + regulator-name = "USB-PWR"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&expander0 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_12v>; + }; + + system-leds { + compatible = "gpio-leds"; + status-led { + label = "helios4:green:status"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + fault-led { + label = "helios4:red:fault"; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; + + io-leds { + compatible = "gpio-leds"; + sata1-led { + label = "helios4:green:ata1"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata1"; + default-state = "off"; + }; + sata2-led { + label = "helios4:green:ata2"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata2"; + default-state = "off"; + }; + sata3-led { + label = "helios4:green:ata3"; + gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata3"; + default-state = "off"; + }; + sata4-led { + label = "helios4:green:ata4"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata4"; + default-state = "off"; + }; + usb-led { + label = "helios4:green:usb"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usb-host"; + default-state = "off"; + }; + }; + + fan1: j10-pwm { + compatible = "pwm-fan"; + pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */ + }; + + fan2: j17-pwm { + compatible = "pwm-fan"; + pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */ + }; + + usb2_phy: usb2-phy { + compatible = "usb-nop-xceiv"; + vbus-regulator = <®_5p0v_usb>; + }; + + usb3_phy: usb3-phy { + compatible = "usb-nop-xceiv"; + }; + + soc { + internal-regs { + i2c@11000 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* + * PCA9655 GPIO expander, up to 1MHz clock. + * 0-Board Revision bit 0 # + * 1-Board Revision bit 1 # + * 5-USB3 overcurrent + * 6-USB3 power + */ + expander0: gpio-expander@20 { + /* + * This is how it should be: + * compatible = "onnn,pca9655", + * "nxp,pca9555"; + * but you can't do this because of + * the way I2C works. + */ + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pca0_pins>; + interrupt-parent = <&gpio0>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + board_rev_bit_0 { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "board-rev-0"; + }; + board_rev_bit_1 { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + input; + line-name = "board-rev-1"; + }; + usb3_ilimit { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + input; + line-name = "usb-overcurrent-status"; + }; + }; + + temp_sensor: temp@4c { + compatible = "ti,lm75"; + reg = <0x4c>; + vcc-supply = <®_3p3v>; + }; + }; + + i2c@11100 { + /* + * External I2C Bus for user peripheral + */ + clock-frequency = <400000>; + pinctrl-0 = <&helios_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + sata@a8000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + }; + + sata1: sata-port@1 { + reg = <1>; + }; + }; + + sata@e0000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata2: sata-port@0 { + reg = <0>; + }; + + sata3: sata-port@1 { + reg = <1>; + }; + }; + + spi@10680 { + pinctrl-0 = <&spi1_pins + µsom_spi1_cs_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + sdhci@d8000 { + bus-width = <4>; + cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-0 = <&helios_sdhci_pins + &helios_sdhci_cd_pins>; + pinctrl-names = "default"; + status = "okay"; + vmmc = <®_3p3v>; + wp-inverted; + }; + + usb@58000 { + usb-phy = <&usb2_phy>; + status = "okay"; + }; + + usb3@f0000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + }; + + pinctrl@18000 { + pca0_pins: pca0-pins { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + microsom_phy0_int_pins: microsom-phy0-int-pins { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + helios_i2c1_pins: i2c1-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c1"; + }; + helios_sdhci_cd_pins: helios-sdhci-cd-pins { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + helios_sdhci_pins: helios-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; + helios_led_pins: helios-led-pins { + marvell,pins = "mpp24", "mpp25", + "mpp49", "mpp50", + "mpp52", "mpp53", + "mpp54"; + marvell,function = "gpio"; + }; + helios_fan_pins: helios-fan-pins { + marvell,pins = "mpp41", "mpp43", + "mpp48", "mpp55"; + marvell,function = "gpio"; + }; + microsom_spi1_cs_pins: spi1-cs-pins { + marvell,pins = "mpp59"; + marvell,function = "spi1"; + }; + }; + }; + }; +}; -- cgit v1.2.3 From 097f0987eb81e6156ea759194481f770c1b64183 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Tue, 26 Jun 2018 10:28:17 -0500 Subject: ARM: dts: da850: Add power-domains to PWM nodes This adds the power-domains property to both the ECAP and EHRPWM PWM nodes. Both have drivers that use pm_runtime to enable the clocks, so they need this property in order to find and enable the clock properly. Signed-off-by: David Lechner Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index de9a8bea100e..d60198e2ae4e 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -532,6 +532,7 @@ reg = <0x300000 0x2000>; clocks = <&psc1 17>, <&ehrpwm_tbclk>; clock-names = "fck", "tbclk"; + power-domains = <&psc1 17>; status = "disabled"; }; ehrpwm1: pwm@302000 { @@ -541,6 +542,7 @@ reg = <0x302000 0x2000>; clocks = <&psc1 17>, <&ehrpwm_tbclk>; clock-names = "fck", "tbclk"; + power-domains = <&psc1 17>; status = "disabled"; }; ecap0: ecap@306000 { @@ -550,6 +552,7 @@ reg = <0x306000 0x80>; clocks = <&psc1 20>; clock-names = "fck"; + power-domains = <&psc1 20>; status = "disabled"; }; ecap1: ecap@307000 { @@ -559,6 +562,7 @@ reg = <0x307000 0x80>; clocks = <&psc1 20>; clock-names = "fck"; + power-domains = <&psc1 20>; status = "disabled"; }; ecap2: ecap@308000 { @@ -568,6 +572,7 @@ reg = <0x308000 0x80>; clocks = <&psc1 20>; clock-names = "fck"; + power-domains = <&psc1 20>; status = "disabled"; }; spi0: spi@41000 { -- cgit v1.2.3 From 4729bef965e5309295b1e01a04b3248ce3060800 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 31 May 2018 15:25:48 -0500 Subject: ARM: dts: da850-lego-ev3: Add Bluetooth nodes This adds nodes for describing the Bluetooth chip and connections on LEGO MINDSTORMS EV3 to da850-lego-ev3.dts. Signed-off-by: David Lechner Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-lego-ev3.dts | 82 ++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts index 331362a6f01e..c4729d0e6c19 100644 --- a/arch/arm/boot/dts/da850-lego-ev3.dts +++ b/arch/arm/boot/dts/da850-lego-ev3.dts @@ -173,6 +173,15 @@ rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>; }; + bt_slow_clk: bt-clock { + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>, <&bt_clock_bias>; + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&ecap2 0 30518 0>; + }; + /* ARM local RAM */ memory@ffff0000 { compatible = "syscon", "simple-mfd"; @@ -216,6 +225,20 @@ bias-disable; }; }; + + bt_clock_bias: bt-clock-bias-groups { + disable { + groups = "cp2"; + bias-disable; + }; + }; + + bt_pic_bias: bt-pic-bias-groups { + disable { + groups = "cp20"; + bias-disable; + }; + }; }; /* Input port 1 */ @@ -225,6 +248,22 @@ pinctrl-0 = <&serial1_rxtx_pins>; }; +&serial2 { + pinctrl-names = "default"; + pinctrl-0 = <&serial2_rxtx_pins>, <&serial2_rtscts_pins>, <&bt_pic_bias>; + status = "okay"; + + bluetooth { + compatible = "ti,cc2560"; + clocks = <&bt_slow_clk>; + clock-names = "ext_clock"; + enable-gpios = <&gpio 73 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + nvmem-cells = <&bdaddr>; + nvmem-cell-names = "bd-address"; + }; +}; + &rtc0 { status = "okay"; }; @@ -243,6 +282,12 @@ pagesize = <64>; read-only; reg = <0x50>; + #address-cells = <1>; + #size-cells = <1>; + + bdaddr: bdaddr@3f06 { + reg = <0x3f06 0x06>; + }; }; }; @@ -327,6 +372,10 @@ }; }; +&ecap2 { + status = "okay"; +}; + &ehrpwm0 { status = "okay"; }; @@ -340,6 +389,39 @@ gpios = <6 GPIO_ACTIVE_HIGH>; output-high; }; + + /* Don't impede Bluetooth clock signal */ + bt_clock_en { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + input; + }; + + /* + * There is a PIC microcontroller for interfacing with an Apple MFi + * chip. This interferes with normal Bluetooth operation, so we need + * to make sure it is turned off. Note: The publicly available + * schematics from LEGO don't show that these pins are connected to + * anything, but they are present in the source code from LEGO. + */ + + bt_pic_en { + gpio-hog; + gpios = <51 GPIO_ACTIVE_HIGH>; + output-low; + }; + + bt_pic_rst { + gpio-hog; + gpios = <78 GPIO_ACTIVE_HIGH>; + output-high; + }; + + bt_pic_cts { + gpio-hog; + gpios = <87 GPIO_ACTIVE_HIGH>; + input; + }; }; &usb_phy { -- cgit v1.2.3 From 328bd82526156fbc42372d22ff1967dc145d81c8 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Wed, 13 Dec 2017 15:24:06 +0100 Subject: ARM: dts: imx51: add CodaHx4 VPU Add the CodaHx4 VPU to the i.MX51 device tree. Signed-off-by: Philipp Zabel Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index fe01b890c715..3f65492c6589 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -588,6 +588,17 @@ clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; + + vpu@83ff4000 { + compatible = "fsl,imx51-vpu", "cnm,codahx4"; + reg = <0x83ff4000 0x1000>; + interrupts = <9>; + clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, + <&clks IMX5_CLK_VPU_GATE>; + clock-names = "per", "ahb"; + resets = <&src 1>; + iram = <&iram>; + }; }; }; }; -- cgit v1.2.3 From f3d80deb080f422ff1df4a715444f156bb51adc1 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 8 Jun 2018 11:06:40 +0200 Subject: ARM: dts: imx: add cooling-cells for cpufreq cooling device Add #cooling-cells for i.MX6/7 SoCs for cpufreq cooling device usage. Signed-off-by: Anson Huang Signed-off-by: Bastian Stender Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl.dtsi | 1 + arch/arm/boot/dts/imx6q.dtsi | 1 + arch/arm/boot/dts/imx6sl.dtsi | 1 + arch/arm/boot/dts/imx6sx.dtsi | 1 + arch/arm/boot/dts/imx6ul.dtsi | 1 + arch/arm/boot/dts/imx7d.dtsi | 1 + 6 files changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index b384913c34dd..a1acd4ddcb1a 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -33,6 +33,7 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6QDL_CLK_ARM>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 70483ce72ba6..894401c5db09 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -38,6 +38,7 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6QDL_CLK_ARM>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 994e48dc1df0..81f48116c5b1 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -60,6 +60,7 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PLL1_SYS>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index d8b94f47498b..7130ab8a7518 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -79,6 +79,7 @@ 198000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6SX_CLK_ARM>, <&clks IMX6SX_CLK_PLL2_PFD2>, <&clks IMX6SX_CLK_STEP>, diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 47a3453a4211..36572b62a4af 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -62,6 +62,7 @@ device_type = "cpu"; reg = <0>; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; operating-points = < /* kHz uV */ 696000 1275000 diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 8d3d123d0a5c..7cbc2ffa4b3a 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -11,6 +11,7 @@ cpu0: cpu@0 { clock-frequency = <996000000>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu1: cpu@1 { -- cgit v1.2.3 From fdfbd7d125fd8e2536954fdd63a5738bceb7896f Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Mon, 18 Jun 2018 17:42:57 +0200 Subject: ARM: dts: imx6: RIoTboard Add chosen stdout-path property The RIoTboard debug uart is connected to serial1. Add a chosen property in the DTS so OS knows what serial port to use for the console. Signed-off-by: Emmanuel Vadot Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-riotboard.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 89b06e20480d..dd3226fe5ecd 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -19,6 +19,10 @@ reg = <0x10000000 0x40000000>; }; + chosen { + stdout-path = "serial1:115200n8"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; -- cgit v1.2.3 From eecd78bc7805964527acdaba5f2b91d7b317aeea Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 20 Jun 2018 16:38:37 +0800 Subject: ARM: dts: imx6sll: declare src module to be compatible to imx51's src i.MX6SLL uses same SRC module as i.MX51, add "fsl,imx51-src" compatible string to enable SRC driver to support setting CPU resume address for cpu-idle and suspend/resume. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index c9b0ccc0e2e2..000e6136a9d6 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -548,7 +548,7 @@ }; src: reset-controller@20d8000 { - compatible = "fsl,imx6sll-src"; + compatible = "fsl,imx6sll-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = , ; -- cgit v1.2.3 From 05a43a262d0360e2ff684862d989ac0fd3cc9e69 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 25 Jun 2018 14:03:03 +0200 Subject: ARM: dts: sun8i: r40: Add HDMI pipeline Add all entries needed for HDMI to function properly. Since R40 has highly configurable pipeline, both mixers and both TCON TVs are added. Board specific DT should then connect them together trough TCON TOP muxers to best fit the purpose of the board. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 268 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 268 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index bd97ca3dc2fa..c95a59aac48f 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -42,8 +42,10 @@ */ #include +#include #include #include +#include / { #address-cells = <1>; @@ -99,12 +101,76 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-r40-display-engine", + "allwinner,sun8i-h3-display-engine"; + allwinner,pipelines = <&mixer0>, <&mixer1>; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-r40-de2-clk", + "allwinner,sun8i-h3-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-r40-de2-mixer-0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + mixer0_out_tcon_top: endpoint { + remote-endpoint = <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@1200000 { + compatible = "allwinner,sun8i-r40-de2-mixer-1"; + reg = <0x01200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_WB>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + reg = <1>; + mixer1_out_tcon_top: endpoint { + remote-endpoint = <&tcon_top_mixer1_in_mixer1>; + }; + }; + }; + }; + nmi_intc: interrupt-controller@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; @@ -485,6 +551,163 @@ }; }; + tcon_top: tcon-top@1c70000 { + compatible = "allwinner,sun8i-r40-tcon-top"; + reg = <0x01c70000 0x1000>; + clocks = <&ccu CLK_BUS_TCON_TOP>, + <&ccu CLK_TCON_TV0>, + <&ccu CLK_TVE0>, + <&ccu CLK_TCON_TV1>, + <&ccu CLK_TVE1>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", + "tcon-tv0", + "tve0", + "tcon-tv1", + "tve1", + "dsi"; + clock-output-names = "tcon-top-tv0", + "tcon-top-tv1", + "tcon-top-dsi"; + resets = <&ccu RST_BUS_TCON_TOP>; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in: port@0 { + reg = <0>; + + tcon_top_mixer0_in_mixer0: endpoint { + remote-endpoint = <&mixer0_out_tcon_top>; + }; + }; + + tcon_top_mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { + reg = <0>; + }; + + tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { + reg = <1>; + }; + + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { + reg = <2>; + }; + + tcon_top_mixer0_out_tcon_tv1: endpoint@3 { + reg = <3>; + }; + }; + + tcon_top_mixer1_in: port@2 { + reg = <2>; + + tcon_top_mixer1_in_mixer1: endpoint { + remote-endpoint = <&mixer1_out_tcon_top>; + }; + }; + + tcon_top_mixer1_out: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { + reg = <0>; + }; + + tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { + reg = <1>; + }; + + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { + reg = <2>; + }; + + tcon_top_mixer1_out_tcon_tv1: endpoint@3 { + reg = <3>; + }; + }; + + tcon_top_hdmi_in: port@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + tcon_top_hdmi_in_tcon_tv0: endpoint@0 { + reg = <0>; + }; + + tcon_top_hdmi_in_tcon_tv1: endpoint@1 { + reg = <1>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg = <5>; + + tcon_top_hdmi_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_tcon_top>; + }; + }; + }; + }; + + tcon_tv0: lcd-controller@1c73000 { + compatible = "allwinner,sun8i-r40-tcon-tv", + "allwinner,sun8i-a83t-tcon-tv"; + reg = <0x01c73000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV0>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv0_in: port@0 { + reg = <0>; + }; + + tcon_tv0_out: port@1 { + reg = <1>; + }; + }; + }; + + tcon_tv1: lcd-controller@1c74000 { + compatible = "allwinner,sun8i-r40-tcon-tv", + "allwinner,sun8i-a83t-tcon-tv"; + reg = <0x01c74000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV1>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv1_in: port@0 { + reg = <0>; + }; + + tcon_tv1_out: port@1 { + reg = <1>; + }; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, @@ -495,6 +718,51 @@ #interrupt-cells = <3>; interrupts = ; }; + + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun8i-r40-dw-hdmi", + "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>; + clock-names = "iahb", "isfr", "tmds"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "hdmi-phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon_top: endpoint { + remote-endpoint = <&tcon_top_hdmi_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun8i-r40-hdmi-phy", + "allwinner,sun50i-a64-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, + <&ccu 7>, <&ccu 16>; + clock-names = "bus", "mod", "pll-0", "pll-1"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; + }; }; timer { -- cgit v1.2.3 From db49c6825901756e711123d948034661f5b075d9 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 25 Jun 2018 14:03:04 +0200 Subject: ARM: dts: sun8i: r40: Enable HDMI output on BananaPi M2 Ultra Since HDMI can be considered as main output, most capable mixer is connected to it (mixer0). Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 45 +++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 25fb048c7df2..4f3d583183dc 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -59,6 +59,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -94,6 +105,10 @@ }; }; +&de { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -118,6 +133,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { status = "okay"; @@ -226,6 +251,26 @@ regulator-name = "vcc-wifi"; }; +&tcon_top_hdmi_in_tcon_tv0 { + remote-endpoint = <&tcon_tv0_out_tcon_top>; +}; + +&tcon_top_mixer0_out_tcon_tv0 { + remote-endpoint = <&tcon_tv0_in_tcon_top>; +}; + +&tcon_tv0_in { + tcon_tv0_in_tcon_top: endpoint { + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; + }; +}; + +&tcon_tv0_out { + tcon_tv0_out_tcon_top: endpoint { + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; -- cgit v1.2.3 From 75ab939394fd0b262ad4b5625a55c2895a73c065 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 27 Jun 2018 10:27:09 +0800 Subject: ARM: dts: sun8i: a83t: Add CPU regulator supplies for A83T boards The OPPs for the A83T CPU cores were added in v4.17 in commit 2db639d8c166 ("ARM: dts: sun8i: a83t: add stable OPP tables and CPUfreq"), but board level regulator supplies for the CPU clusters were only added for the TBS-A711 tablet. This means the other A83T boards do not benefit from voltage scaling, or worse, if the implementation does not scale the frequency when the voltage is fixed, no benefit at all. Add board level CPU cluster power supplies to all the A83T development boards, so they can have proper dynamic CPU voltage and frequency scaling. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 8 ++++++++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 8 ++++++++ arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 8 ++++++++ 3 files changed, 24 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 36ecebaff3c0..1c012a4def16 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -79,6 +79,14 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu100 { + cpu-supply = <®_dcdc3>; +}; + &ehci0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index 3b579d7567c8..c7ce4158d6c8 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -107,6 +107,14 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu100 { + cpu-supply = <®_dcdc3>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index 88decb0747ac..e5f0645e53a7 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -145,6 +145,14 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu100 { + cpu-supply = <®_dcdc3>; +}; + &ehci0 { /* GL830 USB-to-SATA bridge here */ status = "okay"; -- cgit v1.2.3 From bb683d7ad9d53442586cfdd0a79a6d6c1fec344e Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 28 Jun 2018 10:13:35 +0300 Subject: ARM: dts: armada388-clearfog: enable spi flash The SolidRun Armada 388 SOM has the SPI flash populated by default unless the customer explicitly asks otherwise. Enable support by default. Signed-off-by: Baruch Siach Acked-by: Russell King Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-388-clearfog.dts | 2 +- arch/arm/boot/dts/armada-388-clearfog.dtsi | 2 +- arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 1 - 3 files changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts index 5fd0f6f61e77..af76b6cafc63 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/armada-388-clearfog.dts @@ -235,7 +235,7 @@ &spi1 { /* * Add SPI CS pins for clearfog: - * CS0: W25Q32 (not populated on uSOM) + * CS0: W25Q32 * CS1: * CS2: mikrobus */ diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi index 0d9dfdfe977e..e7618e6c5ad5 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dtsi +++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi @@ -230,7 +230,7 @@ &spi1 { /* * Add SPI CS pins for clearfog: - * CS0: W25Q32 (not populated on uSOM) + * CS0: W25Q32 * CS1: PIC microcontroller (Pro models) * CS2: mikrobus */ diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi index 2d1cea131e71..c990d502d9a4 100644 --- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi @@ -99,7 +99,6 @@ compatible = "w25q32", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <3000000>; - status = "disabled"; }; }; -- cgit v1.2.3 From 96487173aaf69216fe4d7f8241ef42a539969789 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 28 Jun 2018 10:13:36 +0300 Subject: ARM: dts: armada388-clearfog: drop future changes disclaimer The current device-tree description of the SolidRun Armada 38x platforms has been successfully tested with production systems. Signed-off-by: Baruch Siach Acked-by: Jon Nettleton Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-388-clearfog-base.dts | 5 ----- arch/arm/boot/dts/armada-388-clearfog-pro.dts | 5 ----- arch/arm/boot/dts/armada-388-clearfog.dts | 5 ----- arch/arm/boot/dts/armada-388-clearfog.dtsi | 5 ----- arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 5 ----- 5 files changed, 25 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/armada-388-clearfog-base.dts index 50ed4ae5c621..53b4bd35522a 100644 --- a/arch/arm/boot/dts/armada-388-clearfog-base.dts +++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts @@ -3,11 +3,6 @@ * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828) * * Copyright (C) 2015 Russell King - * - * This board is in development; the contents of this file work with - * the A1 rev 2.0 of the board, which does not represent final - * production board. Things will change, don't expect this file to - * remain compatible info the future. */ /dts-v1/; diff --git a/arch/arm/boot/dts/armada-388-clearfog-pro.dts b/arch/arm/boot/dts/armada-388-clearfog-pro.dts index 24e4b5a509be..ff890c09c3ed 100644 --- a/arch/arm/boot/dts/armada-388-clearfog-pro.dts +++ b/arch/arm/boot/dts/armada-388-clearfog-pro.dts @@ -3,11 +3,6 @@ * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) * * Copyright (C) 2015 Russell King - * - * This board is in development; the contents of this file work with - * the A1 rev 2.0 of the board, which does not represent final - * production board. Things will change, don't expect this file to - * remain compatible info the future. */ #include "armada-388-clearfog.dts" diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts index af76b6cafc63..89a354b43978 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/armada-388-clearfog.dts @@ -3,11 +3,6 @@ * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) * * Copyright (C) 2015 Russell King - * - * This board is in development; the contents of this file work with - * the A1 rev 2.0 of the board, which does not represent final - * production board. Things will change, don't expect this file to - * remain compatible info the future. */ /dts-v1/; diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi index e7618e6c5ad5..7c6ad2afb094 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dtsi +++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi @@ -3,11 +3,6 @@ * Device Tree include file for SolidRun Clearfog 88F6828 based boards * * Copyright (C) 2015 Russell King - * - * This board is in development; the contents of this file work with - * the A1 rev 2.0 of the board, which does not represent final - * production board. Things will change, don't expect this file to - * remain compatible info the future. */ #include "armada-388.dtsi" diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi index c990d502d9a4..3a7f9c1ac346 100644 --- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi @@ -3,11 +3,6 @@ * Device Tree file for SolidRun Armada 38x Microsom * * Copyright (C) 2015 Russell King - * - * This board is in development; the contents of this file work with - * the A1 rev 2.0 of the board, which does not represent final - * production board. Things will change, don't expect this file to - * remain compatible info the future. */ #include #include -- cgit v1.2.3 From e66e39982ed1f9ee85e9b87fec9c1183b006edc4 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Sat, 23 Jun 2018 21:37:45 +0200 Subject: ARM: dts: pxa: add label to lcd controller node So it can be referenced and filled with more details from board files. Signed-off-by: Daniel Mack Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa2xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index e4ebcde17837..a520b4c14ea9 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -141,7 +141,7 @@ interrupts = <30 31>; }; - lcd-controller@40500000 { + lcdc: lcd-controller@40500000 { compatible = "marvell,pxa2xx-lcdc"; reg = <0x44000000 0x10000>; interrupts = <17>; -- cgit v1.2.3 From 267a113cec976227810f99caf8eaa51f450f5a55 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Sun, 24 Jun 2018 19:42:05 +0200 Subject: arm: dts: pxa3xx: provide correct clk-names property for nand controller node The NAND driver looks for a clock named "core" and falls back to a pdev clock that has a wrong rate if not set. Signed-off-by: Daniel Mack Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa3xx.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 132a3b8ab148..01b2af103825 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -135,6 +135,7 @@ reg = <0x43100000 90>; interrupts = <45>; clocks = <&clks CLK_NAND>; + clock-names = "core"; dmas = <&pdma 97 3>; dma-names = "data"; #address-cells = <1>; -- cgit v1.2.3 From 49e414c32053554736c421b1ac5b645f5c73e879 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Sun, 24 Jun 2018 19:41:34 +0200 Subject: arm: dts: pxa3xx: Add ssp ports to pxa3xx device tree Also fix the documentation for these bindings. The DMA properties have to be passed in the ssp users for now. Signed-off-by: Daniel Mack Signed-off-by: Robert Jarzmik --- .../devicetree/bindings/sound/mrvl,pxa-ssp.txt | 8 ++---- arch/arm/boot/dts/pxa3xx.dtsi | 32 ++++++++++++++++++++++ 2 files changed, 35 insertions(+), 5 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/sound/mrvl,pxa-ssp.txt b/Documentation/devicetree/bindings/sound/mrvl,pxa-ssp.txt index 74c9ba6c2823..efd3fb1f68d2 100644 --- a/Documentation/devicetree/bindings/sound/mrvl,pxa-ssp.txt +++ b/Documentation/devicetree/bindings/sound/mrvl,pxa-ssp.txt @@ -9,20 +9,18 @@ Example: /* upstream device */ - ssp0: ssp@41000000 { + ssp1: ssp@41000000 { compatible = "mrvl,pxa3xx-ssp"; reg = <0x41000000 0x40>; interrupts = <24>; clock-names = "pxa27x-ssp.0"; - dmas = <&dma 13 - &dma 14>; - dma-names = "rx", "tx"; }; /* DAI as user */ ssp_dai0: ssp_dai@0 { compatible = "mrvl,pxa-ssp-dai"; - port = <&ssp0>; + port = <&ssp1>; + #sound-dai-cells = <0>; }; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 01b2af103825..3a8f0edc3af9 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -243,6 +243,38 @@ clocks = <&clks CLK_PWM1>; status = "disabled"; }; + + ssp1: ssp@41000000 { + compatible = "mrvl,pxa3xx-ssp"; + reg = <0x41000000 0x40>; + interrupts = <24>; + clocks = <&clks CLK_SSP1>; + status = "disabled"; + }; + + ssp2: ssp@41700000 { + compatible = "mrvl,pxa3xx-ssp"; + reg = <0x41700000 0x40>; + interrupts = <16>; + clocks = <&clks CLK_SSP2>; + status = "disabled"; + }; + + ssp3: ssp@41900000 { + compatible = "mrvl,pxa3xx-ssp"; + reg = <0x41900000 0x40>; + interrupts = <0>; + clocks = <&clks CLK_SSP3>; + status = "disabled"; + }; + + ssp4: ssp@41a00000 { + compatible = "mrvl,pxa3xx-ssp"; + reg = <0x41a00000 0x40>; + interrupts = <13>; + clocks = <&clks CLK_SSP4>; + status = "disabled"; + }; }; clocks { -- cgit v1.2.3 From bb601b38ddceb6e2b37e4695b2f98e64e4775b66 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Fri, 29 Jun 2018 15:57:18 -0700 Subject: ARM: dts: keystone-k2g-evm: Add "vqmmc-supply" property for mmc0/mmc1 Add "vqmmc-supply" property for mmc0/mmc1 to indicate the supply connected to the IO lines. Also add dt node for ldo1 regulator required for mmc1 vqmmc-supply. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g-evm.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index f028a004ac38..b7f10bf94576 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -37,6 +37,14 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 { + compatible = "regulator-fixed"; + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; }; &k2g_pinctrl { @@ -168,6 +176,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; vmmc-supply = <&vcc3v3_dcin_reg>; + vqmmc-supply = <&vcc3v3_dcin_reg>; cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -176,6 +185,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */ + vqmmc-supply = <&vcc1v8_ldo1_reg>; ti,non-removable; status = "okay"; }; -- cgit v1.2.3 From f7e8a182a41e791cca3d7a9e25adddf2908bddde Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Fri, 29 Jun 2018 15:57:27 -0700 Subject: ARM: dts: keystone-k2g-evm: Use sdhci-omap programming model Use sdhci-omap programming model based on the generic sdhci library for programming the MMC/SD controller. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index a8324a7439da..738b44cf2b0b 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -391,13 +391,10 @@ }; mmc0: mmc@23000000 { - compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc"; + compatible = "ti,k2g-sdhci"; reg = <0x23000000 0x400>; interrupts = ; - dmas = <&edma1 24 0>, <&edma1 25 0>; - dma-names = "tx", "rx"; bus-width = <4>; - ti,needs-special-reset; no-1-8-v; max-frequency = <96000000>; power-domains = <&k2g_pds 0xb>; @@ -407,13 +404,12 @@ }; mmc1: mmc@23100000 { - compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc"; + compatible = "ti,k2g-sdhci"; reg = <0x23100000 0x400>; interrupts = ; - dmas = <&edma1 26 0>, <&edma1 27 0>; - dma-names = "tx", "rx"; bus-width = <8>; - ti,needs-special-reset; + no-1-8-v; + non-removable; max-frequency = <96000000>; power-domains = <&k2g_pds 0xc>; clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>; -- cgit v1.2.3 From 4a23e6ee9f691cfbd6bfc99c2c5aa8d23d8c1662 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Wed, 20 Jun 2018 13:41:16 +0300 Subject: ARM: dts: imx7d-sdb: Restore pwm backlight support This was removed in commit 5eaeaccdaedb ("ARM: dts: imx7d-sdb: Pass 'enable-gpios' and 'power-supply' properties") with a note claiming that GPIO1_IO01 is connected to a pin labeled as "PWREN" on the connector. Despite that label this pin does actually work as a PWM controlling brightness. So restore pwm functionality. Signed-off-by: Leonard Crestez Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 9f9e6a1e3b72..8d137acb9f07 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -108,10 +108,17 @@ gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + panel { compatible = "innolux,at043tn24"; - pinctrl-0 = <&pinctrl_backlight>; - enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; power-supply = <®_lcd_3v3>; port { @@ -704,6 +711,12 @@ }; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + &iomuxc_lpsr { pinctrl_wdog: wdoggrp { fsl,pins = < @@ -711,9 +724,9 @@ >; }; - pinctrl_backlight: backlightgrp { + pinctrl_pwm1: pwm1grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x110b0 + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 >; }; }; -- cgit v1.2.3 From ba72b5a49957d92bfa7101a67e2414e166847291 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Jun 2018 15:06:19 -0300 Subject: ARM: dts: imx51: Add aipstz nodes Currently when trying to use the 'devmem' tool to read/write registers the following bus error is observed: [ 82.689185] Unhandled fault: external abort on non-linefetch (0x1018) at 0xb6ff10c4 [ 82.697071] pgd = (ptrval) [ 82.699920] [b6ff10c4] *pgd=a87c5831, *pte=73fa8383, *ppte=73fa8a33 Bus error Add the aipstz nodes, so that the following function from imx51_dt_init() can work properly: imx_aips_allow_unprivileged_access("fsl,imx51-aipstz"); After adding these nodes, 'devmem' tool can work correctly, which is very useful for debugging purposes. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 3f65492c6589..d5ba31e3cd50 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -250,6 +250,11 @@ }; }; + aipstz1: bridge@73f00000 { + compatible = "fsl,imx51-aipstz"; + reg = <0x73f00000 0x60>; + }; + usbotg: usb@73f80000 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80000 0x0200>; @@ -435,6 +440,11 @@ reg = <0x80000000 0x10000000>; ranges; + aipstz2: bridge@83f00000 { + compatible = "fsl,imx51-aipstz"; + reg = <0x83f00000 0x60>; + }; + iim: iim@83f98000 { compatible = "fsl,imx51-iim", "fsl,imx27-iim"; reg = <0x83f98000 0x4000>; -- cgit v1.2.3 From ff6f5a691cd9f346e323c2a74937c1af5025f751 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Sun, 24 Jun 2018 05:59:29 +0000 Subject: ARM: dts: imx50: fix KPP pin definition typos iMX50 pin mux options for pads KEY_COL2 and KEY_COL3 allow muxing the same KEY_COL instances as the pad name. Fix typos shifting KEY_COL instances. Signed-off-by: Alexander Kurz Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50-pinfunc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx50-pinfunc.h b/arch/arm/boot/dts/imx50-pinfunc.h index 97e6e7f4ebdd..43863347362e 100644 --- a/arch/arm/boot/dts/imx50-pinfunc.h +++ b/arch/arm/boot/dts/imx50-pinfunc.h @@ -34,7 +34,7 @@ #define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0 #define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 0x02c 0x2d8 0x000 0x6 0x0 #define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR 0x02c 0x2d8 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL2__KPP_COL_1 0x030 0x2dc 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL2__KPP_COL_2 0x030 0x2dc 0x000 0x0 0x0 #define MX50_PAD_KEY_COL2__GPIO4_4 0x030 0x2dc 0x000 0x1 0x0 #define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0 #define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 0x030 0x2dc 0x000 0x6 0x0 @@ -44,7 +44,7 @@ #define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0 #define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 0x034 0x2e0 0x000 0x6 0x0 #define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 0x034 0x2e0 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL3__KPP_COL_2 0x038 0x2e4 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL3__KPP_COL_3 0x038 0x2e4 0x000 0x0 0x0 #define MX50_PAD_KEY_COL3__GPIO4_6 0x038 0x2e4 0x000 0x1 0x0 #define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0 #define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 0x038 0x2e4 0x7b8 0x6 0x0 -- cgit v1.2.3 From 54c43959ab7066fb2acf0427d6a1bb983d9971b4 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Sun, 24 Jun 2018 06:15:38 +0000 Subject: ARM: dts: imx50: remove non-existent USB instances According to the i.MX50 Reference Manual, the SoC features one USB OTG and one host controller. Remove the non-existent instances from the DTS which probably got initially copied from the mx53 DTS. Signed-off-by: Alexander Kurz Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50-evk.dts | 8 -------- arch/arm/boot/dts/imx50.dtsi | 18 ------------------ 2 files changed, 26 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts index f0622ec4ba9c..682a99783ee6 100644 --- a/arch/arm/boot/dts/imx50-evk.dts +++ b/arch/arm/boot/dts/imx50-evk.dts @@ -98,14 +98,6 @@ status = "okay"; }; -&usbh2 { - status = "okay"; -}; - -&usbh3 { - status = "okay"; -}; - &usbotg { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index a9b712db9f6c..7fae2ffb76fe 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -209,24 +209,6 @@ status = "disabled"; }; - usbh2: usb@53f80400 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80400 0x0200>; - interrupts = <16>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh3: usb@53f80600 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80600 0x0200>; - interrupts = <17>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - dr_mode = "host"; - status = "disabled"; - }; - gpio1: gpio@53f84000 { compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; reg = <0x53f84000 0x4000>; -- cgit v1.2.3 From 76744502ff328a0a00ca46601da871a96539997d Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Mon, 25 Jun 2018 23:09:32 +0300 Subject: ARM: dts: imx: Add missing chosen/stdout-path This makes it possible to enable earlycon for debugging by just passing an empty "earlycon" argument on the kernel command-line. Signed-off-by: Leonard Crestez Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++++ arch/arm/boot/dts/imx6sl-evk.dts | 4 ++++ arch/arm/boot/dts/imx6sll-evk.dts | 4 ++++ arch/arm/boot/dts/imx7d-sdb.dts | 4 ++++ 4 files changed, 16 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index a59a0fd1eb02..9f11f1fcc3e6 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -6,6 +6,10 @@ #include / { + chosen { + stdout-path = &uart4; + }; + memory@10000000 { reg = <0x10000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 92ad01f676e3..50bdc65670a3 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -12,6 +12,10 @@ model = "Freescale i.MX6 SoloLite EVK Board"; compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; + chosen { + stdout-path = &uart1; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 4684ac4a816b..25438ea03092 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -15,6 +15,10 @@ model = "Freescale i.MX6SLL EVK Board"; compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; + chosen { + stdout-path = &uart1; + }; + memory@80000000 { reg = <0x80000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 8d137acb9f07..c9b3c60b0eb2 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -10,6 +10,10 @@ model = "Freescale i.MX7 SabreSD Board"; compatible = "fsl,imx7d-sdb", "fsl,imx7d"; + chosen { + stdout-path = &uart1; + }; + memory@80000000 { reg = <0x80000000 0x80000000>; }; -- cgit v1.2.3 From 10d11dad4a4e343652fca86bda3b10684be30d4e Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 26 Jun 2018 16:52:41 +0200 Subject: ARM: dts: imx6qdl-colibri: mux SD/MMC card detect explicitly Do not rely on reset/boot defaults and use a default GPIO setting with pull-up enabled. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 76035db96f67..83d7c7d48c3f 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -567,7 +567,7 @@ pinctrl_mmc_cd: gpiommccd { fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 >; }; -- cgit v1.2.3 From c768224360094b3e3b11c81a4163a9e1c7bd3336 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 26 Jun 2018 16:52:42 +0200 Subject: ARM: dts: imx6qdl-colibri: move card detect to module device tree Muxing the card detect only in the carrier board device tree overwrites the USDHC muxing in the module level device tree. Move card detect to the module level device tree since this is also a default pinout of the Colibri standard. If a carrier board requires a different setting it still can overwrite the nodes in the carrier board specific device tree. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 3 --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 3 ++- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 3dee3af1a4c1..9de45a717356 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -221,9 +221,6 @@ /* Colibri MMC */ &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc_cd>; - cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 83d7c7d48c3f..55c90c2fbf69 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -385,7 +385,8 @@ /* Colibri MMC */ &usdhc1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ vqmmc-supply = <®_3p3v>; bus-width = <4>; voltage-ranges = <3300 3300>; -- cgit v1.2.3 From c4288946d43ed2d76247ab757581ce428c90d9ef Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 26 Jun 2018 16:52:43 +0200 Subject: ARM: dts: imx6qdl-colibri: use pull-down on wake-up pin The wake-up pin is pulled low with 100kOhm on the carrier board. The current configuration of 100kOhm pull-up caused lots of interrupts, especially during boot up. Make sure the pin is at a reasonable level at startup by pulling it low on SoC side too. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 55c90c2fbf69..6e937ca20869 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -480,8 +480,7 @@ pinctrl_gpio_keys: gpiokeys { fsl,pins = < - /* Power button */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 >; }; -- cgit v1.2.3 From 9152743b298ef67619766eb55a6ac31055eb5b46 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 26 Jun 2018 20:18:52 -0300 Subject: ARM: dts: imx51: Add sahara crypto support The sahara crypto block on i.MX51 has the same IP version as the one on i.MX53. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index d5ba31e3cd50..5bb727a5b6a3 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -609,6 +609,15 @@ resets = <&src 1>; iram = <&iram>; }; + + sahara: crypto@83ff8000 { + compatible = "fsl,imx53-sahara", "fsl,imx51-sahara"; + reg = <0x83ff8000 0x4000>; + interrupts = <19 20>; + clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, + <&clks IMX5_CLK_SAHARA_IPG_GATE>; + clock-names = "ipg", "ahb"; + }; }; }; }; -- cgit v1.2.3 From 3428d14d8a912b5231e9672261013fdd1bede2de Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 26 Jun 2018 21:05:01 -0300 Subject: ARM: dts: imx6ull: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull.dtsi | 43 +++--------------------------------------- 1 file changed, 3 insertions(+), 40 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index ebc25c98e5e1..70a28628e9b0 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -1,43 +1,6 @@ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2016 Freescale Semiconductor, Inc. #include "imx6ul.dtsi" #include "imx6ull-pinfunc.h" -- cgit v1.2.3 From 3d177f483e2bc1852e119f9f9a58b7d7d65ef18d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 26 Jun 2018 21:34:22 -0300 Subject: ARM: dts: imx53-qsb: Let the codec control MCLK pinctrl The hog pinctrl hog is meant for pins that do not have an associated driver. The MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK pin is the one that provides the MCLK signal to the SGTL5000 codec, so a better represenation is to move it under the codec node. While at it, change the pinctrl value from 0x80000000 to the POR reset value of register IOMUXC_SW_PAD_CTL_PAD_GPIO_0. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-qsb-common.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index ef7658a78836..7423d462d1e4 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -153,7 +153,6 @@ imx53-qsb { pinctrl_hog: hoggrp { fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 MX53_PAD_GPIO_8__GPIO1_8 0x80000000 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 @@ -180,6 +179,12 @@ >; }; + pinctrl_codec: codecgrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + >; + }; + pinctrl_esdhc1: esdhc1grp { fsl,pins = < MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 @@ -310,6 +315,8 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; #sound-dai-cells = <0>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; -- cgit v1.2.3 From 6e1a8a621ed1b9f170172fa13b6855d1b69774ca Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 27 Jun 2018 21:24:21 -0700 Subject: ARM: dts: imx51-zii-rdu1: Populate RAVE SP EEPROM nodes ZII's RDU1s come with up to 3 EEPROMs attached to RAVE SP. Add corresponding nodes to make them availible. Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index 27ea581f7789..3d2baf1eeb4b 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -589,6 +589,8 @@ rave-sp { compatible = "zii,rave-sp-rdu1"; current-speed = <38400>; + #address-cells = <1>; + #size-cells = <1>; watchdog { compatible = "zii,rave-sp-watchdog"; @@ -601,6 +603,33 @@ pwrbutton { compatible = "zii,rave-sp-pwrbutton"; }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "dds-eeprom"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + + eeprom@ae { + compatible = "zii,rave-sp-eeprom"; + reg = <0xae 0x200>; + zii,eeprom-name = "switch-eeprom"; + /* + * Not all RDU1s have this functionality, so we + * rely on the bootloader to enable this + */ + status = "disabled"; + }; }; }; -- cgit v1.2.3 From ec84fd24cfaec7bb4782a2983e933cbf8500ab8b Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 27 Jun 2018 21:24:22 -0700 Subject: ARM: dts: imx6qdl-zii-rdu2: Populate RAVE SP EEPROM nodes ZII's RDU2s come with two EEPROMs attached to RAVE SP. Add corresponding nodes to make them availible. Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 8e154c9bf814..1d38257be27a 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -320,10 +320,28 @@ rave-sp { compatible = "zii,rave-sp-rdu2"; current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; watchdog { compatible = "zii,rave-sp-watchdog"; }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "dds-eeprom"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; }; }; -- cgit v1.2.3 From 8cbcf1d2dbc006baa42fc1656d6ede1631e72b1c Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 27 Jun 2018 21:24:23 -0700 Subject: ARM: dts: imx6qdl-zii-rdu2: Populate RAVE SP backlight node RAVE SP found on RDU2 implements backlight control compatible with the rave-sp-backlight driver. Add a node to make it availible. Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 1d38257be27a..edb5d11c5f4b 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -327,6 +327,10 @@ compatible = "zii,rave-sp-watchdog"; }; + backlight { + compatible = "zii,rave-sp-backlight"; + }; + eeprom@a3 { compatible = "zii,rave-sp-eeprom"; reg = <0xa3 0x4000>; -- cgit v1.2.3 From 4508a44da371f38a0beceb6ff82028359dd8cdaa Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 27 Jun 2018 21:24:24 -0700 Subject: ARM: dts: imx6qdl-zii-rdu2: Populate RAVE SP power button node RAVE SP found on RDU2 implements power button control compatible with the rave-sp-pwrbutton driver. Add a node to make it availible. Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index edb5d11c5f4b..87c60a853f8b 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -331,6 +331,10 @@ compatible = "zii,rave-sp-backlight"; }; + pwrbutton { + compatible = "zii,rave-sp-pwrbutton"; + }; + eeprom@a3 { compatible = "zii,rave-sp-eeprom"; reg = <0xa3 0x4000>; -- cgit v1.2.3 From 2d0b768bd1a8a1b83ac3ce3c5600075ee115fb21 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 28 Jun 2018 09:04:27 +0800 Subject: ARM: dts: imx6sll-evk: enable usdhc3 slot On i.MX6SLL EVK board, SD3 slot can be used for WiFi and other SD accessories, enable it. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 65 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 25438ea03092..bc8d155cbfbc 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -88,6 +88,17 @@ gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_sd3_vmmc: regulator-sd3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_sd3_vmmc>; + regulator-name = "SD3_WIFI"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &cpu0 { @@ -239,7 +250,25 @@ status = "okay"; }; +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd3_vmmc>; + status = "okay"; +}; + &iomuxc { + pinctrl_reg_sd3_vmmc: sd3vmmcgrp { + fsl,pins = < + MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 + >; + }; + pinctrl_usb_otg1_vbus: vbus1grp { fsl,pins = < MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 @@ -310,6 +339,42 @@ >; }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 -- cgit v1.2.3 From 5e7765df703493a108ee3310873c063676a14f35 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 21 Jun 2018 09:37:05 +0200 Subject: ARM: davinci: dts: make psc0 a reset provider The psc driver registers with the reset framework as a provider. Add the #reset-cells property to the psc0 node. Signed-off-by: Bartosz Golaszewski Reviewed-by: David Lechner Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index d60198e2ae4e..f51d112d3e37 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -76,6 +76,7 @@ compatible = "ti,da850-psc0"; reg = <0x10000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; #power-domain-cells = <1>; clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&pll0_sysclk 6>, -- cgit v1.2.3 From 6e2d4b4f3a711a9e6bdb238818c545ef91036ce5 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 21 Jun 2018 09:37:06 +0200 Subject: ARM: davinci: dts: add a reset control to the dsp node The davinci-rproc driver will soon use the reset framework. Add the resets property to the dsp node in da850.dtsi. Signed-off-by: Bartosz Golaszewski Reviewed-by: David Lechner Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index f51d112d3e37..24865ed6f4e4 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -62,6 +62,7 @@ interrupt-parent = <&intc>; interrupts = <28>; clocks = <&psc0 15>; + resets = <&psc0 15>; status = "disabled"; }; soc@1c00000 { -- cgit v1.2.3 From 84f95684d9503d7cff920c716b2c7fd5522217eb Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Fri, 22 Jun 2018 13:49:36 -0500 Subject: ARM: dts: Add SPI0 node for Arria10 Add the SPI0 node for Arria10. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 791ca15c799e..a4dcb68f4322 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -587,6 +587,18 @@ status = "disabled"; }; + spi0: spi@ffda4000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda4000 0x100>; + interrupts = <0 101 4>; + num-cs = <4>; + /*32bit_access;*/ + clocks = <&spi_m_clk>; + status = "disabled"; + }; + spi1: spi@ffda5000 { compatible = "snps,dw-apb-ssi"; #address-cells = <1>; -- cgit v1.2.3 From c7ea1579a17e81c602cfc8121013cf8e39edd32b Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:01:58 +0530 Subject: arm: dts: highbank: Add missing OPP properties for CPUs The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing property (clock latency) as well to make it all work. Signed-off-by: Viresh Kumar Acked-by: Rob Herring Signed-off-by: Olof Johansson --- arch/arm/boot/dts/highbank.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index ed14aeac0566..50278715de76 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -56,6 +56,16 @@ next-level-cache = <&L2>; clocks = <&a9pll>; clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; }; cpu@902 { @@ -65,6 +75,16 @@ next-level-cache = <&L2>; clocks = <&a9pll>; clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; }; cpu@903 { @@ -74,6 +94,16 @@ next-level-cache = <&L2>; clocks = <&a9pll>; clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; }; }; -- cgit v1.2.3 From 47768f372eae030db6fab5225f9504a820d2c07f Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:01:48 +0530 Subject: ARM: dts: ls1021a: Add missing cooling device properties for CPUs The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index c55d479971cc..f18490548c78 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -84,6 +84,7 @@ device_type = "cpu"; reg = <0xf01>; clocks = <&clockgen 1 0>; + #cooling-cells = <2>; }; }; -- cgit v1.2.3 From cc3aba48e0d4f79ca1623248aefb7e83bb8680c8 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 3 Jul 2018 13:43:47 +0800 Subject: ARM: dts: imx51-babbage: Make use of pinctrl_usbh1reg Pinctrl_usbh1reg defines pinmux setting for reset GPIO used by usbh1phy, but is not referenced by that node. Fix that. Signed-off-by: Andrey Smirnov Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index b8ca73d3d379..4fb0d4d480a8 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -177,6 +177,8 @@ usbh1phy: usbh1phy@0 { compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1reg>; reg = <0>; clocks = <&clk_usb>; clock-names = "main_clk"; -- cgit v1.2.3 From 5bb59c8003650993f89a0c99090ac1a8d37fb63e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 28 Jun 2018 18:36:38 +0200 Subject: ARM: dts: imx53-ppd: Add fixed-regulator information Add information about 3V3 power rail to avoid kernel warnings, that dummy regulators have been added. Signed-off-by: Sebastian Reichel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-ppd.dts | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index 3aa6f693fa9f..30bbe0d740ee 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -140,6 +140,25 @@ regulator-always-on; }; + reg_3v3: regulator-3v3 { + /* TPS54320 */ + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3v3_lcd: regulator-3v3-lcd { + /* MIC2009 */ + compatible = "regulator-fixed"; + regulator-name = "LCD_3V3"; + vin-supply = <®_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + pwm_bl: backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 50000>; @@ -154,6 +173,7 @@ 234 237 239 242 244 247 249 252 255>; default-brightness-level = <0>; enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3_lcd>; }; leds { @@ -200,6 +220,7 @@ usbphy2: usbphy2 { compatible = "usb-nop-xceiv"; + vcc-supply = <®_3v3>; reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; clock-names = "main_clk"; clock-frequency = <24000000>; @@ -210,6 +231,7 @@ usbphy3: usbphy3 { compatible = "usb-nop-xceiv"; + vcc-supply = <®_3v3>; reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; clock-names = "main_clk"; @@ -221,6 +243,7 @@ panel-lvds0 { compatible = "nvd,9128"; + power-supply = <®_3v3_lcd>; port { panel_in_lvds0: endpoint { @@ -230,6 +253,14 @@ }; }; +&usbphy0 { + vcc-supply = <®_3v3>; +}; + +&usbphy1 { + vcc-supply = <®_3v3>; +}; + &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; @@ -414,6 +445,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; + phy-supply = <®_3v3>; phy-mode = "rmii"; phy-reset-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; status = "okay"; -- cgit v1.2.3 From 5180ee394fe81849e65bc89bfb54a6ec5fe88c75 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 28 Jun 2018 18:36:39 +0200 Subject: ARM: dts: imx53-ppd: Rename usbphy nodes This renames usbphy nodes 2 & 3, so that they follow the same format as usbphy node 0 & 1 from imx53.dtsi. Signed-off-by: Sebastian Reichel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-ppd.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index 30bbe0d740ee..444ec84cf342 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -218,7 +218,7 @@ }; }; - usbphy2: usbphy2 { + usbphy2: usbphy-2 { compatible = "usb-nop-xceiv"; vcc-supply = <®_3v3>; reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; @@ -229,7 +229,7 @@ assigned-clock-parents = <&clks IMX5_CLK_OSC>; }; - usbphy3: usbphy3 { + usbphy3: usbphy-3 { compatible = "usb-nop-xceiv"; vcc-supply = <®_3v3>; reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; -- cgit v1.2.3 From 5128666b17b4c64c6f9911ea78f578dbaf153bbb Mon Sep 17 00:00:00 2001 From: Nick Dyer Date: Thu, 28 Jun 2018 23:56:26 +0100 Subject: ARM: dts: imx51-zii-rdu1: correct touchscreen axis inversion The RMI4 touchscreen driver applied inversion and axis swap in the wrong order, violating the DT binding for those properties. This was fixed in 645a397, so correct the RDU1 DT to apply the inversion to the correct axis. Tested on Zii RDU1 00-5105-30 rev B Signed-off-by: Nick Dyer Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index 3d2baf1eeb4b..aede622c47a5 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -553,7 +553,7 @@ rmi4-f11@11 { reg = <0x11>; - touchscreen-inverted-y; + touchscreen-inverted-x; touchscreen-swapped-x-y; syna,sensor-type = <1>; }; -- cgit v1.2.3 From 7d034c5c6106b6f9ae13a67eaa98f558f430e33b Mon Sep 17 00:00:00 2001 From: Sébastien Szymanski Date: Fri, 29 Jun 2018 16:52:21 +0200 Subject: ARM: dts: imx6ull: add operating points MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit i.MX6ULL has different operating ranges than i.MX6UL so add the operating points for the i.MX6ULL and remove them from board device trees. A 25mV offset is added to the minimum allowed values like for the i.MX6UL. The valid frequencies are now selected by the cpufreq driver according to ratings stored in fuses since commit 0aa9abd4c212 ("cpufreq: imx6q: check speed grades for i.MX6ULL") Signed-off-by: Sébastien Szymanski Acked-by: Viresh Kumar Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 14 -------------- arch/arm/boot/dts/imx6ull.dtsi | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 14 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi index 3dffbcd50bf6..183193e8580d 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi @@ -20,20 +20,6 @@ &cpu0 { clock-frequency = <792000000>; - operating-points = < - /* kHz uV */ - 792000 1225000 - 528000 1175000 - 396000 1025000 - 198000 950000 - >; - fsl,soc-operating-points = < - /* KHz uV */ - 792000 1175000 - 528000 1175000 - 396000 1175000 - 198000 1175000 - >; }; &iomuxc { diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index 70a28628e9b0..cd1776a7015a 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -11,6 +11,25 @@ /* Delete CAAM node in AIPS-2 (i.MX6UL specific) */ /delete-node/ &crypto; +&cpu0 { + operating-points = < + /* kHz uV */ + 900000 1275000 + 792000 1225000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 900000 1175000 + 792000 1175000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + / { soc { aips3: aips-bus@2200000 { -- cgit v1.2.3 From a33d13e4fe04d46e2b68e879885929f2d7bd7136 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 19 May 2018 15:48:08 -0500 Subject: ARM: dts: am3517-evm: Remove unnessary PMIC parameters The AM3517-EVM uses a TPS65023 PMIC. This is already defined by: compatible = "ti,tps65023" There doesn't seem to be a need to have each regulator in the PMIC with the 'compatible = "regulator-fixed"' since each regulator has a min and max setting. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517-som.dtsi | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am3517-som.dtsi b/arch/arm/boot/dts/am3517-som.dtsi index a6d5ff73c163..7ff7cd135dca 100644 --- a/arch/arm/boot/dts/am3517-som.dtsi +++ b/arch/arm/boot/dts/am3517-som.dtsi @@ -64,7 +64,6 @@ regulators { vdd_core_reg: VDCDC1 { regulator-name = "vdd_core"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -72,7 +71,6 @@ vdd_io_reg: VDCDC2 { regulator-name = "vdd_io"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -80,7 +78,6 @@ vdd_1v8_reg: VDCDC3 { regulator-name = "vdd_1v8"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -88,7 +85,6 @@ vdd_usb18_reg: LDO1 { regulator-name = "vdd_usb18"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -96,7 +92,6 @@ vdd_usb33_reg: LDO2 { regulator-name = "vdd_usb33"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; -- cgit v1.2.3 From e878647ec4dd662f16df1d7fcbfac68a9b20ea81 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 1 Jul 2018 19:56:01 -0300 Subject: ARM: dts: imx6sll: Fix the SPDX notation for header file Per Documentation/process/license-rules.rst the SPDX notation for header file should be /* */ style, so fix it accordingly. Fixes: 9f30b6b1a957 ("ARM: dts: imx: Add basic dtsi file for imx6sll") Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sll-pinfunc.h b/arch/arm/boot/dts/imx6sll-pinfunc.h index b1c40dcdb42f..713a346f4c89 100644 --- a/arch/arm/boot/dts/imx6sll-pinfunc.h +++ b/arch/arm/boot/dts/imx6sll-pinfunc.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP. -- cgit v1.2.3 From 77cf8a009df8a47ba0c8f32b0d6bb6cbfb55a17e Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 2 Jul 2018 10:04:36 +0800 Subject: ARM: dts: imx6: correct anatop regulators range According to i.MX6 datasheet, the LDO_1P1's typical programming operating range is 1.0V to 1.2V, and the LDO_2P5's typical programming operating range is 2.25V to 2.75V, correct LDO_1P1 and LDO_2P5's regulator range settings for i.MX6 SoCs. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 8 ++++---- arch/arm/boot/dts/imx6sx.dtsi | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 81f48116c5b1..c64bd906ad55 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -524,8 +524,8 @@ regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1375000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; regulator-always-on; anatop-reg-offset = <0x110>; anatop-vol-bit-shift = <8>; @@ -554,8 +554,8 @@ regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2850000>; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <2750000>; regulator-always-on; anatop-reg-offset = <0x130>; anatop-vol-bit-shift = <8>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 7130ab8a7518..596763c2fe33 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -592,8 +592,8 @@ regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1375000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; regulator-always-on; anatop-reg-offset = <0x110>; anatop-vol-bit-shift = <8>; @@ -622,8 +622,8 @@ regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2875000>; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <2750000>; regulator-always-on; anatop-reg-offset = <0x130>; anatop-vol-bit-shift = <8>; -- cgit v1.2.3 From d6ace1c5f960e90392c32a07020312f933547cdd Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:01:54 +0530 Subject: ARM: dts: dra74x: Add missing cooling device properties for CPUs The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Fix other missing properties (clocks, supply, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra74x.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 91e93ab588ca..8f9df09155d8 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -18,6 +18,16 @@ compatible = "arm,cortex-a15"; reg = <1>; operating-points-v2 = <&cpu0_opp_table>; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + #cooling-cells = <2>; /* min followed by max */ + + vbb-supply = <&abb_mpu>; }; }; -- cgit v1.2.3 From 484d578b71d4981eb1734f8fffbe42814b043b7f Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:01:55 +0530 Subject: ARM: dts: omap5: Add missing cooling device properties for CPUs The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Fix other missing properties (clocks, supply, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 732b61a0e990..574ac11c0489 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -61,6 +61,20 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; + + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1500000 1250000 + >; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + #cooling-cells = <2>; /* min followed by max */ }; }; -- cgit v1.2.3 From 5f3cc16483d40bbc609a828511ff851296fc62b6 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 29 May 2018 12:00:55 +0300 Subject: ARM: dts: am57xx-idk: Enable dual role for USB2 port Dual-role support was added in v4.12. We should be using it for USB2 port on the am57xx-idk. Cc: [4.16+] Reported-by: Bin Liu Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am571x-idk.dts | 4 ---- arch/arm/boot/dts/am572x-idk-common.dtsi | 4 ---- arch/arm/boot/dts/am57xx-idk-common.dtsi | 7 ++++++- 3 files changed, 6 insertions(+), 9 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index 5bb9d68d6e90..d9a2049a1ea8 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -66,10 +66,6 @@ }; }; -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - &extcon_usb2 { id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/am572x-idk-common.dtsi index c6d858b31011..784639ddf451 100644 --- a/arch/arm/boot/dts/am572x-idk-common.dtsi +++ b/arch/arm/boot/dts/am572x-idk-common.dtsi @@ -57,10 +57,6 @@ }; }; -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - &extcon_usb2 { id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index ad87f1ae904d..c9063ffca524 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -395,8 +395,13 @@ dr_mode = "host"; }; +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + &usb2 { - dr_mode = "peripheral"; + extcon = <&extcon_usb2>; + dr_mode = "otg"; }; &mmc1 { -- cgit v1.2.3 From b0fa6143ae7469f5efde8ce4195a6151519b77f0 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 29 May 2018 12:00:56 +0300 Subject: ARM: dts: dra7-evm: Add extcon to USB2 port Both ports on the dra7-evm and related boards can be used as dual-role ports. Although we don't enable dual-role mode for USB2 port let's add the necessary extcon bits to it. Move the common portion of extcon_usb2 into dra7-evm-common.dtsi Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-evm-common.dtsi | 10 ++++++++++ arch/arm/boot/dts/dra7-evm.dts | 9 --------- arch/arm/boot/dts/dra72-evm-common.dtsi | 1 + 3 files changed, 11 insertions(+), 9 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi index 33230c8b2951..7e18147dc563 100644 --- a/arch/arm/boot/dts/dra7-evm-common.dtsi +++ b/arch/arm/boot/dts/dra7-evm-common.dtsi @@ -20,6 +20,11 @@ id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; }; + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; + }; + sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "DRA7xx-EVM"; @@ -198,8 +203,13 @@ extcon = <&extcon_usb1>; }; +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + &usb2 { dr_mode = "host"; + extcon = <&extcon_usb2>; }; &atl { diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 0894593860d6..6ed5f9156270 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -106,11 +106,6 @@ enable-active-high; }; - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; - }; - vtt_fixed: fixedregulator-vtt { compatible = "regulator-fixed"; regulator-name = "vtt_fixed"; @@ -406,10 +401,6 @@ vdd-supply = <&smps123_reg>; }; -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - &elm { status = "okay"; }; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index df174f5c15d1..e297b923b71a 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -391,6 +391,7 @@ &usb2 { dr_mode = "host"; + extcon = <&extcon_usb2>; }; &mmc1 { -- cgit v1.2.3 From a78936fc8cec309804e4baf9febb4c9fb46680cb Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 29 May 2018 12:00:57 +0300 Subject: ARM: dts: dra71-evm: Add VBUS GPIO to USB1/USB2 extcon The board has USB VBUS detection available over GPIO. Plug it to extcon node of USB1 and USB2 ports. Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra71-evm.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index b7aeaeeead3b..c471bf3277b4 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -265,3 +265,11 @@ /* Supplied by VDA_1V8_PHY */ vdda_video-supply = <&lp8732_ldo1_reg>; }; + +&extcon_usb1 { + vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; +}; + +&extcon_usb2 { + vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; +}; -- cgit v1.2.3 From 382ceeaabdada40637449b395fcf17de2b87a005 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 29 May 2018 12:00:58 +0300 Subject: ARM: dts: dra76-evm: Add VBUS GPIO to USB1/USB2 extcon The board has USB VBUS detection available over GPIO. Plug it to extcon node of USB1 and USB2 ports. Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra76-evm.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index c07f0051844d..f983cfd1cb85 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -436,3 +436,11 @@ phys = <&pcie1_phy>, <&pcie2_phy>; phy-names = "pcie-phy0", "pcie-phy1"; }; + +&extcon_usb1 { + vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; +}; + +&extcon_usb2 { + vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; +}; -- cgit v1.2.3 From 572cf7d7b07d3d61b82024bccb2a45366d58710e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 2 Jul 2018 23:57:20 -0700 Subject: ARM: dts: Improve omap l4per idling with wlcore edge sensitive interrupt The wl1835mod.pdf data sheet says this pretty clearly for WL_IRQ line: "WLAN SDIO out-of-band interrupt line. Set to rising edge (active high) by default." And it seems this interrupt can be optionally configured to use falling edge too since commit bd763482c82e ("wl18xx: wlan_irq: support platform dependent interrupt types"). On omap4, if the wlcore interrupt is configured as level instead of edge, L4PER will stop doing hardware based idling after ifconfig wlan0 down is done and the WL_EN line is pulled down. The symptoms show up with L4PER status registers no longer showing the IDLEST bits as 2 but as 0 for all the active GPIO banks and for L4PER_CLKCTRL. Also the l4per_pwrdm RET count stops increasing in the /sys/kernel/debug/pm_debug/count. While there is also probably a GPIO related issue that needs to be still fixed, this change gets us to the point where we can have L4PER idling. I'm guessing wlcore was at some point configured to use level interrupts because of edge handling issues in gpio-omap. However, with the recent fixes to gpio-omap the edge interrupts seem to be working just fine. Let's change it for all omap boards with wlcore interrupt set as level. Cc: Dave Gerlach Cc: Eyal Reizer Cc: Grygorii Strashko Cc: Kalle Valo Cc: Nishanth Menon Cc: Tero Kristo [tony@atomide.com updated comments a bit for gpio issue] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos.dtsi | 2 +- arch/arm/boot/dts/am335x-evm.dts | 2 +- arch/arm/boot/dts/am335x-evmsk.dts | 2 +- arch/arm/boot/dts/am437x-gp-evm.dts | 2 +- arch/arm/boot/dts/logicpd-som-lv.dtsi | 2 +- arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts | 2 +- arch/arm/boot/dts/omap3-cm-t3517.dts | 2 +- arch/arm/boot/dts/omap3-cm-t3730.dts | 2 +- arch/arm/boot/dts/omap3-evm-common.dtsi | 2 +- arch/arm/boot/dts/omap3-igep0020-rev-f.dts | 2 +- arch/arm/boot/dts/omap3-igep0030-rev-g.dts | 2 +- arch/arm/boot/dts/omap3-zoom3.dts | 2 +- arch/arm/boot/dts/omap4-droid4-xt894.dts | 2 +- arch/arm/boot/dts/omap4-panda-common.dtsi | 2 +- arch/arm/boot/dts/omap4-sdp.dts | 2 +- arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi | 2 +- arch/arm/boot/dts/omap5-board-common.dtsi | 2 +- 17 files changed, 17 insertions(+), 17 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index ed7a5a3daa42..8c6fc4161ad7 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -396,7 +396,7 @@ compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 1356fd6f8da3..c87d01297a01 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -778,7 +778,7 @@ compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio3>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 0c096a795e37..bf1a40e45c97 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -690,7 +690,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio0>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */ + interrupts = <31 IRQ_TYPE_EDGE_RISING>; /* gpio 31 */ ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 60414b1ca404..5b97c20c5ed4 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -790,7 +790,7 @@ compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio1>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <23 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi index 3bb28c03ca74..ac343330d0c8 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -142,7 +142,7 @@ compatible = "ti,wl1273"; reg = <2>; interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 2 */ + interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 2 */ ref-clock-frequency = <26000000>; }; }; diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts index 234afd6d60ec..9d5d53fbe9c0 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts @@ -48,7 +48,7 @@ compatible = "ti,wl1283"; reg = <2>; interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */ + interrupts = <24 IRQ_TYPE_EDGE_RISING>; /* gpio 152 */ ref-clock-frequency = <26000000>; tcxo-clock-frequency = <26000000>; }; diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts index 4994e33bf663..632f52efdf98 100644 --- a/arch/arm/boot/dts/omap3-cm-t3517.dts +++ b/arch/arm/boot/dts/omap3-cm-t3517.dts @@ -141,7 +141,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio5>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 145 */ + interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 145 */ ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts index 8c63ac5bbb12..6e944dfa0f3d 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts @@ -81,7 +81,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio5>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */ + interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index ee64191e41ca..4c1227d1e79b 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -133,7 +133,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio5>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 149 */ + interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 149 */ ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts index 321c2b7a4e9f..285681d7af49 100644 --- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts +++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts @@ -49,6 +49,6 @@ compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio6>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 177 */ + interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 177 */ }; }; diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts index 76dc08868bfb..1adc73bd2ca0 100644 --- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts +++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts @@ -71,6 +71,6 @@ compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio5>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */ + interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ }; }; diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts index 96d0301a336a..aac27a441331 100644 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ b/arch/arm/boot/dts/omap3-zoom3.dts @@ -202,7 +202,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio6>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 162 */ + interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 162 */ ref-clock-frequency = <26000000>; }; }; diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index bdf73cbcec3a..4f00559015a4 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -372,7 +372,7 @@ compatible = "ti,wl1285", "ti,wl1283"; reg = <2>; interrupt-parent = <&gpio4>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; /* gpio100 */ + interrupts = <4 IRQ_TYPE_EDGE_RISING>; /* gpio100 */ ref-clock-frequency = <26000000>; tcxo-clock-frequency = <26000000>; }; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 5501d1b4e6cd..563b47c5f0c7 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -464,7 +464,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio2>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ + interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */ ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 280d92d42bf1..490726b52216 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -493,7 +493,7 @@ compatible = "ti,wl1281"; reg = <2>; interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ + interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */ ref-clock-frequency = <26000000>; tcxo-clock-frequency = <26000000>; }; diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi index 1c5f6f35e1cf..878923473023 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi @@ -72,7 +72,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */ + interrupts = <9 IRQ_TYPE_EDGE_RISING>; /* gpio 41 */ ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index 3b2244560c28..ab6f640b282b 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -364,7 +364,7 @@ pinctrl-names = "default"; pinctrl-0 = <&wlcore_irq_pin>; interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */ + interrupts = <14 IRQ_TYPE_EDGE_RISING>; /* gpio 14 */ ref-clock-frequency = <26000000>; }; }; -- cgit v1.2.3 From 731b409878a3b4387ce824f48228f4e161e20e1c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 2 Jul 2018 23:57:32 -0700 Subject: ARM: dts: Configure duovero for to allow core retention during idle By reconfiguring few GPIOs in the dts file we can make duovero parlor hit retention during idle: 1. Let's a larger debounce value for gpio-keys This will then make gpio-keys use software debounce and the GPIO debounce clock is not enabled. 2. Let's allow WLAN suspend for mwifiex This can be done just by adding keep-power-in-suspend. 3. Let's reconfigure smsc911x driver to use GPIO edge interrupt This will allow using NFSroot while the system idles, and the kernel has quite a few dts files with "smsc,lan9115" compatible using edge interrupts. Then to have the system hit core retention during idle, the UARTs needs to be idled and USB modules need to be unloaded or unbound. Cc: Ash Charles Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-duovero-parlor.dts | 4 +++- arch/arm/boot/dts/omap4-duovero.dtsi | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts index a9a584b5b955..cfcac0d73851 100644 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts @@ -36,6 +36,8 @@ label = "button0"; linux,code = ; gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; wakeup-source; }; }; @@ -140,7 +142,7 @@ ethernet@gpmc { reg = <5 0 0xff>; interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; /* gpio_44 */ + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; /* gpio_44 */ phy-mode = "mii"; diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi index eb123b24c8e3..5e8169153414 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/omap4-duovero.dtsi @@ -248,6 +248,7 @@ ti,bus-width = <4>; ti,non-removable; cap-power-off-card; + keep-power-in-suspend; }; &twl_usb_comparator { -- cgit v1.2.3 From e40c7f75c9bc81a19c3f927769e42fd974fccaa2 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 2 Jul 2018 23:57:42 -0700 Subject: ARM: dts: omap4-droid4: Use software debounce for gpio-keys The default value of 5ms will use GPIO hardware based debounce clocks that will keep L4PER from idling consuming about extra 30mW. Use a value of 10ms that is above the hardware debounce maximum of 7.95ms forcing software based debouncing. This allows droid4 to enter PER retention during idle as long as UARTs are idled and USB modules unloaded or unbound. Note that there seems to be a pending issue with having droid 4 enter core retention during idle where GPIO bank 1 needs to be reset late after init for some reason to not block core retention. In addition to that, we are also missing GPIO related PM runtime calls for omap4 that will be posted separately. Cc: Marcel Partap Cc: Merlijn Wajer Cc: Michael Scott Cc: NeKit Cc: Pavel Machek Cc: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-droid4-xt894.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 4f00559015a4..63105ca92e9c 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -128,6 +128,8 @@ gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ linux,code = ; linux,can-disable; + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; }; slider { @@ -136,7 +138,8 @@ linux,input-type = ; linux,code = ; linux,can-disable; - + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; }; }; -- cgit v1.2.3 From 7c1280267ac0e17df3f1d450cc9c5612a5aba54d Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 6 Jun 2018 17:54:06 +0200 Subject: ARM: dts: am335x-sl50: update backlight nodes This patch updates the backlight nodes to improve the support and describe better how hardware is done. The changes done were: * Use PWM_POLARITY_INVERTED instead of the hardcoded number. * Add pinctrl configuration. * Add the enable gpio definition. * Add the power supply definition. * Add more brightness levels. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sl50.dts | 61 +++++++++++++++++++++++++++++++++++---- 1 file changed, 55 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index 1bcc60424ecd..dedf54d358ae 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "am33xx.dtsi" +#include / { model = "Toby Churchill SL50 Series"; @@ -60,16 +61,44 @@ backlight0: disp0 { compatible = "pwm-backlight"; - pwms = <&ehrpwm1 0 500000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; - default-brightness-level = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&backlight0_pins>; + pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_sys_reg>; }; backlight1: disp1 { compatible = "pwm-backlight"; - pwms = <&ehrpwm1 1 500000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; - default-brightness-level = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&backlight1_pins>; + pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_sys_reg>; }; clocks { @@ -108,6 +137,14 @@ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; }; + vdd_sys_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_sys_reg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; @@ -120,6 +157,18 @@ pinctrl-names = "default"; pinctrl-0 = <&lwb_pins>; + backlight0_pins: pinmux_backlight0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */ + >; + }; + + backlight1_pins: pinmux_backlight1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad10.gpio0_26 */ + >; + }; + led_pins: pinmux_led_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ -- cgit v1.2.3 From 25d2ee9f1b22dc62d06265420296a8cd150ad272 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 6 Jun 2018 17:54:07 +0200 Subject: ARM: dts: am335x-sl50: use phy-phandle declarations phy-phandle is now a preferred method to reference a PHY device. The new method also allows you to specify a reset gpio which is required for this board. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sl50.dts | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index dedf54d358ae..ef8f428bf660 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -256,6 +256,8 @@ /* MDIO */ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + /* Ethernet */ + AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */ >; }; @@ -327,7 +329,6 @@ AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* nKbdOnC - gpmc_ad10.gpio0_26 */ AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* nDispReset - gpmc_ad14.gpio1_14 */ AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ /* PDI Bus - Battery system */ AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ @@ -556,13 +557,8 @@ }; &cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "mii"; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; phy-mode = "mii"; + phy-handle = <ðphy0>; }; &mac { @@ -577,6 +573,12 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; + reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + reset-delay-us = <100>; /* PHY datasheet states 100us min */ + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; }; &sham { -- cgit v1.2.3 From 79932e7ae97dca914963f710ae7950f64021151d Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 6 Jun 2018 17:54:08 +0200 Subject: ARM: dts: am335x-sl50: add a node for the LCD controller Add the pins used by the LCD controller, the panel-info and display-timings information for the MIDAS displays connected to the board. There are two displays in the board, and these, are connected to the LCD controller through a FPGA, so the timings and the resolution is what expects the FPGA, not the MIDAS displays. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sl50.dts | 69 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index ef8f428bf660..c6165d2b09ae 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -114,6 +114,45 @@ }; }; + panel: lcd_panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + tft-alt-mode = <0>; + mono-8bit-mode = <0>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + display-timings { + native-mode = <&timing0>; + timing0: 960x128 { + clock-frequency = <18000000>; + hactive = <960>; + vactive = <272>; + + hback-porch = <40>; + hfront-porch = <16>; + hsync-len = <24>; + hsync-active = <0>; + + vback-porch = <3>; + vfront-porch = <8>; + vsync-len = <4>; + vsync-active = <0>; + }; + }; + }; + sound { compatible = "ti,da830-evm-audio"; ti,model = "AM335x-SL50"; @@ -169,6 +208,31 @@ >; }; + lcd_pins: pinmux_lcd_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + led_pins: pinmux_led_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ @@ -326,7 +390,6 @@ lwb_pins: pinmux_lwb_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) /* SoundPA_en - mcasp0_fsr.gpio3_19 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* nKbdOnC - gpmc_ad10.gpio0_26 */ AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ @@ -598,3 +661,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ehrpwm1_pins>; }; + +&lcdc { + status = "okay"; +}; -- cgit v1.2.3 From f9d1dec9fbce30801975eb177692cc893622ee71 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 6 Jun 2018 17:54:09 +0200 Subject: ARM: dts: am335x-sl50: set dr_mode to otg The board can be either a host, or a peripheral, so set the controller as OTG mode to reflect this. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sl50.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index c6165d2b09ae..133e90970f1e 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -476,7 +476,7 @@ &usb0 { status = "okay"; - dr_mode = "peripheral"; + dr_mode = "otg"; }; &usb1 { -- cgit v1.2.3 From 9843532de118c96a445db6020bd5148b6f11b90a Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 6 Jun 2018 17:54:10 +0200 Subject: ARM: dts: am335x-sl50: add support for DS1339 Real Time Clock Production hardware will go with the DS1339 RTC chip, so replace the old for the new one and also add the nIRQ pin to be able to properly wakeup the system from suspend. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sl50.dts | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index 133e90970f1e..a35807aee5dc 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -9,6 +9,7 @@ #include "am33xx.dtsi" #include +#include / { model = "Toby Churchill SL50 Series"; @@ -377,6 +378,12 @@ >; }; + rtc0_irq_pins: pinmux_rtc0_irq_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad9.gpio0_23 */ + >; + }; + spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MOSI - spi0_d0.spi0_d0 */ @@ -411,9 +418,14 @@ reg = <0x24>; }; - bq32000: rtc@68 { - compatible = "ti,bq32000"; - trickle-resistor-ohms = <1120>; + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc0_irq_pins>; + interrupt-parent = <&gpio0>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */ + wakeup-source; + trickle-resistor-ohms = <2000>; reg = <0x68>; }; -- cgit v1.2.3 From e5f89dbdebc5125460c4e305574cfb36eac9961c Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 6 Jun 2018 17:54:11 +0200 Subject: ARM: dts: am335x-sl50: use audio-graph-card for sound audio-graph-card is recommended for audio bindings. Let's change to it and improve the support by adding the Amplifier configuration and the clock enable control. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sl50.dts | 111 +++++++++++++++++++++++++++----------- 1 file changed, 80 insertions(+), 31 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index a35807aee5dc..0268480003f4 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -108,11 +108,20 @@ #size-cells = <0>; /* audio external oscillator */ - tlv320aic3x_mclk: oscillator@0 { + audio_mclk_fixed: oscillator@0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; /* 24.576MHz */ }; + + audio_mclk: audio_mclk_gate@0 { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&audio_mclk_pins>; + clocks = <&audio_mclk_fixed>; + enable-gpios = <&gpio1 27 0>; + }; }; panel: lcd_panel { @@ -155,19 +164,29 @@ }; sound { - compatible = "ti,da830-evm-audio"; - ti,model = "AM335x-SL50"; - ti,audio-codec = <&audio_codec>; - ti,mcasp-controller = <&mcasp0>; + compatible = "audio-graph-card"; + label = "sound-card"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_pa_pins>; + + widgets = "Headphone", "Headphone Jack", + "Speaker", "Speaker External", + "Line", "Line In", + "Microphone", "Microphone Jack"; - clocks = <&tlv320aic3x_mclk>; - clock-names = "mclk"; + routing = "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "Amplifier", "MONO_LOUT", + "Speaker External", "Amplifier", + "LINE1R", "Line In", + "LINE1L", "Line In", + "MIC3L", "Microphone Jack", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1R", "Line In", - "LINE1L", "Line In"; + dais = <&cpu_port>; + + pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; }; emmc_pwrseq: pwrseq@0 { @@ -197,6 +216,28 @@ pinctrl-names = "default"; pinctrl-0 = <&lwb_pins>; + audio_pins: pinmux_audio_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ + AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */ + >; + }; + + audio_pa_pins: pinmux_audio_pa_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */ + >; + }; + + audio_mclk_pins: pinmux_audio_mclk_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ + >; + }; + backlight0_pins: pinmux_backlight0_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */ @@ -361,16 +402,6 @@ >; }; - audio_pins: pinmux_audio_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ - AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ - AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ - AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */ - >; - }; - ehrpwm1_pins: pinmux_ehrpwm1a_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* gpmc_a2.ehrpwm1a */ @@ -396,7 +427,6 @@ lwb_pins: pinmux_lwb_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) /* SoundPA_en - mcasp0_fsr.gpio3_19 */ AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ @@ -451,12 +481,21 @@ audio_codec: tlv320aic3106@1b { status = "okay"; compatible = "ti,tlv320aic3106"; + #sound-dai-cells = <0>; reg = <0x1b>; + ai3x-micbias-vg = <2>; /* 2.5V */ AVDD-supply = <&ldo4_reg>; IOVDD-supply = <&ldo4_reg>; DRVDD-supply = <&ldo4_reg>; DVDD-supply = <&ldo3_reg>; + + codec_port: port { + codec_endpoint: endpoint { + remote-endpoint = <&cpu_endpoint>; + clocks = <&audio_mclk>; + }; + }; }; /* Ambient Light Sensor */ @@ -522,17 +561,27 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&audio_pins>; - + #sound-dai-cells = <0>; op-mode = <0>; /* MCASP_ISS_MODE */ tdm-slots = <2>; - serial-dir = < - 2 0 1 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 >; - tx-num-evt = <1>; - rx-num-evt = <1>; + tx-num-evt = <32>; + rx-num-evt = <32>; + + cpu_port: port { + cpu_endpoint: endpoint { + remote-endpoint = <&codec_endpoint>; + + dai-format = "dsp_b"; + bitclock-master = <&codec_port>; + frame-master = <&codec_port>; + bitclock-inversion; + clocks = <&audio_mclk>; + }; + }; }; &uart0 { -- cgit v1.2.3 From 70bd28eb4fb3f4e0ca1aaeb005e653ceb075b0dd Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 6 Jun 2018 17:54:12 +0200 Subject: ARM: dts: am335x-sl50: fix label names for all LEDs Fix the label for all LEDs, we made a mistake setting the label names on all LEDs, where says green should say red, and viceversa, where says red should be green. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sl50.dts | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index 0268480003f4..442eccc3b466 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -36,25 +36,25 @@ pinctrl-0 = <&led_pins>; led0 { - label = "sl50:green:usr0"; + label = "sl50:red:usr0"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; default-state = "off"; }; led1 { - label = "sl50:red:usr1"; + label = "sl50:green:usr1"; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; default-state = "off"; }; led2 { - label = "sl50:green:usr2"; + label = "sl50:red:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; default-state = "off"; }; led3 { - label = "sl50:red:usr3"; + label = "sl50:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; default-state = "off"; }; @@ -433,6 +433,12 @@ /* PDI Bus - Battery system */ AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ + /* FPGA */ + AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE7) /* FPGA_DONE - gpmc_ad8.gpio0_22 */ + AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */ + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* FPGA_RUN - gpmc_a1.gpio1_17 */ + AM33XX_IOPAD(0x864, PIN_INPUT_PULLUP | MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */ + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */ >; }; }; -- cgit v1.2.3 From 5e2e1c4fb3a6b98bd23ea5e0d5cd61714997a0c9 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 6 Jun 2018 17:54:13 +0200 Subject: ARM: dts: am335x-sl50: enable tsadc on SL50 board The tsadc is used to read various voltages on the board, so enable it to be able to read these voltages from userspace. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sl50.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index 442eccc3b466..38d57b89f7d3 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -732,3 +732,11 @@ &lcdc { status = "okay"; }; + +&tscadc { + status = "okay"; +}; + +&am335x_adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; +}; -- cgit v1.2.3 From 6bf5e3410f190374371d89a5816d1a4aaae66776 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 8 Jun 2018 06:29:26 -0500 Subject: ARM: dts: am3517-som: Add WL127x Wifi Certain models of the AM3517 SOM from Logic PD come with an integrated WL1271 WiFi. This patch enables the WiFi. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517-evm.dts | 4 -- arch/arm/boot/dts/am3517-som.dtsi | 80 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index 98aadb0f81c5..d7eb6ad76c29 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -220,10 +220,6 @@ cd-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio_127 */ }; -&mmc2 { - status = "disabled"; -}; - &mmc3 { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am3517-som.dtsi b/arch/arm/boot/dts/am3517-som.dtsi index 7ff7cd135dca..a2914067d613 100644 --- a/arch/arm/boot/dts/am3517-som.dtsi +++ b/arch/arm/boot/dts/am3517-som.dtsi @@ -14,6 +14,32 @@ cpu0-supply = <&vdd_core_reg>; }; }; + + wl12xx_buffer: wl12xx_buf { + compatible = "regulator-fixed"; + regulator-name = "wl1271_buf"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_buffer_pins>; + gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */ + regulator-always-on; + vin-supply = <&vdd_1v8_reg>; + }; + + wl12xx_vmmc2: wl12xx_vmmc2 { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_wkup_pins>; + gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */ + startup-delay-us = <70000>; + enable-active-high; + regulator-always-on; + vin-supply = <&wl12xx_buffer>; + }; }; &gpmc { @@ -121,8 +147,53 @@ }; }; +&mmc2 { + interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>; + + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&wl12xx_vmmc2>; + non-removable; + bus-width = <4>; + cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; /* gpio_170 */ + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + + &omap3_pmx_core { + wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */ + OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */ + >; + }; + rtc_pins: pinmux_rtc_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */ @@ -135,3 +206,12 @@ >; }; }; + +&omap3_pmx_wkup { + + wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ + >; + }; +}; -- cgit v1.2.3 From 8b75b3dcb18239b71b351f2b59ebbdb3faa5ce45 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 8 Jun 2018 06:27:36 -0500 Subject: ARM: dts: am3517-som: Add builtin Bluetooth This enables the Bluetooth on the wl1271 available in some models of the AM3517-SOM from Logic PD. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517-som.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am3517-som.dtsi b/arch/arm/boot/dts/am3517-som.dtsi index a2914067d613..dae6e458e59f 100644 --- a/arch/arm/boot/dts/am3517-som.dtsi +++ b/arch/arm/boot/dts/am3517-som.dtsi @@ -169,6 +169,16 @@ }; }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + bluetooth { + compatible = "ti,wl1271-st"; + enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */ + max-speed = <3000000>; + }; +}; &omap3_pmx_core { @@ -205,6 +215,16 @@ OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */ >; }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ + OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */ + >; + }; }; &omap3_pmx_wkup { -- cgit v1.2.3 From 19054d0a0014d9770ac21d2e5f166f584d329441 Mon Sep 17 00:00:00 2001 From: Felix Brack Date: Mon, 11 Jun 2018 16:45:53 +0200 Subject: ARM: dts: am33xx: Fix syntax of alias names DT specifications do not allow the underscore character in alias names. Replace all underscores in alias names by dashes. Signed-off-by: Felix Brack Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 9cd62bc2ca35..d3dd6a16e70a 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -29,8 +29,8 @@ serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; - d_can0 = &dcan0; - d_can1 = &dcan1; + d-can0 = &dcan0; + d-can1 = &dcan1; usb0 = &usb0; usb1 = &usb1; phy0 = &usb0_phy; -- cgit v1.2.3 From 5bd5bce567c658d265ebb169e05b1a9d0f294f95 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 23 Jun 2018 08:24:03 -0500 Subject: ARM: dts: am3517-evm: Enable USB1 Host The AM3517-evm has a single USB Host port connected to hsusb1. This patch enables that USB port. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517-evm.dts | 45 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index d7eb6ad76c29..b834ebe091b3 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -168,6 +168,13 @@ ti,timers = <&timer11>; #pwm-cells = <3>; }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ + #phy-cells = <0>; + }; }; &davinci_emac { @@ -224,7 +231,17 @@ status = "disabled"; }; +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; + &omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_rst_pins>; leds_pins: pinmux_leds_pins { pinctrl-single,pins = < @@ -283,4 +300,32 @@ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ >; }; + + hsusb1_rst_pins: pinmux_hsusb1_rst_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_pins>; + + hsusb1_pins: pinmux_hsusb1_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ + OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ + OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ + OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ + OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ + OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ + OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ + OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ + OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ + OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ + >; + }; }; -- cgit v1.2.3 From b97872d4eb226fa853d0f69c72b24a711e388757 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:02:01 +0530 Subject: ARM: dts: imx: Add missing OPP properties for CPUs The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing properties (like clocks, supply, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl.dtsi | 23 ++++++++++ arch/arm/boot/dts/imx6q-cm-fx6.dts | 66 +++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6q.dtsi | 87 ++++++++++++++++++++++++++++++++++++-- arch/arm/boot/dts/imx7d.dtsi | 5 +++ 4 files changed, 178 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index a1acd4ddcb1a..f0607eb41df4 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -51,6 +51,29 @@ device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 65ef4cacbc71..18ae4f3be6e3 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -187,6 +187,72 @@ >; }; +&cpu1 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu2 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu3 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + &ecspi1 { cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 894401c5db09..bbe65616e16a 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -51,25 +51,106 @@ soc-supply = <®_soc>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 7cbc2ffa4b3a..9a772fc9e3b8 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -18,6 +18,11 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; clock-frequency = <996000000>; operating-points-v2 = <&cpu0_opp_table>; }; -- cgit v1.2.3 From 82210bfd942b891c502afe471cda16eccf565ed5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 3 Jul 2018 10:05:54 -0300 Subject: ARM: dts: imx51: Fix USB PHY duplicate unit-address Currently the following DTC warnings are seen with W=1: arch/arm/boot/dts/imx51-babbage.dtb: Warning (unique_unit_address): /usbphy/usbphy@0: duplicate unit-address (also used in node /usbphy/usbh1phy@0) arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dtb: Warning (unique_unit_address): /usbphy/usbphy@0: duplicate unit-address (also used in node /usbphy/usbh1phy@0) Fix it by moving the USB PHY nodes outside of simple-bus and drop the unneeded unit-address, which matches the bindings documentation at Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt While at it rename the USB PHY node to usbphy1 for consistency. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 27 ++++++++-------------- .../boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | 21 ++++++----------- arch/arm/boot/dts/imx51.dtsi | 17 ++++---------- 3 files changed, 22 insertions(+), 43 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 4fb0d4d480a8..a4a6d4a6b55b 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -170,22 +170,15 @@ mux-ext-port = <3>; }; - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usbh1phy: usbh1phy@0 { - compatible = "usb-nop-xceiv"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1reg>; - reg = <0>; - clocks = <&clk_usb>; - clock-names = "main_clk"; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - vcc-supply = <&vusb_reg>; - #phy-cells = <0>; - }; + usbphy1: usbphy1 { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1reg>; + clocks = <&clk_usb>; + clock-names = "main_clk"; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + vcc-supply = <&vusb_reg>; + #phy-cells = <0>; }; }; @@ -431,7 +424,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1>; vbus-supply = <®_hub_reset>; - fsl,usbphy = <&usbh1phy>; + fsl,usbphy = <&usbphy1>; phy_type = "ulpi"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index b3d952f37cdc..e9e819f2b0b7 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts @@ -83,19 +83,12 @@ fsl,mux-ext-port = <3>; }; - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usbh1phy: usbh1phy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - #phy-cells = <0>; - }; + usbphy1: usbphy1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + clock-frequency = <19200000>; + #phy-cells = <0>; }; }; @@ -275,7 +268,7 @@ &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1>; - fsl,usbphy = <&usbh1phy>; + fsl,usbphy = <&usbphy1>; dr_mode = "host"; phy_type = "ulpi"; status = "okay"; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 5bb727a5b6a3..66e4187022be 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -93,18 +93,11 @@ }; }; - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; + usbphy0: usbphy0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; }; display-subsystem { -- cgit v1.2.3 From 7389172fc3ed5c4c6757e853d7d5bd2cfc6d204b Mon Sep 17 00:00:00 2001 From: Marcus Cooper Date: Wed, 4 Jul 2018 10:30:03 +0200 Subject: ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2 The enabling of the EMAC was reverted as there was an issue on how to handle the integrated PHY and it was getting close to the release window (fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")). When a solution was found, then the changes were restored in 4b236a0fe512 ("arm: dts: sunxi: h3/h5: Restore EMAC changes") and 4904337fe34f ("ARM: dts: sunxi: Restore EMAC changes (boards)"). Unfortunately enabling for the Beelink X2 was missed. This reverts partially commit 6b0e06df5cad (Revert "ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2") Signed-off-by: Marcus Cooper Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index cf1f970b0c6f..5d23667dc2d2 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -123,6 +123,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &hdmi { status = "okay"; }; -- cgit v1.2.3 From 3508f7ceb8cd5750df9d3485e62b70cf5a0a2303 Mon Sep 17 00:00:00 2001 From: PaweÅ‚ Chmiel Date: Fri, 6 Jul 2018 20:32:42 +0200 Subject: ARM: dts: s5pv210: Add missing interrupt-controller property to gph2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds missing interrupt-controller property to gph2 block, to silence following warnings during build: /soc/pinctrl@e0200000/gph2: Missing interrupt-controller or interrupt-map property It's reguired by Samsung Aries boards, an S5PV210 based Samsung Galaxy S (i9000) and Galaxy S 4G phones, which are added in next patches. Signed-off-by: PaweÅ‚ Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-pinctrl.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index 3a79feab11c3..7f0c9d447871 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -258,6 +258,8 @@ gph2: gph2 { gpio-controller; #gpio-cells = <2>; + + interrupt-controller; #interrupt-cells = <2>; }; -- cgit v1.2.3 From 170642468a513eacc694fcd924dd71d07dd28d81 Mon Sep 17 00:00:00 2001 From: PaweÅ‚ Chmiel Date: Sat, 7 Jul 2018 12:09:39 +0200 Subject: ARM: dts: s5pv210: Add initial DTS for Samsung Aries based phones MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This DTS file have initial support Samsung Aries based phones. Initial version have support for: - sdcard - internal memory (present only on non 4g variant) - max8998 pmic and rtc - max17040 fuel gauge - gpio keys - fimd (no panel driver yet) - usb (peripherial mode) - wifi Signed-off-by: PaweÅ‚ Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 419 +++++++++++++++++++++++++++++++++++ 1 file changed, 419 insertions(+) create mode 100644 arch/arm/boot/dts/s5pv210-aries.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi new file mode 100644 index 000000000000..575094ea7024 --- /dev/null +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S5PV210 based Galaxy Aries board device tree source + */ + +/dts-v1/; +#include +#include +#include "s5pv210.dtsi" + +/ { + compatible = "samsung,aries", "samsung,s5pv210"; + + aliases { + i2c6 = &i2c_pmic; + i2c9 = &i2c_fuel; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x05000000 + 0x40000000 0x10000000 + 0x50000000 0x08000000>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_gpio_rst>; + post-power-on-delay-ms = <500>; + power-off-delay-us = <500>; + }; + + i2c_pmic: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "maxim,max8998"; + reg = <0x66>; + interrupt-parent = <&gph0>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + max8998,pmic-buck1-default-dvs-idx = <1>; + max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, + <&gph0 4 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck1-dvs-voltage = <1275000>, <1200000>, + <1050000>, <950000>; + + max8998,pmic-buck2-default-dvs-idx = <0>; + max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>; + + regulators { + ldo2_reg: LDO2 { + regulator-name = "VALIVE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VUSB_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3600000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VLCD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* Till we get panel driver */ + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + regulator-name = "VUSB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VPLL_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "CAM_AF_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "VGA_VDDIO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "VGA_DVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "CAM_ISP_HOST_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + regulator-name = "VGA_AVDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "VCC_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* Till we get panel driver */ + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck1_reg: BUCK1 { + regulator-name = "vddarm"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1250000>; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "vddint"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VCC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; + + cp32khz_reg: EN32KHz-CP { + regulator-name = "32KHz CP"; + }; + + vichg_reg: ENVICHG { + regulator-name = "VICHG"; + regulator-always-on; + }; + + safe1_sreg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + }; + + safe2_sreg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + }; + }; + }; + }; + + i2c_fuel: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + fuelgauge@36 { + compatible = "maxim,max17040"; + interrupt-parent = <&vic0>; + interrupts = <7>; + reg = <0x36>; + }; + }; +}; + +&fimd { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_clk &lcd_data24>; + status = "okay"; + + samsung,invert-vden; + samsung,invert-vclk; + + display-timings { + timing-0 { + /* 480x800@60Hz */ + clock-frequency = <25628040>; + hactive = <480>; + vactive = <800>; + hfront-porch = <16>; + hback-porch = <16>; + hsync-len = <2>; + vfront-porch = <28>; + vback-porch = <1>; + vsync-len = <2>; + }; + }; +}; + +&hsotg { + vusb_a-supply = <&ldo8_reg>; + vusb_d-supply = <&ldo3_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&pinctrl0 { + wlan_bt_en: wlan-bt-en { + samsung,pins = "gpb-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-val = <1>; + }; + + wlan_gpio_rst: wlan-gpio-rst { + samsung,pins = "gpg1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + wifi_host_wake: wifi-host-wake { + samsung,pins = "gph2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + tf_detect: tf-detect { + samsung,pins = "gph3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + wifi_wake: wifi-wake { + samsung,pins = "gph3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&sdhci1 { + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + max-frequency = <38400000>; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4 &wifi_wake &wifi_host_wake &wlan_bt_en>; + pinctrl-names = "default"; + cap-sd-highspeed; + cap-mmc-highspeed; + + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + status = "okay"; + + wlan@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gph2>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&sdhci2 { + bus-width = <4>; + cd-gpios = <&gph3 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <&ldo5_reg>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + status = "okay"; + vbus-supply = <&safe1_sreg>; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; -- cgit v1.2.3 From a3213bfb461cedc25817fd8d20e896db61e47744 Mon Sep 17 00:00:00 2001 From: PaweÅ‚ Chmiel Date: Sat, 7 Jul 2018 12:09:40 +0200 Subject: ARM: dts: s5pv210: Add initial DTS for Samsung Galaxy S phone MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This DTS file have initial support Samsung Galaxy S phone, also known as i9000. It belongs to Samsung Aries devices family. Initial version have support for: - sdcard - internal memory - max8998 pmic and rtc - max17040 fuel gauge - gpio keys - fimd (no panel driver yet) - usb (peripherial mode) - wifi Signed-off-by: PaweÅ‚ Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/s5pv210-galaxys.dts | 77 +++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) create mode 100644 arch/arm/boot/dts/s5pv210-galaxys.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..b0514a956447 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -859,6 +859,7 @@ dtb-$(CONFIG_ARCH_S3C64XX) += \ s3c6410-smdk6410.dtb dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-aquila.dtb \ + s5pv210-galaxys.dtb \ s5pv210-goni.dtb \ s5pv210-smdkc110.dtb \ s5pv210-smdkv210.dtb \ diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts new file mode 100644 index 000000000000..842276749717 --- /dev/null +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include +#include +#include "s5pv210-aries.dtsi" + +/ { + model = "Samsung Galaxy S1 (GT-I9000) based on S5PV210"; + compatible = "samsung,galaxys", "samsung,aries", "samsung,s5pv210"; + + chosen { + stdout-path = &uart2; + /* + * It's hard to change those parameters in stock bootloader, + * since it requires special hardware/cable. + * Let's hardocde bootargs for now, till u-boot port is finished, + * with which it should be easier. + */ + bootargs = "root=/dev/mmcblk2p1 rw rootwait ignore_loglevel earlyprintk"; + }; + + nand_pwrseq: nand-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpj2 7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&massmemory_en>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "power"; + gpios = <&gph2 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + vol-down { + label = "volume_down"; + gpios = <&gph3 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + vol-up { + label = "volume_up"; + gpios = <&gph3 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "home"; + gpios = <&gph3 5 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; +}; + +&pinctrl0 { + massmemory_en: massmemory-en { + samsung,pins = "gpj2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&sdhci0 { + bus-width = <4>; + non-removable; + mmc-pwrseq = <&nand_pwrseq>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; -- cgit v1.2.3 From ac71a5cca57d3996e32e5a7bc3b17075f7c15d15 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Sat, 7 Jul 2018 12:09:41 +0200 Subject: ARM: dts: s5pv210: Add initial DTS for SGH-T959P phone MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This DTS file have initial support Samsung SGH-T959P phone, also known as Samsung Galaxy S 4G or fascinate4g. It belongs to Samsung Aries devices family. Initial version have support for: - sdcard - max8998 pmic and rtc - max17040 fuel gauge - gpio keys - fimd (no panel driver yet) - usb (peripherial mode) - wifi Signed-off-by: Jonathan Bakker Signed-off-by: PaweÅ‚ Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/s5pv210-fascinate4g.dts | 45 +++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm/boot/dts/s5pv210-fascinate4g.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0514a956447..717f8770ccbb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -859,6 +859,7 @@ dtb-$(CONFIG_ARCH_S3C64XX) += \ s3c6410-smdk6410.dtb dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-aquila.dtb \ + s5pv210-fascinate4g.dtb \ s5pv210-galaxys.dtb \ s5pv210-goni.dtb \ s5pv210-smdkc110.dtb \ diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts new file mode 100644 index 000000000000..ccf761b1babf --- /dev/null +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include +#include +#include "s5pv210-aries.dtsi" + +/ { + model = "Samsung Galaxy S Fascinate 4G (SGH-T959P) based on S5PV210"; + compatible = "samsung,fascinate4g", "samsung,aries", "samsung,s5pv210"; + + chosen { + stdout-path = &uart2; + /* + * It's hard to change those parameters in stock bootloader, + * since it requires special hardware/cable. + * Let's hardocde bootargs for now, till u-boot port is finished, + * with which it should be easier. + */ + bootargs = "root=/dev/mmcblk1p1 rw rootwait ignore_loglevel earlyprintk"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "power"; + gpios = <&gph2 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + vol-down { + label = "volume_down"; + gpios = <&gph3 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + vol-up { + label = "volume_up"; + gpios = <&gph3 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; -- cgit v1.2.3 From a37ff8f985cbc5333b735244ffd586e6e0e47346 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 20 May 2018 16:48:44 +0300 Subject: ARM: dts: tegra20: Add Memory Client reset to VDE Hook up Memory Client reset of the Video Decoder to the decoders DT node. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 983dd5c14794..f9495f12e731 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include #include +#include #include #include @@ -282,7 +283,8 @@ ; /* SXE interrupt */ interrupt-names = "sync-token", "bsev", "sxe"; clocks = <&tegra_car TEGRA20_CLK_VDE>; - resets = <&tegra_car 61>; + reset-names = "vde", "mc"; + resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; }; apbmisc@70000800 { @@ -593,11 +595,12 @@ clock-names = "pclk", "clk32k_in"; }; - memory-controller@7000f000 { + mc: memory-controller@7000f000 { compatible = "nvidia,tegra20-mc"; reg = <0x7000f000 0x024 0x7000f03c 0x3c4>; interrupts = ; + #reset-cells = <1>; }; iommu@7000f024 { -- cgit v1.2.3 From d072094b0d4e96a55661f07c0b56077162b38927 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 20 May 2018 16:48:46 +0300 Subject: ARM: dts: tegra30: Add Memory Client reset to VDE Hook up Memory Client reset of the Video Decoder to the decoders DT node. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 09087b9c5e26..3300ff976053 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -404,7 +404,8 @@ ; /* SXE interrupt */ interrupt-names = "sync-token", "bsev", "sxe"; clocks = <&tegra_car TEGRA30_CLK_VDE>; - resets = <&tegra_car 61>; + reset-names = "vde", "mc"; + resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; }; apbmisc@70000800 { @@ -712,6 +713,7 @@ interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; }; fuse@7000f800 { -- cgit v1.2.3 From 8008b6f3ac155ff9351841ac00253cd41119d1d8 Mon Sep 17 00:00:00 2001 From: "Derald D. Woods" Date: Tue, 3 Jul 2018 20:48:30 -0500 Subject: ARM: dts: am3517-evm: Add 'vdd_io_reg' regulator references There are a few peripherals that generate some extra noise when they don't have a regulator assigned to them. This patch assigns them to their actual tps65023 regulator 'vdd_io_reg' (VDCDC2). Signed-off-by: Derald D. Woods Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517-evm.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index b834ebe091b3..1d158cfda15f 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -127,6 +127,7 @@ status = "okay"; pinctrl-names = "default"; enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */ + vcc-supply = <&vdd_io_reg>; port { lcd_in: endpoint { @@ -154,6 +155,7 @@ bl: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; + power-supply = <&vdd_io_reg>; pinctrl-0 = <&backlight_pins>; pwms = <&pwm11 0 5000000 0>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; @@ -210,6 +212,7 @@ reg = <0x21>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <&vdd_io_reg>; }; }; -- cgit v1.2.3 From ab9a13665e7c25b31cbe4f6ea8acf2deaad5cacd Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 4 Jul 2018 09:37:38 +0100 Subject: ARM: dts: pandaboard: add gpio user button The PandaBoard has a user button connected to GPIO. On the ES this is connected to GPIO 113, on all the other Panda editons this is GPIO 121. Signed-off-by: Peter Robinson Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-panda-common.dtsi | 22 ++++++++++++++++++++++ arch/arm/boot/dts/omap4-panda-es.dts | 12 ++++++++++++ 2 files changed, 34 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 563b47c5f0c7..27895c1604b9 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -5,6 +5,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include #include "elpida_ecb240abacn.dtsi" / { @@ -43,6 +44,21 @@ }; }; + gpio_keys: gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = < + &button_pins + >; + + buttonS2 { + label = "button S2"; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ + linux,code = ; + wakeup-source; + }; + }; + sound: sound { compatible = "ti,abe-twl6040"; ti,model = "PandaBoard"; @@ -357,6 +373,12 @@ OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ >; }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */ + >; + }; }; &omap4_pmx_wkup { diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index 940fe4f7c5f6..984f642639fa 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -46,6 +46,12 @@ OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */ >; }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ + >; + }; }; &led_wkgpio_pins { @@ -68,6 +74,12 @@ }; }; +&gpio_keys { + buttonS2 { + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* gpio_113 */ + }; +}; + &gpio1 { ti,no-reset-on-init; }; -- cgit v1.2.3 From 6e1811900b6fe6f2b4665dba6bd6ed32c6b98575 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 3 Jul 2018 09:59:47 +0100 Subject: ARM: tegra: Fix Tegra30 Cardhu PCA954x reset On all versions of Tegra30 Cardhu, the reset signal to the NXP PCA9546 I2C mux is connected to the Tegra GPIO BB0. Currently, this pin on the Tegra is not configured as a GPIO but as a special-function IO (SFIO) that is multiplexing the pin to an I2S controller. On exiting system suspend, I2C commands sent to the PCA9546 are failing because there is no ACK. Although it is not possible to see exactly what is happening to the reset during suspend, by ensuring it is configured as a GPIO and driven high, to de-assert the reset, the failures are no longer seen. Please note that this GPIO is also used to drive the reset signal going to the camera connector on the board. However, given that there is no camera support currently for Cardhu, this should not have any impact. Fixes: 40431d16ff11 ("ARM: tegra: enable PCA9546 on Cardhu") Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-cardhu.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 92a9740c533f..3b1db7b9ec50 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -206,6 +206,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; }; }; -- cgit v1.2.3 From 700253e7b2b293785218faef6a69bc8cb49b6345 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Tue, 3 Jul 2018 17:03:39 +0200 Subject: ARM: tegra: Fix can2 on Tegra30 Apalis CAN2 currently fails on probe as follows: mcp251x spi1.1: Probe failed, err=19 Fix this by enabling input on pin mux of resp. SPI4 pins. Signed-off-by: Marcel Ziswiler Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index d1d21ec2a844..9ff6aafd72b3 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -118,6 +118,7 @@ nvidia,function = "spi4"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; /* CAN_INT2 */ spi2_cs2_n_pw3 { -- cgit v1.2.3 From b8ccf02a5014b8d3a828a859a35b1fb6ceb6e688 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 21 May 2018 11:39:07 -0700 Subject: ARM: dts: bcm283x: Add the PMU to the devicetree. This only probes on arm64 so far, but hopefully that driver will be generalized soon. Signed-off-by: Eric Anholt Acked-by: Stefan Wahren --- arch/arm/boot/dts/bcm2837.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi index 7704bb029605..beb6c502dadc 100644 --- a/arch/arm/boot/dts/bcm2837.dtsi +++ b/arch/arm/boot/dts/bcm2837.dtsi @@ -17,6 +17,12 @@ }; }; + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupt-parent = <&local_intc>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + }; + timer { compatible = "arm,armv7-timer"; interrupt-parent = <&local_intc>; -- cgit v1.2.3 From b7dd29b401f5862ea24df13ee5c10bed8668c14b Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Mon, 2 Jul 2018 14:20:20 +0200 Subject: ARM: dts: bcm283x: Add Transposer block The transposer block is allowing one to write the result of the VC4 composition back to memory instead of displaying it on a screen. Signed-off-by: Boris Brezillon Reviewed-by: Liviu Dudau Reviewed-by: Eric Anholt Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm283x.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 61315cf734ef..31b29646b14c 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -66,6 +66,12 @@ clock-frequency = <1000000>; }; + txp@7e004000 { + compatible = "brcm,bcm2835-txp"; + reg = <0x7e004000 0x20>; + interrupts = <1 11>; + }; + dma: dma@7e007000 { compatible = "brcm,bcm2835-dma"; reg = <0x7e007000 0xf00>; -- cgit v1.2.3 From 00d1ae38404537975d7e055ba2eaa6a11a2148ea Mon Sep 17 00:00:00 2001 From: Clément Péron Date: Thu, 3 May 2018 11:56:18 +0200 Subject: ARM: dts: cygnus: add ethernet0 alias MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to avoid Linux generating a random mac address on every boot, add an ethernet0 alias that will allow u-boot to patch the dtb with the MAC address. Signed-off-by: Clément Péron Acked-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 9fe4f5a6379e..1a05b8f48b54 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -41,6 +41,10 @@ model = "Broadcom Cygnus SoC"; interrupt-parent = <&gic>; + aliases { + ethernet0 = ð0; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From a08e950de6499ff7ed6f62c74512e2bf9f0e0985 Mon Sep 17 00:00:00 2001 From: Mohamed Ismail Abdul Packir Mohamed Date: Wed, 6 Jun 2018 11:21:31 -0700 Subject: ARM: dts: cygnus: enable iproc-hwrng MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the HW rng driver "iproc-rng200" for all cygnus platforms. Signed-off-by: Mohamed Ismail Abdul Packir Mohamed Reviewed-by: Ray Jui Signed-off-by: Scott Branden Tested-by: Clément Péron Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 1a05b8f48b54..b511f88efcb0 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -421,6 +421,11 @@ status = "disabled"; }; + rng: rng@18032000 { + compatible = "brcm,iproc-rng200"; + reg = <0x18032000 0x28>; + }; + sdhci0: sdhci@18041000 { compatible = "brcm,sdhci-iproc-cygnus"; reg = <0x18041000 0x100>; -- cgit v1.2.3 From 37f6130ec39fe14e923d472746a51e6f06f761b7 Mon Sep 17 00:00:00 2001 From: Vivek Unune Date: Mon, 9 Apr 2018 18:31:53 -0400 Subject: ARM: dts: BCM5301X: Make USB 3.0 PHY use MDIO PHY driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, the USB 3.0 PHY in bcm5301x.dtsi uses platform driver which requires register range "ccb-mii" <0x18003000 0x1000>. This range overlaps with MDIO cmd and param registers (<0x18003000 0x8>). Essentially, the platform driver partly acts like a MDIO bus driver, hence to use of this register range. In some Northstar devices like Linksys EA9500, secondary switch is connected via external MDIO. The only way to access and configure the external switch is via MDIO bus. When we enable the MDIO bus in it's current state, the MDIO bus and any child buses fail to register because of the register range overlap. On Northstar, the USB 3.0 PHY is connected at address 0x10 on the internal MDIO bus. This change moves the usb3_phy node and makes it a child node of internal MDIO bus. Thanks to RafaÅ‚ MiÅ‚ecki's commit af850e14a7ae ("phy: bcm-ns-usb3: add MDIO driver using proper bus layer") the same USB 3.0 platform driver can now act as USB 3.0 PHY MDIO driver. Tested on Linksys Panamera (EA9500) Signed-off-by: Vivek Unune Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 4 +++ arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 4 +++ arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 4 +++ arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts | 4 +++ arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 4 +++ arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 4 +++ arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 4 +++ arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 4 +++ arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 4 +++ arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 4 +++ arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 4 +++ arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 4 +++ arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 4 +++ arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 4 +++ arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts | 4 +++ arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 4 +++ arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 4 +++ arch/arm/boot/dts/bcm4709-linksys-ea9200.dts | 4 +++ arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 4 +++ arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 4 +++ arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts | 4 +++ arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 4 +++ arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 4 +++ arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 4 +++ arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 4 +++ arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 4 +++ arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 4 +++ arch/arm/boot/dts/bcm47094.dtsi | 7 +++-- arch/arm/boot/dts/bcm5301x.dtsi | 35 +++++++++++++++++----- arch/arm/boot/dts/bcm94708.dts | 4 +++ arch/arm/boot/dts/bcm94709.dts | 4 +++ arch/arm/boot/dts/bcm953012er.dts | 4 +++ arch/arm/boot/dts/bcm953012hr.dts | 4 +++ arch/arm/boot/dts/bcm953012k.dts | 4 +++ 34 files changed, 159 insertions(+), 11 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts index ff2e551b9058..79d454ff3be4 100644 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts @@ -90,3 +90,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts index 3bcc03788f38..99365bb8c41e 100644 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts @@ -80,3 +80,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts index a587384f8e40..bc330b1f6de0 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts @@ -146,3 +146,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts index 6c8f0ad82332..258d2b251900 100644 --- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts +++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts @@ -38,3 +38,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index ebda45fe9ea4..e7fdaed99bd0 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -57,3 +57,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index 9dd0e22c906a..42bafc644013 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -64,3 +64,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index d7c34fa72b4b..dce35eb79dbe 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -91,3 +91,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts index 2642494c97a1..b7a024b7951b 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts @@ -83,3 +83,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts index e7b09b7b7d25..f7f834cd3448 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts @@ -158,3 +158,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts index 16314fcc6e56..76a2bab3bc6f 100644 --- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts @@ -74,3 +74,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index 328aa90240ce..69e3570e03dd 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -118,3 +118,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts index 8ea46eed26e2..0f6f0fe13bfb 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts @@ -104,3 +104,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index 5eeac7302329..f77089744996 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -57,3 +57,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index da4d9ec62fc6..4d427863756f 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -105,3 +105,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts index c94c732188fb..5f663f848db1 100644 --- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts @@ -99,3 +99,7 @@ &usb2 { vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts index 22271818f901..2033411240c7 100644 --- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts @@ -62,3 +62,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts index 79a9633ec417..77d1687b4228 100644 --- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts @@ -127,3 +127,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts index db744a5e122d..983149b55269 100644 --- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts +++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts @@ -39,3 +39,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts index 9e267d38df4c..ca41481b44bd 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts @@ -101,3 +101,7 @@ &usb3 { vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts index d266131652ad..aa69e656d395 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -182,3 +182,7 @@ &usb3 { vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts index f5bf6586ae07..c7143a9daa1a 100644 --- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts +++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts @@ -104,3 +104,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index d173bcd93b91..03c1ab188576 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -115,3 +115,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index f47afe36d857..cbe8ffef7230 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -33,3 +33,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts index a5cef51cfe4f..3e5e9972cd97 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts @@ -60,3 +60,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts index 7496aabf8f77..7acbecd42950 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts @@ -60,3 +60,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index 53aaa5212610..f4558d9d2769 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -100,3 +100,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts index 0e718edc065a..30719380b6c0 100644 --- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts +++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts @@ -91,3 +91,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi index 4840a782fc05..f7c3e274b354 100644 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -7,9 +7,10 @@ #include "bcm4708.dtsi" / { - usb3_phy: usb3-phy { - compatible = "brcm,ns-bx-usb3-phy"; - }; +}; + +&usb3_phy { + compatible = "brcm,ns-bx-usb3-phy"; }; &uart0 { diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 9a076c409f4e..096fb7681fa2 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -154,13 +154,6 @@ clock-names = "phy-ref-clk"; }; - usb3_phy: usb3-phy { - compatible = "brcm,ns-ax-usb3-phy"; - reg = <0x18105000 0x1000>, <0x18003000 0x1000>; - reg-names = "dmp", "ccb-mii"; - #phy-cells = <0>; - }; - axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; @@ -359,7 +352,33 @@ reg = <0x18003000 0x8>; #size-cells = <1>; #address-cells = <0>; - status = "disabled"; + }; + + mdio-bus-mux { + compatible = "mdio-mux-mmioreg"; + mdio-parent-bus = <&mdio>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x18003000 0x4>; + mux-mask = <0x200>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + usb3_phy: usb3-phy@10 { + compatible = "brcm,ns-ax-usb3-phy"; + reg = <0x10>; + usb3-dmp-syscon = <&usb3_dmp>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb3_dmp: syscon@18105000 { + reg = <0x18105000 0x1000>; }; i2c0: i2c@18009000 { diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts index 2e08c895f281..934f07adfe3c 100644 --- a/arch/arm/boot/dts/bcm94708.dts +++ b/arch/arm/boot/dts/bcm94708.dts @@ -42,3 +42,7 @@ reg = <0x00000000 0x08000000>; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/bcm94709.dts index c37616c67edc..31e4dd098776 100644 --- a/arch/arm/boot/dts/bcm94709.dts +++ b/arch/arm/boot/dts/bcm94709.dts @@ -42,3 +42,7 @@ reg = <0x00000000 0x08000000>; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts index 40e694bfe5ca..17f63c7a0437 100644 --- a/arch/arm/boot/dts/bcm953012er.dts +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -90,3 +90,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/bcm953012hr.dts index 3076e81699cf..11b0f5ed99e6 100644 --- a/arch/arm/boot/dts/bcm953012hr.dts +++ b/arch/arm/boot/dts/bcm953012hr.dts @@ -95,3 +95,7 @@ reg = <0x00700000 0x00900000>; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts index 79c168e2714b..e798055d6989 100644 --- a/arch/arm/boot/dts/bcm953012k.dts +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -113,3 +113,7 @@ &uart1 { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; -- cgit v1.2.3 From a21e7548438f3a8f59f9b9f3a8bc973613d3726a Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Thu, 14 Jun 2018 18:41:47 +0200 Subject: ARM: dts: BCM53573: Add architected timer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's a standard ARM architected timer that was simply missed when initially adding this .dtsi file. Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53573.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index 16007d72c346..453a2a37dabd 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -48,6 +48,14 @@ }; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + clocks { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 2bebdfcdcd0feb58d5df419532a2cedc78a336d7 Mon Sep 17 00:00:00 2001 From: Vivek Unune Date: Mon, 18 Jun 2018 13:41:59 -0400 Subject: ARM: dts: BCM5301X: Add support for Linksys EA9500 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hardware Info ------------- Processor - Broadcom BCM4709C0KFEBG dual-core @ 1.4 GHz Switch - BCM53012 in BCM4709C0KFEBG & external BCM53125 DDR3 RAM - 256 MB Flash - 128 MB (Toshiba TC58BVG0S3HTA00) 2.4GHz - BCM4366 4×4 2.4/5G single chip 802.11ac SoC Power Amp - Skyworks SE2623L 2.4 GHz power amp (x4) 5GHz x 2 - BCM4366 4×4 2.4/5G single chip 802.11ac SoC Power Amp - PLX Technology PEX8603 3-lane, 3-port PCIe switch Ports - 8 Ports, 1 WAN Ports Antennas - 8 Antennas Serial Port - @J6 [GND,TX,RX] (VCC NC) 115200 8n1 Tested with OpenWrt built with DSA driver and Kernel v4.14 Signed-off-by: Vivek Unune Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 229 ++++++++++++++++++++++++ 1 file changed, 229 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index cbe8ffef7230..36efe410dcd7 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -31,6 +31,235 @@ linux,code = ; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; + + rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + wps { + label = "bcm53xx:white:wps"; + gpios = <&chipcommon 22 GPIO_ACTIVE_LOW>; + }; + + usb2 { + label = "bcm53xx:green:usb2"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + power { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + }; + + wifi-disabled { + label = "bcm53xx:amber:wifi-disabled"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + + wifi-enabled { + label = "bcm53xx:white:wifi-enabled"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + + bluebar1 { + label = "bcm53xx:white:bluebar1"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + }; + + bluebar2 { + label = "bcm53xx:white:bluebar2"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + + bluebar3 { + label = "bcm53xx:white:bluebar3"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + + bluebar4 { + label = "bcm53xx:white:bluebar4"; + gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>; + }; + + bluebar5 { + label = "bcm53xx:white:bluebar5"; + gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; + }; + + bluebar6 { + label = "bcm53xx:white:bluebar6"; + gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; + }; + + bluebar7 { + label = "bcm53xx:white:bluebar7"; + gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>; + }; + + bluebar8 { + label = "bcm53xx:white:bluebar8"; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + }; + }; + + mdio-bus-mux { + /* BIT(9) = 1 => external mdio */ + mdio_ext: mdio@200 { + reg = <0x200>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio-mii-mux { + compatible = "mdio-mux-mmioreg"; + mdio-parent-bus = <&mdio_ext>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1800c1c0 0x4>; + + /* BIT(6) = mdc, BIT(7) = mdio */ + mux-mask = <0xc0>; + + mdio-mii@0 { + /* Enable MII function */ + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "brcm,bcm53125"; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + reset-names = "robo_reset"; + reg = <0>; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan5"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan6"; + }; + + port@4 { + reg = <4>; + label = "lan3"; + }; + + sw1_p8: port@8 { + reg = <8>; + ethernet = <&sw0_p0>; + label = "cpu"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 14 GPIO_ACTIVE_HIGH>; +}; + +&srab { + compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; + status = "okay"; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan7"; + }; + + port@2 { + reg = <2>; + label = "lan4"; + }; + + port@3 { + reg = <3>; + label = "lan8"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@8 { + reg = <8>; + ethernet = <&gmac2>; + label = "cpu"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + sw0_p0: port@0 { + reg = <0>; + label = "extsw"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; }; }; -- cgit v1.2.3 From f48ba1ae6ac5e5df6fd4ebd8e9593296396e0831 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 9 Jul 2018 18:05:16 +0200 Subject: ARM: tegra: Remove usage of deprecated skeleton.dtsi Remove the usage of skeleton.dtsi because it was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). It also allows later to fix DTC warnings for missing unit name in /memory nodes. Compiled DTBs are the same as before this commit. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stefan Agner Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 8 ++++++-- arch/arm/boot/dts/tegra124.dtsi | 6 ++++-- arch/arm/boot/dts/tegra20.dtsi | 8 ++++++-- arch/arm/boot/dts/tegra30-apalis.dtsi | 4 ++++ arch/arm/boot/dts/tegra30.dtsi | 8 ++++++-- 5 files changed, 26 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 84c4358dacac..d45337f61b92 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -5,11 +5,15 @@ #include #include -#include "skeleton.dtsi" - / { compatible = "nvidia,tegra114"; interrupt-parent = <&lic>; + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + }; host1x@50000000 { compatible = "nvidia,tegra114-host1x", "simple-bus"; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 174092bfac90..951feea784af 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -7,14 +7,16 @@ #include #include -#include "skeleton.dtsi" - / { compatible = "nvidia,tegra124"; interrupt-parent = <&lic>; #address-cells = <2>; #size-cells = <2>; + memory { + device_type = "memory"; + }; + pcie@1003000 { compatible = "nvidia,tegra124-pcie"; device_type = "pci"; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index f9495f12e731..20ea6b1bbe2f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -5,11 +5,15 @@ #include #include -#include "skeleton.dtsi" - / { compatible = "nvidia,tegra20"; interrupt-parent = <&lic>; + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + }; iram@40000000 { compatible = "mmio-sram"; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 9ff6aafd72b3..01796dcc5fce 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -10,6 +10,10 @@ model = "Toradex Apalis T30"; compatible = "toradex,apalis_t30", "nvidia,tegra30"; + memory { + reg = <0 0>; + }; + pcie@3000 { avdd-pexa-supply = <&vdd2_reg>; vdd-pexa-supply = <&vdd2_reg>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 3300ff976053..0a3267aebbe3 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -5,11 +5,15 @@ #include #include -#include "skeleton.dtsi" - / { compatible = "nvidia,tegra30"; interrupt-parent = <&lic>; + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + }; pcie@3000 { compatible = "nvidia,tegra30-pcie"; -- cgit v1.2.3 From 482997699ef038af7553399d49b7ba74c3301424 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 9 Jul 2018 18:05:17 +0200 Subject: ARM: tegra: Fix unit_address_vs_reg DTC warnings for /memory Add a generic /memory node in each Tegra DTSI (with empty reg property, to be overidden by each DTS) and set proper unit address for /memory nodes to fix the DTC warnings: arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name The DTB after the change is the same as before except adding unit-address to /memory node. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stefan Agner Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 2 +- arch/arm/boot/dts/tegra114-roth.dts | 2 +- arch/arm/boot/dts/tegra114-tn7.dts | 2 +- arch/arm/boot/dts/tegra114.dtsi | 3 ++- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +- arch/arm/boot/dts/tegra124-venice2.dts | 2 +- arch/arm/boot/dts/tegra124.dtsi | 3 ++- arch/arm/boot/dts/tegra20-colibri-512.dtsi | 2 +- arch/arm/boot/dts/tegra20-harmony.dts | 2 +- arch/arm/boot/dts/tegra20-paz00.dts | 2 +- arch/arm/boot/dts/tegra20-seaboard.dts | 2 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +- arch/arm/boot/dts/tegra20-trimslice.dts | 2 +- arch/arm/boot/dts/tegra20-ventana.dts | 2 +- arch/arm/boot/dts/tegra20.dtsi | 3 ++- arch/arm/boot/dts/tegra30-apalis.dtsi | 4 ++-- arch/arm/boot/dts/tegra30-beaver.dts | 2 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 +- arch/arm/boot/dts/tegra30.dtsi | 3 ++- 23 files changed, 28 insertions(+), 24 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index eafff16765b4..1788556b4977 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -23,7 +23,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 7ed7370ee67a..3d3835591cd2 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -28,7 +28,7 @@ }; }; - memory { + memory@80000000 { /* memory >= 0x79600000 is reserved for firmware usage */ reg = <0x80000000 0x79600000>; }; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 7fc4a8b31e45..bfdd1bf61816 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -28,7 +28,7 @@ }; }; - memory { + memory@80000000 { /* memory >= 0x37e00000 is reserved for firmware usage */ reg = <0x80000000 0x37e00000>; }; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index d45337f61b92..0d7a6327e404 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -11,8 +11,9 @@ #address-cells = <1>; #size-cells = <1>; - memory { + memory@80000000 { device_type = "memory"; + reg = <0x80000000 0x0>; }; host1x@50000000 { diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 3455822350c5..573aaa50fff1 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -15,7 +15,7 @@ compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1", "nvidia,tegra124"; - memory { + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 9f960c84ba10..0f0d4a4988b9 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -50,7 +50,7 @@ model = "Toradex Apalis TK1"; compatible = "toradex,apalis-tk1", "nvidia,tegra124"; - memory { + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 6dbcf84dafbc..9151b3ebb839 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -24,7 +24,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 3609367037a6..d5f11d6d987e 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -13,7 +13,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 89bcc178994d..82d139648ef1 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 951feea784af..183c5acafb22 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -13,8 +13,9 @@ #address-cells = <2>; #size-cells = <2>; - memory { + memory@80000000 { device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x0>; }; pcie@1003000 { diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index 5c202b3e3bb1..5623ff8d128c 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -10,7 +10,7 @@ rtc1 = "/rtc@7000e000"; }; - memory { + memory@0 { reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 628a55a9318b..1d96d92b72a7 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { reg = <0x00000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 30436969adc0..ef245291924f 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -19,7 +19,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 284aae351ff2..f91441683aad 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { reg = <0x00000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 872046d48709..20137fc578b1 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -15,7 +15,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index d55c6b240a30..9eb26dc15f6b 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { reg = <0x00000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index ee3fbf941e79..f44551e2d9d0 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { reg = <0x00000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 20ea6b1bbe2f..86d8cd6f9548 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -11,8 +11,9 @@ #address-cells = <1>; #size-cells = <1>; - memory { + memory@0 { device_type = "memory"; + reg = <0 0>; }; iram@40000000 { diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 01796dcc5fce..349c04d18f63 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -10,8 +10,8 @@ model = "Toradex Apalis T30"; compatible = "toradex,apalis_t30", "nvidia,tegra30"; - memory { - reg = <0 0>; + memory@80000000 { + reg = <0x80000000 0x40000000>; }; pcie@3000 { diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index ae52a5039506..1434d50438f9 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x80000000 0x7ff00000>; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 3b1db7b9ec50..fb9222b479d2 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -40,7 +40,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index c44d8c40c410..9bf3327665d3 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -10,7 +10,7 @@ model = "Toradex Colibri T30"; compatible = "toradex,colibri_t30", "nvidia,tegra30"; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 0a3267aebbe3..a6781f653310 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -11,8 +11,9 @@ #address-cells = <1>; #size-cells = <1>; - memory { + memory@80000000 { device_type = "memory"; + reg = <0x80000000 0x0>; }; pcie@3000 { -- cgit v1.2.3 From 35a21229f8e0b461b1db7ab96a4ef390b42b13d2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 9 Jul 2018 18:05:18 +0200 Subject: ARM: tegra: Fix unit_address_vs_reg and avoid_unnecessary_addr_size DTC warnings Remove unneeded address/size cells properties and unit addresses to fix DTC warnings like: arch/arm/boot/dts/tegra30-apalis-eval.dtb: Warning (unit_address_vs_reg): /i2c@7000d000/stmpe811@41/stmpe_touchscreen@0: node has a unit name, but no reg property arch/arm/boot/dts/tegra30-apalis-eval.dtb: Warning (avoid_unnecessary_addr_size): /i2c@7000d000/stmpe811@41: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stefan Agner Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 4 +--- arch/arm/boot/dts/tegra30-beaver.dts | 3 --- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 -- 3 files changed, 1 insertion(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 349c04d18f63..2f807d40c1b7 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -590,8 +590,6 @@ /* STMPE811 touch screen controller */ stmpe811@41 { compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; reg = <0x41>; interrupts = ; interrupt-parent = <&gpio>; @@ -600,7 +598,7 @@ blocks = <0x5>; irq-trigger = <0x1>; - stmpe_touchscreen@0 { + stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 1434d50438f9..b0d40ac8ac6e 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1790,9 +1790,6 @@ vccio-supply = <&vdd_5v_in_reg>; regulators { - #address-cells = <1>; - #size-cells = <0>; - vdd1_reg: vdd1 { regulator-name = "vddio_ddr_1v2"; regulator-min-microvolt = <1200000>; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 9bf3327665d3..526ed71cf7a3 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -351,8 +351,6 @@ /* STMPE811 touch screen controller */ stmpe811@41 { compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; reg = <0x41>; interrupts = ; interrupt-parent = <&gpio>; -- cgit v1.2.3 From 8ab11f8068ef57e5763e1cc91b3dfe23a2482e68 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 9 Jul 2018 18:05:19 +0200 Subject: ARM: tegra: Work safely with 256 MB Colibri-T20 modules Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM (with 1024 MB NAND) flavors. Both of them will use the same DTSI expecting the bootloader to do the fixup of /memory node. However in case it does not happen, let's stay on safe side by limiting the memory to 256 MB for both versions of Colibri-T20. Rename to remove the unnecessary memory size from the device tree file name. While at it, also follow the typical Toradex SoC, module, carrier board hierarchy. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stefan Agner Tested-by: Stefan Agner Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 2 +- arch/arm/boot/dts/tegra20-colibri-512.dtsi | 540 ---------------------------- arch/arm/boot/dts/tegra20-colibri-iris.dts | 106 ++++++ arch/arm/boot/dts/tegra20-colibri.dtsi | 545 +++++++++++++++++++++++++++++ arch/arm/boot/dts/tegra20-iris-512.dts | 106 ------ 5 files changed, 652 insertions(+), 647 deletions(-) delete mode 100644 arch/arm/boot/dts/tegra20-colibri-512.dtsi create mode 100644 arch/arm/boot/dts/tegra20-colibri-iris.dts create mode 100644 arch/arm/boot/dts/tegra20-colibri.dtsi delete mode 100644 arch/arm/boot/dts/tegra20-iris-512.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..5daf9ef53cd2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1039,7 +1039,7 @@ dtb-$(CONFIG_ARCH_TANGO) += \ tango4-vantage-1172.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-harmony.dtb \ - tegra20-iris-512.dtb \ + tegra20-colibri-iris.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ tegra20-plutux.dtb \ diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi deleted file mode 100644 index 5623ff8d128c..000000000000 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ /dev/null @@ -1,540 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra20.dtsi" - -/ { - model = "Toradex Colibri T20 512MB"; - compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - }; - - memory@0 { - reg = <0x00000000 0x20000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&i2c_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - audio_refclk { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - nvidia,pull = ; - nvidia,tristate = ; - }; - crt { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - displaya { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", - "ld4", "ld5", "ld6", "ld7", "ld8", - "ld9", "ld10", "ld11", "ld12", "ld13", - "ld14", "ld15", "ld16", "ld17", - "lhs", "lpw0", "lpw2", "lsc0", - "lsc1", "lsck", "lsda", "lspi", "lvs"; - nvidia,function = "displaya"; - nvidia,tristate = ; - }; - gpio_dte { - nvidia,pins = "dte"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - gpio_gmi { - nvidia,pins = "ata", "atc", "atd", "ate", - "dap1", "dap2", "dap4", "gpu", "irrx", - "irtx", "spia", "spib", "spic"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - gpio_pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - gpio_uac { - nvidia,pins = "uac"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - nvidia,tristate = ; - }; - i2c1 { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - i2c3 { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - i2cddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - nvidia,pull = ; - nvidia,tristate = ; - }; - irda { - nvidia,pins = "uad"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - nand { - nvidia,pins = "kbca", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - }; - owc { - nvidia,pins = "owc"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - nvidia,tristate = ; - }; - pwm { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - nvidia,tristate = ; - }; - sdio4 { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - spi1 { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - spi4 { - nvidia,pins = "slxa", "slxc", "slxd", "slxk"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - uarta { - nvidia,pins = "sdio1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - uartd { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi_refclk { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - usb_gpio { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - vi { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - vi_sc { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - nvidia,pull = ; - nvidia,tristate = ; - }; - }; - }; - - ac97: ac97@70002000 { - status = "okay"; - nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_HIGH>; - nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) - GPIO_ACTIVE_HIGH>; - }; - - /* - * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - clock-frequency = <400000>; - }; - - /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ - i2c_ddc: i2c@7000c400 { - clock-frequency = <10000>; - }; - - /* GEN2_I2C: unused */ - - /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */ - - /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_3v3_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&vdd_3v3_reg>; - vinldo4-supply = <&vdd_3v3_reg>; - vinldo678-supply = <&vdd_3v3_reg>; - vinldo9-supply = <&vdd_3v3_reg>; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - sys_reg: regulator@0 { - reg = <0>; - regulator-compatible = "sys"; - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - regulator@1 { - reg = <1>; - regulator-compatible = "sm0"; - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - regulator@2 { - reg = <2>; - regulator-compatible = "sm1"; - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: regulator@3 { - reg = <3>; - regulator-compatible = "sm2"; - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - regulator@5 { - reg = <5>; - regulator-compatible = "ldo1"; - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - regulator@6 { - reg = <6>; - regulator-compatible = "ldo2"; - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - /* LDO3 is not connected to anything */ - - regulator@8 { - reg = <8>; - regulator-compatible = "ldo4"; - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: regulator@9 { - reg = <9>; - regulator-compatible = "ldo5"; - regulator-name = "vdd_ldo5,vdd_fuse"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - regulator@10 { - reg = <10>; - regulator-compatible = "ldo6"; - regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - hdmi_vdd_reg: regulator@11 { - reg = <11>; - regulator-compatible = "ldo7"; - regulator-name = "vdd_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: regulator@12 { - reg = <12>; - regulator-compatible = "ldo8"; - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - regulator@13 { - reg = <13>; - regulator-compatible = "ldo9"; - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - regulator@14 { - reg = <14>; - regulator-compatible = "ldo_rtc"; - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - }; - - pmc@7000e400 { - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - memory-controller@7000f400 { - emc-table@83250 { - reg = <83250>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <83250>; - nvidia,emc-registers = <0x00000005 0x00000011 - 0x00000004 0x00000002 0x00000004 0x00000004 - 0x00000001 0x0000000a 0x00000002 0x00000002 - 0x00000001 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x0000025f - 0x00000000 0x00000003 0x00000003 0x00000002 - 0x00000002 0x00000001 0x00000008 0x000000c8 - 0x00000003 0x00000005 0x00000003 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00520006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@133200 { - reg = <133200>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <133200>; - nvidia,emc-registers = <0x00000008 0x00000019 - 0x00000006 0x00000002 0x00000004 0x00000004 - 0x00000001 0x0000000a 0x00000002 0x00000002 - 0x00000002 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x0000039f - 0x00000000 0x00000003 0x00000003 0x00000002 - 0x00000002 0x00000001 0x00000008 0x000000c8 - 0x00000003 0x00000007 0x00000003 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00510006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@166500 { - reg = <166500>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <166500>; - nvidia,emc-registers = <0x0000000a 0x00000021 - 0x00000008 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000a 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x000004df - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x00000009 0x000000c8 - 0x00000003 0x00000009 0x00000004 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x004f0006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <333000>; - nvidia,emc-registers = <0x00000014 0x00000041 - 0x0000000f 0x00000005 0x00000004 0x00000005 - 0x00000003 0x0000000a 0x00000005 0x00000005 - 0x00000004 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x000009ff - 0x00000000 0x00000003 0x00000003 0x00000005 - 0x00000005 0x00000001 0x0000000e 0x000000c8 - 0x00000003 0x00000011 0x00000006 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00380006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - sdhci@c8000600 { - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_3v3_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "internal_usb"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm9712-colibri_t20", - "nvidia,tegra-audio-wm9712"; - nvidia,model = "Colibri T20 AC97 Audio"; - - nvidia,audio-routing = - "Headphone", "HPOUTL", - "Headphone", "HPOUTR", - "LineIn", "LINEINL", - "LineIn", "LINEINR", - "Mic", "MIC1"; - - nvidia,ac97-controller = <&ac97>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts new file mode 100644 index 000000000000..57f16c0e9917 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-colibri.dtsi" + +/ { + model = "Toradex Colibri T20 256/512 MB on Iris"; + compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; + + aliases { + serial0 = &uarta; + serial1 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + }; + }; + + pinmux@70000014 { + state_default: pinmux { + hdint { + nvidia,tristate = ; + }; + + i2cddc { + nvidia,tristate = ; + }; + + sdio4 { + nvidia,tristate = ; + }; + + uarta { + nvidia,tristate = ; + }; + + uartd { + nvidia,tristate = ; + }; + }; + }; + + serial@70006000 { + status = "okay"; + }; + + serial@70006300 { + status = "okay"; + }; + + i2c_ddc: i2c@7000c400 { + status = "okay"; + }; + + usb@c5000000 { + status = "okay"; + }; + + usb-phy@c5000000 { + status = "okay"; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <4>; + vmmc-supply = <&vcc_sd_reg>; + vqmmc-supply = <&vcc_sd_reg>; + }; + + regulators { + regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + }; + + vcc_sd_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi new file mode 100644 index 000000000000..dc06b23183e1 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -0,0 +1,545 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "tegra20.dtsi" + +/ { + model = "Toradex Colibri T20 256/512 MB"; + compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; + + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + + memory@0 { + /* + * Set memory to 256 MB to be safe as this could be used on + * 256 or 512 MB module. It is expected from bootloader + * to fix this up for 512 MB version. + */ + reg = <0x00000000 0x10000000>; + }; + + host1x@50000000 { + hdmi@54280000 { + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&i2c_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + audio_refclk { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + nvidia,pull = ; + nvidia,tristate = ; + }; + crt { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + displaya { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", + "ld4", "ld5", "ld6", "ld7", "ld8", + "ld9", "ld10", "ld11", "ld12", "ld13", + "ld14", "ld15", "ld16", "ld17", + "lhs", "lpw0", "lpw2", "lsc0", + "lsc1", "lsck", "lsda", "lspi", "lvs"; + nvidia,function = "displaya"; + nvidia,tristate = ; + }; + gpio_dte { + nvidia,pins = "dte"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + gpio_gmi { + nvidia,pins = "ata", "atc", "atd", "ate", + "dap1", "dap2", "dap4", "gpu", "irrx", + "irtx", "spia", "spib", "spic"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + gpio_pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + gpio_uac { + nvidia,pins = "uac"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + nvidia,tristate = ; + }; + i2c1 { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + i2c3 { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + i2cddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + nvidia,pull = ; + nvidia,tristate = ; + }; + irda { + nvidia,pins = "uad"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + nand { + nvidia,pins = "kbca", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + }; + owc { + nvidia,pins = "owc"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + nvidia,tristate = ; + }; + pwm { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + nvidia,tristate = ; + }; + sdio4 { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + spi1 { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + spi4 { + nvidia,pins = "slxa", "slxc", "slxd", "slxk"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + uarta { + nvidia,pins = "sdio1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + }; + uartd { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + ulpi { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + ulpi_refclk { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + nvidia,pull = ; + nvidia,tristate = ; + }; + usb_gpio { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + nvidia,pull = ; + nvidia,tristate = ; + }; + vi { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + vi_sc { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + nvidia,pull = ; + nvidia,tristate = ; + }; + }; + }; + + ac97: ac97@70002000 { + status = "okay"; + nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) + GPIO_ACTIVE_HIGH>; + nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) + GPIO_ACTIVE_HIGH>; + }; + + /* + * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + clock-frequency = <400000>; + }; + + /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ + i2c_ddc: i2c@7000c400 { + clock-frequency = <10000>; + }; + + /* GEN2_I2C: unused */ + + /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */ + + /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_3v3_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&vdd_3v3_reg>; + vinldo4-supply = <&vdd_3v3_reg>; + vinldo678-supply = <&vdd_3v3_reg>; + vinldo9-supply = <&vdd_3v3_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + /* LDO3 is not connected to anything */ + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + hdmi_vdd_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor@4c { + compatible = "national,lm95245"; + reg = <0x4c>; + }; + }; + + pmc@7000e400 { + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <3875>; + nvidia,sys-clock-req-active-high; + }; + + memory-controller@7000f400 { + emc-table@83250 { + reg = <83250>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <83250>; + nvidia,emc-registers = <0x00000005 0x00000011 + 0x00000004 0x00000002 0x00000004 0x00000004 + 0x00000001 0x0000000a 0x00000002 0x00000002 + 0x00000001 0x00000001 0x00000003 0x00000004 + 0x00000003 0x00000009 0x0000000c 0x0000025f + 0x00000000 0x00000003 0x00000003 0x00000002 + 0x00000002 0x00000001 0x00000008 0x000000c8 + 0x00000003 0x00000005 0x00000003 0x0000000c + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0x00520006 + 0x00000010 0x00000008 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + emc-table@133200 { + reg = <133200>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <133200>; + nvidia,emc-registers = <0x00000008 0x00000019 + 0x00000006 0x00000002 0x00000004 0x00000004 + 0x00000001 0x0000000a 0x00000002 0x00000002 + 0x00000002 0x00000001 0x00000003 0x00000004 + 0x00000003 0x00000009 0x0000000c 0x0000039f + 0x00000000 0x00000003 0x00000003 0x00000002 + 0x00000002 0x00000001 0x00000008 0x000000c8 + 0x00000003 0x00000007 0x00000003 0x0000000c + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0x00510006 + 0x00000010 0x00000008 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + emc-table@166500 { + reg = <166500>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <166500>; + nvidia,emc-registers = <0x0000000a 0x00000021 + 0x00000008 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000a 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000003 0x00000004 + 0x00000003 0x00000009 0x0000000c 0x000004df + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x00000009 0x000000c8 + 0x00000003 0x00000009 0x00000004 0x0000000c + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0x004f0006 + 0x00000010 0x00000008 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <333000>; + nvidia,emc-registers = <0x00000014 0x00000041 + 0x0000000f 0x00000005 0x00000004 0x00000005 + 0x00000003 0x0000000a 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000003 0x00000004 + 0x00000003 0x00000009 0x0000000c 0x000009ff + 0x00000000 0x00000003 0x00000003 0x00000005 + 0x00000005 0x00000001 0x0000000e 0x000000c8 + 0x00000003 0x00000011 0x00000006 0x0000000c + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0x00380006 + 0x00000010 0x00000008 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + usb@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_3v3_reg: regulator@100 { + compatible = "regulator-fixed"; + reg = <100>; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "internal_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-wm9712-colibri_t20", + "nvidia,tegra-audio-wm9712"; + nvidia,model = "Colibri T20 AC97 Audio"; + + nvidia,audio-routing = + "Headphone", "HPOUTL", + "Headphone", "HPOUTR", + "LineIn", "LINEINL", + "LineIn", "LINEINR", + "Mic", "MIC1"; + + nvidia,ac97-controller = <&ac97>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; +}; diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts deleted file mode 100644 index 40126388946d..000000000000 --- a/arch/arm/boot/dts/tegra20-iris-512.dts +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra20-colibri-512.dtsi" - -/ { - model = "Toradex Colibri T20 512MB on Iris"; - compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; - - aliases { - serial0 = &uarta; - serial1 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - }; - }; - - pinmux@70000014 { - state_default: pinmux { - hdint { - nvidia,tristate = ; - }; - - i2cddc { - nvidia,tristate = ; - }; - - sdio4 { - nvidia,tristate = ; - }; - - uarta { - nvidia,tristate = ; - }; - - uartd { - nvidia,tristate = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - i2c_ddc: i2c@7000c400 { - status = "okay"; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <4>; - vmmc-supply = <&vcc_sd_reg>; - vqmmc-supply = <&vcc_sd_reg>; - }; - - regulators { - regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - }; - - vcc_sd_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; -- cgit v1.2.3 From 6c468f109884c2cd8d8bc042945fdd861f375523 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sun, 24 Jun 2018 23:27:26 +0200 Subject: ARM: dts: tegra: add Tegra20 NAND flash controller node Add basic controller device tree node to be extended by individual boards. Use the assigned-clocks mechanism to set NDFLASH clock to a sensible default rate of 150MHz. Signed-off-by: Lucas Stach Signed-off-by: Stefan Agner Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 86d8cd6f9548..15b73bd377f0 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -432,6 +432,21 @@ status = "disabled"; }; + nand-controller@70008000 { + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + clock-names = "nand"; + resets = <&tegra_car 13>; + reset-names = "nand"; + assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + assigned-clock-rates = <150000000>; + status = "disabled"; + }; + pwm: pwm@7000a000 { compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; -- cgit v1.2.3 From 5def854e370ff5c52172fb185932fdbffbf15692 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 24 Jun 2018 23:27:27 +0200 Subject: ARM: dts: tegra: enable NAND flash on Colibri T20 This enables the on-module ONFI conformant NAND flash. Signed-off-by: Lucas Stach Signed-off-by: Stefan Agner Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index dc06b23183e1..e7b9ab09908a 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -218,6 +218,22 @@ GPIO_ACTIVE_HIGH>; }; + nand-controller@70008000 { + status = "okay"; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <8>; + nand-on-flash-bbt; + nand-ecc-algo = "bch"; + nand-is-boot-medium; + nand-ecc-maximize; + wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + }; + }; + /* * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier * board) -- cgit v1.2.3 From 3117c17301edce7583843bdee513e201bb69c37c Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Wed, 4 Jul 2018 15:14:32 +0530 Subject: ARM: dts: da850: Add power-domains to CPPI 4.1 node This adds the power-domains property to CPPI 4.1 node. The CPPI 4.1 DMA driver uses pm_runtime to manage the clocks, so it needs this property in order to find and enable the clock properly. Reviewed-by: David Lechner Tested-by: Bartosz Golaszewski Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 24865ed6f4e4..ab976aa91fae 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -639,6 +639,7 @@ interrupts = <58>; #dma-cells = <2>; #dma-channels = <4>; + power-domains = <&psc1 1>; status = "okay"; }; }; -- cgit v1.2.3 From 6ae8d5c1a8ace610b2afc016b2ea5f5d9d774b71 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Jul 2018 04:05:30 -0700 Subject: ARM: dts: dra762: Add MCAN clock support MCAN is clocked by H14 divider of DPLL_GMAC. Unlike other DPLL dividers this DPLL_GMAC H14 divider is controlled by control module. Adding support for these clocks. Signed-off-by: Lokesh Vutla Signed-off-by: Faiz Abbas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra76x.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index 1c88c581ff18..bfc82636999c 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -17,3 +17,36 @@ &crossbar_mpu { ti,irqs-skip = <10 67 68 133 139 140>; }; + +&scm_conf_clocks { + dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_gmac_x2_ck>; + ti,max-div = <63>; + reg = <0x03fc>; + ti,bit-shift=<20>; + ti,latch-bit=<26>; + assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; + assigned-clock-rates = <80000000>; + }; + + dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; + reg = <0x3fc>; + ti,bit-shift = <29>; + ti,latch-bit=<26>; + assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; + assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; + }; + + mcan_clk: mcan_clk@3fc { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; + ti,bit-shift = <27>; + reg = <0x3fc>; + }; +}; -- cgit v1.2.3 From 09a070a3696771905a4db3d84e021aabe752463b Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Tue, 10 Jul 2018 04:05:30 -0700 Subject: ARM: dts: Add generic interconnect target module node for MCAN The ti-sysc driver provides support for manipulating the idle modes and interconnect level resets. Add the generic interconnect target module node for MCAN to support the same. CC: Tony Lindgren Signed-off-by: Faiz Abbas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra76x.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index bfc82636999c..5157cc431574 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -11,6 +11,24 @@ / { compatible = "ti,dra762", "ti,dra7"; + ocp { + target-module@42c01900 { + compatible = "ti,sysc-dra7-mcan", "ti,sysc"; + ranges = <0x0 0x42c00000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x42c01900 0x4>, + <0x42c01904 0x4>, + <0x42c01908 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | + SYSC_DRA7_MCAN_ENAWAKEUP)>; + ti,syss-mask = <1>; + clocks = <&wkupaon_clkctrl DRA7_ADC_CLKCTRL 0>; + clock-names = "fck"; + }; + }; + }; /* MCAN interrupts are hard-wired to irqs 67, 68 */ -- cgit v1.2.3 From 0adbe832f21ac8478f33aa64627c92fd3225b944 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Tue, 10 Jul 2018 04:05:30 -0700 Subject: ARM: dts: dra76x: Add MCAN node Add support for the MCAN peripheral which supports both classic CAN messages along with the new CAN-FD message. Add MCAN node to evm and enable it with a maximum datarate of 5 mbps Signed-off-by: Faiz Abbas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra76-evm.dts | 6 ++++++ arch/arm/boot/dts/dra76x.dtsi | 13 +++++++++++++ 2 files changed, 19 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index c07f0051844d..0ac533784b11 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -436,3 +436,9 @@ phys = <&pcie1_phy>, <&pcie2_phy>; phy-names = "pcie-phy0", "pcie-phy1"; }; + +&m_can0 { + can-transceiver { + max-bitrate = <5000000>; + }; +}; diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index 5157cc431574..613e4dc0ed3e 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -26,6 +26,19 @@ ti,syss-mask = <1>; clocks = <&wkupaon_clkctrl DRA7_ADC_CLKCTRL 0>; clock-names = "fck"; + + m_can0: mcan@1a00 { + compatible = "bosch,m_can"; + reg = <0x1a00 0x4000>, <0x0 0x18FC>; + reg-names = "m_can", "message_ram"; + interrupt-parent = <&gic>; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&mcan_clk>, <&l3_iclk_div>; + clock-names = "cclk", "hclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; + }; }; }; -- cgit v1.2.3 From 20d85508b8a35138df9248e1903ba9cc1e5b1255 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 10 Jul 2018 22:34:56 +0200 Subject: ARM: dts: sun8i: r40: Remove fallback display engine compatible R40 has pretty unique display pipeline. Because of that, H3 display engine compatible fallback should be removed. Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline") Reviewed-by: Chen-Yu Tsai Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index c95a59aac48f..2afb079a3776 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -102,8 +102,7 @@ }; de: display-engine { - compatible = "allwinner,sun8i-r40-display-engine", - "allwinner,sun8i-h3-display-engine"; + compatible = "allwinner,sun8i-r40-display-engine"; allwinner,pipelines = <&mixer0>, <&mixer1>; status = "disabled"; }; -- cgit v1.2.3 From e64cb21c059ba3b08612727d6f116c3fd7ac9a4d Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 10 Jul 2018 22:35:01 +0200 Subject: ARM: dts: sun8i: r40: Add mixer ids to TCON TOP sun4i-drm DT binding, second paragraph of the first section says: For all connections between components up to the TCONs in the display pipeline, when there are multiple components of the same type at the same depth, the local endpoint ID must be the same as the remote component's index. Add mixer ids in R40 DT as mandated by DT binding. Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline") Reviewed-by: Chen-Yu Tsai Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 2afb079a3776..1dd088d82773 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -576,9 +576,12 @@ #size-cells = <0>; tcon_top_mixer0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - tcon_top_mixer0_in_mixer0: endpoint { + tcon_top_mixer0_in_mixer0: endpoint@0 { + reg = <0>; remote-endpoint = <&mixer0_out_tcon_top>; }; }; @@ -606,9 +609,12 @@ }; tcon_top_mixer1_in: port@2 { + #address-cells = <1>; + #size-cells = <0>; reg = <2>; - tcon_top_mixer1_in_mixer1: endpoint { + tcon_top_mixer1_in_mixer1: endpoint@1 { + reg = <1>; remote-endpoint = <&mixer1_out_tcon_top>; }; }; -- cgit v1.2.3 From f9105d819dff1ad565ed3173851cd4eb996d42b5 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 10 Jul 2018 22:35:07 +0200 Subject: ARM: dts: sun8i: r40: Remove fallback compatible for TCON TV A83T and R40 TCON TV are very similar. However, R40 TCON TV is wired differently, which makes it incompatible with A83T TCON TV. Because of that, remove fallback A83T TCON TV compatible. Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline") Reviewed-by: Chen-Yu Tsai Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 1dd088d82773..6b4fe8eeee99 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -666,8 +666,7 @@ }; tcon_tv0: lcd-controller@1c73000 { - compatible = "allwinner,sun8i-r40-tcon-tv", - "allwinner,sun8i-a83t-tcon-tv"; + compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c73000 0x1000>; interrupts = ; clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; @@ -690,8 +689,7 @@ }; tcon_tv1: lcd-controller@1c74000 { - compatible = "allwinner,sun8i-r40-tcon-tv", - "allwinner,sun8i-a83t-tcon-tv"; + compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c74000 0x1000>; interrupts = ; clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>; -- cgit v1.2.3 From ccefd95f648a695e3fb62015fd3efc667a250a22 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 10 Jul 2018 22:35:08 +0200 Subject: ARM: dts: sun8i: r40: Add missing TCON-TOP - TCON connections Current R40 is missing some graph connections between TCON TOP and TCONs. Add them. Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline") Reviewed-by: Chen-Yu Tsai Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 20 ----------- arch/arm/boot/dts/sun8i-r40.dtsi | 44 +++++++++++++++++++++++ 2 files changed, 44 insertions(+), 20 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 4f3d583183dc..737cf01b1acd 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -251,26 +251,6 @@ regulator-name = "vcc-wifi"; }; -&tcon_top_hdmi_in_tcon_tv0 { - remote-endpoint = <&tcon_tv0_out_tcon_top>; -}; - -&tcon_top_mixer0_out_tcon_tv0 { - remote-endpoint = <&tcon_tv0_in_tcon_top>; -}; - -&tcon_tv0_in { - tcon_tv0_in_tcon_top: endpoint { - remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; - }; -}; - -&tcon_tv0_out { - tcon_tv0_out_tcon_top: endpoint { - remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; - }; -}; - &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 6b4fe8eeee99..e5c7e4804384 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -601,10 +601,12 @@ tcon_top_mixer0_out_tcon_tv0: endpoint@2 { reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; }; tcon_top_mixer0_out_tcon_tv1: endpoint@3 { reg = <3>; + remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; }; }; @@ -634,10 +636,12 @@ tcon_top_mixer1_out_tcon_tv0: endpoint@2 { reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; }; tcon_top_mixer1_out_tcon_tv1: endpoint@3 { reg = <3>; + remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; }; }; @@ -648,10 +652,12 @@ tcon_top_hdmi_in_tcon_tv0: endpoint@0 { reg = <0>; + remote-endpoint = <&tcon_tv0_out_tcon_top>; }; tcon_top_hdmi_in_tcon_tv1: endpoint@1 { reg = <1>; + remote-endpoint = <&tcon_tv1_out_tcon_top>; }; }; @@ -679,11 +685,30 @@ #size-cells = <0>; tcon_tv0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; + + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; + }; + + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; + }; }; tcon_tv0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; + + tcon_tv0_out_tcon_top: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; + }; }; }; }; @@ -702,11 +727,30 @@ #size-cells = <0>; tcon_tv1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; + + tcon_tv1_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>; + }; + + tcon_tv1_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>; + }; }; tcon_tv1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; + + tcon_tv1_out_tcon_top: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>; + }; }; }; }; -- cgit v1.2.3 From 6a7556f604f94461ca802ab69a6dad317c014d30 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 10 Jul 2018 22:35:09 +0200 Subject: ARM: dts: sun8i: r40: Disable TCONs by default. R40 has 4 TCONs, but only 2 of them can receive some kind of output at the same time. Let's disable them by default, so only those which are really connected on board can be enabled in board dts file. Reviewed-by: Chen-Yu Tsai Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 4 ++++ arch/arm/boot/dts/sun8i-r40.dtsi | 2 ++ 2 files changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 737cf01b1acd..c39b9169ea64 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -251,6 +251,10 @@ regulator-name = "vcc-wifi"; }; +&tcon_tv0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index e5c7e4804384..e2cbd4f645c5 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -679,6 +679,7 @@ clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON_TV0>; reset-names = "lcd"; + status = "disabled"; ports { #address-cells = <1>; @@ -721,6 +722,7 @@ clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON_TV1>; reset-names = "lcd"; + status = "disabled"; ports { #address-cells = <1>; -- cgit v1.2.3 From 37fb1f8d4596813bf6d39ebd8e609bfa8aee75cd Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Tue, 10 Jul 2018 10:01:00 +0200 Subject: ARM: dts: sun4i: Switch to new system control compatible string This switches the sun4i-a10 dtsi to use the new compatible for the system-control block (previously named SRAM controller) instead of the deprecated one. The node name is also updated to reflect the fact that the controller described is really about system control rather than SRAM control. Signed-off-by: Paul Kocialkowski [Maxime: Amended the commit message] Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 3a1c6b45c9a1..82f81f06f201 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -190,8 +190,8 @@ #size-cells = <1>; ranges; - sram-controller@1c00000 { - compatible = "allwinner,sun4i-a10-sram-controller"; + system-control@1c00000 { + compatible = "allwinner,sun4i-a10-system-control"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 6b7677c05367db4d46bb80ef3b738a1c039f0ac3 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Tue, 10 Jul 2018 10:01:01 +0200 Subject: ARM: dts: sun5i: Use most-qualified system control compatibles This switches the sun5i dtsi to use the most qualified compatibles for the system-control block (previously named SRAM controller) as well as the SRAM blocks. The node name for system control is also updated to reflect the fact that the controller described is really about system control rather than SRAM control. Signed-off-by: Paul Kocialkowski [Maxime: Removed the A10 compatible for the driver] Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 07f2248ed5f8..b833f4eb3bd2 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -114,8 +114,8 @@ #size-cells = <1>; ranges; - sram-controller@1c00000 { - compatible = "allwinner,sun4i-a10-sram-controller"; + system-control@1c00000 { + compatible = "allwinner,sun5i-a13-system-control"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; @@ -130,7 +130,8 @@ }; emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; + compatible = "allwinner,sun5i-a13-sram-a3-a4", + "allwinner,sun4i-a10-sram-a3-a4"; reg = <0x8000 0x4000>; status = "disabled"; }; @@ -143,7 +144,8 @@ ranges = <0 0x00010000 0x1000>; otg_sram: sram-section@0 { - compatible = "allwinner,sun4i-a10-sram-d"; + compatible = "allwinner,sun5i-a13-sram-d", + "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; }; -- cgit v1.2.3 From f4ca1a5c7e58ef0c38e6c697f7fefb1e081a579d Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Tue, 10 Jul 2018 10:01:02 +0200 Subject: ARM: dts: sun7i: Use most-qualified system control compatibles This switches the sun7i-a20 dtsi to use the most qualified compatibles for the system-control block (previously named SRAM controller) as well as the SRAM blocks. The sun4i-a10 compatibles are kept since these hardware blocks are backward-compatible. The node name for system control is also updated to reflect the fact that the controller described is really about system control rather than SRAM control. Signed-off-by: Paul Kocialkowski Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 35372a0cfc8d..33e28ae7bc2e 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -252,8 +252,9 @@ #size-cells = <1>; ranges; - sram-controller@1c00000 { - compatible = "allwinner,sun4i-a10-sram-controller"; + system-control@1c00000 { + compatible = "allwinner,sun7i-a20-system-control", + "allwinner,sun4i-a10-system-control"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; @@ -267,7 +268,8 @@ ranges = <0 0x00000000 0xc000>; emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; + compatible = "allwinner,sun7i-a20-sram-a3-a4", + "allwinner,sun4i-a10-sram-a3-a4"; reg = <0x8000 0x4000>; status = "disabled"; }; @@ -281,7 +283,8 @@ ranges = <0 0x00010000 0x1000>; otg_sram: sram-section@0 { - compatible = "allwinner,sun4i-a10-sram-d"; + compatible = "allwinner,sun7i-a20-sram-d", + "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; }; -- cgit v1.2.3 From c2e01602dc3290e7ba7a808152624fd09a9ef849 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 10 Jul 2018 10:01:03 +0200 Subject: ARM: dts: sun5i: Add support for the C1 SRAM region with the SRAM controller This adds support for the C1 SRAM region (to be used with the SRAM controller driver) for sun5i-based platforms. The region is shared between the Video Engine and the CPU. Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Signed-off-by: Paul Kocialkowski [Maxime: Fixed the SRAM C size to take the C2 and C3 SRAM into account] Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index b833f4eb3bd2..40e4dc293f14 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -150,6 +150,20 @@ status = "disabled"; }; }; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun5i-a13-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; }; dma: dma-controller@1c02000 { -- cgit v1.2.3 From 77c223c118a14285ca5efa0f457b2c6b15dfc147 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 10 Jul 2018 10:01:04 +0200 Subject: ARM: dts: sun7i: Add support for the C1 SRAM region with the SRAM controller This adds support for the C1 SRAM region (to be used with the SRAM controller driver) for the A20 platform. The region is shared between the Video Engine and the CPU. Signed-off-by: Maxime Ripard Signed-off-by: Paul Kocialkowski [Maxime: Fixed the SRAM C size] Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 33e28ae7bc2e..9c52712af241 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -289,6 +289,20 @@ status = "disabled"; }; }; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun7i-a20-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; }; nmi_intc: interrupt-controller@1c00030 { -- cgit v1.2.3 From ae54cf89d6ca897dc698858935b39e91e7e65535 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 10 Jul 2018 10:01:05 +0200 Subject: ARM: dts: sun8i: a23-a33: Add SRAM controller node and C1 SRAM region This adds a SRAM controller node for the A23 and A33, with support for the C1 SRAM region that is shared between the Video Engine and the CPU. Signed-off-by: Maxime Ripard Signed-off-by: Paul Kocialkowski [Maxime: Fixed the prefix and the compatibles] Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 44f3cad3de75..c16ffcc4db7d 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -124,6 +124,28 @@ #size-cells = <1>; ranges; + system-control@1c00000 { + compatible = "allwinner,sun8i-a23-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0x80000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun8i-a23-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + dma: dma-controller@1c02000 { compatible = "allwinner,sun8i-a23-dma"; reg = <0x01c02000 0x1000>; -- cgit v1.2.3 From 626e6ee210fba380dd652e332493a9b10925f70b Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Tue, 10 Jul 2018 10:01:06 +0200 Subject: ARM: dts: sun8i: h3: Add SRAM controller node and C1 SRAM region This adds a SRAM controller node for the H3, with support for the C1 SRAM region that is shared between the Video Engine and the CPU. Signed-off-by: Paul Kocialkowski [Maxime: Fixed the compatible and commit prefix] Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 41d57c76f290..eec826abb957 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -111,6 +111,28 @@ }; soc { + system-control@1c00000 { + compatible = "allwinner,sun8i-h3-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0x80000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun8i-h3-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + mali: gpu@1c40000 { compatible = "allwinner,sun8i-h3-mali", "arm,mali-400"; reg = <0x01c40000 0x10000>; -- cgit v1.2.3 From 465b3d77b1f8c88d3d28f9da6e4cdd75ce66b6b3 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 5 Jul 2018 22:05:49 +0300 Subject: ARM: dts: imx31: add device tree description of basic controllers The change adds a number of basic peripherals found on i.MX31 SoC: * GPIO controllers, * I2C master controllers, * SPI master controllers, * ATA controller, * SDHC controllers, * RTC, watchdog and PWM contollers, * SDMA, * IRAM, * NAND and WEIM controllers on EMI. The added controller devices were tested on Freescale i.MX31 powered LogicPD Lite SoM and baseboard. DMA functionality was tested on SDHC and SPI controllers so far, thus dmas properties are added to those device nodes only. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx31.dtsi | 223 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 223 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 4642c8169a65..ca1419ca303c 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ // +// Copyright 2016-2018 Vladimir Zapolskiy // Copyright 2012 Denis 'GNUtoo' Carikli / { @@ -15,11 +16,20 @@ memory { device_type = "memory"; }; aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; + spi0 = &spi1; + spi1 = &spi2; + spi2 = &spi3; }; cpus { @@ -47,6 +57,14 @@ interrupt-parent = <&avic>; ranges; + iram: iram@1fffc000 { + compatible = "mmio-sram"; + reg = <0x1fffc000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1fffc000 0x4000>; + }; + aips@43f00000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -54,6 +72,34 @@ reg = <0x43f00000 0x100000>; ranges; + i2c1: i2c@43f80000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f80000 0x4000>; + interrupts = <10>; + clocks = <&clks 33>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@43f84000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f84000 0x4000>; + interrupts = <3>; + clocks = <&clks 35>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ata: ata@43f8c000 { + compatible = "fsl,imx31-pata", "fsl,imx27-pata"; + reg = <0x43f8c000 0x4000>; + interrupts = <15>; + clocks = <&clks 26>; + status = "disabled"; + }; + uart1: serial@43f90000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43f90000 0x4000>; @@ -72,6 +118,29 @@ status = "disabled"; }; + i2c2: i2c@43f98000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f98000 0x4000>; + interrupts = <4>; + clocks = <&clks 34>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@43fa4000 { + compatible = "fsl,imx31-cspi"; + reg = <0x43fa4000 0x4000>; + interrupts = <14>; + clocks = <&clks 10>, <&clks 53>; + clock-names = "ipg", "per"; + dmas = <&sdma 8 8 0>, <&sdma 9 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + kpp: kpp@43fa8000 { compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; reg = <0x43fa8000 0x4000>; @@ -106,6 +175,28 @@ reg = <0x50000000 0x100000>; ranges; + sdhci1: sdhci@50004000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50004000 0x4000>; + interrupts = <9>; + clocks = <&clks 10>, <&clks 20>; + clock-names = "ipg", "per"; + dmas = <&sdma 20 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + sdhci2: sdhci@50008000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50008000 0x4000>; + interrupts = <8>; + clocks = <&clks 10>, <&clks 21>; + clock-names = "ipg", "per"; + dmas = <&sdma 21 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + uart3: serial@5000c000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; @@ -115,6 +206,19 @@ status = "disabled"; }; + spi2: cspi@50010000 { + compatible = "fsl,imx31-cspi"; + reg = <0x50010000 0x4000>; + interrupts = <13>; + clocks = <&clks 10>, <&clks 54>; + clock-names = "ipg", "per"; + dmas = <&sdma 6 8 0>, <&sdma 7 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + iim: iim@5001c000 { compatible = "fsl,imx31-iim", "fsl,imx27-iim"; reg = <0x5001c000 0x1000>; @@ -137,6 +241,19 @@ #clock-cells = <1>; }; + spi3: cspi@53f84000 { + compatible = "fsl,imx31-cspi"; + reg = <0x53f84000 0x4000>; + interrupts = <17>; + clocks = <&clks 10>, <&clks 28>; + clock-names = "ipg", "per"; + dmas = <&sdma 10 8 0>, <&sdma 11 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpt: timer@53f90000 { compatible = "fsl,imx31-gpt"; reg = <0x53f90000 0x4000>; @@ -144,6 +261,112 @@ clocks = <&clks 10>, <&clks 22>; clock-names = "ipg", "per"; }; + + gpio3: gpio@53fa4000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fa4000 0x4000>; + interrupts = <56>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rng@53fb0000 { + compatible = "fsl,imx31-rnga"; + reg = <0x53fb0000 0x4000>; + interrupts = <22>; + clocks = <&clks 29>; + }; + + gpio1: gpio@53fcc000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fcc000 0x4000>; + interrupts = <52>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@53fd0000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fd0000 0x4000>; + interrupts = <51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sdma: sdma@53fd4000 { + compatible = "fsl,imx31-sdma"; + reg = <0x53fd4000 0x4000>; + interrupts = <34>; + clocks = <&clks 10>, <&clks 27>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; + }; + + rtc: rtc@53fd8000 { + compatible = "fsl,imx31-rtc", "fsl,imx21-rtc"; + reg = <0x53fd8000 0x4000>; + interrupts = <25>; + clocks = <&clks 2>, <&clks 40>; + clock-names = "ref", "ipg"; + }; + + wdog: wdog@53fdc000 { + compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; + reg = <0x53fdc000 0x4000>; + clocks = <&clks 41>; + }; + + pwm: pwm@53fe0000 { + compatible = "fsl,imx31-pwm", "fsl,imx27-pwm"; + reg = <0x53fe0000 0x4000>; + interrupts = <26>; + clocks = <&clks 10>, <&clks 42>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; + + emi@b8000000 { /* External Memory Interface */ + compatible = "simple-bus"; + reg = <0xb8000000 0x5000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + nfc: nand@b8000000 { + compatible = "fsl,imx31-nand", "fsl,imx27-nand"; + reg = <0xb8000000 0x1000>; + interrupts = <33>; + clocks = <&clks 9>; + dmas = <&sdma 30 17 0>; + dma-names = "rx-tx"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + weim: weim@b8002000 { + compatible = "fsl,imx31-weim", "fsl,imx27-weim"; + reg = <0xb8002000 0x1000>; + clocks = <&clks 56>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xa0000000 0x08000000 + 1 0 0xa8000000 0x08000000 + 2 0 0xb0000000 0x02000000 + 3 0 0xb2000000 0x02000000 + 4 0 0xb4000000 0x02000000 + 5 0 0xb6000000 0x02000000>; + status = "disabled"; + }; }; }; }; -- cgit v1.2.3 From caaac8cde914ebab128295240cb489841d224170 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 3 Jul 2018 22:29:34 +0300 Subject: ARM: dts: imx31: add LogicPD MX31Lite board description The added DTS contains a combined description of LogicPD MX31 Lite SoM devices, peripherals are routed to ports on a baseboard: * PATA controller, * SD/MMC controller, * 2 GPIO LEDs, * UART controllers, * Freescale MC13783 MFD connected over SPI, * SMSC LAN9117, * ST Micro NAND SLC, 64 MiB, * Intel NOR flash, 16 MiB. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx31-lite.dts | 177 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 179 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx31-lite.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bc63b4c81dfe..fd2f82b09df2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -345,7 +345,8 @@ dtb-$(CONFIG_SOC_IMX27) += \ imx27-phytec-phycore-rdk.dtb \ imx27-phytec-phycard-s-rdk.dtb dtb-$(CONFIG_SOC_IMX31) += \ - imx31-bug.dtb + imx31-bug.dtb \ + imx31-lite.dtb dtb-$(CONFIG_SOC_IMX35) += \ imx35-eukrea-mbimxsd35-baseboard.dtb \ imx35-pdk.dtb diff --git a/arch/arm/boot/dts/imx31-lite.dts b/arch/arm/boot/dts/imx31-lite.dts new file mode 100644 index 000000000000..db52ddccabc3 --- /dev/null +++ b/arch/arm/boot/dts/imx31-lite.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2016-2018 Vladimir Zapolskiy + +/dts-v1/; + +#include "imx31.dtsi" + +#include +#include + +/ { + model = "LogicPD i.MX31 Lite"; + compatible = "logicpd,imx31-lite", "fsl,imx31"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + reg = <0x80000000 0x8000000>; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + led1 { + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ata { + status = "okay"; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&sdhci1 { + bus-width = <4>; + cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13783"; + reg = <0>; + spi-cs-high; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + + fsl,mc13xxx-uses-adc; + fsl,mc13xxx-uses-rtc; + + regulators { + sw1a { /* QVCC */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + sw1b { /* QVCC */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2a { /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2b { /* NVCC10 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + violo { /* NVCC1 and NVCC7 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + viohi { /* VIOHI */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vaudio { /* VAUDIO */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vcam { /* NVCC4 */ + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vgen { /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc2 { /* NVCC3 */ + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&uart1 { + uart-has-rtscts; + status = "okay"; +}; + +/* Routed to the extension board */ +&uart2 { + uart-has-rtscts; + status = "okay"; +}; + +/* Routed to the extension board */ +&uart3 { + uart-has-rtscts; + status = "okay"; +}; + +&weim { + status = "okay"; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x0 0x200000>; + bank-width = <2>; + linux,mtd-name = "physmap-flash.0"; + fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>; + }; + + ethernet@4,0 { + compatible = "smsc,lan9117", "smsc,lan9115"; + reg = <4 0x0 0x100>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,irq-push-pull; + fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>; + }; +}; -- cgit v1.2.3 From 2db286d7361ecde6cb336cc8f10582afa9c09374 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 4 Jul 2018 14:52:50 -0300 Subject: ARM: dts: imx: Remove optional 'fsl,sec-era' property Since commit 654f2b937b38 ("crypto: caam - allow retrieving 'era' from register") the CAAM driver is capable of obtaining the era version by reading the appropriate CAAM registers, so let the CAAM driver discover the era version in run-time instead of hardcoding such information in the device tree. According to Documentation/devicetree/bindings/crypto/fsl-sec4.txt the 'fsl,sec-era' is an optional property and this can be safely removed now. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 1 - arch/arm/boot/dts/imx6sx.dtsi | 1 - arch/arm/boot/dts/imx7s.dtsi | 1 - 3 files changed, 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 911141e24681..61d2d26afbf4 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -922,7 +922,6 @@ crypto: caam@2100000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; #address-cells = <1>; #size-cells = <1>; reg = <0x2100000 0x10000>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 596763c2fe33..881c0dd8d09a 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -815,7 +815,6 @@ crypto: caam@2100000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; #address-cells = <1>; #size-cells = <1>; reg = <0x2100000 0x10000>; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 9ced589bfa96..a052198f6e96 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -842,7 +842,6 @@ crypto: caam@30900000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <8>; #address-cells = <1>; #size-cells = <1>; reg = <0x30900000 0x40000>; -- cgit v1.2.3 From b31cd4377286904d8dd7f45b0846c1dfe79ceb04 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Fri, 6 Jul 2018 19:49:02 -0700 Subject: ARM: dts: imx: Add ZII SCU2 Mezz board Add support for the Zodiac Inflight Innovations SCU2 Mezz board (i.MX51-based). Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Fabio Estevam Signed-off-by: Andrey Gusakov Signed-off-by: Andrey Smirnov Tested-by: Chris Healy Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx51-zii-scu2-mezz.dts | 448 ++++++++++++++++++++++++++++++ 2 files changed, 450 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx51-zii-scu2-mezz.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index fd2f82b09df2..b000f917f336 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -359,7 +359,8 @@ dtb-$(CONFIG_SOC_IMX51) += \ imx51-digi-connectcore-jsk.dtb \ imx51-eukrea-mbimxsd51-baseboard.dtb \ imx51-ts4800.dtb \ - imx51-zii-rdu1.dtb + imx51-zii-rdu1.dtb \ + imx51-zii-scu2-mezz.dtb dtb-$(CONFIG_SOC_IMX53) += \ imx53-ard.dtb \ imx53-cx9020.dtb \ diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts new file mode 100644 index 000000000000..26cf08549df4 --- /dev/null +++ b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts @@ -0,0 +1,448 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; + +#include "imx51.dtsi" + +/ { + model = "ZII SCU2 Mezz Board"; + compatible = "zii,imx51-scu2-mezz", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + /* Will be filled by the bootloader */ + memory@90000000 { + reg = <0x90000000 0>; + }; + + aliases { + mdio-gpio0 = &mdio_gpio; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_mmc_reset>; + gpio = <&gpio3 13 GPIO_ACTIVE_LOW>; + startup-delay-us = <150000>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + mdio_gpio: mdio-gpio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swmdio>; + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>, /* mdc */ + <&gpio2 6 GPIO_ACTIVE_HIGH>; /* mdio */ + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + dsa,member = <0 0>; + eeprom-length = <512>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "port4"; + }; + + port@1 { + reg = <1>; + label = "port5"; + }; + + port@2 { + reg = <2>; + label = "port6"; + }; + + port@3 { + reg = <3>; + label = "port7"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&fec>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@5 { + reg = <5>; + label = "mezz2esb"; + phy-mode = "sgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&cpu { + cpu-supply = <&sw1_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x0 0x0 0x3f83f8 0x0>; + + sysled3: led3@3 { + reg = <3>; + label = "system:red:power"; + linux,default-trigger = "default-on"; + }; + + sysled4: led4@4 { + reg = <4>; + label = "system:green:act"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + + flash@1 { + compatible = "atmel,at45", "atmel,dataflash"; + reg = <1>; + spi-max-frequency = <25000000>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <8>; + non-removable; + no-1-8-v; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc4>; + bus-width = <4>; + no-1-8-v; + no-sdio; + cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + status = "okay"; + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-supply = <&vgen3_reg>; + phy-handle = <ðphy>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + reg = <0>; + max-speed = <100>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-mezz"; + current-speed = <57600>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog-legacy"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&usbotg { + dr_mode = "host"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&vusb2_reg>; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 + MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 + MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 + MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 + >; + }; + + pinctrl_esdhc4: esdhc4grp { + fsl,pins = < + MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 + MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 + MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 + MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 + MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 + MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 + MX51_PAD_NANDF_D0__GPIO4_8 0x100 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 + MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x20a4 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 + MX51_PAD_DI_GP3__FEC_TX_ER 0x2004 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 + MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 + MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 + MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 + MX51_PAD_EIM_A20__GPIO2_14 0x0085 + MX51_PAD_EIM_A21__GPIO2_15 0x00e5 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_4__GPIO1_4 0x85 + MX51_PAD_GPIO1_8__GPIO1_8 0xe5 + >; + }; + + pinctrl_swmdio: swmdiogrp { + fsl,pins = < + MX51_PAD_EIM_D22__GPIO2_6 0x100 + MX51_PAD_EIM_D23__GPIO2_7 0x100 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usb_mmc_reset: usbmmcgrp { + fsl,pins = < + MX51_PAD_CSI1_D9__GPIO3_13 0x85 + >; + }; +}; -- cgit v1.2.3 From 6c74366b8db6fc70b65266bf52c58a89ebc946f1 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:41 +0200 Subject: ARM: dts: imx6q-apalis: add chosen node Add Apalis UART1 as default serial console. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-apalis-eval.dts | 4 ++++ arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 4 ++++ arch/arm/boot/dts/imx6q-apalis-ixora.dts | 4 ++++ 3 files changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index aa0e631f3c0a..621d9709effa 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -62,6 +62,10 @@ rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts index e8dccf552122..4e1c8feaef82 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts @@ -63,6 +63,10 @@ rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 6831dfd24cc1..469e3d0e2827 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -62,6 +62,10 @@ rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; -- cgit v1.2.3 From 5780acda81d3f5378b71d8dead95b8d052dc22ae Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:42 +0200 Subject: ARM: dts: imx6q-apalis-eval: add carrier board 3.3V supply Add the 3.3V main supply on the carrier board. Currently as a fixed supply since not all consumer are modeled yet. This gets also rid of some missing supply warnings. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-apalis-eval.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index 621d9709effa..707ac9a46115 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -113,6 +113,7 @@ */ compatible = "edt,et057090dhu"; backlight = <&backlight>; + power-supply = <®_3v3_sw>; port { lcd_panel_in: endpoint { @@ -131,19 +132,30 @@ enable-active-high; status = "okay"; }; + + reg_3v3_sw: regulator-3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; &backlight { brightness-levels = <0 127 191 223 239 247 251 255>; default-brightness-level = <1>; + power-supply = <®_3v3_sw>; status = "okay"; }; &can1 { + xceiver-supply = <®_3v3_sw>; status = "okay"; }; &can2 { + xceiver-supply = <®_3v3_sw>; status = "okay"; }; -- cgit v1.2.3 From 3b1147a952cf9efb36144c1f7fd847d5a99adb7a Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:43 +0200 Subject: ARM: dts: imx6qdl-apalis/-colibri: prevent 1.8V modes Use no-1-8-v device tree property to indicate that the board does not support 1.8V signaling. The property voltage-ranges seems not appropriate in our case since we do not have level shifters in place. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 6 +++--- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 64fbee61de44..55bcea245df6 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -457,7 +457,7 @@ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; vqmmc-supply = <®_3p3v>; bus-width = <8>; - voltage-ranges = <3300 3300>; + no-1-8-v; status = "disabled"; }; @@ -467,7 +467,7 @@ pinctrl-0 = <&pinctrl_usdhc2>; vqmmc-supply = <®_3p3v>; bus-width = <4>; - voltage-ranges = <3300 3300>; + no-1-8-v; status = "disabled"; }; @@ -477,7 +477,7 @@ pinctrl-0 = <&pinctrl_usdhc3>; vqmmc-supply = <®_3p3v>; bus-width = <8>; - voltage-ranges = <3300 3300>; + no-1-8-v; non-removable; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 6e937ca20869..bb44829dacbe 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -389,7 +389,7 @@ cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ vqmmc-supply = <®_3p3v>; bus-width = <4>; - voltage-ranges = <3300 3300>; + no-1-8-v; status = "disabled"; }; @@ -399,7 +399,7 @@ pinctrl-0 = <&pinctrl_usdhc3>; vqmmc-supply = <®_3p3v>; bus-width = <8>; - voltage-ranges = <3300 3300>; + no-1-8-v; non-removable; status = "okay"; }; -- cgit v1.2.3 From 147299a8fc3a70f02984a6d6a042d0cbf53c46f9 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:44 +0200 Subject: ARM: dts: imx6qdl-apalis/-colibri: disable read-only switch Use the disable-wp to indicate that Apalis and Colibri iMX6 do not make use of the native write-protect signal available on the i.MX 6 SoCs. This prevents warnings: mmc0: host does not support reading read-only switch, assuming write-enable Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 2 ++ arch/arm/boot/dts/imx6qdl-colibri.dtsi | 1 + 2 files changed, 3 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 55bcea245df6..f9bacc9ff2b6 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -457,6 +457,7 @@ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; vqmmc-supply = <®_3p3v>; bus-width = <8>; + disable-wp; no-1-8-v; status = "disabled"; }; @@ -467,6 +468,7 @@ pinctrl-0 = <&pinctrl_usdhc2>; vqmmc-supply = <®_3p3v>; bus-width = <4>; + disable-wp; no-1-8-v; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index bb44829dacbe..8ae17fdf6cf6 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -387,6 +387,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ + disable-wp; vqmmc-supply = <®_3p3v>; bus-width = <4>; no-1-8-v; -- cgit v1.2.3 From 7034de41186f3b49fe987b4626ae1a151760a609 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:45 +0200 Subject: ARM: dts: imx6qdl-apalis/-colibri: remove 1.8V regulator The fixed 1.8V regulator is not used, and there is in fact no fixed 1.8V regulator on the module. Remove it. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 8 -------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 8 -------- 2 files changed, 16 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index f9bacc9ff2b6..2f711fffa06e 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -61,14 +61,6 @@ status = "disabled"; }; - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - reg_2p5v: regulator-2p5v { compatible = "regulator-fixed"; regulator-name = "2P5V"; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 8ae17fdf6cf6..1a147cb0bed0 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -56,14 +56,6 @@ status = "disabled"; }; - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - reg_2p5v: regulator-2p5v { compatible = "regulator-fixed"; regulator-name = "2P5V"; -- cgit v1.2.3 From 7060066d3e9920a4d96e106243e544c14ba0fd79 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:46 +0200 Subject: ARM: dts: imx6qdl-apalis/-colibri: fix on-module regulators Remove the 2.5V regulator, it does not exist. There is 3.3V and 3.3V_AUDIO provided to the module through the edge connector, model those as fixed regulators like we use to do in other Colibri device trees. The SGTL5000 uses 3.3V_AUDIO as VDDA. Note that the driver derives the analog ground voltage (VAG) from this supply. The new value should allow higher output swings before clipping occurs. Refer to the SGTL5000 datasheet for details. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 22 +++++++++++----------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 20 ++++++++++---------- 2 files changed, 21 insertions(+), 21 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 2f711fffa06e..6813f4326807 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -61,17 +61,17 @@ status = "disabled"; }; - reg_2p5v: regulator-2p5v { + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_3p3v: regulator-3p3v { + reg_module_3v3_audio: regulator-module-3v3-audio { compatible = "regulator-fixed"; - regulator-name = "3P3V"; + regulator-name = "+V3.3_AUDIO"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -314,8 +314,8 @@ compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; + VDDA-supply = <®_module_3v3_audio>; + VDDIO-supply = <®_module_3v3>; }; /* STMPE811 touch screen controller */ @@ -447,7 +447,7 @@ &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <8>; disable-wp; no-1-8-v; @@ -458,7 +458,7 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <4>; disable-wp; no-1-8-v; @@ -469,7 +469,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <8>; no-1-8-v; non-removable; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 1a147cb0bed0..9a3bac5be5e2 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -56,17 +56,17 @@ status = "disabled"; }; - reg_2p5v: regulator-2p5v { + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_3p3v: regulator-3p3v { + reg_module_3v3_audio: regulator-module-3v3-audio { compatible = "regulator-fixed"; - regulator-name = "3P3V"; + regulator-name = "+V3.3_AUDIO"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -244,8 +244,8 @@ compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; + VDDA-supply = <®_module_3v3_audio>; + VDDIO-supply = <®_module_3v3>; lrclk-strength = <3>; }; @@ -380,7 +380,7 @@ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ disable-wp; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <4>; no-1-8-v; status = "disabled"; @@ -390,7 +390,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <8>; no-1-8-v; non-removable; -- cgit v1.2.3 From 330f85598e87497974431c0f6f736e413ccf2d27 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:47 +0200 Subject: ARM: dts: imx6qdl-apalis/-colibri: assign VDDD to SGTL5000 VDDD is connected to VGEN4 of the PF0100. This rail should only run at 1.8V since there are multiple consumer and they all expect the rail to be at 1.8V. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 6813f4326807..8c04f42fdb71 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -289,7 +289,7 @@ vgen4_reg: vgen4 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -316,6 +316,7 @@ clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_module_3v3_audio>; VDDIO-supply = <®_module_3v3>; + VDDD-supply = <&vgen4_reg>; }; /* STMPE811 touch screen controller */ diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 9a3bac5be5e2..6821ea511051 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -219,7 +219,7 @@ vgen4_reg: vgen4 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -246,6 +246,7 @@ clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_module_3v3_audio>; VDDIO-supply = <®_module_3v3>; + VDDD-supply = <&vgen4_reg>; lrclk-strength = <3>; }; -- cgit v1.2.3 From b074f057ac60d32f604e0ca3120064e688e9a622 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:48 +0200 Subject: ARM: dts: imx6qdl-apalis/-colibri: remove unused pinctrl groups 100/200MHz states for USDHC3 are not required since the SoC does not support modes faster than DDR52 for the on board eMMC. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 34 ---------------------------------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 34 ---------------------------------- 2 files changed, 68 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 8c04f42fdb71..05f07ea3e8c8 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -947,38 +947,4 @@ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 >; }; - - pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 6821ea511051..87e15e7cb32b 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -692,40 +692,6 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 - >; - }; - pinctrl_weim_cs0: weimcs0grp { fsl,pins = < /* nEXT_CS0 */ -- cgit v1.2.3 From ba4446d4faeb8e60a78915c4f19645beb5f7e6ad Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 11 Jul 2018 08:58:59 +0800 Subject: ARM: dts: imx6sx: add ocram_s support i.MX6SX has a 16KB always-on ocram bank called ocram_s, enable it as another mmio sram. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 881c0dd8d09a..ae10225e8061 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -166,6 +166,12 @@ interrupt-parent = <&gpc>; ranges; + ocram_s: sram@8f8000 { + compatible = "mmio-sram"; + reg = <0x008f8000 0x4000>; + clocks = <&clks IMX6SX_CLK_OCRAM_S>; + }; + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; -- cgit v1.2.3 From 13211eec7b0e1b7b341b482811f69333c940f64c Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Wed, 11 Jul 2018 15:11:17 +0300 Subject: ARM: dts: imx6sl: Convert gpc to new bindings With old bindings imx_gpc_onecell_data always sets num_domains to 2 so the DISPMIX domain can't actually be referenced. The pd is still defined and pm core shuts it down as "unused" so display can't work. Fix this by converting to new gpc bindings by adding pgc nodes and referencing the newly-defined &pu_disp domain from &lcdif. Signed-off-by: Leonard Crestez Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c64bd906ad55..a6b5ca48298f 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -681,10 +681,36 @@ #interrupt-cells = <3>; interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - pu-supply = <®_pu>; - clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; - #power-domain-cells = <1>; + clocks = <&clks IMX6SL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_pu>; + clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, + <&clks IMX6SL_CLK_GPU2D_PODF>; + }; + + pd_disp: power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, + <&clks IMX6SL_CLK_LCDIF_PIX>, + <&clks IMX6SL_CLK_EPDC_AXI>, + <&clks IMX6SL_CLK_EPDC_PIX>, + <&clks IMX6SL_CLK_PXP_AXI>; + }; + }; }; gpr: iomuxc-gpr@20e0000 { @@ -739,6 +765,7 @@ <&clks IMX6SL_CLK_DUMMY>; clock-names = "pix", "axi", "disp_axi"; status = "disabled"; + power-domains = <&pd_disp>; }; dcp: dcp@20fc000 { -- cgit v1.2.3 From 996b1b611e2f604b542e60596e614ee340820eb7 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 10 Jul 2018 22:07:04 -0700 Subject: ARM: dts: imx: Add ZII SCU3 ESB Add support for the Zodiac Inflight Innovations i.MX51-base SCU3 Ethernet Switch Board (ESB) Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Fabio Estevam Signed-off-by: Andrey Gusakov Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 459 +++++++++++++++++++++++++++++++ 2 files changed, 461 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx51-zii-scu3-esb.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b000f917f336..46d9edca187b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -360,7 +360,8 @@ dtb-$(CONFIG_SOC_IMX51) += \ imx51-eukrea-mbimxsd51-baseboard.dtb \ imx51-ts4800.dtb \ imx51-zii-rdu1.dtb \ - imx51-zii-scu2-mezz.dtb + imx51-zii-scu2-mezz.dtb \ + imx51-zii-scu3-esb.dtb dtb-$(CONFIG_SOC_IMX53) += \ imx53-ard.dtb \ imx53-cx9020.dtb \ diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts new file mode 100644 index 000000000000..07bc5fc05076 --- /dev/null +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; + +#include "imx51.dtsi" + +/ { + model = "ZII SCU3 ESB board"; + compatible = "zii,imx51-scu3-esb", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + /* Will be filled by the bootloader */ + memory@90000000 { + reg = <0x90000000 0>; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_mmc_reset>; + gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; + startup-delay-us = <150000>; + }; +}; + +&cpu { + cpu-supply = <&sw1_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x0 0x0 0x3f83f8 0x0>; + + sysled3: led3@3 { + reg = <3>; + label = "system:red:power"; + linux,default-trigger = "default-on"; + }; + + sysled4: led4@4 { + reg = <4>; + label = "system:green:act"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <25000000>; + reg = <1>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <8>; + non-removable; + no-1-8-v; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc4>; + bus-width = <4>; + no-1-8-v; + no-sdio; + cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + fec_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + dsa,member = <0 0>; + eeprom-length = <512>; + interrupt-parent = <&gpio4>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "port1"; + }; + + port@1 { + reg = <1>; + label = "port2"; + }; + + port@2 { + reg = <2>; + label = "port3"; + }; + + port@3 { + reg = <3>; + label = "scu2scu"; + }; + + port@4 { + reg = <4>; + label = "esb2host"; + }; + + port@5 { + reg = <5>; + label = "esb2mezz"; + phy-mode = "sgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "cpu"; + phy-mode = "mii"; + ethernet = <&fec>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&ipu { + status = "disabled"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-esb"; + current-speed = <57600>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchodg-legacy"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&usbotg { + dr_mode = "host"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&vusb2_reg>; +}; + +&wdog1 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 + MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 + MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 + MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 + >; + }; + + pinctrl_esdhc4: esdhc4grp { + fsl,pins = < + MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 + MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 + MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 + MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 + MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 + MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 + MX51_PAD_NANDF_D0__GPIO4_8 0x100 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 + MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 + + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 + MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 + MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 + MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_4__GPIO1_4 0x85 + MX51_PAD_GPIO1_8__GPIO1_8 0xe5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 + MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 + MX51_PAD_USBH1_DATA0__UART2_CTS 0x1c5 + MX51_PAD_USBH1_DATA3__UART2_RTS 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usb_mmc_reset: usbmmcgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x100 + >; + }; +}; -- cgit v1.2.3 From bc36b2aac4f5e4accfe642bb51293f3d318312eb Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Sun, 3 Jun 2018 09:44:05 +0800 Subject: ARM: dts: imx6ul: add GPIO clocks i.MX6UL has GPIO clock gates in CCM CCGR, add clock property for GPIO driver to make sure all GPIO banks work as expected. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 47a3453a4211..e27bd919e28b 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -433,6 +433,7 @@ reg = <0x0209c000 0x4000>; interrupts = , ; + clocks = <&clks IMX6UL_CLK_GPIO1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -446,6 +447,7 @@ reg = <0x020a0000 0x4000>; interrupts = , ; + clocks = <&clks IMX6UL_CLK_GPIO2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -458,6 +460,7 @@ reg = <0x020a4000 0x4000>; interrupts = , ; + clocks = <&clks IMX6UL_CLK_GPIO3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -470,6 +473,7 @@ reg = <0x020a8000 0x4000>; interrupts = , ; + clocks = <&clks IMX6UL_CLK_GPIO4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -482,6 +486,7 @@ reg = <0x020ac000 0x4000>; interrupts = , ; + clocks = <&clks IMX6UL_CLK_GPIO5>; gpio-controller; #gpio-cells = <2>; interrupt-controller; -- cgit v1.2.3 From b6b93a3fe7ed12f0b80800be5df798c19adcc4ee Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 9 Jul 2018 15:19:14 -0300 Subject: ARM: dts: imx51: Add M4IF support As per the i.MX51 Reference Manual the M4IF register region starts at 0x83fd8000 and has a 4kB address range. Add support for it. Signed-off-by: Fabio Estevam Tested-by: Sergey Lapin Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 66e4187022be..b417c39f3772 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -531,6 +531,11 @@ status = "disabled"; }; + m4if: m4if@83fd8000 { + compatible = "fsl,imx51-m4if"; + reg = <0x83fd8000 0x1000>; + }; + weim: weim@83fda000 { #address-cells = <2>; #size-cells = <1>; -- cgit v1.2.3 From 4b301223d0574e6c390a174183d5ffa17cd6a12c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 10 Jul 2018 13:31:44 -0300 Subject: ARM: dts: imx51: Add PMU support Add PMU support in the device tree. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index b417c39f3772..0205db56d913 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -93,6 +93,12 @@ }; }; + pmu: pmu { + compatible = "arm,cortex-a8-pmu"; + interrupt-parent = <&tzic>; + interrupts = <77>; + }; + usbphy0: usbphy0 { compatible = "usb-nop-xceiv"; clocks = <&clks IMX5_CLK_USB_PHY_GATE>; -- cgit v1.2.3 From f2254a39f6225b6dc1173412cfd0f6def0dbcb42 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 10 Jul 2018 13:31:45 -0300 Subject: ARM: dts: imx51: Add tigerp support As per the i.MX51 Reference Manual add an entry for the 'tigerp' region in the device tree. This is needed for accessing the ARM_GPC register to set the DBGEN bit, so that the debug clocks can be turned on. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 0205db56d913..5c4ba91e43ba 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -451,6 +451,11 @@ clocks = <&clks IMX5_CLK_IIM_GATE>; }; + tigerp: tigerp@83fa0000 { + compatible = "fsl,imx51-tigerp"; + reg = <0x83fa0000 0x28>; + }; + owire: owire@83fa4000 { compatible = "fsl,imx51-owire", "fsl,imx21-owire"; reg = <0x83fa4000 0x4000>; -- cgit v1.2.3 From e548eac2b70423590cf7375a7aee5aaeefdfd638 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 10 Jul 2018 13:31:46 -0300 Subject: ARM: dts: imx53: Add tigerp support As per the i.MX53 Reference Manual add an entry for the 'tigerp' region in the device tree. This is needed for accessing the ARM_GPC register to set the DBGEN bit, so that the debug clocks can be turned on. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 1a7a7bb3df45..3fd553c9cf8b 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -672,6 +672,11 @@ status = "disabled"; }; + tigerp: tigerp@63fa0000 { + compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; + reg = <0x63fa0000 0x28>; + }; + owire: owire@63fa4000 { compatible = "fsl,imx53-owire", "fsl,imx21-owire"; reg = <0x63fa4000 0x4000>; -- cgit v1.2.3 From 4a2190aa2e92ba66d46e6bfdb8c68431e0ed9ced Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 10 Jul 2018 13:31:47 -0300 Subject: ARM: dts: imx53: Add a label for the PMU node Add a label for the PMU node so that the board dts may be able to pass the 'secure-reg-access' property like this: &pmu { secure-reg-access; }; This also makes it consistent with the PMU node in imx6qdl.dtsi Signed-off-by: Fabio Estevam Reviewed-by: Sebastian Reichel Tested-by: Sebastian Reichel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 3fd553c9cf8b..6386185ae234 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -113,7 +113,7 @@ }; }; - pmu { + pmu: pmu { compatible = "arm,cortex-a8-pmu"; interrupt-parent = <&tzic>; interrupts = <77>; -- cgit v1.2.3 From 51ecdd779e31ed45709bc32ff7efd4b28c3ce083 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 11 Jul 2018 21:44:50 +0800 Subject: ARM: sun8i: h3: add SY8113B regulator on Banana Pi M2 Zero board Banana Pi M2 Zero board has a SY8113B regulator, which is controlled via GPIO and capable of outputing 1.1V when the PL1 GPIO is set to output 0 or 1.1V when the PL6 GPIO is set to input or output 1, and the output is the power supply of the ARM cores in H3 SoC. Add the device tree node of this regulator and set the cpu's cpu-supply property to it. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- .../arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index 7d01f9322658..1db2541135a7 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -48,6 +48,23 @@ }; }; + reg_vdd_cpux: vdd-cpux-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + + gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ + enable-active-high; + gpios-states = <0x1>; + states = <1100000 0x0 + 1300000 0x1>; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -55,6 +72,10 @@ }; }; +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + &ehci0 { status = "okay"; }; -- cgit v1.2.3 From 8249ede477c50d82c4ce82b0f08f1ce89c919ae7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 12 Jul 2018 11:04:17 +0800 Subject: ARM: dts: sunxi: libretech-all-h3-cc: Enable eMMC module The Libretech ALL-H3-CC has a high density connector for attaching an eMMC module. The module form factor and connection is specific to Libretech, and has provisions for split vmmc/vqmmc (core and I/O) voltage supplies, but this board does not wire the vqmmc side. The H2+/H3/H5 SoCs do not support alternate I/O voltages for eMMC either. Only 3.3V is supported. A specific module that ties vqmmc to vmmc, with both at 3.3V, must be used. Given that a) eMMC is not designed to be hotplugged, b) power is always provided on the pins, and c) MMC controllers can deal with missing cards, we can enable this by default. If a module is attached it will be picked up by the system. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi index f7ffdd6658a2..1eadc132390c 100644 --- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi +++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi @@ -178,6 +178,15 @@ status = "okay"; }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc_io>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &ohci0 { status = "okay"; }; -- cgit v1.2.3 From 359754ed7a1efe0b08f5dd122015af53413c1bed Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Thu, 17 May 2018 16:36:00 +0200 Subject: ARM: dts: stm32: enable USB Host (USBH) EHCI controller on stm32mp157c-ev1 This patch enables USB Host (USBH) EHCI controller on stm32mp157c-ev1. As a hub is used between USBH and USB connectors, no need to enable USBH OHCI controller: all low- and full-speed traffic is managed by the hub. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 3be73d26fc62..0381cddac5a7 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -109,6 +109,12 @@ }; }; +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + &usbphyc { status = "okay"; }; -- cgit v1.2.3 From e2c205ab669b165190b19c1f925d96edba394339 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Thu, 17 May 2018 17:47:00 +0200 Subject: ARM: dts: stm32: add USB OTG HS support for stm32mp157c SoC This patch adds support for USB OTG HS on STM32MP157C SoC. USB OTG HS controller is based on DWC2 controller. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index d14c94034089..04c62acaf5a9 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -626,6 +626,21 @@ clocks = <&rcc DMAMUX>; }; + usbotg_hs: usb-otg@49000000 { + compatible = "snps,dwc2"; + reg = <0x49000000 0x10000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = ; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + dr_mode = "otg"; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; -- cgit v1.2.3 From 0bfa7f78dd226251fc31386346624e89ec79726b Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Thu, 17 May 2018 17:47:00 +0200 Subject: ARM: dts: stm32: enable USB OTG HS on stm32mp157c-ev1 This patch enables USB OTG HS on stm32mp157c-ev1 in Peripheral mode. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 0381cddac5a7..6cad8f175cdc 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -115,6 +115,13 @@ status = "okay"; }; +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + &usbphyc { status = "okay"; }; -- cgit v1.2.3 From 2dca78998a93029514ae8022f3f3bebdb0771973 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Tue, 22 May 2018 17:45:00 +0200 Subject: ARM: dts: stm32: Add ADC support to stm32mp157c stm32mp157c has an ADC block with two physical ADCs. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 04c62acaf5a9..19b003f81a26 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -626,6 +626,42 @@ clocks = <&rcc DMAMUX>; }; + adc: adc@48003000 { + compatible = "st,stm32mp1-adc-core"; + reg = <0x48003000 0x400>; + interrupts = , + ; + clocks = <&rcc ADC12>, <&rcc ADC12_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + interrupt-parent = <&adc>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + adc2: adc@100 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + reg = <0x100>; + interrupt-parent = <&adc>; + interrupts = <1>; + dmas = <&dmamux1 10 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + }; + usbotg_hs: usb-otg@49000000 { compatible = "snps,dwc2"; reg = <0x49000000 0x10000>; -- cgit v1.2.3 From 7beba56566d50144d29c3e805e2b325b8de15b21 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 23 May 2018 11:30:00 +0200 Subject: ARM: dts: stm32: Add DFSDM support to stm32mp157c stm32mp157c has DFSDM (Digital Filter For Sigma Delta Modulators) hardware with 6 filter instances. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 70 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 19b003f81a26..a4d4b62f365c 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -556,6 +556,76 @@ }; }; + dfsdm: dfsdm@4400d000 { + compatible = "st,stm32mp1-dfsdm"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>; + clock-names = "dfsdm"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <0>; + interrupts = ; + dmas = <&dmamux1 101 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <1>; + interrupts = ; + dmas = <&dmamux1 102 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm2: filter@2 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <2>; + interrupts = ; + dmas = <&dmamux1 103 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm3: filter@3 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <3>; + interrupts = ; + dmas = <&dmamux1 104 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm4: filter@4 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <4>; + interrupts = ; + dmas = <&dmamux1 91 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm5: filter@5 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <5>; + interrupts = ; + dmas = <&dmamux1 92 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + }; + m_can1: can@4400e000 { compatible = "bosch,m_can"; reg = <0x4400e000 0x400>, <0x44011000 0x2800>; -- cgit v1.2.3 From dc3f8c86c10d9c3ed481af1cd219de7a37ebe5f0 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 26 Jun 2018 14:54:07 +0200 Subject: ARM: dts: stm32: add SPI support on stm32mp157c This patch adds all SPI instances on stm32mp157c. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 84 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index a4d4b62f365c..518383020b68 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -311,6 +311,34 @@ }; }; + spi2: spi@4000b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = ; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + dmas = <&dmamux1 39 0x400 0x05>, + <&dmamux1 40 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi3: spi@4000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000c000 0x400>; + interrupts = ; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; + dmas = <&dmamux1 61 0x400 0x05>, + <&dmamux1 62 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + usart2: serial@4000e000 { compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>; @@ -494,6 +522,34 @@ status = "disabled"; }; + spi1: spi@44004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = ; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; + dmas = <&dmamux1 37 0x400 0x05>, + <&dmamux1 38 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi4: spi@44005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44005000 0x400>; + interrupts = ; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + dmas = <&dmamux1 83 0x400 0x05>, + <&dmamux1 84 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + timers15: timer@44006000 { #address-cells = <1>; #size-cells = <0>; @@ -556,6 +612,20 @@ }; }; + spi5: spi@44009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44009000 0x400>; + interrupts = ; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + dmas = <&dmamux1 85 0x400 0x05>, + <&dmamux1 86 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + dfsdm: dfsdm@4400d000 { compatible = "st,stm32mp1-dfsdm"; reg = <0x4400d000 0x800>; @@ -971,6 +1041,20 @@ status = "disabled"; }; + spi6: spi@5c001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x5c001000 0x400>; + interrupts = ; + clocks = <&rcc SPI6_K>; + resets = <&rcc SPI6_R>; + dmas = <&mdma1 34 0x0 0x40008 0x0 0x0 0>, + <&mdma1 35 0x0 0x40002 0x0 0x0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + i2c4: i2c@5c002000 { compatible = "st,stm32f7-i2c"; reg = <0x5c002000 0x400>; -- cgit v1.2.3 From 7e29ed4a970ca563693ff0dac21a63977c184ce4 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Thu, 17 May 2018 16:21:00 +0200 Subject: ARM: dts: stm32: add SPI1 support on stm32mp157c-ev1 This patch adds SPI1 support on stm32mp157c-ev1 board. SPI1 is available on GPIO expansion connector but kept disabled so these pins can be used as GPIOs by default. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 16 +++++++++++++++- arch/arm/boot/dts/stm32mp157c-ev1.dts | 6 ++++++ 2 files changed, 21 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index a7125aecd1f7..28bad7401d2c 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -294,7 +294,6 @@ pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - status = "disabled"; gpioz: gpio@54004000 { gpio-controller; @@ -318,6 +317,21 @@ slew-rate = <0>; }; }; + + spi1_pins_a: spi1-0 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 6cad8f175cdc..28284513d886 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -73,6 +73,12 @@ }; }; +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + status = "disabled"; +}; + &timers2 { status = "disabled"; pwm { -- cgit v1.2.3 From 06944a55fe4b98218ab61305839ab5cd19f70ae3 Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Wed, 23 May 2018 17:47:00 +0200 Subject: ARM: dts: stm32: Add syscfg on stm32mp1 System configuration controller is mainly used to manage the compensation cell and other IOs and system related settings. Signed-off-by: Christophe Roullier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 518383020b68..37d9fcb469d7 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -831,6 +831,11 @@ reg = <0x5000d000 0x400>; }; + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + }; + lptimer2: timer@50021000 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 7c045e8be193ef61a34953a22a9eba97f392a2b1 Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Tue, 26 Jun 2018 18:24:26 +0200 Subject: ARM: dts: stm32: Add ethernet dwmac on stm32mp1 Add Ethernet support (Synopsys MAC IP 4.20a) on stm32mp1 SOC. Enable feature supported by the stmmac driver, such as TSO. Signed-off-by: Christophe Roullier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 37d9fcb469d7..e42c1a3a40a4 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -978,6 +978,36 @@ status = "disabled"; }; + stmmac_axi_config_0: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + ethernet0: ethernet@5800a000 { + compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "syscfg-clk"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHSTP>, + <&rcc SYSCFG>; + st,syscon = <&syscfg 0x4>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_0>; + snps,tso; + status = "disabled"; + }; + usbh_ohci: usbh-ohci@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; -- cgit v1.2.3 From a7419ff8b71a10fca551e3e7e89afe6a2b89559f Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Tue, 26 Jun 2018 15:12:23 +0200 Subject: ARM: dts: stm32: add support of ethernet on stm32mp157c-ev1 MAC is connected to a PHY in RGMII mode. Signed-off-by: Christophe Roullier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 46 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-ev1.dts | 20 ++++++++++++++ 2 files changed, 66 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 28bad7401d2c..c4851271e810 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -157,6 +157,52 @@ }; }; + ethernet0_rgmii_pins_a: rgmii-0 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 28284513d886..372bc2ea6b92 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -17,6 +17,26 @@ aliases { serial0 = &uart4; + ethernet0 = ðernet0; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; -- cgit v1.2.3 From b86646881b4fe213ebaa58f3a18351df1a7ed2b1 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Tue, 26 Jun 2018 17:55:13 +0200 Subject: ARM: dts: stm32: remove gpio aliases for stm32mp157c GPIO aliases are not used by stm32 pinctrl driver. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index e42c1a3a40a4..0437e01e8438 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -35,20 +35,6 @@ cpu_on = <0x84000003>; }; - aliases { - gpio0 = &gpioa; - gpio1 = &gpiob; - gpio2 = &gpioc; - gpio3 = &gpiod; - gpio4 = &gpioe; - gpio5 = &gpiof; - gpio6 = &gpiog; - gpio7 = &gpioh; - gpio8 = &gpioi; - gpio9 = &gpioj; - gpio10 = &gpiok; - }; - intc: interrupt-controller@a0021000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; -- cgit v1.2.3 From e880845e29f4393034c6c56f007ecda4fb377efc Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Tue, 26 Jun 2018 18:07:49 +0200 Subject: ARM: dts: stm32: Reorder nodes in stm32mp157c-ed1 Nodes should be ordered in alphabetic order. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 050c30d327db..de8b8a106a36 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -49,17 +49,6 @@ }; }; -&rng1 { - status = "okay"; -}; - -&timers6 { - status = "okay"; - timer@5 { - status = "okay"; - }; -}; - &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; @@ -68,10 +57,21 @@ status = "okay"; }; +&rng1 { + status = "okay"; +}; + &rtc { status = "okay"; }; +&timers6 { + status = "okay"; + timer@5 { + status = "okay"; + }; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; -- cgit v1.2.3 From 5f0f3bac59207562b08124ad28339c6485c9178c Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Mon, 25 Jun 2018 17:43:00 +0200 Subject: ARM: dts: stm32: add iwdg2 support for stm32mp157c This patch adds independent watchdog support for stm32mp157c. Signed-off-by: Ludovic Barre Acked-by: Guenter Roeck Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 0437e01e8438..661be948ab74 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -1034,6 +1034,14 @@ status = "disabled"; }; + iwdg2: watchdog@5a002000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; + clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; + status = "disabled"; + }; + usbphyc: usbphyc@5a006000 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From dd2eda3d97d99781f1889b3e08fd18c6f8ff23c7 Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Mon, 25 Jun 2018 17:43:00 +0200 Subject: ARM: dts: stm32: add iwdg2 support for stm32mp157c-ed1 This patch activates independent watchdog support for stm32mp157c board. Signed-off-by: Ludovic Barre Reviewed-by: Guenter Roeck Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index de8b8a106a36..f77bea49c079 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -57,6 +57,11 @@ status = "okay"; }; +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + &rng1 { status = "okay"; }; -- cgit v1.2.3 From c2888cc2e2b8fc16164de0cca806763831a36f6f Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Fri, 13 Jul 2018 11:21:39 +0200 Subject: ARM: dts: stm32: update iwdg with lsi clock name for stm32f429 This patch updates iwdg watchdog to use lsi clock name. Signed-off-by: Ludovic Barre Acked-by: Guenter Roeck Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 309e7e335ab7..e35d782e7e5f 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -310,6 +310,7 @@ compatible = "st,stm32-iwdg"; reg = <0x40003000 0x400>; clocks = <&clk_lsi>; + clock-names = "lsi"; status = "disabled"; }; -- cgit v1.2.3 From ba62dc1126e85d408db02b91679bc3a780ec5ef0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 11 Jul 2018 22:27:49 +0200 Subject: ARM: dts: nomadik: Cut FSMC timings After the work done by Thomas Petazzoni, the NAND chip timings can be read out from the chip instead of open coded in the device tree, so let's just remove the timing information. Cc: Thomas Petazzoni Signed-off-by: Linus Walleij Signed-off-by: Olof Johansson --- arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 733678b75b88..fca76a696d9d 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -661,7 +661,6 @@ reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; clocks = <&hclksmc>; status = "okay"; - timings = /bits/ 8 <0 0 0 0x10 0x0a 0>; partition@0 { label = "X-Loader(NAND)"; -- cgit v1.2.3 From 423fbae3d04e29dfbfd909672ca1c76d1f7342ef Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 30 May 2018 22:35:39 +0200 Subject: ARM: dts: Add WAN ethernet port to the SQ201 This sets up the ethernet interface and PHY for the WAN ethernet port which uses a Marvell PHY. Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-sq201.dts | 84 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index e5cf9d1a98cd..a57a03e2953b 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -55,6 +55,20 @@ }; }; + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + /* Uses MDC and MDIO */ + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + /* This is a Marvell 88E1111 ethernet transciever */ + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; + soc { flash@30000000 { /* @@ -108,6 +122,7 @@ /* * gpio0fgrp cover line 18 used by reset button * gpio0ggrp cover line 20 used by info LED + * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY * gpio0kgrp cover line 31 used by USB LED */ gpio0_default_pins: pinctrl-gpio0 { @@ -115,9 +130,66 @@ function = "gpio0"; groups = "gpio0fgrp", "gpio0ggrp", + "gpio0hgrp", "gpio0kgrp"; }; }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + }; + /* Settings come from memory dump in PLATO */ + conf0 { + pins = "V8 GMAC0 RXDV"; + skew-delay = <0>; + }; + conf1 { + pins = "Y7 GMAC0 RXC"; + skew-delay = <15>; + }; + conf2 { + pins = "T8 GMAC0 TXEN"; + skew-delay = <7>; + }; + conf3 { + pins = "U8 GMAC0 TXC"; + skew-delay = <10>; + }; + conf4 { + pins = "T10 GMAC1 RXDV"; + skew-delay = <7>; + }; + conf5 { + pins = "Y11 GMAC1 RXC"; + skew-delay = <8>; + }; + conf6 { + pins = "W11 GMAC1 TXEN"; + skew-delay = <7>; + }; + conf7 { + pins = "V11 GMAC1 TXC"; + skew-delay = <5>; + }; + conf8 { + /* The data lines all have default skew */ + pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", + "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", + "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", + "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", + "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", + "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", + "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", + "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; + skew-delay = <7>; + }; + /* Set up drive strength on GMAC0 and GMAC1 to 16 mA */ + conf9 { + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + drive-strength = <16>; + }; + }; }; }; @@ -154,6 +226,18 @@ <0x6000 0 0 4 &pci_intc 2>; }; + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + /* Used for the Vitesse G5 chip, add later */ + }; + }; + ata@63000000 { status = "okay"; }; -- cgit v1.2.3 From fa35007f62b60d9234893688a17936ab8562d11a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 1 Jun 2018 22:50:29 +0200 Subject: ARM: dts: Add Vitesse G5e switch to the Gemini SQ201 This adds the Vitesse G5e ethernet switch to the Square One Itian SQ201 router device tree. Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-sq201.dts | 77 +++++++++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index a57a03e2953b..3787cf3763c4 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -69,6 +69,61 @@ }; }; + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + /* Check pin collisions */ + gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + switch@0 { + compatible = "vitesse,vsc7395"; + reg = <0>; + /* Specified for 2.5 MHz or below */ + spi-max-frequency = <2500000>; + gpio-controller; + #gpio-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + port@1 { + reg = <1>; + label = "lan2"; + }; + port@2 { + reg = <2>; + label = "lan3"; + }; + port@3 { + reg = <3>; + label = "lan4"; + }; + vsc: port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + soc { flash@30000000 { /* @@ -134,6 +189,16 @@ "gpio0kgrp"; }; }; + /* + * gpio0dgrp cover lines used by the SPI + * to the Vitesse G5x chip. + */ + gpio1_default_pins: pinctrl-gpio1 { + mux { + function = "gpio1"; + groups = "gpio1dgrp"; + }; + }; pinctrl-gmii { mux { function = "gmii"; @@ -204,6 +269,11 @@ pinctrl-0 = <&gpio0_default_pins>; }; + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + pci@50000000 { status = "okay"; interrupt-map-mask = <0xf800 0 0 7>; @@ -234,7 +304,12 @@ phy-handle = <&phy0>; }; ethernet-port@1 { - /* Used for the Vitesse G5 chip, add later */ + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; }; }; -- cgit v1.2.3 From 41043ec45bdea5970e7c2d6766caf0793aeeb159 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 16 Jun 2018 15:21:45 +0200 Subject: ARM: dts: Add devicetree for Storlink/Storm SL93512R The Storlink Gemini324 EV-Board also known as Storm Semiconductor SL93512R_BRD is ground zero for the Gemini devices. We add a device tree so we can support it, it turns out to be pretty trivial. Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/gemini-sl93512r.dts | 328 ++++++++++++++++++++++++++++++++++ 2 files changed, 329 insertions(+) create mode 100644 arch/arm/boot/dts/gemini-sl93512r.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..a10ef98c6d75 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -200,6 +200,7 @@ dtb-$(CONFIG_ARCH_GEMINI) += \ gemini-dlink-dns-313.dtb \ gemini-nas4220b.dtb \ gemini-rut1xx.dtb \ + gemini-sl93512r.dtb \ gemini-sq201.dtb \ gemini-wbd111.dtb \ gemini-wbd222.dtb diff --git a/arch/arm/boot/dts/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini-sl93512r.dts new file mode 100644 index 000000000000..ebefb7297379 --- /dev/null +++ b/arch/arm/boot/dts/gemini-sl93512r.dts @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the Storm Semiconductor SL93512R_BRD + * Gemini reference design, also initially called + * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor. + * The series were later acquired by Cortina Systems. + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include + +/ { + model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD"; + compatible = "storlink,gemini324", "storm,sl93512r", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 64 MB Samsung K4H511638B */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait"; + stdout-path = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-wps { + debounce-interval = <50>; + wakeup-source; + linux,code = ; + label = "WPS"; + /* Conflict with NAND flash */ + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + + button-setup { + debounce-interval = <50>; + wakeup-source; + linux,code = ; + label = "factory reset"; + /* Conflict with NAND flash */ + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led-green-harddisk { + label = "sq201:green:harddisk"; + /* Conflict with LCD (no problem) */ + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "disk-activity"; + }; + led-green-wireless { + label = "sq201:green:wireless"; + /* Conflict with NAND flash CE0 (no problem) */ + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + /* Uses MDC and MDIO */ + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + /* This is a Marvell 88E1111 ethernet transciever */ + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + /* Check pin collisions */ + gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + switch@0 { + compatible = "vitesse,vsc7385"; + reg = <0>; + /* Specified for 2.5 MHz or below */ + spi-max-frequency = <2500000>; + gpio-controller; + #gpio-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + port@1 { + reg = <1>; + label = "lan2"; + }; + port@2 { + reg = <2>; + label = "lan3"; + }; + port@3 { + reg = <3>; + label = "lan4"; + }; + vsc: port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + + soc { + flash@30000000 { + status = "okay"; + /* 16MB of flash */ + reg = <0x30000000 0x01000000>; + + partition@0 { + label = "BOOT"; + reg = <0x00000000 0x00020000>; + read-only; + }; + partition@120000 { + label = "Kern"; + reg = <0x00020000 0x00300000>; + }; + partition@320000 { + label = "Ramdisk"; + reg = <0x00320000 0x00600000>; + }; + partition@920000 { + label = "Application"; + reg = <0x00920000 0x00600000>; + }; + partition@f20000 { + label = "VCTL"; + reg = <0x00f20000 0x00020000>; + read-only; + }; + partition@f40000 { + label = "CurConf"; + reg = <0x00f40000 0x000a0000>; + read-only; + }; + partition@fe0000 { + label = "FIS directory"; + reg = <0x00fe0000 0x00020000>; + read-only; + }; + }; + + syscon: syscon@40000000 { + pinctrl { + /* + * gpio0egrp cover line 16 used by HD LED + * gpio0fgrp cover line 17, 18 used by wireless LED and reset button + * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY + * gpio0kgrp cover line 31 used by USB LED + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = "gpio0egrp", + "gpio0fgrp", + "gpio0hgrp"; + }; + }; + /* + * gpio1dgrp cover lines used by SPI for + * the Vitesse chip (28-31) + */ + gpio1_default_pins: pinctrl-gpio1 { + mux { + function = "gpio1"; + groups = "gpio1dgrp"; + }; + }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + }; + /* Control pad skew comes from sl_switch.c in the vendor code */ + conf0 { + pins = "P10 GMAC1 TXC"; + skew-delay = <5>; + }; + conf1 { + pins = "V11 GMAC1 TXEN"; + skew-delay = <7>; + }; + conf2 { + pins = "T11 GMAC1 RXC"; + skew-delay = <8>; + }; + conf3 { + pins = "U11 GMAC1 RXDV"; + skew-delay = <7>; + }; + conf4 { + pins = "V7 GMAC0 TXC"; + skew-delay = <10>; + }; + conf5 { + pins = "P8 GMAC0 TXEN"; + skew-delay = <7>; /* 5 at another place? */ + }; + conf6 { + pins = "T8 GMAC0 RXC"; + skew-delay = <15>; + }; + conf7 { + pins = "R8 GMAC0 RXDV"; + skew-delay = <0>; + }; + conf8 { + /* The data lines all have default skew */ + pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", + "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", + "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", + "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", + "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", + "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; + skew-delay = <7>; + }; + /* Appears in sl351x_gmac.c in the vendor code */ + conf9 { + pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", + "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; + skew-delay = <5>; + }; + }; + }; + }; + + /* Both interfaces brought out on SATA connectors */ + sata: sata@46000000 { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + + gpio0: gpio@4d000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; + }; + + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + + pci@50000000 { + status = "okay"; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ + <0x4800 0 0 2 &pci_intc 1>, + <0x4800 0 0 3 &pci_intc 2>, + <0x4800 0 0 4 &pci_intc 3>, + <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ + <0x5000 0 0 2 &pci_intc 2>, + <0x5000 0 0 3 &pci_intc 3>, + <0x5000 0 0 4 &pci_intc 0>, + <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ + <0x5800 0 0 2 &pci_intc 3>, + <0x5800 0 0 3 &pci_intc 0>, + <0x5800 0 0 4 &pci_intc 1>, + <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ + <0x6000 0 0 2 &pci_intc 0>, + <0x6000 0 0 3 &pci_intc 1>, + <0x6000 0 0 4 &pci_intc 2>; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + ata@63000000 { + status = "okay"; + }; + + ata@63400000 { + status = "okay"; + }; + }; +}; -- cgit v1.2.3 From 2ca48895ba984c9b1fa0e725064decfed527811b Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Mon, 25 Jun 2018 11:57:13 +0200 Subject: arm: dts: mediatek: Fix pio-leds for Bananapi-R2 Pio-leds (near GPIO-Header) are swapped and LOW-active. This patch restores the expected behaviour. Signed-off-by: Frank Wunderlich Reviewed-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 531d905d924f..2b760f90f38c 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -91,19 +91,19 @@ blue { label = "bpi-r2:pio:blue"; - gpios = <&pio 241 GPIO_ACTIVE_HIGH>; + gpios = <&pio 240 GPIO_ACTIVE_LOW>; default-state = "off"; }; green { label = "bpi-r2:pio:green"; - gpios = <&pio 240 GPIO_ACTIVE_HIGH>; + gpios = <&pio 241 GPIO_ACTIVE_LOW>; default-state = "off"; }; red { label = "bpi-r2:pio:red"; - gpios = <&pio 239 GPIO_ACTIVE_HIGH>; + gpios = <&pio 239 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; -- cgit v1.2.3 From c282ea743bb617b9419398254308edfa70c3c64f Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 29 Jun 2018 13:51:00 +1000 Subject: ARM: dts: aspeed: Add G4 USB pinmux Set the default pinmux for EHCI so boards don't have to do it, and document why it is not set for UHCI. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 75df1573380e..1d7ffa9fdb11 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -113,6 +113,8 @@ reg = <0x1e6a1000 0x100>; interrupts = <5>; clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2h_default>; status = "disabled"; }; @@ -123,6 +125,10 @@ #ports = <3>; clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; status = "disabled"; + /* + * No default pinmux, it will follow EHCI, use an explicit pinmux + * override if you don't enable EHCI + */ }; apb { -- cgit v1.2.3 From 112c5a640cfb03b532bea0179991895bbff25aa4 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 29 Jun 2018 13:51:01 +1000 Subject: ARM: dts: aspeed: Add G5 USB host pinmux Set the default pinmux for EHCIs so boards don't have to do it an document why it is not set for UHCI. Remove the properties from the AST2500 EVB board which are now redundant Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2500-evb.dts | 6 ------ arch/arm/boot/dts/aspeed-g5.dtsi | 8 ++++++++ 2 files changed, 8 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index ede11c597673..2bff1b253842 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -82,18 +82,12 @@ &ehci0 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2ah_default>; }; &ehci1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2bh_default>; }; &uhci { status = "okay"; - - /* No pinctrl, this follows the above EHCI settings */ }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 17f2714d18a7..dfdc239b86f6 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -148,6 +148,8 @@ reg = <0x1e6a1000 0x100>; interrupts = <5>; clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ah_default>; status = "disabled"; }; @@ -156,6 +158,8 @@ reg = <0x1e6a3000 0x100>; interrupts = <13>; clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2bh_default>; status = "disabled"; }; @@ -166,6 +170,10 @@ #ports = <2>; clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; status = "disabled"; + /* + * No default pinmux, it will follow EHCI, use an explicit pinmux + * override if you don't enable EHCI + */ }; apb { -- cgit v1.2.3 From 608d05c61cdcd42d0ecdf7ad2d865b54569f79d5 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 29 Jun 2018 13:51:02 +1000 Subject: ARM: dts: aspeed: Add G4 USB Virtual Hub This adds the (disabled by default) device node for the Aspeed virtual hub,a long with clocks and pinmux. Signed-off-by: Benjamin Herrenschmidt Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 1d7ffa9fdb11..54524564037c 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -131,6 +131,16 @@ */ }; + vhub: usb-vhub@1e6a0000 { + compatible = "aspeed,ast2400-usb-vhub"; + reg = <0x1e6a0000 0x300>; + interrupts = <5>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2d_default>; + status = "disabled"; + }; + apb { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From 35578a85d981ffb434b7eb8cd2156388788dcaa0 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 29 Jun 2018 13:51:03 +1000 Subject: ARM: dts: aspeed: Add G5 USB Virtual Hub This adds the (disabled by default) device node for the Aspeed virtual hub,a long with clocks and pinmux. This also adds the missing pinmux definition for it (the kernel driver already knows about it). Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index dfdc239b86f6..6274d3eaf374 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -176,6 +176,16 @@ */ }; + vhub: usb-vhub@1e6a0000 { + compatible = "aspeed,ast2500-usb-vhub"; + reg = <0x1e6a0000 0x300>; + interrupts = <5>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ad_default>; + status = "disabled"; + }; + apb { compatible = "simple-bus"; #address-cells = <1>; @@ -1425,6 +1435,11 @@ groups = "USB2AH"; }; + pinctrl_usb2ad_default: usb2ad_default { + function = "USB2AD"; + groups = "USB2AD"; + }; + pinctrl_usb11bhid_default: usb11bhid_default { function = "USB11BHID"; groups = "USB11BHID"; -- cgit v1.2.3 From b35bbd3d71872d35df17c40b4e4423855d8c5e6f Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 29 Jun 2018 13:51:06 +1000 Subject: ARM: dts: aspeed: Enable vhub on port A of AST2500 EVB This is an eval board, it makes sense to enable many functions by default. This changes the device-tree to set port A to be a USB device and leave port B as a host, along with a little comment explaining how to change it. (the vhub device can only exist on port A on this SoC) Signed-off-by: Benjamin Herrenschmidt Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2500-evb.dts | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index 2bff1b253842..2375449c02d0 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -80,7 +80,13 @@ }; }; -&ehci0 { +/* + * Enable port A as device (via the virtual hub) and port B as + * host by default on the eval board. This can be easily changed + * by replacing the override below with &ehci0 { ... } to enable + * host on both ports. + */ +&vhub { status = "okay"; }; -- cgit v1.2.3 From 0f33bde8859b7746ecdd8af1d1e5dde0e9b899f9 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 18 Jun 2018 14:58:59 +1000 Subject: ARM: dts: aspeed: Fix Romulus VGA frame buffer The reserved memory for the VGA frame buffer is at the wrong address for this system. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 389f5f83bef9..9176b3cda812 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -21,9 +21,9 @@ #size-cells = <1>; ranges; - vga_memory: framebuffer@bf000000 { + vga_memory: framebuffer@9f000000 { no-map; - reg = <0xbf000000 0x01000000>; /* 16M */ + reg = <0x9f000000 0x01000000>; /* 16M */ }; flash_memory: region@98000000 { -- cgit v1.2.3 From 345058a4c5d96a61a06c2d32a61c172da8f0d366 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Tue, 10 Jul 2018 13:09:25 +0800 Subject: arm: dts: mt7623: cleanup MT7623N NAND dts file Normally, we didn't release this kind of baord to user. This specific board exists only in the early stage of development inside MediaTek - and that may confuse peoples. Hence this patch removes related files accordingly. Cc: John Crispin Cc: Sean Wang Signed-off-by: Ryder Lee Acked-by: John Crispin Acked-by: Sean Wang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/Makefile | 1 - arch/arm/boot/dts/mt7623n-rfb-nand.dts | 73 ----------------------------- arch/arm/boot/dts/mt7623n-rfb.dtsi | 86 ---------------------------------- 3 files changed, 160 deletions(-) delete mode 100644 arch/arm/boot/dts/mt7623n-rfb-nand.dts delete mode 100644 arch/arm/boot/dts/mt7623n-rfb.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..dde494e5d9bc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1168,7 +1168,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623a-rfb-emmc.dtb \ mt7623a-rfb-nand.dtb \ mt7623n-rfb-emmc.dtb \ - mt7623n-rfb-nand.dtb \ mt7623n-bananapi-bpi-r2.dtb \ mt8127-moose.dtb \ mt8135-evbp1.dtb diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts b/arch/arm/boot/dts/mt7623n-rfb-nand.dts deleted file mode 100644 index 96ff3c9068ae..000000000000 --- a/arch/arm/boot/dts/mt7623n-rfb-nand.dts +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: John Crispin - * - */ - -/dts-v1/; -#include "mt7623n-rfb.dtsi" - -/ { - model = "MediaTek MT7623N NAND reference board"; - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623"; -}; - -&bch { - status = "okay"; -}; - -&nandc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins_default>; - - nand@0 { - reg = <0>; - spare_per_sector = <64>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <12>; - nand-ecc-step-size = <1024>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "preloader"; - reg = <0x0 0x40000>; - }; - - partition@40000 { - label = "uboot"; - reg = <0x40000 0x80000>; - }; - - partition@c0000 { - label = "uboot-env"; - reg = <0xC0000 0x40000>; - }; - - partition@140000 { - label = "bootimg"; - reg = <0x140000 0x2000000>; - }; - - partition@2140000 { - label = "recovery"; - reg = <0x2140000 0x2000000>; - }; - - partition@4140000 { - label = "rootfs"; - reg = <0x4140000 0x1000000>; - }; - - partition@5140000 { - label = "usrdata"; - reg = <0x5140000 0x1000000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi b/arch/arm/boot/dts/mt7623n-rfb.dtsi deleted file mode 100644 index 5c5cc7da5dd2..000000000000 --- a/arch/arm/boot/dts/mt7623n-rfb.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: John Crispin - * Sean Wang - * - */ - -/dts-v1/; -#include "mt7623.dtsi" -#include "mt6323.dtsi" - -/ { - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - cpus { - cpu0 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu1 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu2 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu3 { - proc-supply = <&mt6323_vproc_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - usb_p1_vbus: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 135 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&mmc0 { - vmmc-supply = <&mt6323_vemc3v3_reg>; - vqmmc-supply = <&mt6323_vio18_reg>; -}; - -&mmc1 { - vmmc-supply = <&mt6323_vmch_reg>; - vqmmc-supply = <&mt6323_vmc_reg>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb1 { - vbus-supply = <&usb_p1_vbus>; - status = "okay"; -}; - -&u3phy1 { - status = "okay"; -}; -- cgit v1.2.3 From 497f6ee16b05621bf118517dd4b7848836d9767e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 11 Jul 2018 18:34:27 -0300 Subject: ARM: dts: imx51-zii-rdu1: Disable internal watchdog imx51-zii-rdu1 has an external watchdog in the environment microcontroller, so disable the internal one. This aligns with what was done in commit 7055f714032c ("ARM: dts: imx6: RDU2: disable internal watchdog") for imx6 rdu2 board. Signed-off-by: Fabio Estevam Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index aede622c47a5..1217e196b93a 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -668,6 +668,10 @@ status = "okay"; }; +&wdog1 { + status = "disabled"; +}; + &iomuxc { pinctrl_ampgpio: ampgpiogrp { fsl,pins = < -- cgit v1.2.3 From 0b9c89e213d227d3649a1cb77bb6b912fbd532f9 Mon Sep 17 00:00:00 2001 From: Alex Gonzalez Date: Thu, 12 Jul 2018 10:20:35 +0200 Subject: ARM: dts: imx6ul: Add DTS for ConnectCore 6UL System-On-Module (SOM) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ConnectCore 6UL System-On-Module has the following hardware specification: * Based on a NXP i.MX6UL SoC * Industrial temperature ranges (-40ºC to +85ºC) * Up to 1GB DDR3 memory * Up to 2GB NAND flash * Dual Ethernet * On module 802.11 WiFi and Bluetooth 4.2 (QCA6564) * On module NXP Kinetis KL03 * On module Microchip ATECC508A crypto element Signed-off-by: Alex Gonzalez Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi | 201 ++++++++++++++++++++++++++++++ 1 file changed, 201 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi new file mode 100644 index 000000000000..c71a84da1af0 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Digi International's ConnectCore 6UL System-On-Module device tree source + * + * Copyright 2018 Digi International, Inc. + * + */ + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x4000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply = <&vdda_adc_3v3>; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pfuze3000: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + int_3v3: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <6250>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm_soc_in: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-ramp-delay = <6250>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <925000>; + }; + }; + + ext_3v3: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr3: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1300000>; + }; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + vdd_snvs_3v3: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vdda_adc_3v3: vldo1 { + compatible = "regulator-fixed"; + regulator-name = "vref-adc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo2_ext: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vdda_wlan: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_high_in: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_int: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4_ext: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vcoin_chg: vcoin { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmigrp { + fsl,pins = < + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; +}; + +®_arm { + vin-supply = <&vdd_arm_soc_in>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&vdd_arm_soc_in>; + regulator-allow-bypass; +}; -- cgit v1.2.3 From 8c7725829989d2711875f60356d22bc5af981ac0 Mon Sep 17 00:00:00 2001 From: Alex Gonzalez Date: Thu, 12 Jul 2018 10:20:36 +0200 Subject: ARM: dts: imx6ul: Add DTS for ConnectCore 6UL SBC Express The ConnectCore 6UL Single Board Computer (SBC) Express contains the ConnectCore 6UL System-On-Module. Its hardware specifications are: * 256MB DDR3 memory * 256MB NAND flash * Single Ethernet * USB Host and USB-OTG * MicroSD external storage * Groove connectors and Raspberry Pi Hat compatible expansion header Signed-off-by: Alex Gonzalez Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts | 200 ++++++++++++++++++++++++ 2 files changed, 201 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 46d9edca187b..d459e2330307 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -541,6 +541,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-udoo-neo-full.dtb dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-14x14-evk.dtb \ + imx6ul-ccimx6ulsbcexpress.dtb \ imx6ul-geam.dtb \ imx6ul-isiot-emmc.dtb \ imx6ul-isiot-nand.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts new file mode 100644 index 000000000000..3792679c0c90 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Digi International's ConnectCore6UL SBC Express board device tree source + * + * Copyright 2018 Digi International, Inc. + * + */ + +/dts-v1/; +#include +#include +#include "imx6ul.dtsi" +#include "imx6ul-ccimx6ulsom.dtsi" + +/ { + model = "Digi International ConnectCore 6UL SBC Express."; + compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom", + "fsl,imx6ul"; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <&ext_3v3>; + status = "okay"; +}; + +&ecspi3 { + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3_master>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + smsc,disable-energy-detect; + reg = <0>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + broken-cd; /* no carrier detect line (use polling) */ + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_adc1: adc1grp { + fsl,pins = < + /* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */ + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_ecspi3_master: ecspi3grp1 { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* Chip Select */ + >; + }; + + pinctrl_ecspi3_slave: ecspi3grp2 { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x10b0 /* Chip Select */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x10b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10071 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + /* General purpose pinctrl */ + pinctrl_hog: hoggrp { + fsl,pins = < + /* GPIOs BANK 3 */ + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xf030 + >; + }; +}; -- cgit v1.2.3 From dd769b09003ec92f088fef1be96bfe90cf44d640 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 12 Jul 2018 10:02:36 -0300 Subject: ARM: dts: imx53-ppd: Enable secure-reg-access Add 'secure-reg-access' property to enable PMU and hardware counters so that they can be properly used with the 'perf' tool. Signed-off-by: Sebastian Reichel [fabio: kept the change only in imx53-ppd context] Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-ppd.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index 444ec84cf342..cdb90bee7b4a 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -594,6 +594,10 @@ }; }; +&pmu { + secure-reg-access; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; -- cgit v1.2.3 From 3ec14f5eb58f5c77713f39159e73422c187f9ca4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 12 Jul 2018 10:02:37 -0300 Subject: ARM: dts: imx51-babbage: Enable secure-reg-access Add 'secure-reg-access' property to enable PMU and hardware counters so that they can be properly used with the 'perf' tool. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index a4a6d4a6b55b..ba60b0cb3cc1 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -396,6 +396,10 @@ status = "okay"; }; +&pmu { + secure-reg-access; +}; + &ssi2 { status = "okay"; }; -- cgit v1.2.3 From b4d5f09fbc00463cee21c28485080e9537c48508 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 12 Jul 2018 10:02:38 -0300 Subject: ARM: dts: imx51-zii-rdu1: Enable secure-reg-access Add 'secure-reg-access' property to enable PMU and hardware counters so that they can be properly used with the 'perf' tool. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index 1217e196b93a..60b4d71c0dfe 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -565,6 +565,10 @@ remote-endpoint = <&display_in>; }; +&pmu { + secure-reg-access; +}; + &ssi2 { status = "okay"; }; -- cgit v1.2.3 From a046e7662dcf2ddd28b84552e20baa03355d8423 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 13 Jul 2018 15:58:25 +0800 Subject: ARM: dts: imx6sll-evk: enable PWM1 for backlight driver Enable pwm1 module on i.MX6SLL EVK board to make backlight driver really work with LCD panel connected. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index bc8d155cbfbc..cc5cf5e666fd 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -213,6 +213,12 @@ }; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -381,4 +387,10 @@ MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 >; }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 + >; + }; }; -- cgit v1.2.3 From e449d3780368364507b19524f8c660dc0409c053 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 13 Jul 2018 15:58:26 +0800 Subject: ARM: dts: imx6sll-evk: correct lcd regulator GPIO pin On i.MX6SLL EVK board, lcd regulator is controlled by GPIO4 IO03 using MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 pin, NOT MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08, correct it. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index cc5cf5e666fd..41e87e626926 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -74,7 +74,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_lcd>; regulator-name = "lcd-pwr"; - gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -289,7 +289,7 @@ pinctrl_reg_lcd: reglcdgrp { fsl,pins = < - MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x17059 + MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 >; }; -- cgit v1.2.3 From 0ad26ef12f570e79871b9be9528ce4bb4ed173d1 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 13 Jul 2018 15:58:27 +0800 Subject: ARM: dts: imx6sll-evk: enable SEIKO 43WVF1G lcdif panel Enable SEIKO 43WVF1G lcdif panel for DRM driver, add necessary properties according to SEIKO 43WVF1G driver's requirement, such as "dvdd-supply", "avdd-supply" and "backlight" etc.. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 76 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 71 insertions(+), 5 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 41e87e626926..dc34da511c9c 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -23,7 +23,7 @@ reg = <0x80000000 0x80000000>; }; - backlight { + backlight_display: backlight-display { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -69,15 +69,22 @@ regulator-boot-on; }; - reg_lcd: regulator-lcd { + reg_lcd_3v3: regulator-lcd-3v3 { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcd>; - regulator-name = "lcd-pwr"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; + regulator-name = "lcd-3v3"; gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; enable-active-high; }; + reg_lcd_5v: regulator-lcd-5v { + compatible = "regulator-fixed"; + regulator-name = "lcd-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -99,6 +106,19 @@ gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&backlight_display>; + dvdd-supply = <®_lcd_3v3>; + avdd-supply = <®_lcd_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; }; &cpu0 { @@ -213,6 +233,18 @@ }; }; +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; @@ -287,7 +319,7 @@ >; }; - pinctrl_reg_lcd: reglcdgrp { + pinctrl_reg_lcd_3v3: reglcd3v3grp { fsl,pins = < MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 >; @@ -388,6 +420,40 @@ >; }; + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 + MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 + MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 + MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 + MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 + MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 + MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 + MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 + MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 + MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 + MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 + MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 + >; + }; + pinctrl_pwm1: pmw1grp { fsl,pins = < MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 -- cgit v1.2.3 From 282706a681634d5e42cfa4dde909be931d4105a4 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Fri, 13 Jul 2018 12:39:35 +0300 Subject: ARM: dts: imx6sl: Add vivante gpu nodes The imx6sl soc has gpu_2d and gpu_vg, no 3d support: etnaviv-gpu 2200000.gpu: model: GC320, revision: 5007 etnaviv-gpu 2204000.gpu: model: GC355, revision: 1215 The IP blocks seem to be already supported. Signed-off-by: Leonard Crestez Reviewed-by: Lucas Stach Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index a6b5ca48298f..7a4f5dace902 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -949,5 +949,25 @@ status = "disabled"; }; }; + + gpu_2d: gpu@2200000 { + compatible = "vivante,gc"; + reg = <0x02200000 0x4000>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "bus", "core"; + power-domains = <&pd_pu>; + }; + + gpu_vg: gpu@2204000 { + compatible = "vivante,gc"; + reg = <0x02204000 0x4000>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "bus", "core"; + power-domains = <&pd_pu>; + }; }; }; -- cgit v1.2.3 From 3221ceeede8af762d823fe7a9ae7883f89e4dfb2 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Fri, 13 Jul 2018 14:49:02 +0200 Subject: ARM: dts: imx: Switch Boundary Devices boards to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Gary Bisson Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-nit6xlite.dts | 38 +------------------------- arch/arm/boot/dts/imx6dl-nitrogen6x.dts | 38 +------------------------- arch/arm/boot/dts/imx6q-nitrogen6_max.dts | 38 +------------------------- arch/arm/boot/dts/imx6q-nitrogen6_som2.dts | 38 +------------------------- arch/arm/boot/dts/imx6q-nitrogen6x.dts | 38 +------------------------- arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 38 +------------------------- arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 38 +------------------------- arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 38 +------------------------- arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 38 +------------------------- arch/arm/boot/dts/imx6qp-nitrogen6_max.dts | 39 +-------------------------- arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts | 39 +-------------------------- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 38 +------------------------- arch/arm/boot/dts/imx7d-nitrogen7.dts | 39 +-------------------------- 13 files changed, 13 insertions(+), 484 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6dl-nit6xlite.dts b/arch/arm/boot/dts/imx6dl-nit6xlite.dts index 30ce2c0cec2b..61fa30991d67 100644 --- a/arch/arm/boot/dts/imx6dl-nit6xlite.dts +++ b/arch/arm/boot/dts/imx6dl-nit6xlite.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts index ec53d7a09572..ef58d3b0ea0d 100644 --- a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts +++ b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2013 Boundary Devices, Inc. * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts b/arch/arm/boot/dts/imx6q-nitrogen6_max.dts index 2a3c44f98eed..03bec0c53063 100644 --- a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts +++ b/arch/arm/boot/dts/imx6q-nitrogen6_max.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts index c5d59baa1a07..eb4eecb6ed22 100644 --- a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts +++ b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x.dts b/arch/arm/boot/dts/imx6q-nitrogen6x.dts index df8ff397a914..435445a34ad0 100644 --- a/arch/arm/boot/dts/imx6q-nitrogen6x.dts +++ b/arch/arm/boot/dts/imx6q-nitrogen6x.dts @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2013 Boundary Devices, Inc. * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index aef4a756ca81..29baf25ae5d0 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include #include diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index 9cb464b65be1..39200e5dc896 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include #include diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index 5e4da6d6fcff..572abd7499b1 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include #include diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index a14872436c5e..98384a6c5d12 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2013 Boundary Devices, Inc. * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include #include diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts b/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts index a39b86036581..741d1ed338ca 100644 --- a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts +++ b/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts index 011726c836cd..1593ac86b2a4 100644 --- a/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts +++ b/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2017 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index 59e52f504922..f81ddfa46ace 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright (C) 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index 70c53e50b2fc..9c6a3fdfcf78 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; -- cgit v1.2.3 From ac270caa1c420cc57ad2ba37679c2cf52c450781 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Fri, 13 Jul 2018 14:49:03 +0200 Subject: ARM: dts: imx7d-nitrogen7: use OF graph to describe the display To make use of the new eLCDIF DRM driver OF graph description is required. Describe the display using OF graph nodes. Signed-off-by: Gary Bisson Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-nitrogen7.dts | 48 +++++++++++------------------------ 1 file changed, 15 insertions(+), 33 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index 9c6a3fdfcf78..d8aac4a2d02a 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -11,11 +11,6 @@ model = "Boundary Devices i.MX7 Nitrogen7 Board"; compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d"; - aliases { - fb-lcd = &lcdif; - t-lcd = &t_lcd; - }; - memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -28,7 +23,7 @@ default-on; }; - backlight-j20 { + backlight_lcd: backlight-j20 { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -36,6 +31,17 @@ status = "okay"; }; + panel-lcd { + compatible = "okaya,rs800480t-7x0gp"; + backlight = <&backlight_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; @@ -280,35 +286,11 @@ }; &lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - lcd-supply = <®_vref_3v3>; - display = <&display0>; status = "okay"; - display0: lcd-display { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&t_lcd>; - t_lcd: t_lcd_default { - /* default to Okaya display */ - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <48>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + port { + lcdif_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; -- cgit v1.2.3 From 2da6b9ce6a634773d22f157461d1119cd69e2672 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Fri, 13 Jul 2018 14:49:04 +0200 Subject: ARM: dts: imx6sx-nitrogen6sx: remove obsolete display configuration This display configuration isn't working as-is as it depends on the tfp410 LCD to HDMI bridge. This will need to be updated later once the DRM MXSFB driver will be the default. Signed-off-by: Gary Bisson Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 71 -------------------------------- 1 file changed, 71 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index f81ddfa46ace..adb5cc7d8ce2 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -11,11 +11,6 @@ model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board"; compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx"; - aliases { - fb-lcd = &lcdif1; - t-lcd = &t_lcd; - }; - memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -225,38 +220,6 @@ status = "okay"; }; -&lcdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif1>; - lcd-supply = <®_3p3v>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&t_lcd>; - t_lcd: t_lcd_default { - clock-frequency = <74160000>; - hactive = <1280>; - vactive = <720>; - hback-porch = <220>; - hfront-porch = <110>; - vback-porch = <20>; - vfront-porch = <5>; - hsync-len = <40>; - vsync-len = <5>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; @@ -488,40 +451,6 @@ >; }; - pinctrl_lcdif1: lcdif1grp { - fsl,pins = < - MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 - MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 - MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 - MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 - MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 - MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 - MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 - MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 - MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 - MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 - MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 - MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 - MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 - MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 - MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 - MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 - MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 - MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 - MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 - MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 - MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 - MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 - MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 - MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 - MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 - MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 - MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 - >; - }; - pinctrl_pcie: pciegrp { fsl,pins = < MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0 -- cgit v1.2.3 From a1a30f892894ff27b747a04d032fee72ade1bdca Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Fri, 13 Jul 2018 10:30:04 -0700 Subject: ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config Instead of relying on default values, configure PAD_AUD3_BB_CK to be a GPIO explicitly. While at, it change the pad configuration to enable a 100K pull-down (the pin is used as IRQ_TYPE_LEVEL_HIGH). Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Lunn Reviewed-by: Andrew Lunn Signed-off-by: Andrey Smirnov Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index 07bc5fc05076..a7ede537e12a 100644 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -221,6 +221,8 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; ports { #address-cells = <1>; @@ -426,6 +428,12 @@ >; }; + pinctrl_switch: switchgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 -- cgit v1.2.3 From 129e96672f03cfd0181a0fb65446d61d05c2aa58 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 17 Jul 2018 14:44:38 +0800 Subject: ARM: dts: imx51-zii-scu3-esb: Fix RAVE SP watchdog compatible string It looks like I made a nasty typo in the original patch which resulted in missing watchdog device. Fix it. Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Lunn Signed-off-by: Andrey Smirnov Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index a7ede537e12a..e6ebac8f43e4 100644 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -325,7 +325,7 @@ #size-cells = <1>; watchdog { - compatible = "zii,rave-sp-watchodg-legacy"; + compatible = "zii,rave-sp-watchdog-legacy"; }; eeprom@a4 { -- cgit v1.2.3 From 929d1b09cae21da94a1829f0f3032152f6ec0784 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Sat, 14 Jul 2018 09:53:58 +0800 Subject: ARM: dts: imx6sl-evk: add missing GPIO iomux setting On i.MX6SL EVK board, the MX6SL_PAD_KEY_ROW5 pin is used as lcd 3v3 regulator control pin, need to make sure MX6SL_PAD_KEY_ROW5 is muxed as GPIO function for controlling lcd 3v3 regulator. Signed-off-by: Anson Huang Reviewed-by; Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-evk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 50bdc65670a3..046cfabc37e5 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -77,6 +77,8 @@ reg_lcd_3v3: regulator-lcd-3v3 { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; regulator-name = "lcd-3v3"; gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; enable-active-high; @@ -410,6 +412,12 @@ >; }; + pinctrl_reg_lcd_3v3: reglcd3v3grp { + fsl,pins = < + MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 -- cgit v1.2.3 From bb3e3fbbac862fa72951283e3632e1cf21a68223 Mon Sep 17 00:00:00 2001 From: Neeraj Dantu Date: Fri, 13 Jul 2018 16:33:14 +0000 Subject: ARM: dts: Add DT support for Octavo Systems OSD3358-SM-RED based on TI AM335x OSD3358-SM-RED is a dev board for OSD335x System-in-Package(SiP) devices from Octavo Systems. This board family can be indentified by the A335BNLTOS00 in the at24 eeprom: A2: [aa 55 33 ee 41 33 33 35 42 4e 4c 54 4f 53 30 30 |.U3.A335BNLTOS00|] https://octavosystems.com/octavo_products/osd3358-sm-red/ Signed-off-by: Neeraj Dantu CC: Tony Lindgren CC: Robert Nelson CC: Jason Kridner Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/am335x-osd3358-sm-red.dts | 457 ++++++++++++++++++++++++++++ 2 files changed, 459 insertions(+), 1 deletion(-) create mode 100755 arch/arm/boot/dts/am335x-osd3358-sm-red.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..d1ff69c68165 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -698,7 +698,8 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-shc.dtb \ am335x-sbc-t335.dtb \ am335x-sl50.dtb \ - am335x-wega-rdk.dtb + am335x-wega-rdk.dtb \ + am335x-osd3358-sm-red.dtb dtb-$(CONFIG_ARCH_OMAP4) += \ omap4-droid4-xt894.dtb \ omap4-duovero-parlor.dtb \ diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts new file mode 100755 index 000000000000..4d969013f99a --- /dev/null +++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts @@ -0,0 +1,457 @@ +//SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2018 Octavo Systems LLC - http://www.octavosystems.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-osd335x-common.dtsi" +#include + +#include + +/ { + model = "Octavo Systems OSD3358-SM-RED"; + compatible = "oct,osd3358-sm-refdesign", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&am33xx_pinmux { + nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + + nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + >; + }; + + mcasp0_pins: mcasp0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + >; + }; + + flash_enable: flash-enable { + pinctrl-single,pins = < + AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ + >; + }; + + imu_interrupt: imu-interrupt { + pinctrl-single,pins = < + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_rx_er.gpio3_2 */ + >; + }; + + ethernet_interrupt: ethernet-interrupt{ + pinctrl-single,pins = < + AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_col.gpio3_0 */ + >; + }; +}; + +&lcdc { + status = "okay"; + + /* If you want to get 24 bit RGB and 16 BGR mode instead of + * current 16 bit RGB and 24 BGR modes, set the propety + * below to "crossed" and uncomment the video-ports -property + * in tda19988 node. + * AM335x errata for wiring: + * http://www.ti.com/lit/er/sprz360i/sprz360i.pdf + */ + + blue-and-red-wiring = "straight"; + + port { + lcdc_0: endpoint { + remote-endpoint = <&hdmi_0>; + }; + }; +}; + +&i2c0 { + tda19988: hdmi-encoder@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + + /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ + /* video-ports = <0x234501>; */ + + #sound-dai-cells = <0>; + audio-ports = < TDA998x_I2S 0x03>; + + port { + hdmi_0: endpoint { + remote-endpoint = <&lcdc_0>; + }; + }; + }; + + mpu9250: imu@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + interrupt-parent = <&gpio3>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + ax8975@c { + compatible = "ak,ak8975"; + reg = <0x0c>; + }; + }; + /*invensense,int_config = <0x10>; + invensense,level_shifter = <0>; + invensense,orientation = [01 00 00 00 01 00 00 00 01]; + invensense,sec_slave_type = <0>; + invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89];*/ + }; + + bmp280: pressure@78 { + compatible = "bosch,bmp280"; + reg = <0x76>; + }; +}; + +&rtc { + system-power-controller; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +/ { + clk_mcasp0_fixed: clk-mcasp0-fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + clk_mcasp0: clk-mcasp0 { + #clock-cells = <0>; + compatible = "gpio-gate-clock"; + clocks = <&clk_mcasp0_fixed>; + enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "TI BeagleBone Black"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + dailink0_master: simple-audio-card,cpu { + sound-dai = <&mcasp0>; + clocks = <&clk_mcasp0>; + }; + + simple-audio-card,codec { + sound-dai = <&tda19988>; + }; + }; + + chosen { + stdout-path = &uart0; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led2 { + label = "beaglebone:green:usr0"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led3 { + label = "beaglebone:green:usr1"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led4 { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led5 { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + user_leds_s0: user-leds-s0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; + + i2c2_pins: pinmux-i2c2-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + >; + }; + + uart0_pins: pinmux-uart0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux-clkout2-pin { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw-default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_txd3 */ + AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_txd2 */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ + AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_txclk */ + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rxclk */ + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */ + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw-sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins: pinmux-mmc1-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ + >; + }; + + emmc_pins: pinmux-emmc-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; +}; + + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; + interrupts-extended = <&intc 18 &tps 0>; + interrupt-names = "mc", "vbus"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <4>; + phy-mode = "rgmii-txid"; +}; + +&mac { + slaves = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&mmc1 { + status = "okay"; + bus-width = <0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&rtc { + clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; +}; -- cgit v1.2.3 From 9896b67eaf4b72b31481aa17266790d28c9c0a6c Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 17 Jul 2018 13:12:02 +0800 Subject: ARM: dts: imx6qdl-sabresd: make pfuze100 sw4 always on On i.MX6QDL Sabre-SD board, pfuze100 sw4 supplies GPS, touch and RGMII etc., these modules do NOT implement power domain control, so pfuze100 sw4 needs to be always on to make sure these modules work normally. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 15744ad52535..6e46a195b399 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -341,6 +341,7 @@ sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { -- cgit v1.2.3 From 4de4238133f439790c3abd41523ae44dba826bd8 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 17 Jul 2018 13:12:03 +0800 Subject: ARM: dts: imx6sx-sdb-reva: make pfuze100 sw4 always on On i.MX6SX SDB Rev-A board, pfuze100 sw4 supplies csi, audio codec and i2c etc., these modules do NOT implement power domain control, so pfuze100 sw4 needs to be always on to make sure these modules work normally. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sdb-reva.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index e3533e74ccc8..9cc6ff206aea 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -63,6 +63,7 @@ sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { -- cgit v1.2.3 From 2afad1be58098e3f661428a0a70060f935f0b5dc Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 17 Jul 2018 13:12:04 +0800 Subject: ARM: dts: imx6sll-evk: make pfuze100 sw4 always on On i.MX6SLL EVK board, pfuze100 sw4 supplies LPDDR3 which is critical for system, must be always on. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index dc34da511c9c..c8e115564ba2 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -177,6 +177,7 @@ sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { -- cgit v1.2.3 From 0982a24f2401d8ac89e4694a21af3c118354f6ef Mon Sep 17 00:00:00 2001 From: Robin Gong Date: Tue, 17 Jul 2018 13:12:05 +0800 Subject: ARM: dts: imx6sl-evk: make pfuze100 sw4 always on On i.MX6SL EVK board, pfuze100 sw4 supplies LPDDR2 which is critical for system, must be always on. Signed-off-by: Robin Gong Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-evk.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 046cfabc37e5..679b4482ab13 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -201,6 +201,7 @@ sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { -- cgit v1.2.3 From 25cd17a2360ee285a314e55affcfb0d7fa6aac0d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 16 Jul 2018 23:08:45 -0300 Subject: ARM: dts: imx6ul-pico-hobbit: Do not hardcode the memory size There are two variants of imx6ul-pico boards: one with 256MB and another one with 512MB of RAM. Do not hardcode the memory size in the device tree and let the bootloader fill the correct value instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-pico-hobbit.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 47682b8c023c..0c09420f9951 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -51,8 +51,9 @@ model = "Technexion Pico i.MX6UL Board"; compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; + /* Will be filled by the bootloader */ memory@80000000 { - reg = <0x80000000 0x10000000>; + reg = <0x80000000 0>; }; chosen { -- cgit v1.2.3 From 91f6278bfa3966529c61808bd3cb8f05d7ed5dc6 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Tue, 17 Jul 2018 08:51:49 +0200 Subject: ARM: dts: am335x: add am335x-sancloud-bbe board support The "Beaglebone Enhanced" by Sancloud is based on the Beaglebone Black, but with the following differences: * Gigabit capable PHY * Extra USB hub, optional i2c control * lps3331ap barometer connected over i2c * MPU6050 6 axis MEMS accelerometer/gyro connected over i2c * 1GiB DDR3 RAM * RTL8723 Wifi/Bluetooth connected over USB Tested on a revision G board. Signed-off-by: Koen Kooi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am335x-sancloud-bbe.dts | 136 ++++++++++++++++++++++++++++++ 2 files changed, 137 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-sancloud-bbe.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d1ff69c68165..06e4e228d721 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -695,6 +695,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-pepper.dtb \ am335x-phycore-rdk.dtb \ am335x-pocketbeagle.dtb \ + am335x-sancloud-bbe.dtb \ am335x-shc.dtb \ am335x-sbc-t335.dtb \ am335x-sl50.dtb \ diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts new file mode 100644 index 000000000000..7b8e7417a11e --- /dev/null +++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include + +/ { + model = "SanCloud BeagleBone Enhanced"; + compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + usb_hub_ctrl: usb_hub_ctrl { + pinctrl-single,pins = < + AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLUP | MUX_MODE7) /* rmii1_refclk.gpio0_29 */ + >; + }; + + mpu6050_pins: pinmux_mpu6050_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE7) /* uart0_ctsn.gpio1_8 */ + >; + }; + + lps3331ap_pins: pinmux_lps3331ap_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */ + >; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rgmii-txid"; +}; + +&i2c0 { + lps331ap: barometer@5c { + compatible = "st,lps331ap-press"; + st,drdy-int-pin = <1>; + reg = <0x5c>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; + }; + + mpu6050: accelerometer@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + interrupt-parent = <&gpio0>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + orientation = <0xff 0 0 0 1 0 0 0 0xff>; + }; + + usb2512b: usb-hub@2c { + compatible = "microchip,usb2512b"; + reg = <0x2c>; + reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + /* wifi on port 4 */ + }; +}; -- cgit v1.2.3 From 22a001e8544fa9d89a1d3d7491ca1d8f9466b69d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 14 Jul 2018 11:45:56 +0200 Subject: ARM: dts: Add ethernet and switch to D-Link DIR-685 This adds the Ethernet and Realtek switch device to the D-Link DIR-685 Gemini-based device. Signed-off-by: Linus Walleij Signed-off-by: David S. Miller --- arch/arm/boot/dts/gemini-dlink-dir-685.dts | 140 ++++++++++++++++++++++++++++- 1 file changed, 139 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index fb5c954ab95a..6f258b50eb44 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -156,6 +156,100 @@ }; }; + /* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */ + switch { + compatible = "realtek,rtl8366rb"; + /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ + mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + realtek,disable-leds; + + switch_intc: interrupt-controller { + /* GPIO 15 provides the interrupt */ + interrupt-parent = <&gpio0>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-handle = <&phy0>; + }; + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&phy1>; + }; + port@2 { + reg = <2>; + label = "lan2"; + phy-handle = <&phy2>; + }; + port@3 { + reg = <3>; + label = "lan3"; + phy-handle = <&phy3>; + }; + port@4 { + reg = <4>; + label = "wan"; + phy-handle = <&phy4>; + }; + rtl8366rb_cpu_port: port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + }; + + mdio { + compatible = "realtek,smi-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: phy@0 { + reg = <0>; + interrupt-parent = <&switch_intc>; + interrupts = <0>; + }; + phy1: phy@1 { + reg = <1>; + interrupt-parent = <&switch_intc>; + interrupts = <1>; + }; + phy2: phy@2 { + reg = <2>; + interrupt-parent = <&switch_intc>; + interrupts = <2>; + }; + phy3: phy@3 { + reg = <3>; + interrupt-parent = <&switch_intc>; + interrupts = <3>; + }; + phy4: phy@4 { + reg = <4>; + interrupt-parent = <&switch_intc>; + interrupts = <12>; + }; + }; + }; + soc { flash@30000000 { /* @@ -223,10 +317,12 @@ * gpio0bgrp cover line 7 used by WPS LED * gpio0cgrp cover line 8, 13 used by keys * and 11, 12 used by the HD LEDs + * and line 14, 15 used by RTL8366 + * RESET and phy ready * gpio0egrp cover line 16 used by VDISP * gpio0fgrp cover line 17 used by TK IRQ * gpio0ggrp cover line 20 used by panel CS - * gpio0hgrp cover line 21,22 used by RTL8366RB + * gpio0hgrp cover line 21,22 used by RTL8366RB MDIO */ gpio0_default_pins: pinctrl-gpio0 { mux { @@ -250,6 +346,32 @@ groups = "gpio1bgrp"; }; }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp"; + }; + conf0 { + pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV", + "Y7 GMAC0 RXC", "Y11 GMAC1 RXC", + "T8 GMAC0 TXEN", "W11 GMAC1 TXEN", + "U8 GMAC0 TXC", "V11 GMAC1 TXC", + "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", + "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", + "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", + "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", + "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", + "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", + "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", + "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; + skew-delay = <7>; + }; + /* Set up drive strength on GMAC0 to 16 mA */ + conf1 { + groups = "gmii_gmac0_grp"; + drive-strength = <16>; + }; + }; }; }; @@ -291,6 +413,22 @@ <0x6000 0 0 4 &pci_intc 2>; }; + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; + ata@63000000 { status = "okay"; }; -- cgit v1.2.3 From a2df75ab0aba98daf7fa4828cf8a669c636c6382 Mon Sep 17 00:00:00 2001 From: Lei YU Date: Wed, 9 May 2018 17:35:59 +0800 Subject: ARM: dts: aspeed: Use 24MHz fixed clock for pwm The aspeed pwm driver always sets the clock source to 24MHz, specify the fixed clock in device tree to make sure the driver is using the correct clock frequency to calculate the fan speed. Signed-off-by: Lei YU Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 2 +- arch/arm/boot/dts/aspeed-g5.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 54524564037c..680336ac06f8 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -240,7 +240,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x1e786000 0x1000>; - clocks = <&syscon ASPEED_CLK_APB>; + clocks = <&syscon ASPEED_CLK_24M>; resets = <&syscon ASPEED_RESET_PWM>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 6274d3eaf374..02e70ad3ab70 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -299,7 +299,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x1e786000 0x1000>; - clocks = <&syscon ASPEED_CLK_APB>; + clocks = <&syscon ASPEED_CLK_24M>; resets = <&syscon ASPEED_RESET_PWM>; status = "disabled"; }; -- cgit v1.2.3 From 38dc27c85e642cd6229f3a4b2c85128501852158 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:01:51 +0530 Subject: ARM: dts: uniphier: Add missing cooling device properties for CPUs The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-pxs2.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 641d96119d4f..e2d1a22c5950 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -36,6 +36,7 @@ enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -46,6 +47,7 @@ enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -56,6 +58,7 @@ enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; }; }; -- cgit v1.2.3 From 56962b44a59a870b665dfa31f549fb37995a7624 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 16 Jul 2018 21:06:51 -0700 Subject: ARM: dts: vf610: Add ZII SSMB SPU3 board Add support for Zodiac Inflight Innovations SSMB SPU3 board (VF610-based). Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrew Lunn Signed-off-by: Andrey Smirnov Tested-by: Chris Healy Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 343 ++++++++++++++++++++++++++++++ 2 files changed, 345 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d459e2330307..6e25bae58492 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -577,7 +577,8 @@ dtb-$(CONFIG_SOC_VF610) += \ vf610m4-cosmic.dtb \ vf610-twr.dtb \ vf610-zii-dev-rev-b.dtb \ - vf610-zii-dev-rev-c.dtb + vf610-zii-dev-rev-c.dtb \ + vf610-zii-ssmb-spu3.dtb dtb-$(CONFIG_ARCH_MXS) += \ imx23-evk.dtb \ imx23-olinuxino.dtb \ diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts new file mode 100644 index 000000000000..b692117d7839 --- /dev/null +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Device tree file for ZII's SSMB SPU3 board + * + * SSMB - SPU3 Switch Management Board + * SPU - Seat Power Unit + * + * Copyright (C) 2015, 2016 Zodiac Inflight Innovations + * + * Based on an original 'vf610-twr.dts' which is Copyright 2015, + * Freescale Semiconductor, Inc. + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 SSMB SPU3 Board"; + compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + max-brightness = <1>; + }; + }; + + reg_vcc_3v3_mcu: regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + /* + * Some SPU3s come with SPI-NOR chip DNPed, so we leave this + * node disabled by default and rely on bootloader to enable + * it when appropriate. + */ + status = "disabled"; + + m25p128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partition@0 { + label = "m25p128-0"; + reg = <0x0 0x01000000>; + }; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom-length = <65536>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_1"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_1000_2"; + }; + + port@3 { + reg = <3>; + label = "eth_cu_1000_3"; + }; + + port@4 { + reg = <4>; + label = "eth_cu_1000_4"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_5"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_6"; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + gpio6: pca9505@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + at24c04@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "nameplate"; + }; + + at24c04@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + fsl,pins = < + VF610_PAD_PTE2__GPIO_107 0x31c2 + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB23__UART1_TX 0x21a2 + VF610_PAD_PTB24__UART1_RX 0x21a1 + >; + }; +}; -- cgit v1.2.3 From ea8f1d7af608a333989ef60cbe9d1edd84fe6080 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 17 Jul 2018 14:55:24 +0530 Subject: ARM: dts: imx6dl-mamoj: Add parallel display support This patch adds parallel display support for i.MX6DL Mamoj board along with relevant backlight through pwm. LCD power sequence is added by 'Michael Trimarchi'. Signed-off-by: Simone CIANNI Signed-off-by: Raffaele RECALCATI Signed-off-by: Michael Trimarchi Signed-off-by: Jagan Teki Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-mamoj.dts | 185 +++++++++++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/imx6dl-mamoj.dts index 6b2d29138bed..38e94fd11a3f 100644 --- a/arch/arm/boot/dts/imx6dl-mamoj.dts +++ b/arch/arm/boot/dts/imx6dl-mamoj.dts @@ -6,11 +6,133 @@ /dts-v1/; +#include #include "imx6dl.dtsi" / { model = "BTicino i.MX6DL Mamoj board"; compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl"; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */ + brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>; + default-brightness-level = <7>; + }; + + display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel-lcd { + compatible = "rocktech,rk070er9427"; + backlight = <&backlight_lcd>; + power-supply = <®_lcd_lr>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_lcd_3v3: regulator-lcd-dvdd { + compatible = "regulator-fixed"; + regulator-name = "lcd-dvdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 1 0>; + enable-active-high; + startup-delay-us = <21000>; + }; + + reg_lcd_power: regulator-lcd-power { + compatible = "regulator-fixed"; + regulator-name = "lcd-enable"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 6 0>; + enable-active-high; + vin-supply = <®_lcd_3v3>; + }; + + reg_lcd_vgl: regulator-lcd-vgl { + compatible = "regulator-fixed"; + regulator-name = "lcd-vgl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + startup-delay-us = <6000>; + enable-active-high; + vin-supply = <®_lcd_power>; + }; + + reg_lcd_vgh: regulator-lcd-vgh { + compatible = "regulator-fixed"; + regulator-name = "lcd-vgh"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <6000>; + enable-active-high; + vin-supply = <®_lcd_avdd>; + }; + + reg_lcd_vcom: regulator-lcd-vcom { + compatible = "regulator-fixed"; + regulator-name = "lcd-vcom"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; + startup-delay-us = <11000>; + enable-active-high; + vin-supply = <®_lcd_vgh>; + }; + + reg_lcd_lr: regulator-lcd-lr { + compatible = "regulator-fixed"; + regulator-name = "lcd-lr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_lcd_vcom>; + }; + + reg_lcd_avdd: regulator-lcd-avdd { + compatible = "regulator-fixed"; + regulator-name = "lcd-avdd"; + regulator-min-microvolt = <10280000>; + regulator-max-microvolt = <10280000>; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + startup-delay-us = <6000>; + enable-active-high; + vin-supply = <®_lcd_vgl>; + }; }; &fec { @@ -147,6 +269,16 @@ }; }; +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; @@ -200,6 +332,59 @@ >; }; + pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */ + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */ + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */ + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x40013058 /* EN_LCD33V */ + MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x4001b0b0 /* EN_AVDD */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x40013058 /* ENVGH */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x40013058 /* ENVGL */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x40013058 /* LCD_POWER */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x40013058 /* EN_VCOM_LCD */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x40013058 /* LCD_L_R */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x40013058 /* LCD_U_D */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 -- cgit v1.2.3 From faed0d59c587615fb01b3729d03aea83b00ac1c2 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 17 Jul 2018 14:55:25 +0530 Subject: ARM: dts: imx6dl-mamoj: Add Wifi support Add TI WL18XX Wifi for BTicino i.MX6DL board. Signed-off-by: Simone CIANNI Signed-off-by: Raffaele RECALCATI Signed-off-by: Michael Trimarchi Signed-off-by: Jagan Teki Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-mamoj.dts | 53 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/imx6dl-mamoj.dts index 38e94fd11a3f..530cb20ccc86 100644 --- a/arch/arm/boot/dts/imx6dl-mamoj.dts +++ b/arch/arm/boot/dts/imx6dl-mamoj.dts @@ -133,6 +133,18 @@ enable-active-high; vin-supply = <®_lcd_vgl>; }; + + reg_wl18xx_vmmc: regulator-wl18xx-vmcc { + compatible = "regulator-fixed"; + regulator-name = "vwl1807"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; }; &fec { @@ -285,6 +297,30 @@ status = "okay"; }; +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + vmmc-supply = <®_wl18xx_vmmc>; + no-1-8-v; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + tcxo-clock-frequency = <26000000>; + }; +}; + &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -392,6 +428,17 @@ >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10079 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -406,4 +453,10 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 >; }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x4001b0b0 + >; + }; }; -- cgit v1.2.3 From af1cab82109c31a41a3d24bafea9e1e9bcd0f981 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Tue, 17 Jul 2018 14:55:26 +0530 Subject: ARM: dts: imx6dl-mamoj: Add usb host and device support Add USB host and device support for BTicino i.MX6DL Mamoj board. Signed-off-by: Simone CIANNI Signed-off-by: Raffaele RECALCATI Signed-off-by: Michael Trimarchi Signed-off-by: Jagan Teki Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-mamoj.dts | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/imx6dl-mamoj.dts index 530cb20ccc86..df8607fe4142 100644 --- a/arch/arm/boot/dts/imx6dl-mamoj.dts +++ b/arch/arm/boot/dts/imx6dl-mamoj.dts @@ -134,6 +134,17 @@ vin-supply = <®_lcd_vgl>; }; + reg_usb_host: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbhost-vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhost>; + regulator-min-microvolt = <50000000>; + regulator-max-microvolt = <50000000>; + gpio = <&gpio6 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_wl18xx_vmmc: regulator-wl18xx-vmcc { compatible = "regulator-fixed"; regulator-name = "vwl1807"; @@ -297,6 +308,16 @@ status = "okay"; }; +&usbh1 { + vbus-supply = <®_usb_host>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -428,6 +449,12 @@ >; }; + pinctrl_usbhost: usbhostgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069 -- cgit v1.2.3 From c998911f525a53ca932f30717716bbb78e83a4ec Mon Sep 17 00:00:00 2001 From: Anton Gerasimov Date: Wed, 28 Mar 2018 16:17:34 +0200 Subject: ARM: dts: zynq: Add support for Z-turn board Add a dts for MYIR Z-turn board and respective target in Makefile. Signed-off-by: Anton Gerasimov Signed-off-by: Michal Simek --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zynq-zturn.dts | 116 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 117 insertions(+) create mode 100644 arch/arm/boot/dts/zynq-zturn.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..1fa68c7eed11 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1109,6 +1109,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb \ zynq-zed.dtb \ + zynq-zturn.dtb \ zynq-zybo.dtb \ zynq-zybo-z7.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/zynq-zturn.dts new file mode 100644 index 000000000000..b25beaed874d --- /dev/null +++ b/arch/arm/boot/dts/zynq-zturn.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 Andrea Merello + * Copyright (C) 2017 Alexander Graf + * + * Based on zynq-zed.dts which is: + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Zynq Z-Turn MYIR Board"; + compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + serial1 = &uart0; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + usr-led1 { + label = "usr-led1"; + gpios = <&gpio0 0x0 0x1>; + default-state = "off"; + }; + + usr-led2 { + label = "usr-led2"; + gpios = <&gpio0 0x9 0x1>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + K1 { + label = "K1"; + gpios = <&gpio0 0x32 0x1>; + linux,code = <0x66>; + gpio-key,wakeup; + autorepeat; + }; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0x0>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&can0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + stlm75@49 { + status = "okay"; + compatible = "lm75"; + reg = <0x49>; + }; + + accelerometer@53 { + compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; + reg = <0x53>; + interrupt-parent = <&intc>; + interrupts = <0x0 0x1e 0x4>; + }; +}; -- cgit v1.2.3 From 025ba1841e5de5d5a0980cafee8a93a87332d112 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Apr 2016 11:23:34 +0200 Subject: ARM: dts: zynq: Add mmc alias for zc702/zc706/zed/zybo Add missing mmc alias. Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-zc702.dts | 1 + arch/arm/boot/dts/zynq-zc706.dts | 1 + arch/arm/boot/dts/zynq-zed.dts | 1 + arch/arm/boot/dts/zynq-zybo.dts | 1 + 4 files changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index f2330b0cb63d..e7a5eec7a5b0 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -14,6 +14,7 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + mmc0 = &sdhci0; }; memory@0 { diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index 3ad1260ff2a1..552741a847ba 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -14,6 +14,7 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + mmc0 = &sdhci0; }; memory@0 { diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index 53c6883ce1f6..252153913a15 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -13,6 +13,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + mmc0 = &sdhci0; }; memory@0 { diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts index a6c00e7fa767..db9ddc71ea3a 100644 --- a/arch/arm/boot/dts/zynq-zybo.dts +++ b/arch/arm/boot/dts/zynq-zybo.dts @@ -13,6 +13,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + mmc0 = &sdhci0; }; memory@0 { -- cgit v1.2.3 From ef4c422d167afcd15c8bae1f841ef59334c1f973 Mon Sep 17 00:00:00 2001 From: Luis Araneda Date: Thu, 12 Jul 2018 00:10:19 -0400 Subject: ARM: dts: zynq: Set correct manufacturer for ZedBoard and MicroZed boards Both boards are made by Avnet, Inc. So add an additional value to the compatible property Signed-off-by: Luis Araneda Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-microzed.dts | 2 +- arch/arm/boot/dts/zynq-zed.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/zynq-microzed.dts index aa4a0b6defb8..574ef2276182 100644 --- a/arch/arm/boot/dts/zynq-microzed.dts +++ b/arch/arm/boot/dts/zynq-microzed.dts @@ -8,7 +8,7 @@ / { model = "Zynq MicroZED Development Board"; - compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; + compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index 252153913a15..cd9300906726 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -8,7 +8,7 @@ / { model = "Zynq Zed Development Board"; - compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; + compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; -- cgit v1.2.3 From 28432332457b9f9380b8d85a9cd3adae2a59f469 Mon Sep 17 00:00:00 2001 From: Luis Araneda Date: Thu, 12 Jul 2018 00:10:20 -0400 Subject: ARM: dts: zynq: correct and improve the model property of dt files Replace the current value of the model property by a more accurate description of each board (which includes the manufacturer), as some of the boards had the same value ("Xilinx Zynq") Signed-off-by: Luis Araneda Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-cc108.dts | 2 +- arch/arm/boot/dts/zynq-microzed.dts | 2 +- arch/arm/boot/dts/zynq-parallella.dts | 2 +- arch/arm/boot/dts/zynq-zc702.dts | 2 +- arch/arm/boot/dts/zynq-zc706.dts | 2 +- arch/arm/boot/dts/zynq-zc770-xm010.dts | 2 +- arch/arm/boot/dts/zynq-zc770-xm011.dts | 2 +- arch/arm/boot/dts/zynq-zc770-xm012.dts | 2 +- arch/arm/boot/dts/zynq-zc770-xm013.dts | 2 +- arch/arm/boot/dts/zynq-zed.dts | 2 +- arch/arm/boot/dts/zynq-zybo-z7.dts | 2 +- arch/arm/boot/dts/zynq-zybo.dts | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/zynq-cc108.dts b/arch/arm/boot/dts/zynq-cc108.dts index 1a0f631c1d8d..8b9ab9bba23b 100644 --- a/arch/arm/boot/dts/zynq-cc108.dts +++ b/arch/arm/boot/dts/zynq-cc108.dts @@ -12,8 +12,8 @@ /include/ "zynq-7000.dtsi" / { + model = "Xilinx CC108 board"; compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { ethernet0 = &gem0; diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/zynq-microzed.dts index 574ef2276182..6ed84fb15902 100644 --- a/arch/arm/boot/dts/zynq-microzed.dts +++ b/arch/arm/boot/dts/zynq-microzed.dts @@ -7,7 +7,7 @@ /include/ "zynq-7000.dtsi" / { - model = "Zynq MicroZED Development Board"; + model = "Avnet MicroZed board"; compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; aliases { diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts index c05f4b67d4c1..54592aeb92b9 100644 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ b/arch/arm/boot/dts/zynq-parallella.dts @@ -12,7 +12,7 @@ /include/ "zynq-7000.dtsi" / { - model = "Adapteva Parallella Board"; + model = "Adapteva Parallella board"; compatible = "adapteva,parallella", "xlnx,zynq-7000"; aliases { diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index e7a5eec7a5b0..6653e34409cd 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -7,7 +7,7 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC702 Development Board"; + model = "Xilinx ZC702 board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; aliases { diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index 552741a847ba..77943c16d33f 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -7,7 +7,7 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC706 Development Board"; + model = "Xilinx ZC706 board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; aliases { diff --git a/arch/arm/boot/dts/zynq-zc770-xm010.dts b/arch/arm/boot/dts/zynq-zc770-xm010.dts index 6884f1ad66b7..0e1bfdd3421f 100644 --- a/arch/arm/boot/dts/zynq-zc770-xm010.dts +++ b/arch/arm/boot/dts/zynq-zc770-xm010.dts @@ -8,8 +8,8 @@ #include "zynq-7000.dtsi" / { + model = "Xilinx ZC770 XM010 board"; compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { ethernet0 = &gem0; diff --git a/arch/arm/boot/dts/zynq-zc770-xm011.dts b/arch/arm/boot/dts/zynq-zc770-xm011.dts index b78883cee96a..b7f65862c022 100644 --- a/arch/arm/boot/dts/zynq-zc770-xm011.dts +++ b/arch/arm/boot/dts/zynq-zc770-xm011.dts @@ -8,8 +8,8 @@ #include "zynq-7000.dtsi" / { + model = "Xilinx ZC770 XM011 board"; compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { i2c0 = &i2c1; diff --git a/arch/arm/boot/dts/zynq-zc770-xm012.dts b/arch/arm/boot/dts/zynq-zc770-xm012.dts index c3169d63600d..d2359b789eb8 100644 --- a/arch/arm/boot/dts/zynq-zc770-xm012.dts +++ b/arch/arm/boot/dts/zynq-zc770-xm012.dts @@ -8,8 +8,8 @@ #include "zynq-7000.dtsi" / { + model = "Xilinx ZC770 XM012 board"; compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { i2c0 = &i2c0; diff --git a/arch/arm/boot/dts/zynq-zc770-xm013.dts b/arch/arm/boot/dts/zynq-zc770-xm013.dts index 8bb66859d774..651913f1afa2 100644 --- a/arch/arm/boot/dts/zynq-zc770-xm013.dts +++ b/arch/arm/boot/dts/zynq-zc770-xm013.dts @@ -8,8 +8,8 @@ #include "zynq-7000.dtsi" / { + model = "Xilinx ZC770 XM013 board"; compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { ethernet0 = &gem1; diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index cd9300906726..6a5a93aa6552 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -7,7 +7,7 @@ #include "zynq-7000.dtsi" / { - model = "Zynq Zed Development Board"; + model = "Avnet ZedBoard board"; compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000"; aliases { diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/zynq-zybo-z7.dts index 1e713dc98920..be40be9b7222 100644 --- a/arch/arm/boot/dts/zynq-zybo-z7.dts +++ b/arch/arm/boot/dts/zynq-zybo-z7.dts @@ -3,7 +3,7 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZYBO Z7 Development Board"; + model = "Digilent Zybo Z7 board"; compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000"; aliases { diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts index db9ddc71ea3a..755f6f109d5a 100644 --- a/arch/arm/boot/dts/zynq-zybo.dts +++ b/arch/arm/boot/dts/zynq-zybo.dts @@ -7,7 +7,7 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZYBO Development Board"; + model = "Digilent Zybo board"; compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; aliases { -- cgit v1.2.3 From 7d90ca6f19199a54d3f8417c5f36c50dfa0accc8 Mon Sep 17 00:00:00 2001 From: Luis Araneda Date: Thu, 12 Jul 2018 01:50:46 -0400 Subject: ARM: dts: zynq: Fix memory size on the Zybo Z7 board According to the reference manual, the board has two Micron MT41K256M16HA-125 DDR3L memory ICs, which have 512 MiB each Tested on a ZYBO-Z7-20 board Signed-off-by: Luis Araneda Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-zybo-z7.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/zynq-zybo-z7.dts index be40be9b7222..ea67afbe8335 100644 --- a/arch/arm/boot/dts/zynq-zybo-z7.dts +++ b/arch/arm/boot/dts/zynq-zybo-z7.dts @@ -13,7 +13,7 @@ memory@0 { device_type = "memory"; - reg = <0x0 0x20000000>; + reg = <0x0 0x40000000>; }; chosen { -- cgit v1.2.3 From edd62b9a98be2d60ff990874e488ba25a80280d0 Mon Sep 17 00:00:00 2001 From: Luis Araneda Date: Thu, 12 Jul 2018 01:50:47 -0400 Subject: ARM: dts: zynq: Use gpio constants for the Zybo Z7 board Include GPIO dt-bindings and use GPIO_ACTIVE_* constants to improve readability Signed-off-by: Luis Araneda Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-zybo-z7.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/zynq-zybo-z7.dts index ea67afbe8335..7f19b767e991 100644 --- a/arch/arm/boot/dts/zynq-zybo-z7.dts +++ b/arch/arm/boot/dts/zynq-zybo-z7.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /dts-v1/; #include "zynq-7000.dtsi" +#include / { model = "Digilent Zybo Z7 board"; @@ -24,7 +25,7 @@ usb_phy0: phy0 { #phy-cells = <0>; compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio0 46 1>; + reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; }; }; -- cgit v1.2.3 From a2b7baf4abee17b28a4fff3d16575217da75cfa9 Mon Sep 17 00:00:00 2001 From: Luis Araneda Date: Thu, 12 Jul 2018 01:50:48 -0400 Subject: ARM: dts: zynq: Add LEDs to the Zybo Z7 board Add an LED node, connected to the Processing System (PS) Signed-off-by: Luis Araneda Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-zybo-z7.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/zynq-zybo-z7.dts index 7f19b767e991..357b78a5c11b 100644 --- a/arch/arm/boot/dts/zynq-zybo-z7.dts +++ b/arch/arm/boot/dts/zynq-zybo-z7.dts @@ -22,6 +22,15 @@ stdout-path = "serial0:115200n8"; }; + gpio-leds { + compatible = "gpio-leds"; + + ld4 { + label = "zynq-zybo-z7:green:ld4"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + }; + usb_phy0: phy0 { #phy-cells = <0>; compatible = "usb-nop-xceiv"; -- cgit v1.2.3 From 9153bf9fb5290cd91deefa99f2983a851f2ca5da Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 17 Jul 2018 16:53:32 +0200 Subject: ARM: dts: zynq: Remove #address/#size-cells from gpio-keys dts reports incorrect usage of these properties in gpio-keys node. Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary The patch is removing these useless properties. Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-zc702.dts | 2 -- arch/arm/boot/dts/zynq-zturn.dts | 2 -- 2 files changed, 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 6653e34409cd..cc5a3dc2b4a0 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -29,8 +29,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; sw14 { label = "sw14"; diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/zynq-zturn.dts index b25beaed874d..b38704657960 100644 --- a/arch/arm/boot/dts/zynq-zturn.dts +++ b/arch/arm/boot/dts/zynq-zturn.dts @@ -49,8 +49,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; K1 { label = "K1"; -- cgit v1.2.3 From b689ea74a671be3fb32cbe228626bfee6fbdf02e Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 18 Jul 2018 11:40:39 +0000 Subject: ARM: dts: sun8i: a83t: Remove unused address-cells/size-cells of dwmac-sun8i ddress-cells/size-cells is unnecessary for dwmac-sun8i node. It was in early days, but since a mdio node is used, it could be removed. This patch fix the following DT warning: Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 2be23d600957..00a02b037320 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -902,8 +902,6 @@ reset-names = "stmmaceth"; clocks = <&ccu 27>; clock-names = "stmmaceth"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; mdio: mdio { -- cgit v1.2.3 From 24770a3160662be1161bc1255d36a963d84a0b0b Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 18 Jul 2018 11:40:40 +0000 Subject: ARM: dts: sun8i: r40: Remove unused address-cells/size-cells of dwmac-sun8i address-cells/size-cells is unnecessary for dwmac-sun8i node. It was in early days, but since a mdio node is used, it could be removed. This patch fix the following DT warning: Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index e2cbd4f645c5..ffd9f00f74a4 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -539,8 +539,6 @@ reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_GMAC>; clock-names = "stmmaceth"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; gmac_mdio: mdio { -- cgit v1.2.3 From 8fb147322a8fdec96852d537affe9623d307edfb Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 18 Jul 2018 11:40:38 +0000 Subject: ARM: dts: sunxi-h3-h5: Remove unused address-cells/size-cells of dwmac-sun8i address-cells/size-cells is unnecessary for dwmac-sun8i node. It was in early days, but since a mdio node is used, it could be removed. This patch fix the following DT warning: Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index c3bff1105e5d..fc6131315c47 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -506,8 +506,6 @@ reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; mdio: mdio { -- cgit v1.2.3 From d1ed755dde8f14921deeb0cb0257ba8905dfc9fa Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 11 Jul 2018 11:25:08 +0200 Subject: ARM: dts: sun5i: Fix the SRAM A3-A4 declaration According to the system control bindings, the A3-A4 SRAM node should be a child node of the SRAM it belongs to. However, it was introduced at the same level, therefore breaking the binding. Fix this. Fixes: 85870196258f ("ARM: sun5i: a13: Merge common controllers into the common DTSI") Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 40e4dc293f14..8bfb36651177 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -127,13 +127,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00000000 0xc000>; - }; - emac_sram: sram-section@8000 { - compatible = "allwinner,sun5i-a13-sram-a3-a4", - "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; + emac_sram: sram-section@8000 { + compatible = "allwinner,sun5i-a13-sram-a3-a4", + "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "disabled"; + }; }; sram_d: sram@10000 { -- cgit v1.2.3 From fc37204432d218409400b1cf6abd4a650bd987eb Mon Sep 17 00:00:00 2001 From: Ben Whitten Date: Fri, 15 Jun 2018 14:40:51 +0100 Subject: ARM: dts: at91: add labels to soc dtsi for derivative boards This adds labels to commonly used device-tree nodes so that derivative boards can avoid ahb/apb hierarchy. Signed-off-by: Ben Whitten Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9x5.dtsi | 8 ++++---- arch/arm/boot/dts/sama5d3.dtsi | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index a3c3c3128148..11c0ef102ab1 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -389,13 +389,13 @@ }; }; - rstc@fffffe00 { + reset_controller: rstc@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; }; - shdwc@fffffe10 { + shutdown_controller: shdwc@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; @@ -470,7 +470,7 @@ clock-names = "dma_clk"; }; - pinctrl@fffff400 { + pinctrl: pinctrl@fffff400 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; @@ -1206,7 +1206,7 @@ }; }; - watchdog@fffffe40 { + watchdog: watchdog@fffffe40 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index eae5e1ee9cd8..1408fa4a62e4 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -494,7 +494,7 @@ atmel,external-irqs = <47>; }; - pinctrl@fffff200 { + pinctrl: pinctrl@fffff200 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; @@ -1340,13 +1340,13 @@ }; }; - rstc@fffffe00 { + reset_controller: rstc@fffffe00 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; }; - shutdown-controller@fffffe10 { + shutdown_controller: shutdown-controller@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; @@ -1359,7 +1359,7 @@ clocks = <&mck>; }; - watchdog@fffffe40 { + watchdog: watchdog@fffffe40 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; -- cgit v1.2.3 From 044565558639ebcd6bc6bc7dd97001792e43a671 Mon Sep 17 00:00:00 2001 From: Ben Whitten Date: Fri, 15 Jun 2018 14:40:52 +0100 Subject: ARM: dts: add support for Laird WB45N cpu module and DVK This adds support for Lairds combo CPU module, featuring on board Atheros wifi, CSR Bluetooth radio and, Atmel CPU. https://www.lairdtech.com/products/wb45nbt Signed-off-by: Ben Whitten Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/at91-wb45n.dts | 64 +++++++++++++++ arch/arm/boot/dts/at91-wb45n.dtsi | 165 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 230 insertions(+) create mode 100644 arch/arm/boot/dts/at91-wb45n.dts create mode 100644 arch/arm/boot/dts/at91-wb45n.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..8544fd0b398d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -38,6 +38,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ at91-ariettag25.dtb \ at91-cosino_mega2560.dtb \ at91-kizboxmini.dtb \ + at91-wb45n.dtb \ at91sam9g15ek.dtb \ at91sam9g25ek.dtb \ at91sam9g35ek.dtb \ diff --git a/arch/arm/boot/dts/at91-wb45n.dts b/arch/arm/boot/dts/at91-wb45n.dts new file mode 100644 index 000000000000..5b9512a6c89c --- /dev/null +++ b/arch/arm/boot/dts/at91-wb45n.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-wb45n.dts - Device Tree file for WB45NBT board + * + * Copyright (C) 2018 Laird + * + */ +/dts-v1/; +#include "at91-wb45n.dtsi" + +/ { + model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; + compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + irqbtn@18 { + reg = <18>; + label = "IRQBTN"; + linux,code = <99>; + gpios = <&pioB 18 GPIO_ACTIVE_LOW>; + gpio-key,wakeup = <1>; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&macb0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&usart0 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/at91-wb45n.dtsi b/arch/arm/boot/dts/at91-wb45n.dtsi new file mode 100644 index 000000000000..ebe61a25ca96 --- /dev/null +++ b/arch/arm/boot/dts/at91-wb45n.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-wb45n.dtsi - Device Tree file for WB45NBT board + * + * Copyright (C) 2018 Laird + * + */ + +#include "at91sam9g25.dtsi" + +/ { + model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; + compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + atheros { + compatible = "atheros,ath6kl"; + atheros,board-id = "SD32"; + }; +}; + +&reset_controller { + compatible = "atmel,sama5d3-rstc"; +}; + +&shutdown_controller { + atmel,wakeup-mode = "low"; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&ebi { + status = "okay"; + nand_controller: nand-controller { + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb &pinctrl_nand_oe_we>; + pinctrl-names = "default"; + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bs"; + reg = <0x0 0x20000>; + }; + + uboot@20000 { + label = "u-boot"; + reg = <0x20000 0x80000>; + }; + + ubootenv@a0000 { + label = "u-boot-env"; + reg = <0xa0000 0x20000>; + }; + + ubootenv@c0000 { + label = "redund-env"; + reg = <0xc0000 0x20000>; + }; + + kernel-a@e0000 { + label = "kernel-a"; + reg = <0xe0000 0x280000>; + }; + + kernel-b@360000 { + label = "kernel-b"; + reg = <0x360000 0x280000>; + }; + + rootfs-a@5e0000 { + label = "rootfs-a"; + reg = <0x5e0000 0x2600000>; + }; + + rootfs-b@2be0000 { + label = "rootfs-b"; + reg = <0x2be0000 0x2600000>; + }; + + user@51e0000 { + label = "user"; + reg = <0x51e0000 0x2dc0000>; + }; + + logs@7fa0000 { + label = "logs"; + reg = <0x7fa0000 0x60000>; + }; + + }; + }; + }; +}; + +&usb0 { + num-ports = <2>; + atmel,vbus-gpio = < + &pioB 12 GPIO_ACTIVE_HIGH + &pioA 31 GPIO_ACTIVE_HIGH + >; + atmel,oc-gpio = <&pioB 13 GPIO_ACTIVE_LOW>; +}; + +&macb0 { + phy-mode = "rmii"; +}; + +&spi0 { + cs-gpios = <&pioA 14 0>, <&pioA 7 0>, <0>, <0>; +}; + +&usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_board_usb2>; + atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; +}; + +&mmc0 { + pinctrl-0 = < + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&pinctrl { + usb2 { + pinctrl_board_usb2: usb2-board { + atmel,pins = + ; /* PB11 gpio vbus sense, deglitch */ + }; + }; +}; + -- cgit v1.2.3 From e8274426b4b770123ee5bf3a3d5fc5f9c89cee66 Mon Sep 17 00:00:00 2001 From: Ben Whitten Date: Fri, 15 Jun 2018 14:40:53 +0100 Subject: ARM: dts: add support for Laird WB50N cpu module and DVK This adds support for Lairds CPU module, featuring Atheros wifi, CSR Bluetooth and, Atmel SAMA5D3 CPU. https://www.lairdtech.com/products/wb50nbt-wi-fi-bluetooth-module Signed-off-by: Ben Whitten Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/at91-wb50n.dts | 112 +++++++++++++++++++++ arch/arm/boot/dts/at91-wb50n.dtsi | 198 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 311 insertions(+) create mode 100644 arch/arm/boot/dts/at91-wb50n.dts create mode 100644 arch/arm/boot/dts/at91-wb50n.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8544fd0b398d..f39aa108e102 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -52,6 +52,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d2_xplained.dtb \ at91-sama5d3_xplained.dtb \ at91-tse850-3.dtb \ + at91-wb50n.dtb \ sama5d31ek.dtb \ sama5d33ek.dtb \ sama5d34ek.dtb \ diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts new file mode 100644 index 000000000000..8cecc7051a86 --- /dev/null +++ b/arch/arm/boot/dts/at91-wb50n.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-wb50n.dts - Device Tree file for wb50n evaluation board + * + * Copyright (C) 2018 Laird + * + */ + +/dts-v1/; +#include "at91-wb50n.dtsi" + +/ { + model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; + compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + btn0@10 { + reg = <10>; + label = "BTNESC"; + linux,code = <1>; /* ESC button */ + gpios = <&pioA 10 GPIO_ACTIVE_LOW>; + gpio-key,wakeup = <1>; + }; + + irqbtn@31 { + reg = <31>; + label = "IRQBTN"; + linux,code = <99>; /* SysReq button */ + gpios = <&pioE 31 GPIO_ACTIVE_LOW>; + gpio-key,wakeup = <1>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "wb50n:blue:led0"; + gpios = <&pioA 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led1 { + label = "wb50n:green:led1"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + label = "wb50n:red:led2"; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&mmc0 { + status = "okay"; +}; + +&macb1 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +/* On BB40 this port is labeled UART1 */ +&usart0 { + status = "okay"; +}; + +/* On BB40 this port is labeled UART0 */ +&usart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <8000000>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/at91-wb50n.dtsi b/arch/arm/boot/dts/at91-wb50n.dtsi new file mode 100644 index 000000000000..85692c8ef2b1 --- /dev/null +++ b/arch/arm/boot/dts/at91-wb50n.dtsi @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-wb50n.dtsi - Device Tree include file for wb50n cpu module + * + * Copyright (C) 2018 Laird + * + */ + +#include "sama5d31.dtsi" + +/ { + model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; + compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + chosen { + bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; +}; + +&pinctrl { + board { + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = ; /* PC26 GPIO with pullup deglitch */ + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = ; /* PB13 GPIO with deglitch */ + }; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&slow_osc { + atmel,osc-bypass; +}; + +&usart1_clk { + atmel,clk-output-range = <0 132000000>; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>; + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; + status = "okay"; + atheros@0 { + compatible = "atheros,ath6kl"; + atheros,board-id = "SD32"; + reg = <0>; + bus-width = <4>; + }; +}; + +&macb1 { + phy-mode = "rmii"; +}; + +&dbgu { + dmas = <0>, <0>; /* Do not use DMA for dbgu */ +}; + +/* On BB40 this port is labeled UART1 */ +&usart0 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; +}; + +/* On BB40 this port is labeled UART0 */ +&usart1 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + dtr-gpios = <&pioD 13 GPIO_ACTIVE_LOW>; + dsr-gpios = <&pioD 11 GPIO_ACTIVE_LOW>; + dcd-gpios = <&pioD 7 GPIO_ACTIVE_LOW>; + rng-gpios = <&pioD 8 GPIO_ACTIVE_LOW>; +}; + +/* USART3 is direct-connect to the Bluetooth UART on the radio SIP */ +&usart3 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>; + status = "okay"; +}; + +&spi1 { + cs-gpios = <&pioC 25 0>, <0>, <0>, <0>; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand: nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bs"; + reg = <0x0 0x20000>; + }; + + uboot@20000 { + label = "u-boot"; + reg = <0x20000 0x80000>; + }; + + ubootenv@a0000 { + label = "u-boot-env"; + reg = <0xa0000 0x20000>; + }; + + ubootenv@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x20000>; + }; + + kernel-a@e0000 { + label = "kernel-a"; + reg = <0xe0000 0x500000>; + }; + + kernel-b@5e0000 { + label = "kernel-b"; + reg = <0x5e0000 0x500000>; + }; + + rootfs-a@ae0000 { + label = "rootfs-a"; + reg = <0xae0000 0x3000000>; + }; + + rootfs-b@3ae0000 { + label = "rootfs-b"; + reg = <0x3ae0000 0x3000000>; + }; + + user@6ae0000 { + label = "user"; + reg = <0x6ae0000 0x14e0000>; + }; + }; + }; +}; + +&usb0 { + atmel,vbus-gpio = <&pioB 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; +}; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <&pioA 2 GPIO_ACTIVE_LOW>; + atmel,oc-gpio = <&pioA 4 GPIO_ACTIVE_LOW>; +}; -- cgit v1.2.3 From fd2c7ef94311791dd5cfbe9a099c96a9eedfab78 Mon Sep 17 00:00:00 2001 From: Ben Whitten Date: Fri, 15 Jun 2018 14:40:54 +0100 Subject: ARM: dts: add support for Gatwick board based on WB50N Add support for the LoRa gateway from Laird, the RG1xx. This board houses the WB50NBT CPU module along with a Semtech SX1301 based concentrator card. https://www.lairdtech.com/products/rg1xx-lora-gateway Signed-off-by: Ben Whitten Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/at91-gatwick.dts | 121 +++++++++++++++++++++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/arm/boot/dts/at91-gatwick.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f39aa108e102..adb48a10ae08 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ at91-sama5d3_xplained.dtb \ + at91-gatwick.dtb \ at91-tse850-3.dtb \ at91-wb50n.dtb \ sama5d31ek.dtb \ diff --git a/arch/arm/boot/dts/at91-gatwick.dts b/arch/arm/boot/dts/at91-gatwick.dts new file mode 100644 index 000000000000..5a81cab5fc3a --- /dev/null +++ b/arch/arm/boot/dts/at91-gatwick.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-gatwick.dts - Device Tree file for the Gatwick board + * + * Copyright (C) 2018 Laird + * + */ +/dts-v1/; +#include "at91-wb50n.dtsi" +#include + +/ { + model = "Laird Workgroup Bridge 50N - Project Gatwick"; + compatible = "laird,gatwick", "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + gpio_keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&pioE 31 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + ethernet { + label = "gatwick:yellow:ethernet"; + gpios = <&pioA 10 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + wifi { + label = "gatwick:green:wifi"; + gpios = <&pioA 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + ble { + label = "gatwick:blue:ble"; + gpios = <&pioA 22 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + lora { + label = "gatwick:orange:lora"; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + blank { + label = "gatwick:green:blank"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + user { + label = "gatwick:yellow:user"; + gpios = <&pioA 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&pinctrl { + board { + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; /* PE31 GPIO with pullup deglitch */ + }; + }; +}; + +&mmc0 { + status = "okay"; +}; + +&macb1 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +/* FTDI USART */ +&usart0 { + status = "okay"; +}; + +/* GPS USART */ +&usart1 { + pinctrl-0 = <&pinctrl_usart1>; + status = "okay"; +}; + +&spi1 { + status = "okay"; + + spidev@0 { + compatible = "semtech,sx1301"; + reg = <0>; + spi-max-frequency = <8000000>; + }; +}; + +&usb1 { + status = "okay"; + /delete-property/atmel,oc-gpio; +}; + +&usb2 { + status = "okay"; +}; -- cgit v1.2.3 From ef8375bea216a91194d0aac041d5c38a5db089ce Mon Sep 17 00:00:00 2001 From: Ben Whitten Date: Fri, 15 Jun 2018 14:40:55 +0100 Subject: ARM: dts: add support for Laird SOM60 module and DVK boards This adds support for Lairds upcoming SOM module, featuring Marvell WiFi and Bluetooth, 2Gb NAND / 1Gb LPDDR SDRAM, and an Atmel SAMA5D3 CPU. Signed-off-by: Ben Whitten Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/at91-dvk_som60.dts | 95 +++++++++++ arch/arm/boot/dts/at91-dvk_su60_somc.dtsi | 159 ++++++++++++++++++ arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi | 90 ++++++++++ arch/arm/boot/dts/at91-som60.dtsi | 230 ++++++++++++++++++++++++++ 5 files changed, 575 insertions(+) create mode 100644 arch/arm/boot/dts/at91-dvk_som60.dts create mode 100644 arch/arm/boot/dts/at91-dvk_su60_somc.dtsi create mode 100644 arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi create mode 100644 arch/arm/boot/dts/at91-som60.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index adb48a10ae08..b9c0d9d00a6e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ at91-sama5d3_xplained.dtb \ + at91-dvk_som60.dtb \ at91-gatwick.dtb \ at91-tse850-3.dtb \ at91-wb50n.dtb \ diff --git a/arch/arm/boot/dts/at91-dvk_som60.dts b/arch/arm/boot/dts/at91-dvk_som60.dts new file mode 100644 index 000000000000..ededd5b0d27b --- /dev/null +++ b/arch/arm/boot/dts/at91-dvk_som60.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-dvk_som60.dts - Device Tree file for the DVK SOM60 board + * + * Copyright (C) 2018 Laird, + * 2018 Ben Whitten + * + */ +/dts-v1/; +#include "at91-som60.dtsi" +#include "at91-dvk_su60_somc.dtsi" +#include "at91-dvk_su60_somc_lcm.dtsi" + +/ { + model = "Laird DVK SOM60"; + compatible = "laird,dvk-som60", "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = &dbgu; + tick-timer = &pit; + }; +}; + +&mmc0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&ssc0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&usart1 { + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&pit { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&macb0 { + status = "okay"; +}; + +&macb1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi new file mode 100644 index 000000000000..bb86f17ed5ed --- /dev/null +++ b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-dvk_su60_somc.dtsi - Device Tree file for the DVK SOM60 base board + * + * Copyright (C) 2018 Laird, + * 2018 Ben Whitten + * + */ + +/ { + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; + + atmel,model = "wm8904 @ DVK-SOM60"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + + status = "okay"; + }; +}; + +&mmc0 { + status = "okay"; + + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + slot@0 { + bus-width = <4>; + cd-gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; + cd-inverted; + }; +}; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */ + spi-flash@0 { + compatible = "mxicy,mx25u4035", "jedec,spi-nor"; + spi-max-frequency = <33000000>; + reg = <0>; + }; +}; + +&ssc0 { + atmel,clk-from-rk-pin; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + wm8904: wm8904@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pck2>; + clock-names = "mclk"; + }; +}; + +&i2c1 { + status = "okay"; + + eeprom@87 { + compatible = "giantec,gt24c32a", "atmel,24c32"; + reg = <87>; + pagesize = <32>; + }; +}; + +&usart1 { + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&pit { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&macb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@7 { + reg = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_geth_int>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; +}; + +&macb1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@1 { + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_int>; + interrupt-parent = <&pioC>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi new file mode 100644 index 000000000000..4b9176dc5d02 --- /dev/null +++ b/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-dvk_su60_somc_lcm.dtsi - Device Tree file for the DVK SOM60 LCD board + * + * Copyright (C) 2018 Laird, + * 2018 Ben Whitten + * + */ + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + panel: panel { + compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92", "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc_lcd_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + vcc_lcd_reg: fixedregulator_lcd { + compatible = "regulator-fixed"; + regulator-name = "VCC LCM"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + status = "okay"; + }; +}; + +&pinctrl { + board { + pinctrl_lcd_ctp_int: lcd_ctp_int { + atmel,pins = + ; + }; + }; +}; + +&i2c1 { + status = "okay"; + + ft5426@56 { + compatible = "focaltech,ft5426", "edt,edt-ft5406"; + reg = <56>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_ctp_int>; + + interrupt-parent = <&pioC>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&hlcdc { + status = "okay"; + + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + + port@0 { + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91-som60.dtsi b/arch/arm/boot/dts/at91-som60.dtsi new file mode 100644 index 000000000000..241682a207c5 --- /dev/null +++ b/arch/arm/boot/dts/at91-som60.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-som60.dtsi - Device Tree file for the SOM60 module + * + * Copyright (C) 2018 Laird, + * 2018 Ben Whitten + * + */ +#include "sama5d36.dtsi" + +/ { + model = "Laird SOM60"; + compatible = "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = &dbgu; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; +}; + +&pinctrl { + board { + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + ; + }; + + pinctrl_mmc0_en: mmc0_en { + atmel,pins = + ; + }; + + pinctrl_nand0_wp: nand0_wp { + atmel,pins = + ; + }; + + pinctrl_usb_vbus: usb_vbus { + atmel,pins = + ; + /* Conflicts with USART2_SCK */ + }; + + pinctrl_usart2_sck: usart2_sck { + atmel,pins = + ; + /* Conflicts with USB_VBUS */ + }; + + pinctrl_usb_oc: usb_oc { + atmel,pins = + ; + /* Conflicts with USART3_SCK */ + }; + + pinctrl_usart3_sck: usart3_sck { + atmel,pins = + ; + /* Conflicts with USB_OC */ + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; + }; + + pinctrl_geth_int: geth_int { + atmel,pins = + ; + /* Conflicts with USART1_SCK */ + }; + + pinctrl_usart1_sck: usart1_sck { + atmel,pins = + ; + /* Conflicts with GETH_INT */ + }; + + pinctrl_eth_int: eth_int { + atmel,pins = + ; + }; + + pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { + atmel,pins = + ; + }; + }; +}; + +&mmc0 { + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +&mmc1 { + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&spi0 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; +}; + +&usart0 { + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; +}; + +&usart1 { + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; +}; + +&usart2 { + pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts_cts>; +}; + +&usart3 { + pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>; +}; + +&adc0 { + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + >; +}; + +&macb0 { + phy-mode = "rgmii"; +}; + +&macb1 { + phy-mode = "rmii"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand: nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + ubootspl@0 { + label = "u-boot-spl"; + reg = <0x0 0x20000>; + }; + + uboot@20000 { + label = "u-boot"; + reg = <0x20000 0x80000>; + }; + + ubootenv@a0000 { + label = "u-boot-env"; + reg = <0xa0000 0x20000>; + }; + + ubootenv@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x20000>; + }; + + ubi@e0000 { + label = "ubi"; + reg = <0xe0000 0xfe00000>; + }; + }; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + atmel,vbus-gpio = <&pioC 14 GPIO_ACTIVE_HIGH>; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_vbus &pinctrl_usb_oc>; + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 20 GPIO_ACTIVE_HIGH + 0>; + atmel,oc-gpio = <0 + &pioE 15 GPIO_ACTIVE_LOW + 0>; +}; -- cgit v1.2.3 From c8cbc1c20c29697e7335a5044fe6c60aa5c6e922 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 17 Jul 2018 17:03:53 +0300 Subject: ARM: dts: at91: fix typos for SSC TD functions Fix typo for TD function of pins PIN_PB22 and PIN_PC14 Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/sama5d2-pinfunc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sama5d2-pinfunc.h b/arch/arm/boot/dts/sama5d2-pinfunc.h index e57191fb83de..1c01a6f843d8 100644 --- a/arch/arm/boot/dts/sama5d2-pinfunc.h +++ b/arch/arm/boot/dts/sama5d2-pinfunc.h @@ -375,7 +375,7 @@ #define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) #define PIN_PB22__LCDDAT11 PINMUX_PIN(PIN_PB22, 1, 1) #define PIN_PB22__A11 PINMUX_PIN(PIN_PB22, 2, 1) -#define PIN_PB22__TDO PINMUX_PIN(PIN_PB22, 3, 1) +#define PIN_PB22__TD0 PINMUX_PIN(PIN_PB22, 3, 1) #define PIN_PB22__TIOA2 PINMUX_PIN(PIN_PB22, 4, 2) #define PIN_PB22__FLEXCOM3_IO1 PINMUX_PIN(PIN_PB22, 5, 3) #define PIN_PB22__GMDC PINMUX_PIN(PIN_PB22, 6, 3) @@ -556,7 +556,7 @@ #define PIN_PC14__LCDDAT6 PINMUX_PIN(PIN_PC14, 1, 2) #define PIN_PC14__GRX0 PINMUX_PIN(PIN_PC14, 2, 1) #define PIN_PC14__ISC_D5 PINMUX_PIN(PIN_PC14, 3, 1) -#define PIN_PC14__TDO PINMUX_PIN(PIN_PC14, 5, 2) +#define PIN_PC14__TD0 PINMUX_PIN(PIN_PC14, 5, 2) #define PIN_PC14__A3 PINMUX_PIN(PIN_PC14, 6, 2) #define PIN_PC15 79 #define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) -- cgit v1.2.3 From 19fddda14765dc72b0a5ed9ce9ea5940587c6403 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 19 Jul 2018 12:57:24 -0700 Subject: ARM: dts: vf610: Add ZII CFU1 board Add support for the Zodiac Inflight Innovations CFU1 board (VF610-based). Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrew Lunn Signed-off-by: Andrey Smirnov Tested-by: Chris Healy Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/vf610-zii-cfu1.dts | 305 +++++++++++++++++++++++++++++++++++ 2 files changed, 306 insertions(+) create mode 100644 arch/arm/boot/dts/vf610-zii-cfu1.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6e25bae58492..1bb5a1d526eb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -576,6 +576,7 @@ dtb-$(CONFIG_SOC_VF610) += \ vf610-cosmic.dtb \ vf610m4-cosmic.dtb \ vf610-twr.dtb \ + vf610-zii-cfu1.dtb \ vf610-zii-dev-rev-b.dtb \ vf610-zii-dev-rev-c.dtb \ vf610-zii-ssmb-spu3.dtb diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts new file mode 100644 index 000000000000..37777cf22e67 --- /dev/null +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 CFU1 Board"; + compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + max-brightness = <1>; + }; + + led-fail { + label = "zii:red:fail"; + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + max-brightness = <1>; + }; + + led-status { + label = "zii:green:status"; + gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + max-brightness = <1>; + }; + + led-debug-a { + label = "zii:green:debug_a"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + max-brightness = <1>; + }; + + led-debug-b { + label = "zii:green:debug_b"; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + max-brightness = <1>; + }; + }; + + reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + status = "okay"; + + m25p128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partition@0 { + label = "m25p128-0"; + reg = <0x0 0x01000000>; + }; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6085"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + reg = <0>; + eeprom-length = <512>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "eth_cu_1000_1"; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_2"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_1000_3"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + pca9554@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + at24c04@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + label = "nvm"; + }; + + at24c04@54 { + compatible = "atmel,24c04"; + reg = <0x54>; + label = "nameplate"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30fe + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + VF610_PAD_PTE3__GPIO_108 0x31c2 + VF610_PAD_PTE4__GPIO_109 0x31c2 + VF610_PAD_PTE5__GPIO_110 0x31c2 + VF610_PAD_PTE6__GPIO_111 0x31c2 + >; + }; + + pinctrl_switch: switch-grp { + fsl,pins = < + VF610_PAD_PTB28__GPIO_98 0x3061 + VF610_PAD_PTE2__GPIO_107 0x1042 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; +}; -- cgit v1.2.3 From 55e20919709878d2391eab20252a0a0b9d1fe20a Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 19 Jul 2018 13:00:02 -0700 Subject: ARM: dts: vf610-zii-ssmb-spu3: Fix W=1 level warnings Fix a couple of things that were causing warning when building DTB with W=1. Cc: Fabio Estevam Cc: cphealy@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index b692117d7839..fe357668865b 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -23,7 +23,7 @@ stdout-path = &uart0; }; - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; @@ -128,8 +128,6 @@ compatible = "marvell,mv88e6190"; pinctrl-0 = <&pinctrl_gpio_switch0>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; reg = <0>; eeprom-length = <65536>; reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; -- cgit v1.2.3 From 33a8d5a595dd0f9b7f801c1cddb26dc05bc33a73 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 19 Jul 2018 16:24:19 +0800 Subject: ARM: dts: imx7d: remove "operating-points" property for cpu1 Commit b97872d4eb22 ("ARM: dts: imx: Add missing OPP properties for CPUs") added "operating-points" property for all CPUs, but i.MX7D already has "operating-points-v2" property on both CPUs, so no need to add "operating-points" property again, this patch removes it. Fixes: b97872d4eb22 ("ARM: dts: imx: Add missing OPP properties for CPUs") Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d.dtsi | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 9a772fc9e3b8..7cbc2ffa4b3a 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -18,11 +18,6 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; - operating-points = < - /* KHz uV */ - 996000 1075000 - 792000 975000 - >; clock-frequency = <996000000>; operating-points-v2 = <&cpu0_opp_table>; }; -- cgit v1.2.3 From 8f42cb7f64c7ffcb2168305ea6e9724cd82562ef Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 5 Jul 2018 23:04:31 -0700 Subject: ARM: dts: omap4: Add l4 interconnect hierarchy and ti-sysc data Let's add proper interconnect hierarchy for l4 interconnect instances with the related ti-sysc interconnect module data as documented in Documentation/devicetree/bindings/bus/ti-sysc.txt. Using ti-sysc driver binding allows us to start dropping legacy platform data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of ti-sysc dts data. For setting up a proper hierarchy for the interconnect and ti-sysc data, there are multiple reasons: 1. We can use dts ranges to protect registers from being ioremapped from other devices and prevent hard to track issues with failed flush of posted write between modules 2. Some of the ranges may not be accessible to operating systems at all if configured so on high-security devices 3. The interconnect hierarchy provides proper clockdomain hierarchy that can be used for genpd later on 4. We can avoid almost all deferred probe related issues simply by probing the resource providing interconnect instance first for l4 wkup instance 5. With deferred probe issues gone, we can probe everything later at module_init time except for system timer and interrupt controller and their clocks. This data is generated based on platform data from a booted system and the interconnect acces protection registers for ranges. To avoid regressions, we initially validate the device tree provided data against the existing platform data on boot. Each interconnect instance is typically divided into segments to avoid powering up the whole interconnect. And each segment has one or more ranges TI specific interconnect target modules connected to it. Some devices can also have a separate data access port directly to the parent L3 interconnect for DMA that can be set up as a separate range. Note that we cannot yet include this file from omap4.dtsi until child devices are moved to their proper locations in the interconnect hierarchy in the following patch. Otherwise we would have the each module probed twice. Also note that this does not yet add l4 abe instance, that will be added separately later on. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4.dtsi | 1817 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 1817 insertions(+) create mode 100644 arch/arm/boot/dts/omap4-l4.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi new file mode 100644 index 000000000000..3e756fde929d --- /dev/null +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -0,0 +1,1817 @@ +// SPDX-License-Identifier: GPL-2.0 +&l4_cfg { /* 0x4a000000 */ + compatible = "ti,omap4-l4-cfg", "simple-bus"; + reg = <0x4a000000 0x800>, + <0x4a000800 0x800>, + <0x4a001000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ + <0x00080000 0x4a080000 0x080000>, /* segment 1 */ + <0x00100000 0x4a100000 0x080000>, /* segment 2 */ + <0x00180000 0x4a180000 0x080000>, /* segment 3 */ + <0x00200000 0x4a200000 0x080000>, /* segment 4 */ + <0x00280000 0x4a280000 0x080000>, /* segment 5 */ + <0x00300000 0x4a300000 0x080000>; /* segment 6 */ + + segment@0 { /* 0x4a000000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00002000 0x00002000 0x001000>, /* ap 3 */ + <0x00003000 0x00003000 0x001000>, /* ap 4 */ + <0x00004000 0x00004000 0x001000>, /* ap 5 */ + <0x00005000 0x00005000 0x001000>, /* ap 6 */ + <0x00056000 0x00056000 0x001000>, /* ap 7 */ + <0x00057000 0x00057000 0x001000>, /* ap 8 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ + <0x00058000 0x00058000 0x004000>, /* ap 10 */ + <0x00062000 0x00062000 0x001000>, /* ap 11 */ + <0x00063000 0x00063000 0x001000>, /* ap 12 */ + <0x00008000 0x00008000 0x002000>, /* ap 23 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 24 */ + <0x00066000 0x00066000 0x001000>, /* ap 25 */ + <0x00067000 0x00067000 0x001000>, /* ap 26 */ + <0x0005e000 0x0005e000 0x002000>, /* ap 80 */ + <0x00060000 0x00060000 0x001000>, /* ap 81 */ + <0x00064000 0x00064000 0x001000>, /* ap 86 */ + <0x00065000 0x00065000 0x001000>; /* ap 87 */ + + target-module@2000 { /* 0x4a002000, ap 3 06.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "ctrl_module_core"; + reg = <0x2000 0x4>, + <0x2010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@4000 { /* 0x4a004000, ap 5 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@8000 { /* 0x4a008000, ap 23 32.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x2000>; + }; + + target-module@56000 { /* 0x4a056000, ap 7 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "dma_system"; + reg = <0x56000 0x4>, + <0x5602c 0x4>, + <0x56028 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */ + clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x56000 0x1000>; + }; + + target-module@58000 { /* 0x4a058000, ap 10 0e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "hsi"; + reg = <0x58000 0x4>, + <0x58010 0x4>, + <0x58014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x58000 0x4000>; + }; + + target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5e000 0x2000>; + }; + + target-module@62000 { /* 0x4a062000, ap 11 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "usb_tll_hs"; + reg = <0x62000 0x4>, + <0x62010 0x4>, + <0x62014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x62000 0x1000>; + }; + + target-module@64000 { /* 0x4a064000, ap 86 1e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "usb_host_hs"; + reg = <0x64000 0x4>, + <0x64010 0x4>, + <0x64014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x64000 0x1000>; + }; + + target-module@66000 { /* 0x4a066000, ap 25 26.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmu_dsp"; + reg = <0x66000 0x4>, + <0x66010 0x4>, + <0x66014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ + clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x66000 0x1000>; + }; + }; + + segment@80000 { /* 0x4a080000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ + <0x0005a000 0x000da000 0x001000>, /* ap 14 */ + <0x0005b000 0x000db000 0x001000>, /* ap 15 */ + <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ + <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ + <0x0005e000 0x000de000 0x001000>, /* ap 18 */ + <0x00060000 0x000e0000 0x001000>, /* ap 19 */ + <0x00061000 0x000e1000 0x001000>, /* ap 20 */ + <0x00074000 0x000f4000 0x001000>, /* ap 27 */ + <0x00075000 0x000f5000 0x001000>, /* ap 28 */ + <0x00076000 0x000f6000 0x001000>, /* ap 29 */ + <0x00077000 0x000f7000 0x001000>, /* ap 30 */ + <0x00036000 0x000b6000 0x001000>, /* ap 69 */ + <0x00037000 0x000b7000 0x001000>, /* ap 70 */ + <0x0004d000 0x000cd000 0x001000>, /* ap 78 */ + <0x0004e000 0x000ce000 0x001000>, /* ap 79 */ + <0x00029000 0x000a9000 0x001000>, /* ap 82 */ + <0x0002a000 0x000aa000 0x001000>, /* ap 83 */ + <0x0002b000 0x000ab000 0x001000>, /* ap 84 */ + <0x0002c000 0x000ac000 0x001000>, /* ap 85 */ + <0x0002d000 0x000ad000 0x001000>, /* ap 88 */ + <0x0002e000 0x000ae000 0x001000>; /* ap 89 */ + + target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x29000 0x1000>; + }; + + target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "usb_otg_hs"; + reg = <0x2b400 0x4>, + <0x2b404 0x4>, + <0x2b408 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2b000 0x1000>; + }; + + target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "ocp2scp_usb_phy"; + reg = <0x2d000 0x4>, + <0x2d010 0x4>, + <0x2d014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2d000 0x1000>; + }; + + target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + + target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4d000 0x1000>; + }; + + target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */ + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu"; + reg = <0x59038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + }; + + target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */ + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_iva"; + reg = <0x5b038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + }; + + target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */ + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; + reg = <0x5d038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + }; + + target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + }; + + target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox"; + reg = <0x74000 0x4>, + <0x74010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ + clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x74000 0x1000>; + }; + + target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spinlock"; + reg = <0x76000 0x4>, + <0x76010 0x4>, + <0x76014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ + clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x76000 0x1000>; + }; + }; + + segment@100000 { /* 0x4a100000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */ + <0x00001000 0x00101000 0x001000>, /* ap 22 */ + <0x00002000 0x00102000 0x001000>, /* ap 61 */ + <0x00003000 0x00103000 0x001000>, /* ap 62 */ + <0x00008000 0x00108000 0x001000>, /* ap 63 */ + <0x00009000 0x00109000 0x001000>, /* ap 64 */ + <0x0000a000 0x0010a000 0x001000>, /* ap 65 */ + <0x0000b000 0x0010b000 0x001000>; /* ap 66 */ + + target-module@0 { /* 0x4a100000, ap 21 2a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "ctrl_module_pad_core"; + reg = <0x0 0x4>, + <0x10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@2000 { /* 0x4a102000, ap 61 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@8000 { /* 0x4a108000, ap 63 62.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@a000 { /* 0x4a10a000, ap 65 50.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "fdif"; + reg = <0xa000 0x4>, + <0xa010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + ti,sysc-delay-us = <2>; + /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */ + clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + }; + + segment@180000 { /* 0x4a180000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; + + segment@200000 { /* 0x4a200000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */ + <0x0001f000 0x0021f000 0x001000>, /* ap 32 */ + <0x0000a000 0x0020a000 0x001000>, /* ap 33 */ + <0x0000b000 0x0020b000 0x001000>, /* ap 34 */ + <0x00004000 0x00204000 0x001000>, /* ap 35 */ + <0x00005000 0x00205000 0x001000>, /* ap 36 */ + <0x00006000 0x00206000 0x001000>, /* ap 37 */ + <0x00007000 0x00207000 0x001000>, /* ap 38 */ + <0x00012000 0x00212000 0x001000>, /* ap 39 */ + <0x00013000 0x00213000 0x001000>, /* ap 40 */ + <0x0000c000 0x0020c000 0x001000>, /* ap 41 */ + <0x0000d000 0x0020d000 0x001000>, /* ap 42 */ + <0x00010000 0x00210000 0x001000>, /* ap 43 */ + <0x00011000 0x00211000 0x001000>, /* ap 44 */ + <0x00016000 0x00216000 0x001000>, /* ap 45 */ + <0x00017000 0x00217000 0x001000>, /* ap 46 */ + <0x00014000 0x00214000 0x001000>, /* ap 47 */ + <0x00015000 0x00215000 0x001000>, /* ap 48 */ + <0x00018000 0x00218000 0x001000>, /* ap 49 */ + <0x00019000 0x00219000 0x001000>, /* ap 50 */ + <0x00020000 0x00220000 0x001000>, /* ap 51 */ + <0x00021000 0x00221000 0x001000>, /* ap 52 */ + <0x00026000 0x00226000 0x001000>, /* ap 53 */ + <0x00027000 0x00227000 0x001000>, /* ap 54 */ + <0x00028000 0x00228000 0x001000>, /* ap 55 */ + <0x00029000 0x00229000 0x001000>, /* ap 56 */ + <0x0002a000 0x0022a000 0x001000>, /* ap 57 */ + <0x0002b000 0x0022b000 0x001000>, /* ap 58 */ + <0x0001c000 0x0021c000 0x001000>, /* ap 59 */ + <0x0001d000 0x0021d000 0x001000>; /* ap 60 */ + + target-module@4000 { /* 0x4a204000, ap 35 42.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@6000 { /* 0x4a206000, ap 37 4a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x1000>; + }; + + target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@c000 { /* 0x4a20c000, ap 41 20.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + + target-module@10000 { /* 0x4a210000, ap 43 52.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x1000>; + }; + + target-module@12000 { /* 0x4a212000, ap 39 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x12000 0x1000>; + }; + + target-module@14000 { /* 0x4a214000, ap 47 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x14000 0x1000>; + }; + + target-module@16000 { /* 0x4a216000, ap 45 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x16000 0x1000>; + }; + + target-module@18000 { /* 0x4a218000, ap 49 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000 0x1000>; + }; + + target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1c000 0x1000>; + }; + + target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000 0x1000>; + }; + + target-module@20000 { /* 0x4a220000, ap 51 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@26000 { /* 0x4a226000, ap 53 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + }; + + target-module@28000 { /* 0x4a228000, ap 55 2e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>; + }; + + target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + }; + }; + + segment@280000 { /* 0x4a280000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; + + segment@300000 { /* 0x4a300000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ + <0x00040000 0x00340000 0x001000>, /* ap 68 */ + <0x00020000 0x00320000 0x004000>, /* ap 71 */ + <0x00024000 0x00324000 0x002000>, /* ap 72 */ + <0x00026000 0x00326000 0x001000>, /* ap 73 */ + <0x00027000 0x00327000 0x001000>, /* ap 74 */ + <0x00028000 0x00328000 0x001000>, /* ap 75 */ + <0x00029000 0x00329000 0x001000>, /* ap 76 */ + <0x00030000 0x00330000 0x010000>, /* ap 77 */ + <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ + <0x0002c000 0x0032c000 0x004000>; /* ap 91 */ + + target-module@0 { /* 0x4a300000, ap 67 14.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x00020000>, + <0x00020000 0x00020000 0x00004000>, + <0x00024000 0x00024000 0x00002000>, + <0x00026000 0x00026000 0x00001000>, + <0x00027000 0x00027000 0x00001000>, + <0x00028000 0x00028000 0x00001000>, + <0x00029000 0x00029000 0x00001000>, + <0x0002a000 0x0002a000 0x00002000>, + <0x0002c000 0x0002c000 0x00004000>, + <0x00030000 0x00030000 0x00010000>; + }; + }; +}; + +&l4_wkup { /* 0x4a300000 */ + compatible = "ti,omap4-l4-wkup", "simple-bus"; + reg = <0x4a300000 0x800>, + <0x4a300800 0x800>, + <0x4a301000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */ + <0x00010000 0x4a310000 0x010000>, /* segment 1 */ + <0x00020000 0x4a320000 0x010000>; /* segment 2 */ + + segment@0 { /* 0x4a300000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00006000 0x00006000 0x002000>, /* ap 3 */ + <0x00008000 0x00008000 0x001000>, /* ap 4 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ + <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ + <0x00004000 0x00004000 0x001000>, /* ap 17 */ + <0x00005000 0x00005000 0x001000>, /* ap 18 */ + <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ + <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ + + target-module@4000 { /* 0x4a304000, ap 17 24.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "counter_32k"; + reg = <0x4000 0x4>, + <0x4004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@6000 { /* 0x4a306000, ap 3 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x2000>; + }; + + target-module@a000 { /* 0x4a30a000, ap 15 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "ctrl_module_wkup"; + reg = <0xc000 0x4>, + <0xc010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + }; + + segment@10000 { /* 0x4a310000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ + <0x00001000 0x00011000 0x001000>, /* ap 6 */ + <0x00004000 0x00014000 0x001000>, /* ap 7 */ + <0x00005000 0x00015000 0x001000>, /* ap 8 */ + <0x00008000 0x00018000 0x001000>, /* ap 9 */ + <0x00009000 0x00019000 0x001000>, /* ap 10 */ + <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ + <0x0000d000 0x0001d000 0x001000>, /* ap 12 */ + <0x0000e000 0x0001e000 0x001000>, /* ap 21 */ + <0x0000f000 0x0001f000 0x001000>; /* ap 22 */ + + target-module@0 { /* 0x4a310000, ap 5 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio1"; + reg = <0x0 0x4>, + <0x10 0x4>, + <0x114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>, + <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@4000 { /* 0x4a314000, ap 7 18.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "wd_timer2"; + reg = <0x4000 0x4>, + <0x4010 0x4>, + <0x4014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + ti,hwmods = "timer1"; + reg = <0x8000 0x4>, + <0x8010 0x4>, + <0x8014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@c000 { /* 0x4a31c000, ap 11 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "kbd"; + reg = <0xc000 0x4>, + <0xc010 0x4>, + <0xc014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + + target-module@e000 { /* 0x4a31e000, ap 21 30.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "ctrl_module_pad_wkup"; + reg = <0xe000 0x4>, + <0xe010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe000 0x1000>; + }; + }; + + segment@20000 { /* 0x4a320000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ + <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ + <0x00000000 0x00020000 0x001000>, /* ap 23 */ + <0x00001000 0x00021000 0x001000>, /* ap 24 */ + <0x00002000 0x00022000 0x001000>, /* ap 25 */ + <0x00003000 0x00023000 0x001000>, /* ap 26 */ + <0x00004000 0x00024000 0x001000>, /* ap 27 */ + <0x00005000 0x00025000 0x001000>, /* ap 28 */ + <0x00007000 0x00027000 0x000400>, /* ap 29 */ + <0x00008000 0x00028000 0x000800>, /* ap 30 */ + <0x00009000 0x00029000 0x000400>; /* ap 31 */ + + target-module@0 { /* 0x4a320000, ap 23 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@2000 { /* 0x4a322000, ap 25 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@4000 { /* 0x4a324000, ap 27 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@6000 { /* 0x4a326000, ap 13 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00006000 0x00001000>, + <0x00001000 0x00007000 0x00000400>, + <0x00002000 0x00008000 0x00000800>, + <0x00003000 0x00009000 0x00000400>; + }; + }; +}; + +&l4_per { /* 0x48000000 */ + compatible = "ti,omap4-l4-per", "simple-bus"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ + <0x00200000 0x48200000 0x200000>; /* segment 1 */ + + segment@0 { /* 0x48000000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x000400>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00020000 0x00020000 0x001000>, /* ap 3 */ + <0x00021000 0x00021000 0x001000>, /* ap 4 */ + <0x00032000 0x00032000 0x001000>, /* ap 5 */ + <0x00033000 0x00033000 0x001000>, /* ap 6 */ + <0x00034000 0x00034000 0x001000>, /* ap 7 */ + <0x00035000 0x00035000 0x001000>, /* ap 8 */ + <0x00036000 0x00036000 0x001000>, /* ap 9 */ + <0x00037000 0x00037000 0x001000>, /* ap 10 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ + <0x00040000 0x00040000 0x010000>, /* ap 13 */ + <0x00050000 0x00050000 0x001000>, /* ap 14 */ + <0x00055000 0x00055000 0x001000>, /* ap 15 */ + <0x00056000 0x00056000 0x001000>, /* ap 16 */ + <0x00057000 0x00057000 0x001000>, /* ap 17 */ + <0x00058000 0x00058000 0x001000>, /* ap 18 */ + <0x00059000 0x00059000 0x001000>, /* ap 19 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 20 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 21 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 22 */ + <0x0005d000 0x0005d000 0x001000>, /* ap 23 */ + <0x0005e000 0x0005e000 0x001000>, /* ap 24 */ + <0x00060000 0x00060000 0x001000>, /* ap 25 */ + <0x0006a000 0x0006a000 0x001000>, /* ap 26 */ + <0x0006b000 0x0006b000 0x001000>, /* ap 27 */ + <0x0006c000 0x0006c000 0x001000>, /* ap 28 */ + <0x0006d000 0x0006d000 0x001000>, /* ap 29 */ + <0x0006e000 0x0006e000 0x001000>, /* ap 30 */ + <0x0006f000 0x0006f000 0x001000>, /* ap 31 */ + <0x00070000 0x00070000 0x001000>, /* ap 32 */ + <0x00071000 0x00071000 0x001000>, /* ap 33 */ + <0x00072000 0x00072000 0x001000>, /* ap 34 */ + <0x00073000 0x00073000 0x001000>, /* ap 35 */ + <0x00061000 0x00061000 0x001000>, /* ap 36 */ + <0x00096000 0x00096000 0x001000>, /* ap 37 */ + <0x00097000 0x00097000 0x001000>, /* ap 38 */ + <0x00076000 0x00076000 0x001000>, /* ap 39 */ + <0x00077000 0x00077000 0x001000>, /* ap 40 */ + <0x00078000 0x00078000 0x001000>, /* ap 41 */ + <0x00079000 0x00079000 0x001000>, /* ap 42 */ + <0x00086000 0x00086000 0x001000>, /* ap 43 */ + <0x00087000 0x00087000 0x001000>, /* ap 44 */ + <0x00088000 0x00088000 0x001000>, /* ap 45 */ + <0x00089000 0x00089000 0x001000>, /* ap 46 */ + <0x000b0000 0x000b0000 0x001000>, /* ap 47 */ + <0x000b1000 0x000b1000 0x001000>, /* ap 48 */ + <0x00098000 0x00098000 0x001000>, /* ap 49 */ + <0x00099000 0x00099000 0x001000>, /* ap 50 */ + <0x0009a000 0x0009a000 0x001000>, /* ap 51 */ + <0x0009b000 0x0009b000 0x001000>, /* ap 52 */ + <0x0009c000 0x0009c000 0x001000>, /* ap 53 */ + <0x0009d000 0x0009d000 0x001000>, /* ap 54 */ + <0x0009e000 0x0009e000 0x001000>, /* ap 55 */ + <0x0009f000 0x0009f000 0x001000>, /* ap 56 */ + <0x00090000 0x00090000 0x002000>, /* ap 57 */ + <0x00092000 0x00092000 0x001000>, /* ap 58 */ + <0x000a4000 0x000a4000 0x001000>, /* ap 59 */ + <0x000a6000 0x000a6000 0x001000>, /* ap 60 */ + <0x000a8000 0x000a8000 0x004000>, /* ap 61 */ + <0x000ac000 0x000ac000 0x001000>, /* ap 62 */ + <0x000ad000 0x000ad000 0x001000>, /* ap 63 */ + <0x000ae000 0x000ae000 0x001000>, /* ap 64 */ + <0x000b2000 0x000b2000 0x001000>, /* ap 65 */ + <0x000b3000 0x000b3000 0x001000>, /* ap 66 */ + <0x000b4000 0x000b4000 0x001000>, /* ap 67 */ + <0x000b5000 0x000b5000 0x001000>, /* ap 68 */ + <0x000b8000 0x000b8000 0x001000>, /* ap 69 */ + <0x000b9000 0x000b9000 0x001000>, /* ap 70 */ + <0x000ba000 0x000ba000 0x001000>, /* ap 71 */ + <0x000bb000 0x000bb000 0x001000>, /* ap 72 */ + <0x000d1000 0x000d1000 0x001000>, /* ap 73 */ + <0x000d2000 0x000d2000 0x001000>, /* ap 74 */ + <0x000d5000 0x000d5000 0x001000>, /* ap 75 */ + <0x000d6000 0x000d6000 0x001000>, /* ap 76 */ + <0x000a2000 0x000a2000 0x001000>, /* ap 79 */ + <0x000a3000 0x000a3000 0x001000>, /* ap 80 */ + <0x00001400 0x00001400 0x000400>, /* ap 81 */ + <0x00001800 0x00001800 0x000400>, /* ap 82 */ + <0x00001c00 0x00001c00 0x000400>, /* ap 83 */ + <0x000a5000 0x000a5000 0x001000>; /* ap 84 */ + + target-module@20000 { /* 0x48020000, ap 3 06.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart3"; + reg = <0x20050 0x4>, + <0x20054 0x4>, + <0x20058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@32000 { /* 0x48032000, ap 5 02.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + ti,hwmods = "timer2"; + reg = <0x32000 0x4>, + <0x32010 0x4>, + <0x32014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>; + }; + + target-module@34000 { /* 0x48034000, ap 7 04.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer3"; + reg = <0x34000 0x4>, + <0x34010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x34000 0x1000>; + }; + + target-module@36000 { /* 0x48036000, ap 9 0e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer4"; + reg = <0x36000 0x4>, + <0x36010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + + target-module@3e000 { /* 0x4803e000, ap 11 08.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer9"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + }; + + target-module@40000 { /* 0x48040000, ap 13 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x10000>; + }; + + target-module@55000 { /* 0x48055000, ap 15 0c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio2"; + reg = <0x55000 0x4>, + <0x55010 0x4>, + <0x55114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x55000 0x1000>; + }; + + target-module@57000 { /* 0x48057000, ap 17 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio3"; + reg = <0x57000 0x4>, + <0x57010 0x4>, + <0x57114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x57000 0x1000>; + }; + + target-module@59000 { /* 0x48059000, ap 19 10.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio4"; + reg = <0x59000 0x4>, + <0x59010 0x4>, + <0x59114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + }; + + target-module@5b000 { /* 0x4805b000, ap 21 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio5"; + reg = <0x5b000 0x4>, + <0x5b010 0x4>, + <0x5b114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + }; + + target-module@5d000 { /* 0x4805d000, ap 23 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio6"; + reg = <0x5d000 0x4>, + <0x5d010 0x4>, + <0x5d114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + }; + + target-module@60000 { /* 0x48060000, ap 25 1e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c3"; + reg = <0x60000 0x8>, + <0x60010 0x8>, + <0x60090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + }; + + target-module@6a000 { /* 0x4806a000, ap 26 18.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart1"; + reg = <0x6a050 0x4>, + <0x6a054 0x4>, + <0x6a058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6a000 0x1000>; + }; + + target-module@6c000 { /* 0x4806c000, ap 28 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart2"; + reg = <0x6c050 0x4>, + <0x6c054 0x4>, + <0x6c058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6c000 0x1000>; + }; + + target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart4"; + reg = <0x6e050 0x4>, + <0x6e054 0x4>, + <0x6e058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6e000 0x1000>; + }; + + target-module@70000 { /* 0x48070000, ap 32 28.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c1"; + reg = <0x70000 0x8>, + <0x70010 0x8>, + <0x70090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x70000 0x1000>; + }; + + target-module@72000 { /* 0x48072000, ap 34 30.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c2"; + reg = <0x72000 0x8>, + <0x72010 0x8>, + <0x72090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x72000 0x1000>; + }; + + target-module@76000 { /* 0x48076000, ap 39 38.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "slimbus2"; + reg = <0x76000 0x4>, + <0x76010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x76000 0x1000>; + }; + + target-module@78000 { /* 0x48078000, ap 41 1a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "elm"; + reg = <0x78000 0x4>, + <0x78010 0x4>, + <0x78014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x78000 0x1000>; + }; + + target-module@86000 { /* 0x48086000, ap 43 24.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + ti,hwmods = "timer10"; + reg = <0x86000 0x4>, + <0x86010 0x4>, + <0x86014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x86000 0x1000>; + }; + + target-module@88000 { /* 0x48088000, ap 45 2e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer11"; + reg = <0x88000 0x4>, + <0x88010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x88000 0x1000>; + }; + + target-module@90000 { /* 0x48090000, ap 57 2a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x90000 0x2000>; + }; + + target-module@96000 { /* 0x48096000, ap 37 26.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp4"; + reg = <0x9608c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x96000 0x1000>; + }; + + target-module@98000 { /* 0x48098000, ap 49 22.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi1"; + reg = <0x98000 0x4>, + <0x98010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000 0x1000>; + }; + + target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi2"; + reg = <0x9a000 0x4>, + <0x9a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9a000 0x1000>; + }; + + target-module@9c000 { /* 0x4809c000, ap 53 36.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc1"; + reg = <0x9c000 0x4>, + <0x9c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9c000 0x1000>; + }; + + target-module@9e000 { /* 0x4809e000, ap 55 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9e000 0x1000>; + }; + + target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa2000 0x1000>; + }; + + target-module@a4000 { /* 0x480a4000, ap 59 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x000a4000 0x00001000>, + <0x00001000 0x000a5000 0x00001000>; + }; + + target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x4000>; + }; + + target-module@ad000 { /* 0x480ad000, ap 63 50.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc3"; + reg = <0xad000 0x4>, + <0xad010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xad000 0x1000>; + }; + + target-module@b0000 { /* 0x480b0000, ap 47 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb0000 0x1000>; + }; + + target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "hdq1w"; + reg = <0xb2000 0x4>, + <0xb2014 0x4>, + <0xb2018 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + ti,no-reset-on-init; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb2000 0x1000>; + }; + + target-module@b4000 { /* 0x480b4000, ap 67 46.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc2"; + reg = <0xb4000 0x4>, + <0xb4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb4000 0x1000>; + }; + + target-module@b8000 { /* 0x480b8000, ap 69 58.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi3"; + reg = <0xb8000 0x4>, + <0xb8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb8000 0x1000>; + }; + + target-module@ba000 { /* 0x480ba000, ap 71 32.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi4"; + reg = <0xba000 0x4>, + <0xba010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xba000 0x1000>; + }; + + target-module@d1000 { /* 0x480d1000, ap 73 44.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc4"; + reg = <0xd1000 0x4>, + <0xd1010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd1000 0x1000>; + }; + + target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc5"; + reg = <0xd5000 0x4>, + <0xd5010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd5000 0x1000>; + }; + }; + + segment@200000 { /* 0x48200000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */ + <0x00151000 0x00351000 0x001000>; /* ap 78 */ + + target-module@150000 { /* 0x48350000, ap 77 4c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c4"; + reg = <0x150000 0x8>, + <0x150010 0x8>, + <0x150090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x150000 0x1000>; + }; + }; +}; + -- cgit v1.2.3 From 4bce678624227b5f5e020a3ff05205d40f6677c0 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 6 Jul 2018 02:55:34 -0700 Subject: ARM: dts: omap4: Probe watchdog 3 with ti-sysc Before updating wdt2 to probe with ti-sysc we want to have wdt3 probed with ti-sysc to avoid having them unnecessarily swap order. With ti-sysc, we probe child devices at module_init time while and until l4 abe interconnect is converted to use ti-sysc, wdt3 will probe earlier with legacy platform data. Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index e554b6e039f3..bbc347755c7b 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -787,12 +787,33 @@ ti,hwmods = "wd_timer2"; }; - wdt3: wdt@40130000 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - reg = <0x40130000 0x80>, /* MPU private access */ - <0x49030000 0x80>; /* L3 Interconnect */ - interrupts = ; + target-module@40130000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "wd_timer3"; + reg = <0x40130000 0x4>, + <0x40130010 0x4>, + <0x40130014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): abe, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40130000 0x1000>, /* MPU private access */ + <0x49030000 0x49030000 0x0080>; /* L3 Interconnect */ + + wdt3: wdt@0 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x0 0x80>; + interrupts = ; + }; }; mcpdm: mcpdm@40132000 { -- cgit v1.2.3 From 84badc5ec5fc01e7cb16f5e1628b2fe8d8965a57 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 5 Jul 2018 23:19:37 -0700 Subject: ARM: dts: omap4: Move l4 child devices to probe them with ti-sysc With l4 interconnect hierarchy and ti-sysc interconnect target module data in place, we can simply move all the related child devices to their proper location and enable probing using ti-sysc. In general the first child device address range starts at range 0 from the ti-sysc interconnect target so the move involves adjusting the child device reg properties for that. And we cannot yet move mmu_dsp until we have a proper reset controller driver for rstctrl registers. In case of any regressions, problem devices can be reverted to probe with legacy platform data as needed by moving them back and removing the related interconnect target module node. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4.dtsi | 645 ++++++++++++++++++++++++++++- arch/arm/boot/dts/omap4-panda-es.dts | 2 +- arch/arm/boot/dts/omap4.dtsi | 781 +---------------------------------- 3 files changed, 643 insertions(+), 785 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 3e756fde929d..999a8649ea15 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -55,22 +55,83 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; + + omap4_scm_core: scm@0 { + compatible = "ti,omap4-scm-core", "simple-bus"; + reg = <0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + }; + + omap_control_usb2phy: control-phy@300 { + compatible = "ti,control-phy-usb2"; + reg = <0x300 0x4>; + reg-names = "power"; + }; + + omap_control_usbotg: control-phy@33c { + compatible = "ti,control-phy-otghs"; + reg = <0x33c 0x4>; + reg-names = "otghs_control"; + }; + }; }; target-module@4000 { /* 0x4a004000, ap 5 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4000 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; + + cm1: cm1@0 { + compatible = "ti,omap4-cm1", "simple-bus"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + cm1_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm1_clockdomains: clockdomains { + }; + }; }; target-module@8000 { /* 0x4a008000, ap 23 32.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x8000 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x2000>; + + cm2: cm2@0 { + compatible = "ti,omap4-cm2", "simple-bus"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + cm2_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm2_clockdomains: clockdomains { + }; + }; }; target-module@56000 { /* 0x4a056000, ap 7 0a.0 */ @@ -97,6 +158,18 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x56000 0x1000>; + + sdma: dma-controller@0 { + compatible = "ti,omap4430-sdma"; + reg = <0x0 0x1000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <127>; + }; }; target-module@58000 { /* 0x4a058000, ap 10 0e.0 */ @@ -124,6 +197,39 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x58000 0x4000>; + + hsi: hsi@0 { + compatible = "ti,omap4-hsi"; + reg = <0x0 0x4000>, + <0x4a05c000 0x1000>; + reg-names = "sys", "gdd"; + + clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; + clock-names = "hsi_fck"; + + interrupts = ; + interrupt-names = "gdd_mpu"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x4000>; + + hsi_port1: hsi-port@2000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x2000 0x800>, + <0x2800 0x800>; + reg-names = "tx", "rx"; + interrupts = ; + }; + + hsi_port2: hsi-port@3000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x3000 0x800>, + <0x3800 0x800>; + reg-names = "tx", "rx"; + interrupts = ; + }; + }; }; target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */ @@ -154,6 +260,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x62000 0x1000>; + + usbhstll: usbhstll@0 { + compatible = "ti,usbhs-tll"; + reg = <0x0 0x1000>; + interrupts = ; + }; }; target-module@64000 { /* 0x4a064000, ap 86 1e.0 */ @@ -178,6 +290,33 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x64000 0x1000>; + + usbhshost: usbhshost@0 { + compatible = "ti,usbhs-host"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + clocks = <&init_60m_fclk>, + <&xclk60mhsp1_ck>, + <&xclk60mhsp2_ck>; + clock-names = "refclk_60m_int", + "refclk_60m_ext_p1", + "refclk_60m_ext_p2"; + + usbhsohci: ohci@800 { + compatible = "ti,ohci-omap3"; + reg = <0x800 0x400>; + interrupts = ; + remote-wakeup-connected; + }; + + usbhsehci: ehci@c00 { + compatible = "ti,ehci-omap"; + reg = <0xc00 0x400>; + interrupts = ; + }; + }; }; target-module@66000 { /* 0x4a066000, ap 25 26.0 */ @@ -199,6 +338,9 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x66000 0x1000>; + + /* mmu_dsp cannot be moved before reset driver */ + status = "disabled"; }; }; @@ -261,6 +403,20 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2b000 0x1000>; + + usb_otg_hs: usb_otg_hs@0 { + compatible = "ti,omap4-musb"; + reg = <0x0 0x7ff>; + interrupts = , ; + interrupt-names = "mc", "dma"; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + multipoint = <1>; + num-eps = <16>; + ram-bits = <12>; + ctrl-module = <&omap_control_usbotg>; + }; }; target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */ @@ -282,6 +438,22 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2d000 0x1000>; + + ocp2scp@0 { + compatible = "ti,omap-ocp2scp"; + reg = <0x0 0x1f>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + usb2_phy: usb2phy@80 { + compatible = "ti,omap-usb2"; + reg = <0x80 0x58>; + ctrl-module = <&omap_control_usb2phy>; + clocks = <&usb_phy_cm_clk32k>; + clock-names = "wkupclk"; + #phy-cells = <0>; + }; + }; }; target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */ @@ -316,6 +488,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x59000 0x1000>; + + smartreflex_mpu: smartreflex@0 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0x0 0x80>; + interrupts = ; + }; }; target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */ @@ -334,6 +512,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5b000 0x1000>; + + smartreflex_iva: smartreflex@0 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0x0 0x80>; + interrupts = ; + }; }; target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */ @@ -352,6 +536,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5d000 0x1000>; + + smartreflex_core: smartreflex@0 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0x0 0x80>; + interrupts = ; + }; }; target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */ @@ -378,6 +568,23 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x74000 0x1000>; + + mailbox: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; + mbox_ipu: mbox_ipu { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_dsp: mbox_dsp { + ti,mbox-tx = <3 0 0>; + ti,mbox-rx = <2 0 0>; + }; + }; }; target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */ @@ -401,6 +608,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x76000 0x1000>; + + hwspinlock: spinlock@0 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x0 0x1000>; + #hwlock-cells = <1>; + }; }; }; @@ -431,6 +644,39 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; + + omap4_pmx_core: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0196>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap4_padconf_global: omap4_padconf_global@5a0 { + compatible = "syscon", + "simple-bus"; + reg = <0x5a0 0x170>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5a0 0x170>; + + pbias_regulator: pbias_regulator@60 { + compatible = "ti,pbias-omap4", "ti,pbias-omap"; + reg = <0x60 0x4>; + syscon = <&omap4_padconf_global>; + pbias_mmc_reg: pbias_mmc_omap4 { + regulator-name = "pbias_mmc_omap4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; }; target-module@2000 { /* 0x4a102000, ap 61 3c.0 */ @@ -469,6 +715,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa000 0x1000>; + + /* No child device binding or driver in mainline */ }; }; @@ -717,22 +965,59 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0x0 0x20>; + }; }; target-module@6000 { /* 0x4a306000, ap 3 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x6000 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6000 0x2000>; + + prm: prm@0 { + compatible = "ti,omap4-prm"; + reg = <0x0 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; }; target-module@a000 { /* 0x4a30a000, ap 15 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xa000 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa000 0x1000>; + + scrm: scrm@0 { + compatible = "ti,omap4-scrm"; + reg = <0x0 0x2000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; }; target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */ @@ -749,6 +1034,11 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; + + omap4_scm_wkup: scm@c000 { + compatible = "ti,omap4-scm-wkup"; + reg = <0xc000 0x1000>; + }; }; }; @@ -767,7 +1057,7 @@ <0x0000e000 0x0001e000 0x001000>, /* ap 21 */ <0x0000f000 0x0001f000 0x001000>; /* ap 22 */ - target-module@0 { /* 0x4a310000, ap 5 14.0 */ + gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "gpio1"; reg = <0x0 0x4>, @@ -789,6 +1079,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; + + gpio1: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + ti,gpio-always-on; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@4000 { /* 0x4a314000, ap 7 18.0 */ @@ -811,6 +1112,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; + + wdt2: wdt@0 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x0 0x80>; + interrupts = ; + }; }; target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ @@ -835,6 +1142,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-alwon; + }; }; target-module@c000 { /* 0x4a31c000, ap 11 20.0 */ @@ -859,6 +1175,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; + + keypad: keypad@0 { + compatible = "ti,omap4-keypad"; + reg = <0x0 0x80>; + interrupts = ; + reg-names = "mpu"; + }; }; target-module@e000 { /* 0x4a31e000, ap 21 30.0 */ @@ -875,6 +1198,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe000 0x1000>; + + omap4_pmx_wkup: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; }; }; @@ -1054,6 +1390,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; + + uart3: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; }; target-module@32000 { /* 0x48032000, ap 5 02.0 */ @@ -1078,6 +1421,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x32000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@34000 { /* 0x48034000, ap 7 04.0 */ @@ -1098,6 +1449,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x34000 0x1000>; + + timer3: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@36000 { /* 0x48036000, ap 9 0e.0 */ @@ -1118,6 +1477,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x36000 0x1000>; + + timer4: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@3e000 { /* 0x4803e000, ap 11 08.0 */ @@ -1138,6 +1505,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; + + timer9: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-pwm; + }; }; target-module@40000 { /* 0x48040000, ap 13 0a.0 */ @@ -1170,6 +1546,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x55000 0x1000>; + + gpio2: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@57000 { /* 0x48057000, ap 17 16.0 */ @@ -1194,6 +1580,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x57000 0x1000>; + + gpio3: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@59000 { /* 0x48059000, ap 19 10.0 */ @@ -1218,6 +1614,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x59000 0x1000>; + + gpio4: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@5b000 { /* 0x4805b000, ap 21 12.0 */ @@ -1242,6 +1648,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5b000 0x1000>; + + gpio5: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@5d000 { /* 0x4805d000, ap 23 14.0 */ @@ -1266,6 +1682,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5d000 0x1000>; + + gpio6: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@60000 { /* 0x48060000, ap 25 1e.0 */ @@ -1290,6 +1716,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; + + i2c3: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; }; target-module@6a000 { /* 0x4806a000, ap 26 18.0 */ @@ -1313,6 +1747,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6a000 0x1000>; + + uart1: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; }; target-module@6c000 { /* 0x4806c000, ap 28 20.0 */ @@ -1336,6 +1777,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6c000 0x1000>; + + uart2: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; }; target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */ @@ -1359,6 +1807,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6e000 0x1000>; + + uart4: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; }; target-module@70000 { /* 0x48070000, ap 32 28.0 */ @@ -1383,6 +1838,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x70000 0x1000>; + + i2c1: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; }; target-module@72000 { /* 0x48072000, ap 34 30.0 */ @@ -1407,6 +1870,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x72000 0x1000>; + + i2c2: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; }; target-module@76000 { /* 0x48076000, ap 39 38.0 */ @@ -1426,6 +1897,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x76000 0x1000>; + + /* No child device binding or driver in mainline */ }; target-module@78000 { /* 0x48078000, ap 41 1a.0 */ @@ -1448,6 +1921,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x78000 0x1000>; + + elm: elm@0 { + compatible = "ti,am3352-elm"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; }; target-module@86000 { /* 0x48086000, ap 43 24.0 */ @@ -1472,6 +1952,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x86000 0x1000>; + + timer10: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-pwm; + }; }; target-module@88000 { /* 0x48088000, ap 45 2e.0 */ @@ -1492,6 +1981,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x88000 0x1000>; + + timer11: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-pwm; + }; }; target-module@90000 { /* 0x48090000, ap 57 2a.0 */ @@ -1519,6 +2017,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x96000 0x1000>; + + mcbsp4: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>; /* L4 Interconnect */ + reg-names = "mpu"; + interrupts = ; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 31>, + <&sdma 32>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; target-module@98000 { /* 0x48098000, ap 49 22.0 */ @@ -1539,6 +2050,25 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x98000 0x1000>; + + mcspi1: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <4>; + dmas = <&sdma 35>, + <&sdma 36>, + <&sdma 37>, + <&sdma 38>, + <&sdma 39>, + <&sdma 40>, + <&sdma 41>, + <&sdma 42>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; }; target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */ @@ -1559,6 +2089,20 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9a000 0x1000>; + + mcspi2: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma 43>, + <&sdma 44>, + <&sdma 45>, + <&sdma 46>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; }; target-module@9c000 { /* 0x4809c000, ap 53 36.0 */ @@ -1583,6 +2127,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9c000 0x1000>; + + mmc1: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,dual-volt; + ti,needs-special-reset; + dmas = <&sdma 61>, <&sdma 62>; + dma-names = "tx", "rx"; + pbias-supply = <&pbias_mmc_reg>; + }; }; target-module@9e000 { /* 0x4809e000, ap 55 48.0 */ @@ -1640,6 +2195,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xad000 0x1000>; + + mmc3: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 77>, <&sdma 78>; + dma-names = "tx", "rx"; + }; }; target-module@b0000 { /* 0x480b0000, ap 47 40.0 */ @@ -1667,6 +2231,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb2000 0x1000>; + + hdqw1w: 1w@0 { + compatible = "ti,omap3-1w"; + reg = <0x0 0x1000>; + interrupts = ; + }; }; target-module@b4000 { /* 0x480b4000, ap 67 46.0 */ @@ -1691,6 +2261,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb4000 0x1000>; + + mmc2: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 47>, <&sdma 48>; + dma-names = "tx", "rx"; + }; }; target-module@b8000 { /* 0x480b8000, ap 69 58.0 */ @@ -1711,6 +2290,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb8000 0x1000>; + + mcspi3: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma 15>, <&sdma 16>; + dma-names = "tx0", "rx0"; + }; }; target-module@ba000 { /* 0x480ba000, ap 71 32.0 */ @@ -1731,6 +2321,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xba000 0x1000>; + + mcspi4: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <1>; + dmas = <&sdma 70>, <&sdma 71>; + dma-names = "tx0", "rx0"; + }; }; target-module@d1000 { /* 0x480d1000, ap 73 44.0 */ @@ -1755,6 +2356,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd1000 0x1000>; + + mmc4: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 57>, <&sdma 58>; + dma-names = "tx", "rx"; + }; }; target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */ @@ -1779,6 +2389,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd5000 0x1000>; + + mmc5: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 59>, <&sdma 60>; + dma-names = "tx", "rx"; + }; }; }; @@ -1811,6 +2430,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x150000 0x1000>; + + i2c4: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; }; diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index 940fe4f7c5f6..ee9bca8d3e96 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -68,6 +68,6 @@ }; }; -&gpio1 { +&gpio1_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index bbc347755c7b..1a96d4317c97 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -139,174 +139,13 @@ interrupts = , ; - l4_cfg: l4@4a000000 { - compatible = "ti,omap4-l4-cfg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a000000 0x1000000>; - - cm1: cm1@4000 { - compatible = "ti,omap4-cm1", "simple-bus"; - reg = <0x4000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4000 0x2000>; - - cm1_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm1_clockdomains: clockdomains { - }; - }; - - cm2: cm2@8000 { - compatible = "ti,omap4-cm2", "simple-bus"; - reg = <0x8000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8000 0x2000>; - - cm2_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm2_clockdomains: clockdomains { - }; - }; - - omap4_scm_core: scm@2000 { - compatible = "ti,omap4-scm-core", "simple-bus"; - reg = <0x2000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x1000>; - ti,hwmods = "ctrl_module_core"; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - omap4_padconf_core: scm@100000 { - compatible = "ti,omap4-scm-padconf-core", - "simple-bus"; - reg = <0x100000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x100000 0x1000>; - ti,hwmods = "ctrl_module_pad_core"; - - omap4_pmx_core: pinmux@40 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x40 0x0196>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap4_padconf_global: omap4_padconf_global@5a0 { - compatible = "syscon", - "simple-bus"; - reg = <0x5a0 0x170>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5a0 0x170>; - - pbias_regulator: pbias_regulator@60 { - compatible = "ti,pbias-omap4", "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap4_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap4 { - regulator-name = "pbias_mmc_omap4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; - }; - - l4_wkup: l4@300000 { - compatible = "ti,omap4-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x300000 0x40000>; - - counter32k: counter@4000 { - compatible = "ti,omap-counter32k"; - reg = <0x4000 0x20>; - ti,hwmods = "counter_32k"; - }; - - prm: prm@6000 { - compatible = "ti,omap4-prm"; - reg = <0x6000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x6000 0x2000>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@a000 { - compatible = "ti,omap4-scrm"; - reg = <0xa000 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - omap4_scm_wkup: scm@c000 { - compatible = "ti,omap4-scm-wkup"; - reg = <0xc000 0x1000>; - ti,hwmods = "ctrl_module_wkup"; - }; + l4_wkup: interconnect@4a300000 { + }; - omap4_padconf_wkup: padconf@1e000 { - compatible = "ti,omap4-scm-padconf-wkup", - "simple-bus"; - reg = <0x1e000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e000 0x1000>; - ti,hwmods = "ctrl_module_pad_wkup"; + l4_cfg: interconnect@4a000000 { + }; - omap4_pmx_wkup: pinmux@40 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x40 0x0038>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - }; - }; + l4_per: interconnect@48000000 { }; ocmcram: ocmcram@40304000 { @@ -314,114 +153,6 @@ reg = <0x40304000 0xa000>; /* 40k */ }; - sdma: dma-controller@4a056000 { - compatible = "ti,omap4430-sdma"; - reg = <0x4a056000 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - ti,hwmods = "dma_system"; - }; - - gpio1: gpio@4a310000 { - compatible = "ti,omap4-gpio"; - reg = <0x4a310000 0x200>; - interrupts = ; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@48055000 { - compatible = "ti,omap4-gpio"; - reg = <0x48055000 0x200>; - interrupts = ; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@48057000 { - compatible = "ti,omap4-gpio"; - reg = <0x48057000 0x200>; - interrupts = ; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@48059000 { - compatible = "ti,omap4-gpio"; - reg = <0x48059000 0x200>; - interrupts = ; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@4805b000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805b000 0x200>; - interrupts = ; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@4805d000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805d000 0x200>; - interrupts = ; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - target-module@48076000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "slimbus2"; - reg = <0x48076000 0x4>, - <0x48076010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48076000 0x001000>; - - /* No child device binding or driver in mainline */ - }; - - elm: elm@48078000 { - compatible = "ti,am3352-elm"; - reg = <0x48078000 0x2000>; - interrupts = ; - ti,hwmods = "elm"; - status = "disabled"; - }; - gpmc: gpmc@50000000 { compatible = "ti,omap4430-gpmc"; reg = <0x50000000 0x1000>; @@ -442,302 +173,6 @@ #gpio-cells = <2>; }; - uart1: serial@4806a000 { - compatible = "ti,omap4-uart"; - reg = <0x4806a000 0x100>; - interrupts = ; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap4-uart"; - reg = <0x4806c000 0x100>; - interrupts = ; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - }; - - uart3: serial@48020000 { - compatible = "ti,omap4-uart"; - reg = <0x48020000 0x100>; - interrupts = ; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - }; - - uart4: serial@4806e000 { - compatible = "ti,omap4-uart"; - reg = <0x4806e000 0x100>; - interrupts = ; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; - - target-module@4a0db000 { - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_iva"; - reg = <0x4a0db038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a0db000 0x001000>; - - smartreflex_iva: smartreflex@0 { - compatible = "ti,omap4-smartreflex-iva"; - reg = <0 0x80>; - interrupts = ; - }; - }; - - target-module@4a0dd000 { - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_core"; - reg = <0x4a0dd038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a0dd000 0x001000>; - - smartreflex_core: smartreflex@0 { - compatible = "ti,omap4-smartreflex-core"; - reg = <0 0x80>; - interrupts = ; - }; - }; - - target-module@4a0d9000 { - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_mpu"; - reg = <0x4a0d9038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a0d9000 0x001000>; - - smartreflex_mpu: smartreflex@0 { - compatible = "ti,omap4-smartreflex-mpu"; - reg = <0 0x80>; - interrupts = ; - }; - }; - - hwspinlock: spinlock@4a0f6000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x4a0f6000 0x1000>; - ti,hwmods = "spinlock"; - #hwlock-cells = <1>; - }; - - i2c1: i2c@48070000 { - compatible = "ti,omap4-i2c"; - reg = <0x48070000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap4-i2c"; - reg = <0x48072000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap4-i2c"; - reg = <0x48060000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - }; - - i2c4: i2c@48350000 { - compatible = "ti,omap4-i2c"; - reg = <0x48350000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c4"; - }; - - mcspi1: spi@48098000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48098000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap4-mcspi"; - reg = <0x4809a000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - hdqw1w: 1w@480b2000 { - compatible = "ti,omap3-1w"; - reg = <0x480b2000 0x1000>; - interrupts = ; - ti,hwmods = "hdq1w"; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480b8000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480ba000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x4809c000 0x400>; - interrupts = ; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480b4000 0x400>; - interrupts = ; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480ad000 0x400>; - interrupts = ; - ti,hwmods = "mmc3"; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - - mmc4: mmc@480d1000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480d1000 0x400>; - interrupts = ; - ti,hwmods = "mmc4"; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; - }; - - mmc5: mmc@480d5000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480d5000 0x400>; - interrupts = ; - ti,hwmods = "mmc5"; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - - hsi: hsi@4a058000 { - compatible = "ti,omap4-hsi"; - reg = <0x4a058000 0x4000>, - <0x4a05c000 0x1000>; - reg-names = "sys", "gdd"; - ti,hwmods = "hsi"; - - clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; - clock-names = "hsi_fck"; - - interrupts = ; - interrupt-names = "gdd_mpu"; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a058000 0x4000>; - - hsi_port1: hsi-port@2000 { - compatible = "ti,omap4-hsi-port"; - reg = <0x2000 0x800>, - <0x2800 0x800>; - reg-names = "tx", "rx"; - interrupts = ; - }; - - hsi_port2: hsi-port@3000 { - compatible = "ti,omap4-hsi-port"; - reg = <0x3000 0x800>, - <0x3800 0x800>; - reg-names = "tx", "rx"; - interrupts = ; - }; - }; - mmu_dsp: mmu@4a066000 { compatible = "ti,omap4-iommu"; reg = <0x4a066000 0x100>; @@ -779,14 +214,6 @@ #iommu-cells = <0>; ti,iommu-bus-err-back; }; - - wdt2: wdt@4a314000 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - reg = <0x4a314000 0x80>; - interrupts = ; - ti,hwmods = "wd_timer2"; - }; - target-module@40130000 { compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "wd_timer3"; @@ -959,28 +386,6 @@ */ }; - mcbsp4: mcbsp@48096000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x48096000 0xff>; /* L4 Interconnect */ - reg-names = "mpu"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp4"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - keypad: keypad@4a31c000 { - compatible = "ti,omap4-keypad"; - reg = <0x4a31c000 0x80>; - interrupts = ; - reg-names = "mpu"; - ti,hwmods = "kbd"; - }; - dmm@4e000000 { compatible = "ti,omap4-dmm"; reg = <0x4e000000 0x800>; @@ -1012,95 +417,6 @@ hw-caps-temp-alert; }; - ocp2scp@4a0ad000 { - compatible = "ti,omap-ocp2scp"; - reg = <0x4a0ad000 0x1f>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "ocp2scp_usb_phy"; - usb2_phy: usb2phy@4a0ad080 { - compatible = "ti,omap-usb2"; - reg = <0x4a0ad080 0x58>; - ctrl-module = <&omap_control_usb2phy>; - clocks = <&usb_phy_cm_clk32k>; - clock-names = "wkupclk"; - #phy-cells = <0>; - }; - }; - - mailbox: mailbox@4a0f4000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4a0f4000 0x200>; - interrupts = ; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox_dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; - }; - - target-module@4a10a000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "fdif"; - reg = <0x4a10a000 0x4>, - <0x4a10a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - ti,sysc-delay-us = <2>; - clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a10a000 0x1000>; - - /* No child device binding or driver in mainline */ - }; - - timer1: timer@4a318000 { - compatible = "ti,omap3430-timer"; - reg = <0x4a318000 0x80>; - interrupts = ; - ti,hwmods = "timer1"; - ti,timer-alwon; - clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; - clock-names = "fck"; - }; - - timer2: timer@48032000 { - compatible = "ti,omap3430-timer"; - reg = <0x48032000 0x80>; - interrupts = ; - ti,hwmods = "timer2"; - }; - - timer3: timer@48034000 { - compatible = "ti,omap4430-timer"; - reg = <0x48034000 0x80>; - interrupts = ; - ti,hwmods = "timer3"; - }; - - timer4: timer@48036000 { - compatible = "ti,omap4430-timer"; - reg = <0x48036000 0x80>; - interrupts = ; - ti,hwmods = "timer4"; - }; - timer5: timer@40138000 { compatible = "ti,omap4430-timer"; reg = <0x40138000 0x80>, @@ -1138,92 +454,6 @@ ti,timer-dsp; }; - timer9: timer@4803e000 { - compatible = "ti,omap4430-timer"; - reg = <0x4803e000 0x80>; - interrupts = ; - ti,hwmods = "timer9"; - ti,timer-pwm; - }; - - timer10: timer@48086000 { - compatible = "ti,omap3430-timer"; - reg = <0x48086000 0x80>; - interrupts = ; - ti,hwmods = "timer10"; - ti,timer-pwm; - }; - - timer11: timer@48088000 { - compatible = "ti,omap4430-timer"; - reg = <0x48088000 0x80>; - interrupts = ; - ti,hwmods = "timer11"; - ti,timer-pwm; - }; - - usbhstll: usbhstll@4a062000 { - compatible = "ti,usbhs-tll"; - reg = <0x4a062000 0x1000>; - interrupts = ; - ti,hwmods = "usb_tll_hs"; - }; - - usbhshost: usbhshost@4a064000 { - compatible = "ti,usbhs-host"; - reg = <0x4a064000 0x800>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&init_60m_fclk>, - <&xclk60mhsp1_ck>, - <&xclk60mhsp2_ck>; - clock-names = "refclk_60m_int", - "refclk_60m_ext_p1", - "refclk_60m_ext_p2"; - - usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3"; - reg = <0x4a064800 0x400>; - interrupts = ; - remote-wakeup-connected; - }; - - usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap"; - reg = <0x4a064c00 0x400>; - interrupts = ; - }; - }; - - omap_control_usb2phy: control-phy@4a002300 { - compatible = "ti,control-phy-usb2"; - reg = <0x4a002300 0x4>; - reg-names = "power"; - }; - - omap_control_usbotg: control-phy@4a00233c { - compatible = "ti,control-phy-otghs"; - reg = <0x4a00233c 0x4>; - reg-names = "otghs_control"; - }; - - usb_otg_hs: usb_otg_hs@4a0ab000 { - compatible = "ti,omap4-musb"; - reg = <0x4a0ab000 0x7ff>; - interrupts = , ; - interrupt-names = "mc", "dma"; - ti,hwmods = "usb_otg_hs"; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - ctrl-module = <&omap_control_usbotg>; - }; - aes1: aes@4b501000 { compatible = "ti,omap4-aes"; ti,hwmods = "aes1"; @@ -1398,4 +628,5 @@ }; }; +#include "omap4-l4.dtsi" #include "omap44xx-clocks.dtsi" -- cgit v1.2.3 From 770368961767aa8116ca44a9bd3f90c11ca4c30b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 6 Jul 2018 00:44:29 -0700 Subject: ARM: dts: omap4: Add l4 ranges for 4460 Compared to 4430, 4460 and 4470 just have slightly different l4 cfg ranges. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4.dtsi | 4 ++-- arch/arm/boot/dts/omap4460.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 999a8649ea15..6eb26b837446 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -888,7 +888,7 @@ #size-cells = <1>; }; - segment@300000 { /* 0x4a300000 */ + l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -904,7 +904,7 @@ <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ <0x0002c000 0x0032c000 0x004000>; /* ap 91 */ - target-module@0 { /* 0x4a300000, ap 67 14.0 */ + l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */ compatible = "ti,sysc"; status = "disabled"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi index ad97493e4e46..2223dc0d63c0 100644 --- a/arch/arm/boot/dts/omap4460.dtsi +++ b/arch/arm/boot/dts/omap4460.dtsi @@ -92,4 +92,40 @@ coefficients = <348 (-9301)>; }; +/* Only some L4 CFG interconnect ranges are different on 4460 */ +&l4_cfg_segment_300000 { + ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ + <0x00040000 0x00340000 0x001000>, /* ap 68 */ + <0x00020000 0x00320000 0x004000>, /* ap 71 */ + <0x00024000 0x00324000 0x002000>, /* ap 72 */ + <0x00026000 0x00326000 0x001000>, /* ap 73 */ + <0x00027000 0x00327000 0x001000>, /* ap 74 */ + <0x00028000 0x00328000 0x001000>, /* ap 75 */ + <0x00029000 0x00329000 0x001000>, /* ap 76 */ + <0x00030000 0x00330000 0x010000>, /* ap 77 */ + <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ + <0x0002c000 0x0032c000 0x004000>, /* ap 91 */ + <0x00010000 0x00310000 0x008000>, /* ap 92 */ + <0x00018000 0x00318000 0x004000>, /* ap 93 */ + <0x0001c000 0x0031c000 0x002000>, /* ap 94 */ + <0x0001e000 0x0031e000 0x002000>; /* ap 95 */ +}; + +&l4_cfg_target_0 { + ranges = <0x00000000 0x00000000 0x00010000>, + <0x00010000 0x00010000 0x00008000>, + <0x00018000 0x00018000 0x00004000>, + <0x0001c000 0x0001c000 0x00002000>, + <0x0001e000 0x0001e000 0x00002000>, + <0x00020000 0x00020000 0x00004000>, + <0x00024000 0x00024000 0x00002000>, + <0x00026000 0x00026000 0x00001000>, + <0x00027000 0x00027000 0x00001000>, + <0x00028000 0x00028000 0x00001000>, + <0x00029000 0x00029000 0x00001000>, + <0x0002a000 0x0002a000 0x00002000>, + <0x0002c000 0x0002c000 0x00004000>, + <0x00030000 0x00030000 0x00010000>; +}; + /include/ "omap446x-clocks.dtsi" -- cgit v1.2.3 From eea7f21b1e2dc0c0ea5e9719b1b31320661d5dfe Mon Sep 17 00:00:00 2001 From: Sricharan R Date: Wed, 20 Jun 2018 14:53:39 +0530 Subject: ARM: dts: qcom: Fix 'interrupts = <>' property to use proper macros Fix all nodes to use proper GIC_* macros for the interrupt type and the interrupt trigger settings to avoid the boot warnings. Signed-off-by: Sricharan R Tested-by: Abhishek Sahu Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 41 ++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 17 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 1e0a3b446f7a..70790ac242d1 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include / { model = "Qualcomm IPQ8064"; @@ -43,7 +44,8 @@ cpu-pmu { compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; + interrupts = ; }; reserved-memory { @@ -97,7 +99,7 @@ clock-names = "ahbix-clk", "mi2s-osr-clk", "mi2s-bit-clk"; - interrupts = <0 85 1>; + interrupts = ; interrupt-names = "lpass-irq-lpaif"; reg = <0x28100000 0x10000>; reg-names = "lpass-lpaif"; @@ -111,7 +113,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 16 0x4>; + interrupts = ; }; intc: interrupt-controller@2000000 { @@ -125,11 +127,16 @@ timer@200a000 { compatible = "qcom,kpss-timer", "qcom,kpss-wdt-ipq8064", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>, - <1 4 0x301>, - <1 5 0x301>; + interrupts = , + , + , + , + ; reg = <0x0200a000 0x100>; clock-frequency = <25000000>, <32768>; @@ -177,7 +184,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x12490000 0x1000>, <0x12480000 0x1000>; - interrupts = <0 195 0x0>; + interrupts = ; clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -186,7 +193,7 @@ i2c@124a0000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x124a0000 0x1000>; - interrupts = <0 196 0>; + interrupts = ; clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; clock-names = "core", "iface"; @@ -215,7 +222,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16340000 0x1000>, <0x16300000 0x1000>; - interrupts = <0 152 0x0>; + interrupts = ; clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -224,7 +231,7 @@ i2c@16380000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16380000 0x1000>; - interrupts = <0 153 0>; + interrupts = ; clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; clock-names = "core", "iface"; @@ -252,7 +259,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x1a240000 0x1000>, <0x1a200000 0x1000>; - interrupts = <0 154 0x0>; + interrupts = ; clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -261,7 +268,7 @@ i2c@1a280000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x1a280000 0x1000>; - interrupts = <0 155 0>; + interrupts = ; clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; @@ -274,7 +281,7 @@ spi@1a280000 { compatible = "qcom,spi-qup-v1.1.1"; reg = <0x1a280000 0x1000>; - interrupts = <0 155 0>; + interrupts = ; clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; @@ -301,7 +308,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16640000 0x1000>, <0x16600000 0x1000>; - interrupts = <0 158 0x0>; + interrupts = ; clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -323,7 +330,7 @@ compatible = "qcom,ipq806x-ahci", "generic-ahci"; reg = <0x29000000 0x180>; - interrupts = <0 209 0x0>; + interrupts = ; clocks = <&gcc SFAB_SATA_S_H_CLK>, <&gcc SATA_H_CLK>, -- cgit v1.2.3 From 03864e57770a9541e7ff3990bacf2d9a2fffcd5d Mon Sep 17 00:00:00 2001 From: Bhushan Shah Date: Mon, 9 Jul 2018 14:46:28 +0530 Subject: ARM: dts: qcom: msm8974-hammerhead: increase load on l20 for sdhci The kernel would not boot on the hammerhead hardware due to the following error: mmc0: Timeout waiting for hardware interrupt. mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== mmc0: sdhci: Sys addr: 0x00000200 | Version: 0x00003802 mmc0: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000200 mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000023 mmc0: sdhci: Present: 0x03e80000 | Host ctl: 0x00000034 mmc0: sdhci: Power: 0x00000001 | Blk gap: 0x00000000 mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x00000007 mmc0: sdhci: Timeout: 0x0000000e | Int stat: 0x00000000 mmc0: sdhci: Int enab: 0x02ff900b | Sig enab: 0x02ff100b mmc0: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000 mmc0: sdhci: Caps: 0x642dc8b2 | Caps_1: 0x00008007 mmc0: sdhci: Cmd: 0x00000c1b | Max curr: 0x00000000 mmc0: sdhci: Resp[0]: 0x00000c00 | Resp[1]: 0x00000000 mmc0: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 mmc0: sdhci: Host ctl2: 0x00000008 mmc0: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x70040220 mmc0: sdhci: ============================================ mmc0: Card stuck in wrong state! mmcblk0 card_busy_detect status: 0xe00 mmc0: cache flush error -110 mmc0: Reset 0x1 never completed. This patch increases the load on l20 to 0.2 amps for the sdhci and allows the device to boot normally. Signed-off-by: Bhushan Shah Signed-off-by: Brian Masney Suggested-by: Bjorn Andersson Tested-by: Brian Masney Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 4dc0b347b1ee..c2dc9d09484a 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -189,6 +189,8 @@ regulator-max-microvolt = <2950000>; regulator-boot-on; + regulator-system-load = <200000>; + regulator-allow-set-load; }; l21 { -- cgit v1.2.3 From b0c28f2765813e816740028dd85e64e46eee15a0 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:02:00 +0530 Subject: ARM: dts: qcom: Add missing OPP properties for CPUs The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing property (clock latency) as well to make it all work. Signed-off-by: Viresh Kumar Reviewed-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 7bcd7635e723..78db67337ed4 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -77,6 +77,14 @@ reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points = < + /* kHz uV (fixed) */ + 48000 1100000 + 200000 1100000 + 500000 1100000 + 666000 1100000 + >; + clock-latency = <256000>; }; cpu@2 { @@ -88,6 +96,14 @@ reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points = < + /* kHz uV (fixed) */ + 48000 1100000 + 200000 1100000 + 500000 1100000 + 666000 1100000 + >; + clock-latency = <256000>; }; cpu@3 { @@ -99,6 +115,14 @@ reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points = < + /* kHz uV (fixed) */ + 48000 1100000 + 200000 1100000 + 500000 1100000 + 666000 1100000 + >; + clock-latency = <256000>; }; }; -- cgit v1.2.3 From 945d004788319fb5863de3b2e4831064902dd10c Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 20 Jul 2018 18:11:50 +0800 Subject: ARM: dts: berlin: Add missing OPP properties for CPUs The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing properties (clocks, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar Signed-off-by: Jisheng Zhang Signed-off-by: Olof Johansson --- arch/arm/boot/dts/berlin2.dtsi | 10 ++++++++++ arch/arm/boot/dts/berlin2q.dtsi | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index db67377af266..d2f7d984bba5 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -50,6 +50,16 @@ device_type = "cpu"; next-level-cache = <&l2>; reg = <1>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; }; }; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 516a7ce25791..99d6872a6dfc 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -45,6 +45,17 @@ device_type = "cpu"; next-level-cache = <&l2>; reg = <1>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; }; cpu2: cpu@2 { @@ -52,6 +63,17 @@ device_type = "cpu"; next-level-cache = <&l2>; reg = <2>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; }; cpu3: cpu@3 { @@ -59,6 +81,17 @@ device_type = "cpu"; next-level-cache = <&l2>; reg = <3>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; }; }; -- cgit v1.2.3 From eac058068107152ca176ec04c28e84499e596a49 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Wed, 18 Jul 2018 12:59:27 +0000 Subject: ARM: dts: exynos: Add missing interrupts for pwm node on Exynos5 Add missing GIC interrupts property for pwm nodes. Signed-off-by: Anand Moon Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 5d2f0a06fbef..67f9b4504a42 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -169,6 +169,11 @@ pwm: pwm@12dd0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x12DD0000 0x100>; + interrupts = , + , + , + , + ; samsung,pwm-outputs = <0>, <1>, <2>, <3>; #pwm-cells = <3>; }; -- cgit v1.2.3 From 8199e49ff1f654bbe8bed90fd6710bc097a89d02 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Wed, 30 May 2018 10:16:58 +0530 Subject: ARM: dts: r8a77(43|9[013]): Add missing OPP properties for CPUs The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing properties (like, clock latency, voltage tolerance, etc) as well to make it all work. Signed-off-by: Viresh Kumar Reviewed-by: Simon Horman Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 9 +++++++++ arch/arm/boot/dts/r8a7790.dtsi | 34 ++++++++++++++++++++++++++++++++-- arch/arm/boot/dts/r8a7791.dtsi | 14 ++++++++++++-- arch/arm/boot/dts/r8a7793.dtsi | 15 +++++++++++++-- 4 files changed, 66 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 142949d7066f..e4fb31c4f0ee 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -98,8 +98,17 @@ reg = <1>; clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; + clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7743_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; }; L2_CA15: cache-controller-0 { diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 4d06b154bd7e..c4324b1a2ec4 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -79,12 +79,12 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1300000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -104,6 +104,16 @@ power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu2: cpu@2 { @@ -115,6 +125,16 @@ power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu3: cpu@3 { @@ -126,6 +146,16 @@ power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu4: cpu@100 { diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 6e1dd7ad7bd6..d1d726a1364a 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -78,11 +78,11 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7791_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1500000 1000000>, @@ -101,6 +101,16 @@ clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; }; L2_CA15: cache-controller-0 { diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 4abecfc0ca98..1e6439b85a6b 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -70,10 +70,10 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7793_PD_CA15_CPU0>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1500000 1000000>, @@ -92,6 +92,17 @@ clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; power-domains = <&sysc R8A7793_PD_CA15_CPU1>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + next-level-cache = <&L2_CA15>; }; L2_CA15: cache-controller-0 { -- cgit v1.2.3 From cdbfaf640a23334a7bd2d8a8689051711a4e23c2 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 11 Jun 2018 23:49:36 +0900 Subject: ARM: dts: convert to SPDX identifier for Renesas boards Signed-off-by: Wolfram Sang Acked-by: Yoshihiro Shimoda Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/emev2-kzm9d.dts | 5 +---- arch/arm/boot/dts/emev2.dtsi | 5 +---- arch/arm/boot/dts/iwg20d-q7-common.dtsi | 5 +---- arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi | 5 +---- arch/arm/boot/dts/r7s72100-genmai.dts | 5 +---- arch/arm/boot/dts/r7s72100-gr-peach.dts | 5 +---- arch/arm/boot/dts/r7s72100-rskrza1.dts | 5 +---- arch/arm/boot/dts/r7s72100.dtsi | 5 +---- arch/arm/boot/dts/r8a73a4-ape6evm.dts | 5 +---- arch/arm/boot/dts/r8a73a4.dtsi | 5 +---- arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 5 +---- arch/arm/boot/dts/r8a7740.dtsi | 5 +---- arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts | 5 +---- arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 5 +---- arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 5 +---- arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 5 +---- arch/arm/boot/dts/r8a7743.dtsi | 5 +---- arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts | 5 +---- arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 5 +---- arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 5 +---- arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 5 +---- arch/arm/boot/dts/r8a7745.dtsi | 5 +---- arch/arm/boot/dts/r8a7778-bockw.dts | 5 +---- arch/arm/boot/dts/r8a7778.dtsi | 5 +---- arch/arm/boot/dts/r8a7779-marzen.dts | 5 +---- arch/arm/boot/dts/r8a7779.dtsi | 5 +---- arch/arm/boot/dts/r8a7790-lager.dts | 5 +---- arch/arm/boot/dts/r8a7790.dtsi | 5 +---- arch/arm/boot/dts/r8a7791-koelsch.dts | 5 +---- arch/arm/boot/dts/r8a7791-porter.dts | 5 +---- arch/arm/boot/dts/r8a7791.dtsi | 5 +---- arch/arm/boot/dts/r8a7792-blanche.dts | 5 +---- arch/arm/boot/dts/r8a7792-wheat.dts | 5 +---- arch/arm/boot/dts/r8a7792.dtsi | 5 +---- arch/arm/boot/dts/r8a7793-gose.dts | 5 +---- arch/arm/boot/dts/r8a7793.dtsi | 5 +---- arch/arm/boot/dts/r8a7794-alt.dts | 5 +---- arch/arm/boot/dts/r8a7794-silk.dts | 5 +---- arch/arm/boot/dts/r8a7794.dtsi | 5 +---- arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi | 5 +---- arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi | 5 +---- arch/arm/boot/dts/sh73a0-kzm9g.dts | 5 +---- arch/arm/boot/dts/sh73a0.dtsi | 5 +---- 43 files changed, 43 insertions(+), 172 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 0af44b7eadb9..1bb8e5c9d029 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the KZM9D board * * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index fec1241b858f..373ea8720769 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the EMEV2 SoC * * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi index 66954aaf2c47..5cae74eb6cdd 100644 --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi index 476273b3f994..0e99df218252 100644 --- a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi +++ b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ / { diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index 5af2a0116ff2..474baa0c7cfc 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Genmai board * * Copyright (C) 2013-14 Renesas Solutions Corp. * Copyright (C) 2014 Wolfram Sang, Sang Engineering - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts index 779f724b4531..fe1a4aa4d7cb 100644 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the GR-Peach board * * Copyright (C) 2017 Jacopo Mondi * Copyright (C) 2016 Renesas Electronics - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index 5dcaaf131d27..8ee44a100e9a 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the RZ/A1H RSK board * * Copyright (C) 2016 Renesas Electronics - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index a54822e97bac..2211f88ede2a 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r7s72100 SoC * * Copyright (C) 2013-14 Renesas Solutions Corp. * Copyright (C) 2014 Wolfram Sang, Sang Engineering - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 125c39c0222f..d530f451467e 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the APE6EVM board * * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 080d037f5733..dd865f3c2eda 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a73a4 SoC * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Magnus Damm - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 03b00d87b39b..32757caa2584 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the armadillo 800 eva board * * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index eb9a911deefb..383cba68dbba 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7740 SoC * * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts index d90eb8464222..327545119ee3 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index 6aa6b7467704..b683db4da8b1 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZ/G1M Qseven board * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi index d364685d9184..0e2e033cc849 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZG1M-20M Qseven SOM * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "r8a7743.dtsi" diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts index 3d918d106593..ca0e0fc9b246 100644 --- a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the SK-RZG1M board * * Copyright (C) 2016-2017 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index e4fb31c4f0ee..24715f74ae08 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7743 SoC * * Copyright (C) 2016-2017 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts index d34de8266ccd..2aeebfc9e4f1 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZG1E SODIMM carrier board + HDMI daughter * board * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "r8a7745-iwg22d-sodimm.dts" diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts index a4058f4cfbcd..1db220cfc1a1 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZG1E SODIMM carrier board * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi index 29b6e10fdf96..41f111b99a75 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "r8a7745.dtsi" diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts index b4d679b04ad6..655b10bb42d5 100644 --- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts +++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the SK-RZG1E board * * Copyright (C) 2016-2017 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 1cb7a7ab0418..c53f7ff20695 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7745 SoC * * Copyright (C) 2016-2017 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index c79d55eb43c5..de808d2ea856 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Reference Device Tree Source for the Bock-W board * @@ -8,10 +9,6 @@ * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 3b49f9ed2e2b..1bce16cc6b20 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for Renesas r8a7778 * @@ -8,10 +9,6 @@ * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index 4b9006bac3cb..a4d0038363f0 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Marzen board * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index e79ae306eedd..6b997bc016ee 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for Renesas r8a7779 * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 092610e3f953..50312e752e2f 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Lager board * * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded, Inc. * Copyright (C) 2015-2016 Renesas Electronics Corporation - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index c4324b1a2ec4..0925bdca438f 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7790 SoC * * Copyright (C) 2015 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 8ab793d8b2fd..ce22db01fbba 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Koelsch board * * Copyright (C) 2013 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index 5f77d73d7462..f02036e5de01 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Porter board * * Copyright (C) 2015 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index d1d726a1364a..991ac6feedd5 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7791 SoC * * Copyright (C) 2013-2015 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index 04fb70931b3b..f92301290b02 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Blanche board * * Copyright (C) 2014 Renesas Electronics Corporation * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index db01de7a3811..f46f4567b3d4 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Wheat board * * Copyright (C) 2016 Renesas Electronics Corporation * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index f44257dd86f6..63a978ec81cc 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7792 SoC * * Copyright (C) 2016 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index aa209f6e5d71..6b2f3a4fd13d 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Gose board * * Copyright (C) 2014-2015 Renesas Electronics Corporation - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 1e6439b85a6b..620a570307ff 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7793 SoC * * Copyright (C) 2014-2015 Renesas Electronics Corporation - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index e17027532941..ef7e2a837df6 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Alt board * * Copyright (C) 2014 Renesas Electronics Corporation - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 7808aaee6644..daec965889d3 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the SILK board * * Copyright (C) 2014 Renesas Electronics Corporation * Copyright (C) 2014-2015 Renesas Solutions Corp. * Copyright (C) 2014-2015 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 736196903d22..ea2ca4bdaf1c 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7794 SoC * * Copyright (C) 2014 Renesas Electronics Corporation * Copyright (C) 2014 Ulrich Hecht - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include diff --git a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi index 238d14bb0ebe..79fce67ebb1c 100644 --- a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi +++ b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Common file for the AA104XD12 panel connected to Renesas R-Car boards * * Copyright (C) 2014 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ / { diff --git a/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi index 04aafd479775..6e7589ea7562 100644 --- a/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi +++ b/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Common file for the AA121TD01 panel connected to Renesas R-Car boards * * Copyright (C) 2015 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ / { diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index 3d65f1f6d78b..daac0c6078c5 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the KZM-A9-GT board * @@ -5,10 +6,6 @@ * * Based on sh73a0-kzm9g.dts * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index c953648a5f41..e8f0a07c4564 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the SH73A0 SoC * * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include -- cgit v1.2.3 From 769d7248a7aae5dace1c5c776c98b352d3d93617 Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Thu, 14 Jun 2018 11:56:32 +0100 Subject: ARM: dts: Renesas R9A06G032 base device tree file This adds the Renesas R9A06G032 bare bone support. This currently only handles the SYSCTRL block note, generic parts (gic, architected timer) and a UART. Signed-off-by: Michel Pollet Reviewed-by: Geert Uytterhoeven [simon: updated MAINTAINERS file [simon: do not use r9a06g032-sysctrl.h as it is not in the renesas tree yet] Signed-off-by: Simon Horman --- MAINTAINERS | 1 + arch/arm/boot/dts/r9a06g032.dtsi | 113 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi (limited to 'arch/arm/boot/dts') diff --git a/MAINTAINERS b/MAINTAINERS index 9d5eeff51b5f..4c85ac04872d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1969,6 +1969,7 @@ S: Supported F: arch/arm/boot/dts/emev2* F: arch/arm/boot/dts/r7s* F: arch/arm/boot/dts/r8a* +F: arch/arm/boot/dts/r9a* F: arch/arm/boot/dts/sh* F: arch/arm/configs/shmobile_defconfig F: arch/arm/include/debug/renesas-scif.S diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi new file mode 100644 index 000000000000..339d0958011e --- /dev/null +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + */ + +#include + +/ { + compatible = "renesas,r9a06g032"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clocks = <&sysctrl 84>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clocks = <&sysctrl 84>; + }; + }; + + ext_jtag_clk: extjtagclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ext_mclk: extmclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + + ext_rgmii_ref: extrgmiiref { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ext_rtc_clk: extrtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + sysctrl: system-controller@4000c000 { + compatible = "renesas,r9a06g032-sysctrl"; + reg = <0x4000c000 0x1000>; + status = "okay"; + #clock-cells = <1>; + + clocks = <&ext_mclk>, <&ext_rtc_clk>, + <&ext_jtag_clk>, <&ext_rgmii_ref>; + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + }; + + uart0: serial@40060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x40060000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl 146>; + clock-names = "baudclk"; + status = "disabled"; + }; + + gic: gic@44101000 { + compatible = "arm,cortex-a7-gic", "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x44101000 0x1000>, /* Distributer */ + <0x44102000 0x2000>, /* CPU interface */ + <0x44104000 0x2000>, /* Virt interface control */ + <0x44106000 0x2000>; /* Virt CPU interface */ + interrupts = + ; + }; + }; + + timer { + compatible = "arm,cortex-a7-timer", + "arm,armv7-timer"; + interrupt-parent = <&gic>; + arm,cpu-registers-not-fw-configured; + always-on; + interrupts = + , + , + , + ; + }; +}; -- cgit v1.2.3 From df7112c9461458c2a2069e9a4a7962fd16bf62bf Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Thu, 14 Jun 2018 11:56:33 +0100 Subject: ARM: dts: Renesas RZN1D-DB Board base file This adds a base device tree file for the RZN1-DB board, with only the basic support allowing the system to boot to a prompt. Only one UART is used, with only a single CPU running. Signed-off-by: Michel Pollet Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..c07f077d8e99 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -819,6 +819,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a7793-gose.dtb \ r8a7794-alt.dtb \ r8a7794-silk.dtb \ + r9a06g032-rzn1d400-db.dtb \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1108-evb.dtb \ diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts new file mode 100644 index 000000000000..4e57ae2688fc --- /dev/null +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZN1D-DB Board + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + */ + +/dts-v1/; + +#include "r9a06g032.dtsi" + +/ { + model = "RZN1D-DB Board"; + compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3 From f8fc94dbcf2d166b865991afb6c827aa56dc0de2 Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Thu, 28 Jun 2018 09:17:14 +0100 Subject: ARM: dts: Renesas R9A06G032 SMP enable method Add a special enable method for the second CA7 of the R9A06G032 as well as the default value for the "cpu-release-addr" property. Signed-off-by: Michel Pollet Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r9a06g032.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 339d0958011e..afe29c95a006 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -29,6 +29,8 @@ compatible = "arm,cortex-a7"; reg = <1>; clocks = <&sysctrl 84>; + enable-method = "renesas,r9a06g032-smp"; + cpu-release-addr = <0 0x4000c204>; }; }; -- cgit v1.2.3 From c85aabb841f5ed544b492544e8280f2a9c1cc647 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 3 Jul 2018 22:41:09 +0200 Subject: ARM: dts: gr-peach: Add GR-Peach audiocamerashield support Add device tree header for GR-Peach's audiocamerashield with MT9V111 image sensor. Signed-off-by: Jacopo Mondi Reviewed-by: Simon Horman Signed-off-by: Simon Horman --- arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi | 79 +++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi b/arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi new file mode 100644 index 000000000000..e31a9e3c18a2 --- /dev/null +++ b/arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the GR-Peach audiocamera shield expansion board + * + * Copyright (C) 2017 Jacopo Mondi + */ + +#include "r7s72100.dtsi" +#include +#include + +/ { + /* On-board camera clock. */ + camera_clk: camera_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + +&pinctrl { + i2c1_pins: i2c1 { + /* P1_2 as SCL; P1_3 as SDA */ + pinmux = , ; + }; + + vio_pins: vio { + /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */ + pinmux = , /* VIO_VD */ + , /* VIO_HD */ + , /* VIO_D0 */ + , /* VIO_D1 */ + , /* VIO_D2 */ + , /* VIO_D3 */ + , /* VIO_D4 */ + , /* VIO_D5 */ + , /* VIO_D6 */ + , /* VIO_D7 */ + ; /* VIO_CLK */ + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <100000>; + + camera@48 { + compatible = "aptina,mt9v111"; + reg = <0x48>; + + clocks = <&camera_clk>; + + port { + mt9v111_out: endpoint { + remote-endpoint = <&ceu_in>; + }; + }; + }; +}; + +&ceu { + pinctrl-names = "default"; + pinctrl-0 = <&vio_pins>; + + status = "okay"; + + port { + ceu_in: endpoint { + hsync-active = <1>; + vsync-active = <1>; + bus-width = <8>; + pclk-sample = <1>; + remote-endpoint = <&mt9v111_out>; + }; + }; +}; -- cgit v1.2.3 From c03e2f12a2967f1639ee53299b72922ee3472528 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Jul 2018 15:25:49 +0200 Subject: ARM: dts: r8a77470: Use r8a77470-cpg-mssr binding definitions Replace the hardcoded clock indices by R8A77470_CLK_* symbols. Signed-off-by: Geert Uytterhoeven Reviewed-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index c85032f9605b..87d32d3e23de 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -7,7 +7,7 @@ #include #include -#include +#include / { compatible = "renesas,r8a77470"; #address-cells = <2>; @@ -22,7 +22,7 @@ compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE 0>; + clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; power-domains = <&sysc 5>; next-level-cache = <&L2_CA7>; }; @@ -209,7 +209,7 @@ reg = <0 0xe6e60000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE 5>, <&scif_clk>; + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; @@ -225,7 +225,7 @@ reg = <0 0xe6e68000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE 5>, <&scif_clk>; + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; @@ -241,7 +241,7 @@ reg = <0 0xe6e58000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE 5>, <&scif_clk>; + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; @@ -257,7 +257,7 @@ reg = <0 0xe6ea8000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE 5>, <&scif_clk>; + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, <&dmac1 0x2f>, <&dmac1 0x30>; @@ -273,7 +273,7 @@ reg = <0 0xe6ee0000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 715>, - <&cpg CPG_CORE 5>, <&scif_clk>; + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, <&dmac1 0xfb>, <&dmac1 0xfc>; @@ -289,7 +289,7 @@ reg = <0 0xe6ee8000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 714>, - <&cpg CPG_CORE 5>, <&scif_clk>; + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, <&dmac1 0xfd>, <&dmac1 0xfe>; -- cgit v1.2.3 From 43efe4fab743149df2310c3293c8f7f4fb3a53e1 Mon Sep 17 00:00:00 2001 From: Simon Shields Date: Sat, 21 Jul 2018 22:50:49 +1000 Subject: ARM: dts: exynos: Add max77693 pinctrl config for Midas Currently, we assume that the bootloader has correctly configured the interrupt pin for max77693. This might not actually be the case - so it's better to configure it explicitly. Signed-off-by: Simon Shields Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-midas.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index dc11ca1673e8..4a194a35b8a0 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -138,6 +138,8 @@ compatible = "maxim,max77693"; interrupt-parent = <&gpx1>; interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&max77693_irq>; reg = <0x66>; regulators { @@ -1007,6 +1009,11 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep1>; + max77693_irq: max77693-irq { + samsung,pins = "gpx1-5"; + samsung,pin-pud = ; + }; + hdmi_hpd: hdmi-hpd { samsung,pins = "gpx3-7"; samsung,pin-pud = ; -- cgit v1.2.3 From 492413dd6d19448c40e2ac946b65f8e60dd306e1 Mon Sep 17 00:00:00 2001 From: Simon Shields Date: Sat, 21 Jul 2018 22:50:50 +1000 Subject: ARM: dts: exynos: Add pinctrl config for Midas keys This pins are externally pulled up, and so we should explicitly configure them to disable the SoC-internal pull-downs. Previously we relied on the bootloader doing this in order to allow the buttons to function properly. Signed-off-by: Simon Shields Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-midas.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 4a194a35b8a0..635e5ea87a6c 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -94,6 +94,8 @@ gpio-keys { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; key-down { gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; @@ -1009,6 +1011,11 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep1>; + gpio_keys: gpio-keys { + samsung,pins = "gpx0-1", "gpx2-2", "gpx2-7", "gpx3-3"; + samsung,pin-pud = ; + }; + max77693_irq: max77693-irq { samsung,pins = "gpx1-5"; samsung,pin-pud = ; -- cgit v1.2.3 From e2bae133b5c41af3fd82f26edfa3222242a7ae6e Mon Sep 17 00:00:00 2001 From: Simon Shields Date: Sat, 21 Jul 2018 22:50:51 +1000 Subject: ARM: dts: exynos: Add pinctrl for Midas fuelgauge IRQ pin This pin is externally pulled up, so we should disable the SoC's pull down resistor in order for the interrupt to function properly. Signed-off-by: Simon Shields Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-midas.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 635e5ea87a6c..58b298d8441c 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -188,6 +188,8 @@ compatible = "maxim,max17047"; interrupt-parent = <&gpx2>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&max77693_fuel_irq>; reg = <0x36>; maxim,over-heat-temp = <700>; @@ -1021,6 +1023,11 @@ samsung,pin-pud = ; }; + max77693_fuel_irq: max77693-fuel-irq { + samsung,pins = "gpx2-3"; + samsung,pin-pud = ; + }; + hdmi_hpd: hdmi-hpd { samsung,pins = "gpx3-7"; samsung,pin-pud = ; -- cgit v1.2.3 From 73d2f79471f85bd9931e5e88307049e490f10970 Mon Sep 17 00:00:00 2001 From: Simon Shields Date: Sat, 21 Jul 2018 22:50:52 +1000 Subject: ARM: dts: exynos: Configure max77686 IRQ pin on Midas This pin is externally pulled up, so we need to disable the SoC's internal pull-down. Signed-off-by: Simon Shields Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-midas.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 58b298d8441c..dd56e4d53145 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -580,6 +580,8 @@ compatible = "maxim,max77686"; interrupt-parent = <&gpx0>; interrupts = <7 IRQ_TYPE_NONE>; + pinctrl-0 = <&max77686_irq>; + pinctrl-names = "default"; reg = <0x09>; #clock-cells = <1>; @@ -1018,6 +1020,11 @@ samsung,pin-pud = ; }; + max77686_irq: max77686-irq { + samsung,pins = "gpx0-7"; + samsung,pin-pud = ; + }; + max77693_irq: max77693-irq { samsung,pins = "gpx1-5"; samsung,pin-pud = ; -- cgit v1.2.3 From 965228d33cd2b47adb493bb1864761420c632e41 Mon Sep 17 00:00:00 2001 From: Simon Shields Date: Sat, 21 Jul 2018 22:50:53 +1000 Subject: ARM: dts: exynos: Configure Midas SD card CD pin This pin is externally pulled up, so we need to disable the SoC's internal pull down resistor to allow it to function properly. Signed-off-by: Simon Shields Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-midas.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index dd56e4d53145..c0476c290977 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -1035,6 +1035,11 @@ samsung,pin-pud = ; }; + sdhci2_cd: sdhci2-cd-irq { + samsung,pins = "gpx3-4"; + samsung,pin-pud = ; + }; + hdmi_hpd: hdmi-hpd { samsung,pins = "gpx3-7"; samsung,pin-pud = ; @@ -1266,7 +1271,7 @@ bus-width = <4>; cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; cd-inverted; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; pinctrl-names = "default"; vmmc-supply = <&ldo21_reg>; status = "okay"; -- cgit v1.2.3 From c0476a31fb381e02637549bfe45632a4140dd201 Mon Sep 17 00:00:00 2001 From: Steven Vanden Branden Date: Mon, 23 Jul 2018 18:09:54 +0200 Subject: ARM: dts: sun4i: Add GPU node Add mali gpu node to sun4i a10 platforms. Tested with offscreen rendering with lima mesa (freedesktop gitlab) Signed-off-by: Steven Vanden Branden Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 82f81f06f201..3d62a8950720 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -1001,6 +1001,27 @@ status = "disabled"; }; + mali: gpu@1c40000 { + compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = <69>, + <70>, + <71>, + <72>, + <73>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pmu"; + clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_GPU>; + + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; + fe0: display-frontend@1e00000 { compatible = "allwinner,sun4i-a10-display-frontend"; reg = <0x01e00000 0x20000>; -- cgit v1.2.3 From 2450ceaf21798183f51bfdbd7d314635dbb62f4c Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 24 Jul 2018 14:24:02 +1000 Subject: ARM: dts: aspeed: Add coprocessor interrupt controller Add a node for the CVIC (the coprocessor interrupt controller) and add a label to the SRAM node so it can be referenced from the board device-tree file. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 8 +++++++- arch/arm/boot/dts/aspeed-g5.dtsi | 9 ++++++++- 2 files changed, 15 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 680336ac06f8..b23a983f95a5 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -92,6 +92,12 @@ reg = <0x1e6c0080 0x80>; }; + cvic: copro-interrupt-controller@1e6c2000 { + compatible = "aspeed,ast2400-cvic", "aspeed-cvic"; + valid-sources = <0x7fffffff>; + reg = <0x1e6c2000 0x80>; + }; + mac0: ethernet@1e660000 { compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; reg = <0x1e660000 0x180>; @@ -177,7 +183,7 @@ status = "disabled"; }; - sram@1e720000 { + sram: sram@1e720000 { compatible = "mmio-sram"; reg = <0x1e720000 0x8000>; // 32K }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 02e70ad3ab70..87fdc146ff52 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -127,6 +127,13 @@ reg = <0x1e6c0080 0x80>; }; + cvic: copro-interrupt-controller@1e6c2000 { + compatible = "aspeed,ast2500-cvic", "aspeed-cvic"; + valid-sources = <0xffffffff>; + copro-sw-interrupts = <1>; + reg = <0x1e6c2000 0x80>; + }; + mac0: ethernet@1e660000 { compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e660000 0x180>; @@ -229,7 +236,7 @@ status = "disabled"; }; - sram@1e720000 { + sram: sram@1e720000 { compatible = "mmio-sram"; reg = <0x1e720000 0x9000>; // 36K }; -- cgit v1.2.3 From 3723c63247854c97fe044c12a40e29043e9bbc1b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 23 Aug 2018 17:01:26 -0700 Subject: treewide: convert ISO_8859-1 text comments to utf-8 Almost all files in the kernel are either plain text or UTF-8 encoded. A couple however are ISO_8859-1, usually just a few characters in a C comments, for historic reasons. This converts them all to UTF-8 for consistency. Link: http://lkml.kernel.org/r/20180724111600.4158975-1-arnd@arndb.de Signed-off-by: Arnd Bergmann Acked-by: Simon Horman [IPVS portion] Acked-by: Jonathan Cameron [IIO] Acked-by: Michael Ellerman [powerpc] Acked-by: Rob Herring Cc: Joe Perches Cc: Arnd Bergmann Cc: Samuel Ortiz Cc: "David S. Miller" Cc: Rob Herring Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- .../devicetree/bindings/net/nfc/pn544.txt | 2 +- arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 2 +- arch/arm/crypto/sha256_glue.c | 2 +- arch/arm/crypto/sha256_neon_glue.c | 4 +- drivers/crypto/vmx/ghashp8-ppc.pl | 12 +-- drivers/iio/dac/ltc2632.c | 2 +- drivers/power/reset/ltc2952-poweroff.c | 4 +- kernel/events/callchain.c | 2 +- net/netfilter/ipvs/Kconfig | 8 +- net/netfilter/ipvs/ip_vs_mh.c | 4 +- tools/power/cpupower/po/de.po | 44 ++++---- tools/power/cpupower/po/fr.po | 120 ++++++++++----------- 12 files changed, 103 insertions(+), 103 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/net/nfc/pn544.txt b/Documentation/devicetree/bindings/net/nfc/pn544.txt index 5b937403fed6..92f399ec22b8 100644 --- a/Documentation/devicetree/bindings/net/nfc/pn544.txt +++ b/Documentation/devicetree/bindings/net/nfc/pn544.txt @@ -2,7 +2,7 @@ Required properties: - compatible: Should be "nxp,pn544-i2c". -- clock-frequency: I²C work frequency. +- clock-frequency: I²C work frequency. - reg: address on the bus - interrupts: GPIO interrupt to which the chip is connected - enable-gpios: Output GPIO pin used for enabling/disabling the PN544 diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index 5d096528e75a..71c27ea0b53e 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -1,7 +1,7 @@ /* * Copyright 2014 Open Source Support GmbH * - * David Lanzendörfer + * David Lanzendörfer * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual diff --git a/arch/arm/crypto/sha256_glue.c b/arch/arm/crypto/sha256_glue.c index bf8ccff2c9d0..0ae900e778f3 100644 --- a/arch/arm/crypto/sha256_glue.c +++ b/arch/arm/crypto/sha256_glue.c @@ -2,7 +2,7 @@ * Glue code for the SHA256 Secure Hash Algorithm assembly implementation * using optimized ARM assembler and NEON instructions. * - * Copyright © 2015 Google Inc. + * Copyright © 2015 Google Inc. * * This file is based on sha256_ssse3_glue.c: * Copyright (C) 2013 Intel Corporation diff --git a/arch/arm/crypto/sha256_neon_glue.c b/arch/arm/crypto/sha256_neon_glue.c index 9bbee56fbdc8..1d82c6cd31a4 100644 --- a/arch/arm/crypto/sha256_neon_glue.c +++ b/arch/arm/crypto/sha256_neon_glue.c @@ -2,10 +2,10 @@ * Glue code for the SHA256 Secure Hash Algorithm assembly implementation * using NEON instructions. * - * Copyright © 2015 Google Inc. + * Copyright © 2015 Google Inc. * * This file is based on sha512_neon_glue.c: - * Copyright © 2014 Jussi Kivilinna + * Copyright © 2014 Jussi Kivilinna * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free diff --git a/drivers/crypto/vmx/ghashp8-ppc.pl b/drivers/crypto/vmx/ghashp8-ppc.pl index f746af271460..38b06503ede0 100644 --- a/drivers/crypto/vmx/ghashp8-ppc.pl +++ b/drivers/crypto/vmx/ghashp8-ppc.pl @@ -129,9 +129,9 @@ $code=<<___; le?vperm $IN,$IN,$IN,$lemask vxor $zero,$zero,$zero - vpmsumd $Xl,$IN,$Hl # H.lo·Xi.lo - vpmsumd $Xm,$IN,$H # H.hi·Xi.lo+H.lo·Xi.hi - vpmsumd $Xh,$IN,$Hh # H.hi·Xi.hi + vpmsumd $Xl,$IN,$Hl # H.lo·Xi.lo + vpmsumd $Xm,$IN,$H # H.hi·Xi.lo+H.lo·Xi.hi + vpmsumd $Xh,$IN,$Hh # H.hi·Xi.hi vpmsumd $t2,$Xl,$xC2 # 1st phase @@ -187,11 +187,11 @@ $code=<<___; .align 5 Loop: subic $len,$len,16 - vpmsumd $Xl,$IN,$Hl # H.lo·Xi.lo + vpmsumd $Xl,$IN,$Hl # H.lo·Xi.lo subfe. r0,r0,r0 # borrow?-1:0 - vpmsumd $Xm,$IN,$H # H.hi·Xi.lo+H.lo·Xi.hi + vpmsumd $Xm,$IN,$H # H.hi·Xi.lo+H.lo·Xi.hi and r0,r0,$len - vpmsumd $Xh,$IN,$Hh # H.hi·Xi.hi + vpmsumd $Xh,$IN,$Hh # H.hi·Xi.hi add $inp,$inp,r0 vpmsumd $t2,$Xl,$xC2 # 1st phase diff --git a/drivers/iio/dac/ltc2632.c b/drivers/iio/dac/ltc2632.c index 28e9b7656b20..15d498fc4758 100644 --- a/drivers/iio/dac/ltc2632.c +++ b/drivers/iio/dac/ltc2632.c @@ -1,7 +1,7 @@ /* * LTC2632 Digital to analog convertors spi driver * - * Copyright 2017 Maxime Roussin-Bélanger + * Copyright 2017 Maxime Roussin-Bélanger * expanded by Silvan Murer * * Licensed under the GPL-2. diff --git a/drivers/power/reset/ltc2952-poweroff.c b/drivers/power/reset/ltc2952-poweroff.c index 6b911b6b10a6..c484584745bc 100644 --- a/drivers/power/reset/ltc2952-poweroff.c +++ b/drivers/power/reset/ltc2952-poweroff.c @@ -2,7 +2,7 @@ * LTC2952 (PowerPath) driver * * Copyright (C) 2014, Xsens Technologies BV - * Maintainer: René Moll + * Maintainer: René Moll * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -319,6 +319,6 @@ static struct platform_driver ltc2952_poweroff_driver = { module_platform_driver(ltc2952_poweroff_driver); -MODULE_AUTHOR("René Moll "); +MODULE_AUTHOR("René Moll "); MODULE_DESCRIPTION("LTC PowerPath power-off driver"); MODULE_LICENSE("GPL v2"); diff --git a/kernel/events/callchain.c b/kernel/events/callchain.c index c187aa3df3c8..24a77c34e9ad 100644 --- a/kernel/events/callchain.c +++ b/kernel/events/callchain.c @@ -4,7 +4,7 @@ * Copyright (C) 2008 Thomas Gleixner * Copyright (C) 2008-2011 Red Hat, Inc., Ingo Molnar * Copyright (C) 2008-2011 Red Hat, Inc., Peter Zijlstra - * Copyright © 2009 Paul Mackerras, IBM Corp. + * Copyright © 2009 Paul Mackerras, IBM Corp. * * For licensing details see kernel-base/COPYING */ diff --git a/net/netfilter/ipvs/Kconfig b/net/netfilter/ipvs/Kconfig index 05dc1b77e466..cad48d07c818 100644 --- a/net/netfilter/ipvs/Kconfig +++ b/net/netfilter/ipvs/Kconfig @@ -296,10 +296,10 @@ config IP_VS_MH_TAB_INDEX stored in a hash table. This table is assigned by a preference list of the positions to each destination until all slots in the table are filled. The index determines the prime for size of - the table as 251, 509, 1021, 2039, 4093, 8191, 16381, 32749, - 65521 or 131071. When using weights to allow destinations to - receive more connections, the table is assigned an amount - proportional to the weights specified. The table needs to be large + the table as 251, 509, 1021, 2039, 4093, 8191, 16381, 32749, + 65521 or 131071. When using weights to allow destinations to + receive more connections, the table is assigned an amount + proportional to the weights specified. The table needs to be large enough to effectively fit all the destinations multiplied by their respective weights. diff --git a/net/netfilter/ipvs/ip_vs_mh.c b/net/netfilter/ipvs/ip_vs_mh.c index 0f795b186eb3..94d9d349ebb0 100644 --- a/net/netfilter/ipvs/ip_vs_mh.c +++ b/net/netfilter/ipvs/ip_vs_mh.c @@ -5,10 +5,10 @@ * */ -/* The mh algorithm is to assign a preference list of all the lookup +/* The mh algorithm is to assign a preference list of all the lookup * table positions to each destination and populate the table with * the most-preferred position of destinations. Then it is to select - * destination with the hash key of source IP address through looking + * destination with the hash key of source IP address through looking * up a the lookup table. * * The algorithm is detailed in: diff --git a/tools/power/cpupower/po/de.po b/tools/power/cpupower/po/de.po index 78c09e51663a..840c17cc450a 100644 --- a/tools/power/cpupower/po/de.po +++ b/tools/power/cpupower/po/de.po @@ -323,12 +323,12 @@ msgstr " Hardwarebedingte Grenzen der Taktfrequenz: " #: utils/cpufreq-info.c:256 #, c-format msgid " available frequency steps: " -msgstr " mögliche Taktfrequenzen: " +msgstr " mögliche Taktfrequenzen: " #: utils/cpufreq-info.c:269 #, c-format msgid " available cpufreq governors: " -msgstr " mögliche Regler: " +msgstr " mögliche Regler: " #: utils/cpufreq-info.c:280 #, c-format @@ -381,7 +381,7 @@ msgstr "Optionen:\n" msgid " -e, --debug Prints out debug information [default]\n" msgstr "" " -e, --debug Erzeugt detaillierte Informationen, hilfreich\n" -" zum Aufspüren von Fehlern\n" +" zum Aufspüren von Fehlern\n" #: utils/cpufreq-info.c:475 #, c-format @@ -424,7 +424,7 @@ msgstr " -p, --policy Findet die momentane Taktik heraus *\n" #: utils/cpufreq-info.c:482 #, c-format msgid " -g, --governors Determines available cpufreq governors *\n" -msgstr " -g, --governors Erzeugt eine Liste mit verfügbaren Reglern *\n" +msgstr " -g, --governors Erzeugt eine Liste mit verfügbaren Reglern *\n" #: utils/cpufreq-info.c:483 #, c-format @@ -450,7 +450,7 @@ msgstr "" #, c-format msgid " -s, --stats Shows cpufreq statistics if available\n" msgstr "" -" -s, --stats Zeigt, sofern möglich, Statistiken über cpufreq an.\n" +" -s, --stats Zeigt, sofern möglich, Statistiken über cpufreq an.\n" #: utils/cpufreq-info.c:487 #, c-format @@ -473,9 +473,9 @@ msgid "" "cpufreq\n" " interface in 2.4. and early 2.6. kernels\n" msgstr "" -" -o, --proc Erzeugt Informationen in einem ähnlichem Format zu " +" -o, --proc Erzeugt Informationen in einem ähnlichem Format zu " "dem\n" -" der /proc/cpufreq-Datei in 2.4. und frühen 2.6.\n" +" der /proc/cpufreq-Datei in 2.4. und frühen 2.6.\n" " Kernel-Versionen\n" #: utils/cpufreq-info.c:491 @@ -491,7 +491,7 @@ msgstr "" #: utils/cpufreq-info.c:492 utils/cpuidle-info.c:152 #, c-format msgid " -h, --help Prints out this screen\n" -msgstr " -h, --help Gibt diese Kurzübersicht aus\n" +msgstr " -h, --help Gibt diese Kurzübersicht aus\n" #: utils/cpufreq-info.c:495 #, c-format @@ -501,7 +501,7 @@ msgid "" msgstr "" "Sofern kein anderer Parameter als '-c, --cpu' angegeben wird, liefert " "dieses\n" -"Programm Informationen, die z.B. zum Berichten von Fehlern nützlich sind.\n" +"Programm Informationen, die z.B. zum Berichten von Fehlern nützlich sind.\n" #: utils/cpufreq-info.c:497 #, c-format @@ -557,7 +557,7 @@ msgid "" "select\n" msgstr "" " -d FREQ, --min FREQ neue minimale Taktfrequenz, die der Regler\n" -" auswählen darf\n" +" auswählen darf\n" #: utils/cpufreq-set.c:28 #, c-format @@ -566,7 +566,7 @@ msgid "" "select\n" msgstr "" " -u FREQ, --max FREQ neue maximale Taktfrequenz, die der Regler\n" -" auswählen darf\n" +" auswählen darf\n" #: utils/cpufreq-set.c:29 #, c-format @@ -579,20 +579,20 @@ msgid "" " -f FREQ, --freq FREQ specific frequency to be set. Requires userspace\n" " governor to be available and loaded\n" msgstr "" -" -f FREQ, --freq FREQ setze exakte Taktfrequenz. Benötigt den Regler\n" +" -f FREQ, --freq FREQ setze exakte Taktfrequenz. Benötigt den Regler\n" " 'userspace'.\n" #: utils/cpufreq-set.c:32 #, c-format msgid " -r, --related Switches all hardware-related CPUs\n" msgstr "" -" -r, --related Setze Werte für alle CPUs, deren Taktfrequenz\n" +" -r, --related Setze Werte für alle CPUs, deren Taktfrequenz\n" " hardwarebedingt identisch ist.\n" #: utils/cpufreq-set.c:33 utils/cpupower-set.c:28 utils/cpupower-info.c:27 #, c-format msgid " -h, --help Prints out this screen\n" -msgstr " -h, --help Gibt diese Kurzübersicht aus\n" +msgstr " -h, --help Gibt diese Kurzübersicht aus\n" #: utils/cpufreq-set.c:35 #, fuzzy, c-format @@ -618,8 +618,8 @@ msgstr "" " angenommen\n" "2. Der Parameter -f bzw. --freq kann mit keinem anderen als dem Parameter\n" " -c bzw. --cpu kombiniert werden\n" -"3. FREQuenzen können in Hz, kHz (Standard), MHz, GHz oder THz eingegeben\n" -" werden, indem der Wert und unmittelbar anschließend (ohne Leerzeichen!)\n" +"3. FREQuenzen können in Hz, kHz (Standard), MHz, GHz oder THz eingegeben\n" +" werden, indem der Wert und unmittelbar anschließend (ohne Leerzeichen!)\n" " die Einheit angegeben werden. (Bsp: 1GHz )\n" " (FREQuenz in kHz =^ MHz * 1000 =^ GHz * 1000000).\n" @@ -638,7 +638,7 @@ msgid "" msgstr "" "Beim Einstellen ist ein Fehler aufgetreten. Typische Fehlerquellen sind:\n" "- nicht ausreichende Rechte (Administrator)\n" -"- der Regler ist nicht verfügbar bzw. nicht geladen\n" +"- der Regler ist nicht verfügbar bzw. nicht geladen\n" "- die angegebene Taktik ist inkorrekt\n" "- eine spezifische Frequenz wurde angegeben, aber der Regler 'userspace'\n" " kann entweder hardwarebedingt nicht genutzt werden oder ist nicht geladen\n" @@ -821,7 +821,7 @@ msgstr "" #: utils/cpuidle-info.c:48 #, fuzzy, c-format msgid "Available idle states:" -msgstr " mögliche Taktfrequenzen: " +msgstr " mögliche Taktfrequenzen: " #: utils/cpuidle-info.c:71 #, c-format @@ -924,7 +924,7 @@ msgstr "Aufruf: cpufreq-info [Optionen]\n" msgid " -s, --silent Only show general C-state information\n" msgstr "" " -e, --debug Erzeugt detaillierte Informationen, hilfreich\n" -" zum Aufspüren von Fehlern\n" +" zum Aufspüren von Fehlern\n" #: utils/cpuidle-info.c:150 #, fuzzy, c-format @@ -933,9 +933,9 @@ msgid "" "acpi/processor/*/power\n" " interface in older kernels\n" msgstr "" -" -o, --proc Erzeugt Informationen in einem ähnlichem Format zu " +" -o, --proc Erzeugt Informationen in einem ähnlichem Format zu " "dem\n" -" der /proc/cpufreq-Datei in 2.4. und frühen 2.6.\n" +" der /proc/cpufreq-Datei in 2.4. und frühen 2.6.\n" " Kernel-Versionen\n" #: utils/cpuidle-info.c:209 @@ -949,7 +949,7 @@ msgstr "" #~ " -c CPU, --cpu CPU CPU number which information shall be determined " #~ "about\n" #~ msgstr "" -#~ " -c CPU, --cpu CPU Nummer der CPU, über die Informationen " +#~ " -c CPU, --cpu CPU Nummer der CPU, über die Informationen " #~ "herausgefunden werden sollen\n" #~ msgid "" diff --git a/tools/power/cpupower/po/fr.po b/tools/power/cpupower/po/fr.po index 245ad20a9bf9..b46ca2548f86 100644 --- a/tools/power/cpupower/po/fr.po +++ b/tools/power/cpupower/po/fr.po @@ -212,7 +212,7 @@ msgstr "" #: utils/cpupower.c:91 #, c-format msgid "Report errors and bugs to %s, please.\n" -msgstr "Veuillez rapportez les erreurs et les bogues à %s, s'il vous plait.\n" +msgstr "Veuillez rapportez les erreurs et les bogues à %s, s'il vous plait.\n" #: utils/cpupower.c:114 #, c-format @@ -227,14 +227,14 @@ msgstr "" #: utils/cpufreq-info.c:31 #, c-format msgid "Couldn't count the number of CPUs (%s: %s), assuming 1\n" -msgstr "Détermination du nombre de CPUs (%s : %s) impossible. Assume 1\n" +msgstr "Détermination du nombre de CPUs (%s : %s) impossible. Assume 1\n" #: utils/cpufreq-info.c:63 #, c-format msgid "" " minimum CPU frequency - maximum CPU frequency - governor\n" msgstr "" -" Fréquence CPU minimale - Fréquence CPU maximale - régulateur\n" +" Fréquence CPU minimale - Fréquence CPU maximale - régulateur\n" #: utils/cpufreq-info.c:151 #, c-format @@ -302,12 +302,12 @@ msgstr " pilote : %s\n" #: utils/cpufreq-info.c:219 #, fuzzy, c-format msgid " CPUs which run at the same hardware frequency: " -msgstr " CPUs qui doivent changer de fréquences en même temps : " +msgstr " CPUs qui doivent changer de fréquences en même temps : " #: utils/cpufreq-info.c:230 #, fuzzy, c-format msgid " CPUs which need to have their frequency coordinated by software: " -msgstr " CPUs qui doivent changer de fréquences en même temps : " +msgstr " CPUs qui doivent changer de fréquences en même temps : " #: utils/cpufreq-info.c:241 #, c-format @@ -317,22 +317,22 @@ msgstr "" #: utils/cpufreq-info.c:247 #, c-format msgid " hardware limits: " -msgstr " limitation matérielle : " +msgstr " limitation matérielle : " #: utils/cpufreq-info.c:256 #, c-format msgid " available frequency steps: " -msgstr " plage de fréquence : " +msgstr " plage de fréquence : " #: utils/cpufreq-info.c:269 #, c-format msgid " available cpufreq governors: " -msgstr " régulateurs disponibles : " +msgstr " régulateurs disponibles : " #: utils/cpufreq-info.c:280 #, c-format msgid " current policy: frequency should be within " -msgstr " tactique actuelle : la fréquence doit être comprise entre " +msgstr " tactique actuelle : la fréquence doit être comprise entre " #: utils/cpufreq-info.c:282 #, c-format @@ -345,18 +345,18 @@ msgid "" "The governor \"%s\" may decide which speed to use\n" " within this range.\n" msgstr "" -"Le régulateur \"%s\" est libre de choisir la vitesse\n" -" dans cette plage de fréquences.\n" +"Le régulateur \"%s\" est libre de choisir la vitesse\n" +" dans cette plage de fréquences.\n" #: utils/cpufreq-info.c:293 #, c-format msgid " current CPU frequency is " -msgstr " la fréquence actuelle de ce CPU est " +msgstr " la fréquence actuelle de ce CPU est " #: utils/cpufreq-info.c:296 #, c-format msgid " (asserted by call to hardware)" -msgstr " (vérifié par un appel direct du matériel)" +msgstr " (vérifié par un appel direct du matériel)" #: utils/cpufreq-info.c:304 #, c-format @@ -377,7 +377,7 @@ msgstr "Options :\n" #: utils/cpufreq-info.c:474 #, fuzzy, c-format msgid " -e, --debug Prints out debug information [default]\n" -msgstr " -e, --debug Afficher les informations de déboguage\n" +msgstr " -e, --debug Afficher les informations de déboguage\n" #: utils/cpufreq-info.c:475 #, c-format @@ -385,8 +385,8 @@ msgid "" " -f, --freq Get frequency the CPU currently runs at, according\n" " to the cpufreq core *\n" msgstr "" -" -f, --freq Obtenir la fréquence actuelle du CPU selon le point\n" -" de vue du coeur du système de cpufreq *\n" +" -f, --freq Obtenir la fréquence actuelle du CPU selon le point\n" +" de vue du coeur du système de cpufreq *\n" #: utils/cpufreq-info.c:477 #, c-format @@ -394,8 +394,8 @@ msgid "" " -w, --hwfreq Get frequency the CPU currently runs at, by reading\n" " it from hardware (only available to root) *\n" msgstr "" -" -w, --hwfreq Obtenir la fréquence actuelle du CPU directement par\n" -" le matériel (doit être root) *\n" +" -w, --hwfreq Obtenir la fréquence actuelle du CPU directement par\n" +" le matériel (doit être root) *\n" #: utils/cpufreq-info.c:479 #, c-format @@ -403,13 +403,13 @@ msgid "" " -l, --hwlimits Determine the minimum and maximum CPU frequency " "allowed *\n" msgstr "" -" -l, --hwlimits Affiche les fréquences minimales et maximales du CPU " +" -l, --hwlimits Affiche les fréquences minimales et maximales du CPU " "*\n" #: utils/cpufreq-info.c:480 #, c-format msgid " -d, --driver Determines the used cpufreq kernel driver *\n" -msgstr " -d, --driver Affiche le pilote cpufreq utilisé *\n" +msgstr " -d, --driver Affiche le pilote cpufreq utilisé *\n" #: utils/cpufreq-info.c:481 #, c-format @@ -420,7 +420,7 @@ msgstr " -p, --policy Affiche la tactique actuelle de cpufreq *\n" #, c-format msgid " -g, --governors Determines available cpufreq governors *\n" msgstr "" -" -g, --governors Affiche les régulateurs disponibles de cpufreq *\n" +" -g, --governors Affiche les régulateurs disponibles de cpufreq *\n" #: utils/cpufreq-info.c:483 #, fuzzy, c-format @@ -429,7 +429,7 @@ msgid "" "frequency *\n" msgstr "" " -a, --affected-cpus Affiche quels sont les CPUs qui doivent changer de\n" -" fréquences en même temps *\n" +" fréquences en même temps *\n" #: utils/cpufreq-info.c:484 #, fuzzy, c-format @@ -438,7 +438,7 @@ msgid "" " coordinated by software *\n" msgstr "" " -a, --affected-cpus Affiche quels sont les CPUs qui doivent changer de\n" -" fréquences en même temps *\n" +" fréquences en même temps *\n" #: utils/cpufreq-info.c:486 #, c-format @@ -453,7 +453,7 @@ msgid "" " -y, --latency Determines the maximum latency on CPU frequency " "changes *\n" msgstr "" -" -l, --hwlimits Affiche les fréquences minimales et maximales du CPU " +" -l, --hwlimits Affiche les fréquences minimales et maximales du CPU " "*\n" #: utils/cpufreq-info.c:488 @@ -469,7 +469,7 @@ msgid "" " interface in 2.4. and early 2.6. kernels\n" msgstr "" " -o, --proc Affiche les informations en utilisant l'interface\n" -" fournie par /proc/cpufreq, présente dans les " +" fournie par /proc/cpufreq, présente dans les " "versions\n" " 2.4 et les anciennes versions 2.6 du noyau\n" @@ -485,7 +485,7 @@ msgstr "" #: utils/cpufreq-info.c:492 utils/cpuidle-info.c:152 #, c-format msgid " -h, --help Prints out this screen\n" -msgstr " -h, --help affiche l'aide-mémoire\n" +msgstr " -h, --help affiche l'aide-mémoire\n" #: utils/cpufreq-info.c:495 #, c-format @@ -493,8 +493,8 @@ msgid "" "If no argument or only the -c, --cpu parameter is given, debug output about\n" "cpufreq is printed which is useful e.g. for reporting bugs.\n" msgstr "" -"Par défaut, les informations de déboguage seront affichées si aucun\n" -"argument, ou bien si seulement l'argument -c (--cpu) est donné, afin de\n" +"Par défaut, les informations de déboguage seront affichées si aucun\n" +"argument, ou bien si seulement l'argument -c (--cpu) est donné, afin de\n" "faciliter les rapports de bogues par exemple\n" #: utils/cpufreq-info.c:497 @@ -517,8 +517,8 @@ msgid "" "You can't specify more than one --cpu parameter and/or\n" "more than one output-specific argument\n" msgstr "" -"On ne peut indiquer plus d'un paramètre --cpu, tout comme l'on ne peut\n" -"spécifier plus d'un argument de formatage\n" +"On ne peut indiquer plus d'un paramètre --cpu, tout comme l'on ne peut\n" +"spécifier plus d'un argument de formatage\n" #: utils/cpufreq-info.c:600 utils/cpufreq-set.c:82 utils/cpupower-set.c:42 #: utils/cpupower-info.c:42 utils/cpuidle-info.c:213 @@ -529,7 +529,7 @@ msgstr "option invalide\n" #: utils/cpufreq-info.c:617 #, c-format msgid "couldn't analyze CPU %d as it doesn't seem to be present\n" -msgstr "analyse du CPU %d impossible puisqu'il ne semble pas être présent\n" +msgstr "analyse du CPU %d impossible puisqu'il ne semble pas être présent\n" #: utils/cpufreq-info.c:620 utils/cpupower-info.c:142 #, c-format @@ -547,8 +547,8 @@ msgid "" " -d FREQ, --min FREQ new minimum CPU frequency the governor may " "select\n" msgstr "" -" -d FREQ, --min FREQ nouvelle fréquence minimale du CPU à utiliser\n" -" par le régulateur\n" +" -d FREQ, --min FREQ nouvelle fréquence minimale du CPU à utiliser\n" +" par le régulateur\n" #: utils/cpufreq-set.c:28 #, c-format @@ -556,13 +556,13 @@ msgid "" " -u FREQ, --max FREQ new maximum CPU frequency the governor may " "select\n" msgstr "" -" -u FREQ, --max FREQ nouvelle fréquence maximale du CPU à utiliser\n" -" par le régulateur\n" +" -u FREQ, --max FREQ nouvelle fréquence maximale du CPU à utiliser\n" +" par le régulateur\n" #: utils/cpufreq-set.c:29 #, c-format msgid " -g GOV, --governor GOV new cpufreq governor\n" -msgstr " -g GOV, --governor GOV active le régulateur GOV\n" +msgstr " -g GOV, --governor GOV active le régulateur GOV\n" #: utils/cpufreq-set.c:30 #, c-format @@ -570,9 +570,9 @@ msgid "" " -f FREQ, --freq FREQ specific frequency to be set. Requires userspace\n" " governor to be available and loaded\n" msgstr "" -" -f FREQ, --freq FREQ fixe la fréquence du processeur à FREQ. Il faut\n" -" que le régulateur « userspace » soit disponible \n" -" et activé.\n" +" -f FREQ, --freq FREQ fixe la fréquence du processeur à FREQ. Il faut\n" +" que le régulateur « userspace » soit disponible \n" +" et activé.\n" #: utils/cpufreq-set.c:32 #, c-format @@ -582,7 +582,7 @@ msgstr "" #: utils/cpufreq-set.c:33 utils/cpupower-set.c:28 utils/cpupower-info.c:27 #, fuzzy, c-format msgid " -h, --help Prints out this screen\n" -msgstr " -h, --help affiche l'aide-mémoire\n" +msgstr " -h, --help affiche l'aide-mémoire\n" #: utils/cpufreq-set.c:35 #, fuzzy, c-format @@ -602,11 +602,11 @@ msgid "" " (FREQuency in kHz =^ Hz * 0.001 =^ MHz * 1000 =^ GHz * 1000000).\n" msgstr "" "Remarque :\n" -"1. Le CPU numéro 0 sera utilisé par défaut si -c (ou --cpu) est omis ;\n" -"2. l'argument -f FREQ (ou --freq FREQ) ne peut être utilisé qu'avec --cpu ;\n" -"3. on pourra préciser l'unité des fréquences en postfixant sans aucune " +"1. Le CPU numéro 0 sera utilisé par défaut si -c (ou --cpu) est omis ;\n" +"2. l'argument -f FREQ (ou --freq FREQ) ne peut être utilisé qu'avec --cpu ;\n" +"3. on pourra préciser l'unité des fréquences en postfixant sans aucune " "espace\n" -" les valeurs par hz, kHz (par défaut), MHz, GHz ou THz\n" +" les valeurs par hz, kHz (par défaut), MHz, GHz ou THz\n" " (kHz =^ Hz * 0.001 =^ MHz * 1000 =^ GHz * 1000000).\n" #: utils/cpufreq-set.c:57 @@ -622,21 +622,21 @@ msgid "" "frequency\n" " or because the userspace governor isn't loaded?\n" msgstr "" -"En ajustant les nouveaux paramètres, une erreur est apparue. Les sources\n" +"En ajustant les nouveaux paramètres, une erreur est apparue. Les sources\n" "d'erreur typique sont :\n" -"- droit d'administration insuffisant (êtes-vous root ?) ;\n" -"- le régulateur choisi n'est pas disponible, ou bien n'est pas disponible " +"- droit d'administration insuffisant (êtes-vous root ?) ;\n" +"- le régulateur choisi n'est pas disponible, ou bien n'est pas disponible " "en\n" " tant que module noyau ;\n" "- la tactique n'est pas disponible ;\n" -"- vous voulez utiliser l'option -f/--freq, mais le régulateur « userspace »\n" -" n'est pas disponible, par exemple parce que le matériel ne le supporte\n" -" pas, ou bien n'est tout simplement pas chargé.\n" +"- vous voulez utiliser l'option -f/--freq, mais le régulateur « userspace »\n" +" n'est pas disponible, par exemple parce que le matériel ne le supporte\n" +" pas, ou bien n'est tout simplement pas chargé.\n" #: utils/cpufreq-set.c:170 #, c-format msgid "wrong, unknown or unhandled CPU?\n" -msgstr "CPU inconnu ou non supporté ?\n" +msgstr "CPU inconnu ou non supporté ?\n" #: utils/cpufreq-set.c:302 #, c-format @@ -653,7 +653,7 @@ msgid "" "At least one parameter out of -f/--freq, -d/--min, -u/--max, and\n" "-g/--governor must be passed\n" msgstr "" -"L'un de ces paramètres est obligatoire : -f/--freq, -d/--min, -u/--max et\n" +"L'un de ces paramètres est obligatoire : -f/--freq, -d/--min, -u/--max et\n" "-g/--governor\n" #: utils/cpufreq-set.c:347 @@ -810,7 +810,7 @@ msgstr "" #: utils/cpuidle-info.c:48 #, fuzzy, c-format msgid "Available idle states:" -msgstr " plage de fréquence : " +msgstr " plage de fréquence : " #: utils/cpuidle-info.c:71 #, c-format @@ -911,7 +911,7 @@ msgstr "Usage : cpufreq-info [options]\n" #: utils/cpuidle-info.c:149 #, fuzzy, c-format msgid " -s, --silent Only show general C-state information\n" -msgstr " -e, --debug Afficher les informations de déboguage\n" +msgstr " -e, --debug Afficher les informations de déboguage\n" #: utils/cpuidle-info.c:150 #, fuzzy, c-format @@ -921,7 +921,7 @@ msgid "" " interface in older kernels\n" msgstr "" " -o, --proc Affiche les informations en utilisant l'interface\n" -" fournie par /proc/cpufreq, présente dans les " +" fournie par /proc/cpufreq, présente dans les " "versions\n" " 2.4 et les anciennes versions 2.6 du noyau\n" @@ -929,19 +929,19 @@ msgstr "" #, fuzzy, c-format msgid "You can't specify more than one output-specific argument\n" msgstr "" -"On ne peut indiquer plus d'un paramètre --cpu, tout comme l'on ne peut\n" -"spécifier plus d'un argument de formatage\n" +"On ne peut indiquer plus d'un paramètre --cpu, tout comme l'on ne peut\n" +"spécifier plus d'un argument de formatage\n" #~ msgid "" #~ " -c CPU, --cpu CPU CPU number which information shall be determined " #~ "about\n" #~ msgstr "" -#~ " -c CPU, --cpu CPU Numéro du CPU pour lequel l'information sera " -#~ "affichée\n" +#~ " -c CPU, --cpu CPU Numéro du CPU pour lequel l'information sera " +#~ "affichée\n" #~ msgid "" #~ " -c CPU, --cpu CPU number of CPU where cpufreq settings shall be " #~ "modified\n" #~ msgstr "" -#~ " -c CPU, --cpu CPU numéro du CPU à prendre en compte pour les\n" +#~ " -c CPU, --cpu CPU numéro du CPU à prendre en compte pour les\n" #~ " changements\n" -- cgit v1.2.3 From 496f3347d834aec91c38b45d6249ed00f58ad233 Mon Sep 17 00:00:00 2001 From: Neeraj Dantu Date: Tue, 28 Aug 2018 16:37:58 +0000 Subject: ARM: dts: Fix file permission for am335x-osd3358-sm-red.dts Fix wrong mode for dts file added by commit bb3e3fbbac86 ("ARM: dts: Add DT support for Octavo Systems OSD3358-SM-RED based on TI AM335x"). Signed-off-by: Neeraj Dantu CC: Robert Nelson CC: Jason Kridner Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-osd3358-sm-red.dts | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 arch/arm/boot/dts/am335x-osd3358-sm-red.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts old mode 100755 new mode 100644 -- cgit v1.2.3