From 665c8ec1222a6ede0615e9bcca914d1834da12de Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:26:00 +0200 Subject: ARM: dts: STiH4xx: Simplify clock binding of STiH4xx platforms This patch simplifies the clock binding because we had too much detail. Signed-off-by: Gabriel Fernandez --- arch/arm/boot/dts/stih407-clock.dtsi | 18 +++++++++--------- arch/arm/boot/dts/stih410-clock.dtsi | 16 ++++++++-------- arch/arm/boot/dts/stih418-clock.dtsi | 16 ++++++++-------- 3 files changed, 25 insertions(+), 25 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index ad45f5e8fac7..38a56d7edab3 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -42,7 +42,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + compatible = "st,stih407-clkgen-plla9"; clocks = <&clk_sysin>; @@ -55,7 +55,7 @@ */ clk_m_a9: clk-m-a9@92b0000 { #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + compatible = "st,stih407-clkgen-a9-mux"; reg = <0x92b0000 0x10000>; clocks = <&clockgen_a9_pll 0>, @@ -96,7 +96,7 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -117,7 +117,7 @@ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-C", "st,quadfs"; + compatible = "st,quadfs-pll"; reg = <0x9103000 0x1000>; clocks = <&clk_sysin>; @@ -134,7 +134,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -143,7 +143,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll1"; clocks = <&clk_sysin>; @@ -199,7 +199,7 @@ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9104000 0x1000>; clocks = <&clk_sysin>; @@ -233,7 +233,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9106000 0x1000>; clocks = <&clk_sysin>; @@ -287,7 +287,7 @@ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9107000 0x1000>; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index fd5049682181..e8f4d4421e62 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -44,7 +44,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + compatible = "st,stih407-clkgen-plla9"; clocks = <&clk_sysin>; @@ -98,7 +98,7 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -122,7 +122,7 @@ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-C", "st,quadfs"; + compatible = "st,quadfs-pll"; reg = <0x9103000 0x1000>; clocks = <&clk_sysin>; @@ -140,7 +140,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -150,7 +150,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll1"; clocks = <&clk_sysin>; @@ -218,7 +218,7 @@ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9104000 0x1000>; clocks = <&clk_sysin>; @@ -254,7 +254,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9106000 0x1000>; clocks = <&clk_sysin>; @@ -308,7 +308,7 @@ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9107000 0x1000>; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index ae6d9978ea19..0fd0fa54132c 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -44,7 +44,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"; + compatible = "st,stih418-clkgen-plla9"; clocks = <&clk_sysin>; @@ -98,7 +98,7 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -120,7 +120,7 @@ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-C", "st,quadfs"; + compatible = "st,quadfs-pll"; reg = <0x9103000 0x1000>; clocks = <&clk_sysin>; @@ -137,7 +137,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -146,7 +146,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll1"; clocks = <&clk_sysin>; @@ -212,7 +212,7 @@ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9104000 0x1000>; clocks = <&clk_sysin>; @@ -248,7 +248,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9106000 0x1000>; clocks = <&clk_sysin>; @@ -309,7 +309,7 @@ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9107000 0x1000>; clocks = <&clk_sysin>; -- cgit v1.2.3 From ee7ff1b4afb0c2298e37b5169ec74e21cd077c85 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:26:00 +0200 Subject: ARM: dts: STiH407: Enable clock propagation for audio clocks This patch is used in the clock driver to apply a clock propagation flag on the audio clocks of STiH407 Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih407-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 38a56d7edab3..c4a8f1cb3195 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -216,7 +216,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-audio", "st,flexgen"; clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_quadfs 1>, -- cgit v1.2.3 From 66ac420ab324faba09995a11c7faff7009d8d681 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STiH410: Enable clock propagation for audio clocks This patch is used in the clock driver to apply a clock propagation flag on the audio clocks of STiH410 Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih410-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index e8f4d4421e62..aec2aa736c8c 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -235,7 +235,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-audio", "st,flexgen"; clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_quadfs 1>, -- cgit v1.2.3 From 97e7abdb8910df3ecebcbd0805f69535df71da82 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STiH418: Enable clock propagation for audio clocks This patch is used in the clock driver to apply a clock propagation flag on the audio clocks of STiH418 Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih418-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index 0fd0fa54132c..a1835833ca64 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -229,7 +229,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-audio", "st,flexgen"; clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_quadfs 1>, -- cgit v1.2.3 From 295971d01f4d5a248d33f95bf20ed423aed19199 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STiH407: Enable synchronous clock mode for video clocks This patch enables the synchronous clock mode for video clocks on STiH407 board. Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih407-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index c4a8f1cb3195..13029c03d7c6 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -256,7 +256,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-video", "st,flexgen"; clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, -- cgit v1.2.3 From 9bc4ec59ab48ec2acd40c14afe227e074a485849 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STiH410: Enable synchronous clock mode for video clocks This patch enables the synchronous clock mode for video clocks on STiH410 board. Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih410-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index aec2aa736c8c..8598effd6c01 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -277,7 +277,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-video", "st,flexgen"; clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, -- cgit v1.2.3 From 3b8b9f7fd25d28b323f58ac67cf577d7bf0cc6bb Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STiH418: Enable synchronous clock mode for video clocks This patch enables the synchronous clock mode for video clocks on STiH418 board. Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih418-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index a1835833ca64..ee6614b79f7d 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -271,7 +271,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-video", "st,flexgen"; clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, -- cgit v1.2.3 From a0bfc7d068f685565f15f5f1e113eb293b68980b Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STi: STiH407: clock configuration to address 720p and 1080p It is necessary to properly configure these clocks in order to address 720p and 1080p HDMI resolution. Signed-off-by: Vincent Abriou Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih407.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index d60f0d8add26..291ffacbd2e0 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -16,7 +16,10 @@ #size-cells = <1>; assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, <&clk_s_d2_flexgen CLK_PIX_GDP1>, @@ -26,14 +29,21 @@ assigned-clock-parents = <0>, <0>, + <0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>; - assigned-clock-rates = <297000000>, <297000000>; + assigned-clock-rates = <297000000>, + <108000000>, + <0>, + <400000000>, + <400000000>; ranges; -- cgit v1.2.3 From 3a74152ce62e7ec1b8a5604b10e40d2a66d8f43b Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STiH410: clock configuration to address 720p and 1080p It is necessary to properly configure these clocks in order to address 720p and 1080p HDMI resolution. Signed-off-by: Vincent Abriou Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih410.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index 6850f5861dc3..2d231300bf27 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -103,7 +103,10 @@ #size-cells = <1>; assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, <&clk_s_d2_flexgen CLK_PIX_GDP1>, @@ -113,14 +116,21 @@ assigned-clock-parents = <0>, <0>, + <0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>; - assigned-clock-rates = <297000000>, <297000000>; + assigned-clock-rates = <297000000>, + <108000000>, + <0>, + <400000000>, + <400000000>; ranges; -- cgit v1.2.3