From 549f3ae1beb187e53f4cec7ee0cbe79b01d27111 Mon Sep 17 00:00:00 2001 From: Pratyush Anand Date: Mon, 14 Apr 2014 15:27:36 +0530 Subject: ARM: SPEAr13xx: Add pcie and miphy DT nodes This patch adds necessary DT nodes for pcie controllers and miphys for SPEAr13xx SoCs. SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works in ahci mode. Because of this, these nodes are marked "disabled" by default. In order to use pcie controller on evaluation boards do necessary modifications on board and enable (By replacing "disabled" with "okay") pcie and miphy from respective 'evb' dtsi file. Phy specific initialization was previously done from spear1340.c, which isn't required anymore as we have separate drivers for it. Remove it. Acked-by: Arnd Bergmann Acked-by: Viresh Kumar Signed-off-by: Pratyush Anand Signed-off-by: Mohit Kumar [viresh: fixed logs/cclist/checkpatch warnings, clubbed multiple patches into one] Signed-off-by: Viresh Kumar --- arch/arm/boot/dts/spear1340.dtsi | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/spear1340.dtsi') diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi index 54d128d35681..e71df0f2cb52 100644 --- a/arch/arm/boot/dts/spear1340.dtsi +++ b/arch/arm/boot/dts/spear1340.dtsi @@ -31,10 +31,38 @@ status = "disabled"; }; - ahci@b1000000 { + miphy0: miphy@eb800000 { + compatible = "st,spear1340-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 72 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; + status = "disabled"; + }; + + pcie0: pcie@b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 68 0x4>; + num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ status = "disabled"; }; -- cgit v1.2.3