From 8906d654992b472ce270d056f523ec21dd06cd3c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 22 Jul 2013 11:52:37 +0100 Subject: ARM: dts: Remove '0x's from OMAP5 DTS file Cc: Tony Lindgren Signed-off-by: Lee Jones Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts/omap5.dtsi') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 7cdea1bfea09..ecc06a99fd4d 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -604,7 +604,7 @@ ti,hwmods = "wd_timer2"; }; - emif1: emif@0x4c000000 { + emif1: emif@4c000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif1"; phy-type = <2>; /* DDR PHY type: Intelli PHY */ @@ -615,7 +615,7 @@ hw-caps-temp-alert; }; - emif2: emif@0x4d000000 { + emif2: emif@4d000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif2"; phy-type = <2>; /* DDR PHY type: Intelli PHY */ -- cgit v1.2.3 From e3a412c9eed08a246d9542645d102c194059cb2b Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Wed, 21 Aug 2013 20:01:32 +0530 Subject: ARM: dts: OMAP5: add palmas-usb node Without this node, there will be no palmas driver to notify dwc3 that a cable has been connected and, without that, dwc3 will never initialize. Signed-off-by: Felipe Balbi [kishon@ti.com: added dt properties for enabling vbus/id interrupts and fixed vbus-supply value after SMPS10 is modeled as 2 regulators] Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-uevm.dts | 12 ++++++++++++ arch/arm/boot/dts/omap5.dtsi | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/omap5.dtsi') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 05b9b126f084..da25a14d919f 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -272,6 +272,13 @@ interrupt-controller; #interrupt-cells = <2>; + extcon_usb3: palmas_usb { + compatible = "ti,palmas-usb-vid"; + ti,enable-vbus-detection; + ti,enable-id-detection; + ti,wakeup; + }; + palmas_pmic { compatible = "ti,palmas-pmic"; interrupt-parent = <&palmas>; @@ -479,6 +486,11 @@ phys = <0 &hsusb2_phy &hsusb3_phy>; }; +&usb3 { + extcon = <&extcon_usb3>; + vbus-supply = <&smps10_out1_reg>; +}; + &mcspi1 { }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index ecc06a99fd4d..6192c458bea1 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -634,7 +634,7 @@ ti,type = <2>; }; - omap_dwc3@4a020000 { + usb3: omap_dwc3@4a020000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss"; reg = <0x4a020000 0x10000>; -- cgit v1.2.3 From 5b025848e17a8659e2ebac21935daaa01799834b Mon Sep 17 00:00:00 2001 From: Sricharan R Date: Thu, 10 Oct 2013 13:20:13 +0530 Subject: ARM: dts: OMAP5: Remove clock-frequency field for cpu timers The arm arch timers frequency are now programmed in the CNTFREQ per-cpu register by the timer code using the secure API [1]. So remove the redundant entry from the dts. [1] http://marc.info/?l=linux-omap&m=138139106312786&w=2 Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/boot/dts/omap5.dtsi') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 6192c458bea1..6a558cedffd6 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -52,7 +52,6 @@ , , ; - clock-frequency = <6144000>; }; gic: interrupt-controller@48211000 { -- cgit v1.2.3 From f12ecbe2ea3c01b61e93af815723939a27511abc Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 15 Oct 2013 12:37:50 +0530 Subject: ARM: dts: omap: Add reset/idle on init bindings for OMAP On OMAP we have co-processor IPs, memory controllers, GPIOs which control regulators and power switches to PMIC, and SoC internal Bus IPs, some or most of which should either not be reset or idled or both at init. (In some cases there are erratas which prevent an IP from being reset) Have a way to pass this information from DT. Update the am33xx/omap4 and omap5 dtsi files with the new bindings for modules which either should not be idled. reset or both. A later patch would cleanup the same information that exists today as part of the hwmod data files. Signed-off-by: Rajendra Nayak Signed-off-by: Benoit Cousson --- Documentation/devicetree/bindings/arm/omap/omap.txt | 3 ++- arch/arm/boot/dts/am33xx.dtsi | 2 ++ arch/arm/boot/dts/omap4.dtsi | 3 +++ arch/arm/boot/dts/omap5.dtsi | 2 ++ 4 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/omap5.dtsi') diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index 91b7049affa1..808c1543b0f8 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -21,7 +21,8 @@ Required properties: Optional properties: - ti,no_idle_on_suspend: When present, it prevents the PM to idle the module during suspend. - +- ti,no-reset-on-init: When present, the module should not be reset at init +- ti,no-idle-on-init: When present, the module should not be idled at init Example: diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 7db3c81d1563..58cf5b91a118 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -674,6 +674,7 @@ reg = <0x44d00000 0x4000 /* M3 UMEM */ 0x44d80000 0x2000>; /* M3 DMEM */ ti,hwmods = "wkup_m3"; + ti,no-reset-on-init; }; elm: elm@48080000 { @@ -713,6 +714,7 @@ gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; + ti,no-idle-on-init; reg = <0x50000000 0x2000>; interrupts = <100>; gpmc,num-cs = <7>; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 6be1f5678f1a..6ca45b0d346b 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -214,6 +214,7 @@ gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; + ti,no-idle-on-init; }; uart1: serial@4806a000 { @@ -492,6 +493,7 @@ reg = <0x4c000000 0x100>; interrupts = ; ti,hwmods = "emif1"; + ti,no-idle-on-init; phy-type = <1>; hw-caps-read-idle-ctrl; hw-caps-ll-interface; @@ -503,6 +505,7 @@ reg = <0x4d000000 0x100>; interrupts = ; ti,hwmods = "emif2"; + ti,no-idle-on-init; phy-type = <1>; hw-caps-read-idle-ctrl; hw-caps-ll-interface; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 6a558cedffd6..f518ec6b6e49 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -606,6 +606,7 @@ emif1: emif@4c000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif1"; + ti,no-idle-on-init; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4c000000 0x400>; interrupts = ; @@ -617,6 +618,7 @@ emif2: emif@4d000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif2"; + ti,no-idle-on-init; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4d000000 0x400>; interrupts = ; -- cgit v1.2.3 From c47ee6ee8b93a41428846f86fa36dc80cee432ce Mon Sep 17 00:00:00 2001 From: George Cherian Date: Thu, 10 Oct 2013 16:19:54 +0530 Subject: ARM: dts: OMAP5: Add dr_mode for dwc3 Added dr_mode property in dwc3 and set its default mode to device. Signed-off-by: George Cherian Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts/omap5.dtsi') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index f518ec6b6e49..53686e46f482 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -649,6 +649,7 @@ reg = <0x4a030000 0x10000>; interrupts = ; usb-phy = <&usb2_phy>, <&usb3_phy>; + dr_mode = "peripheral"; tx-fifo-resize; }; }; -- cgit v1.2.3 From 20b80942ef4e3156a1c4aa5628d1bcb3479812da Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 16 Oct 2013 15:21:03 -0500 Subject: ARM: dts: OMAP3+: Add i2c aliases Currently, on OMAP5, i2c1 and i2c5 defer probe due to pinctrl dependencies. This changes the i2c ID each bus is registered with in i2c-dev interface. As a result of this, many userspace tools break and there is no consistent manner to fix the same if the i2c dev interface have no consistent numbering. Since this could happen for other OMAP derivatives, provide i2c alias for all OMAP3+ SoCs to allow ordering the i2c devices correctly. Signed-off-by: Nishanth Menon Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/dra7.dtsi | 5 +++++ arch/arm/boot/dts/omap3.dtsi | 3 +++ arch/arm/boot/dts/omap4.dtsi | 4 ++++ arch/arm/boot/dts/omap5.dtsi | 5 +++++ 4 files changed, 17 insertions(+) (limited to 'arch/arm/boot/dts/omap5.dtsi') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c01ef769761f..98ff6553edbc 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -20,6 +20,11 @@ interrupt-parent = <&gic>; aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + i2c4 = &i2c5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 16420ae16004..493b6d4373d1 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -19,6 +19,9 @@ interrupt-parent = <&intc>; aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 6ca45b0d346b..0d8fdbad43fa 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -17,6 +17,10 @@ interrupt-parent = <&gic>; aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 53686e46f482..2cb72ba1dd05 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -21,6 +21,11 @@ interrupt-parent = <&gic>; aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + i2c4 = &i2c5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; -- cgit v1.2.3 From b8981d71b59a42af614c231b3e3df4858c18a75e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 16 Oct 2013 10:39:04 -0500 Subject: ARM: dts: omap5-uevm: add smps123 supply for CPU regulator smps123 supply from Palmas PMIC powers CPU0 on OMAP5uEVM. Based on a patch by J Keerthy Signed-off-by: Nishanth Menon Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-uevm.dts | 4 ++++ arch/arm/boot/dts/omap5.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/omap5.dtsi') diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 8d8030569378..22d9b51dbd16 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -501,3 +501,7 @@ pinctrl-names = "default"; pinctrl-0 = <&uart5_pins>; }; + +&cpu0 { + cpu0-supply = <&smps123_reg>; +}; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 2cb72ba1dd05..b3158738991a 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -38,7 +38,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; -- cgit v1.2.3 From 6c24894d9f1319fd23644e1c9f9b2b675fc20b1a Mon Sep 17 00:00:00 2001 From: J Keerthy Date: Wed, 16 Oct 2013 10:39:06 -0500 Subject: ARM: dts: OMAP5: Add CPU OPP table Add DT OPP table for OMAP54xx family of devices. This data is decoded by OF with of_init_opp_table() helper function. The data is based on OMAP543x ES2.0 DM Operating Condition Addendum Version 0.6(April 2013) NOTE: The voltage and frequency values work well only on NOM samples and are supposed to work properly only with ABB/AVS for ALL OPPs. TODO: Add SPEED BIN OPP after ABB and AVS support so the cpufreq works on all samples seamlessly. Clock node is pending alignment for clock dts conversion [nm@ti.com: sync to latest and fixes] Signed-off-by: Nishanth Menon Signed-off-by: J Keerthy Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts/omap5.dtsi') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index b3158738991a..154d92fae1d5 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -42,6 +42,13 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; + + operating-points = < + /* kHz uV */ + 500000 880000 + 1000000 1060000 + 1500000 1250000 + >; }; cpu@1 { device_type = "cpu"; -- cgit v1.2.3 From fe0e09e48cc3566b240a6b79e7e9cd54f7f48755 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 10 Oct 2013 16:15:34 -0500 Subject: ARM: dts: OMAP5: Add hwspinlock node Add the hwspinlock device tree node for OMAP5 SoCs. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts/omap5.dtsi') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 154d92fae1d5..a791846421d1 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -287,6 +287,12 @@ ti,hwmods = "i2c5"; }; + hwspinlock: spinlock@4a0f6000 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x4a0f6000 0x1000>; + ti,hwmods = "spinlock"; + }; + mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; reg = <0x48098000 0x200>; -- cgit v1.2.3