From c4f2fc00defc65950dfabce7a4c70cd2a289111d Mon Sep 17 00:00:00 2001 From: Marian Mihailescu Date: Thu, 23 Nov 2017 15:34:30 +0100 Subject: ARM: dts: exynos: Add CPU perf counters to Exynos54xx boards Enable support for ARM Performance Monitoring Units available in Cortex-A7 and Cortex-A15 CPU cores for Exynos54xx SoCs (5410, 5420 and 5422/5800). The PMUs interrupts are defined in the common exynos54xx.dtsi device tree, but the PMUs are enabled and have their interrupt CPU affinity defined next to each SoC's cpus node. Tested with perf on Odroid XU4 (Exynos5422): armv7_cortex_a7 PMU driver: 5 counters available armv7_cortex_a15 PMU driver: 7 counters available Suggested-by: Marek Szyprowski Signed-off-by: Marian Mihailescu Signed-off-by: Willy Wolff [mszyprow: reordered nodes according to krzk request, fixed typos] Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos54xx.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts/exynos54xx.dtsi') diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index b45678212f1a..8f87ab1dd9e3 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -29,6 +29,26 @@ }; soc: soc { + arm_a7_pmu: arm-a7-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + status = "disabled"; + }; + + arm_a15_pmu: arm-a15-pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&combiner>; + interrupts = <1 2>, + <7 0>, + <16 6>, + <19 2>; + status = "disabled"; + }; + sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x54000>; -- cgit v1.2.3