From db0f68529a6a7f3f42486398275926be946903b0 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 23 Feb 2016 18:37:22 +0200 Subject: ARM: dts: am335x: Disable wait pin monitoring for NAND The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and can't be used for wait state insertion for NAND I/O read/write. So disable read/write wait monitoring as per Reference Manual's suggestion [1]. [1] AM335x TRM: SPRUH73L: 7.1.3.3.12.2 NAND Device-Ready Pin Cc: Teresa Remmet Cc: Ilya Ledvich Cc: Yegor Yefremov Cc: Rostislav Lisovy Cc: Enric Balletbo i Serra Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-igep0033.dtsi | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm/boot/dts/am335x-igep0033.dtsi') diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index 4cfe0419a535..6c3a9bf3638a 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -152,12 +152,9 @@ gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; -- cgit v1.2.3