From 2da0d487781b2b27c1e114976257f455eb25def4 Mon Sep 17 00:00:00 2001 From: Jérôme Pouiller Date: Thu, 17 Feb 2022 11:32:48 +0100 Subject: staging: wfx: fix DT bindings location MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, the DT bindings the wfx driver cannot be processed by make dt_binding_check. We need to place it somewhere into Documentation/devicetree/bindings/. After that change, we are able to get warnings from dt_binding_check and fix them. Signed-off-by: Jérôme Pouiller Link: https://lore.kernel.org/r/20220217103248.183770-1-Jerome.Pouiller@silabs.com Signed-off-by: Greg Kroah-Hartman --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index fca970a46e77..65227f6aabd0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17652,6 +17652,7 @@ F: drivers/platform/x86/touchscreen_dmi.c SILICON LABS WIRELESS DRIVERS (for WFxxx series) M: Jérôme Pouiller S: Supported +F: Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml F: drivers/staging/wfx/ SILICON MOTION SM712 FRAME BUFFER DRIVER -- cgit v1.2.3 From ca7918f21466545250033b5bd077c2fbab0247a3 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Wed, 16 Mar 2022 13:48:02 +0100 Subject: MAINTAINERS: remove the obsolete file entry for staging in ANDROID DRIVERS Commit 721412ed3d81 ("staging: remove ashmem") removes the last android driver from staging, but misses to adjust MAINTAINERS. Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a broken reference. Remove the obsolete file entry in ANDROID DRIVERS. Signed-off-by: Lukas Bulwahn Link: https://lore.kernel.org/r/20220316124802.372-1-lukas.bulwahn@gmail.com Signed-off-by: Greg Kroah-Hartman --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index a53ef77ffd2b..bf58c6c4f812 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1259,7 +1259,6 @@ L: linux-kernel@vger.kernel.org S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git F: drivers/android/ -F: drivers/staging/android/ ANDROID GOLDFISH PIC DRIVER M: Miodrag Dinic -- cgit v1.2.3 From 7a6ee0bbab2551d7189ce0f5e625fef4d612ebea Mon Sep 17 00:00:00 2001 From: Arınç ÜNAL Date: Tue, 15 Mar 2022 19:01:50 +0300 Subject: mips: dts: ralink: add MT7621 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc dual-core CPU, a 5-port 10/100/1000 switch/PHY and one RGMII. Add the devicetrees for GB-PC1 and GB-PC2 devices which use MT7621 SoC. Acked-by: Sergio Paracuellos Acked-by: Thomas Bogendoerfer Signed-off-by: Arınç ÜNAL Link: https://lore.kernel.org/r/20220315160149.3617-1-arinc.unal@arinc9.com Signed-off-by: Greg Kroah-Hartman --- MAINTAINERS | 7 + arch/mips/boot/dts/ralink/Makefile | 4 + arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts | 128 ++++++ arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts | 122 +++++ arch/mips/boot/dts/ralink/mt7621.dtsi | 497 +++++++++++++++++++++ arch/mips/ralink/Kconfig | 5 + drivers/staging/Kconfig | 2 - drivers/staging/Makefile | 1 - drivers/staging/mt7621-dts/Kconfig | 11 - drivers/staging/mt7621-dts/Makefile | 5 - drivers/staging/mt7621-dts/TODO | 5 - drivers/staging/mt7621-dts/gbpc1.dts | 128 ------ drivers/staging/mt7621-dts/gbpc2.dts | 122 ----- drivers/staging/mt7621-dts/mt7621.dtsi | 497 --------------------- 14 files changed, 763 insertions(+), 771 deletions(-) create mode 100644 arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts create mode 100644 arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts create mode 100644 arch/mips/boot/dts/ralink/mt7621.dtsi delete mode 100644 drivers/staging/mt7621-dts/Kconfig delete mode 100644 drivers/staging/mt7621-dts/Makefile delete mode 100644 drivers/staging/mt7621-dts/TODO delete mode 100644 drivers/staging/mt7621-dts/gbpc1.dts delete mode 100644 drivers/staging/mt7621-dts/gbpc2.dts delete mode 100644 drivers/staging/mt7621-dts/mt7621.dtsi (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index bf58c6c4f812..fd140717854d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16180,6 +16180,13 @@ L: linux-mips@vger.kernel.org S: Maintained F: arch/mips/ralink +RALINK MT7621 MIPS ARCHITECTURE +M: Arınç ÜNAL +M: Sergio Paracuellos +L: linux-mips@vger.kernel.org +S: Maintained +F: arch/mips/boot/dts/ralink/mt7621* + RALINK RT2X00 WIRELESS LAN DRIVER M: Stanislaw Gruszka M: Helmut Schaa diff --git a/arch/mips/boot/dts/ralink/Makefile b/arch/mips/boot/dts/ralink/Makefile index 6c26dfa0a903..11732b8c8163 100644 --- a/arch/mips/boot/dts/ralink/Makefile +++ b/arch/mips/boot/dts/ralink/Makefile @@ -6,4 +6,8 @@ dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb dtb-$(CONFIG_DTB_OMEGA2P) += omega2p.dtb dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb +dtb-$(CONFIG_SOC_MT7621) += \ + mt7621-gnubee-gb-pc1.dtb \ + mt7621-gnubee-gb-pc2.dtb + obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts new file mode 100644 index 000000000000..5892bcf71595 --- /dev/null +++ b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +#include "mt7621.dtsi" + +#include +#include + +/ { + compatible = "gnubee,gb-pc1", "mediatek,mt7621-soc"; + model = "GB-PC1"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x1c000000>, + <0x20000000 0x04000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + palmbus: palmbus@1e000000 { + i2c@900 { + status = "okay"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power { + label = "green:power"; + gpios = <&gpio 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + system { + label = "green:system"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "disk-activity"; + }; + }; +}; + +&sdhci { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + broken-flash-reset; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x1fb0000>; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: state-default { + gpio-pinmux { + groups = "rgmii2", "uart3", "wdt"; + function = "gpio"; + }; + }; +}; + +ðernet { + pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>; +}; + +&switch0 { + ports { + port@0 { + status = "okay"; + label = "ethblack"; + }; + + port@4 { + status = "okay"; + label = "ethblue"; + }; + }; +}; diff --git a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts new file mode 100644 index 000000000000..a7fce8de6147 --- /dev/null +++ b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +#include "mt7621.dtsi" + +#include +#include + +/ { + compatible = "gnubee,gb-pc2", "mediatek,mt7621-soc"; + model = "GB-PC2"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x1c000000>, + <0x20000000 0x04000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + palmbus: palmbus@1e000000 { + i2c@900 { + status = "okay"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; +}; + +&sdhci { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + broken-flash-reset; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x1fb0000>; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: state-default { + gpio-pinmux { + groups = "wdt"; + function = "gpio"; + }; + }; +}; + +ðernet { + gmac1: mac@1 { + status = "okay"; + phy-handle = <ðphy7>; + }; + + mdio-bus { + ethphy7: ethernet-phy@7 { + reg = <7>; + phy-mode = "rgmii-rxid"; + }; + }; +}; + +&switch0 { + ports { + port@0 { + status = "okay"; + label = "ethblack"; + }; + + port@4 { + status = "okay"; + label = "ethblue"; + }; + }; +}; diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi new file mode 100644 index 000000000000..3222684915ac --- /dev/null +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -0,0 +1,497 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7621-soc"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips1004Kc"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "mips,mips1004Kc"; + reg = <1>; + }; + }; + + cpuintc: cpuintc { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + aliases { + serial0 = &uartlite; + }; + + + mmc_fixed_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "mmc_power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + }; + + mmc_fixed_1v8_io: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "mmc_io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + }; + + palmbus: palmbus@1e000000 { + compatible = "palmbus"; + reg = <0x1e000000 0x100000>; + ranges = <0x0 0x1e000000 0x0fffff>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc: syscon@0 { + compatible = "mediatek,mt7621-sysc", "syscon"; + reg = <0x0 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; + ralink,memctl = <&memc>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; + }; + + wdt: wdt@100 { + compatible = "mediatek,mt7621-wdt"; + reg = <0x100 0x100>; + }; + + gpio: gpio@600 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "mediatek,mt7621-gpio"; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 95>; + interrupt-controller; + reg = <0x600 0x100>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + i2c: i2c@900 { + compatible = "mediatek,mt7621-i2c"; + reg = <0x900 0x100>; + + clocks = <&sysc MT7621_CLK_I2C>; + clock-names = "i2c"; + resets = <&sysc MT7621_RST_I2C>; + reset-names = "i2c"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + }; + + memc: syscon@5000 { + compatible = "mediatek,mt7621-memc", "syscon"; + reg = <0x5000 0x1000>; + }; + + uartlite: uartlite@c00 { + compatible = "ns16550a"; + reg = <0xc00 0x100>; + + clocks = <&sysc MT7621_CLK_UART1>; + clock-names = "uart1"; + + interrupt-parent = <&gic>; + interrupts = ; + + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test; + }; + + spi0: spi@b00 { + status = "disabled"; + + compatible = "ralink,mt7621-spi"; + reg = <0xb00 0x100>; + + clocks = <&sysc MT7621_CLK_SPI>; + clock-names = "spi"; + + resets = <&sysc MT7621_RST_SPI>; + reset-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>; + }; + }; + + pinctrl: pinctrl { + compatible = "ralink,rt2880-pinmux"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + + spi_pins: spi0-pins { + pinmux { + groups = "spi"; + function = "spi"; + }; + }; + + uart1_pins: uart1-pins { + pinmux { + groups = "uart1"; + function = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + pinmux { + groups = "uart2"; + function = "uart2"; + }; + }; + + uart3_pins: uart3-pins { + pinmux { + groups = "uart3"; + function = "uart3"; + }; + }; + + rgmii1_pins: rgmii1-pins { + pinmux { + groups = "rgmii1"; + function = "rgmii1"; + }; + }; + + rgmii2_pins: rgmii2-pins { + pinmux { + groups = "rgmii2"; + function = "rgmii2"; + }; + }; + + mdio_pins: mdio0-pins { + pinmux { + groups = "mdio"; + function = "mdio"; + }; + }; + + pcie_pins: pcie0-pins { + pinmux { + groups = "pcie"; + function = "gpio"; + }; + }; + + nand_pins: nand0-pins { + spi-pinmux { + groups = "spi"; + function = "nand1"; + }; + + sdhci-pinmux { + groups = "sdhci"; + function = "nand2"; + }; + }; + + sdhci_pins: sdhci0-pins { + pinmux { + groups = "sdhci"; + function = "sdhci"; + }; + }; + }; + + sdhci: sdhci@1e130000 { + status = "disabled"; + + compatible = "mediatek,mt7620-mmc"; + reg = <0x1e130000 0x4000>; + + bus-width = <4>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&mmc_fixed_3v3>; + vqmmc-supply = <&mmc_fixed_1v8_io>; + disable-wp; + + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sdhci_pins>; + pinctrl-1 = <&sdhci_pins>; + + clocks = <&sysc MT7621_CLK_SHXC>, + <&sysc MT7621_CLK_50M>; + clock-names = "source", "hclk"; + + interrupt-parent = <&gic>; + interrupts = ; + }; + + xhci: xhci@1e1c0000 { + compatible = "mediatek,mt8173-xhci"; + reg = <0x1e1c0000 0x1000 + 0x1e1d0700 0x0100>; + reg-names = "mac", "ippc"; + + clocks = <&sysc MT7621_CLK_XTAL>; + clock-names = "sys_ck"; + + interrupt-parent = <&gic>; + interrupts = ; + }; + + gic: interrupt-controller@1fbc0000 { + compatible = "mti,gic"; + reg = <0x1fbc0000 0x2000>; + + interrupt-controller; + #interrupt-cells = <3>; + + mti,reserved-cpu-vectors = <7>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&sysc MT7621_CLK_CPU>; + }; + }; + + cpc: cpc@1fbf0000 { + compatible = "mti,mips-cpc"; + reg = <0x1fbf0000 0x8000>; + }; + + cdmm: cdmm@1fbf8000 { + compatible = "mti,mips-cdmm"; + reg = <0x1fbf8000 0x8000>; + }; + + ethernet: ethernet@1e100000 { + compatible = "mediatek,mt7621-eth"; + reg = <0x1e100000 0x10000>; + + clocks = <&sysc MT7621_CLK_FE>, + <&sysc MT7621_CLK_ETH>; + clock-names = "fe", "ethif"; + + #address-cells = <1>; + #size-cells = <0>; + + resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>; + reset-names = "fe", "eth"; + + interrupt-parent = <&gic>; + interrupts = ; + + mediatek,ethsys = <&sysc>; + + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "off"; + phy-mode = "rgmii-rxid"; + }; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch0: switch0@0 { + compatible = "mediatek,mt7621"; + reg = <0>; + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; + reset-names = "mcm"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + status = "off"; + reg = <0>; + label = "lan0"; + }; + + port@1 { + status = "off"; + reg = <1>; + label = "lan1"; + }; + + port@2 { + status = "off"; + reg = <2>; + label = "lan2"; + }; + + port@3 { + status = "off"; + reg = <3>; + label = "lan3"; + }; + + port@4 { + status = "off"; + reg = <4>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + }; + + pcie: pcie@1e140000 { + compatible = "mediatek,mt7621-pci"; + reg = <0x1e140000 0x100>, /* host-pci bridge registers */ + <0x1e142000 0x100>, /* pcie port 0 RC control registers */ + <0x1e143000 0x100>, /* pcie port 1 RC control registers */ + <0x1e144000 0x100>; /* pcie port 2 RC control registers */ + #address-cells = <3>; + #size-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + + device_type = "pci"; + + ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ + <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0xF800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; + resets = <&sysc MT7621_RST_PCIE0>; + clocks = <&sysc MT7621_CLK_PCIE0>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy0"; + ranges; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; + resets = <&sysc MT7621_RST_PCIE1>; + clocks = <&sysc MT7621_CLK_PCIE1>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy1"; + ranges; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + resets = <&sysc MT7621_RST_PCIE2>; + clocks = <&sysc MT7621_CLK_PCIE2>; + phys = <&pcie2_phy 0>; + phy-names = "pcie-phy2"; + ranges; + }; + }; + + pcie0_phy: pcie-phy@1e149000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1e149000 0x0700>; + clocks = <&sysc MT7621_CLK_XTAL>; + #phy-cells = <1>; + }; + + pcie2_phy: pcie-phy@1e14a000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1e14a000 0x0700>; + clocks = <&sysc MT7621_CLK_XTAL>; + #phy-cells = <1>; + }; +}; diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 120adad51d6a..f9fe15630abb 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -54,10 +54,15 @@ choice select HAVE_PCI select PCI_DRIVERS_GENERIC select SOC_BUS + + help + The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc dual-core CPU, + a 5-port 10/100/1000 switch/PHY and one RGMII. endchoice choice prompt "Devicetree selection" + depends on !SOC_MT7621 default DTB_RT_NONE help Select the devicetree. diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index af60ca591c99..932acb4e8cbc 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -80,8 +80,6 @@ source "drivers/staging/vc04_services/Kconfig" source "drivers/staging/pi433/Kconfig" -source "drivers/staging/mt7621-dts/Kconfig" - source "drivers/staging/axis-fifo/Kconfig" source "drivers/staging/fieldbus/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index ad59134e97ad..3ffb35ccfae2 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -30,7 +30,6 @@ obj-$(CONFIG_KS7010) += ks7010/ obj-$(CONFIG_GREYBUS) += greybus/ obj-$(CONFIG_BCM2835_VCHIQ) += vc04_services/ obj-$(CONFIG_PI433) += pi433/ -obj-$(CONFIG_SOC_MT7621) += mt7621-dts/ obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo/ obj-$(CONFIG_FIELDBUS_DEV) += fieldbus/ obj-$(CONFIG_QLGE) += qlge/ diff --git a/drivers/staging/mt7621-dts/Kconfig b/drivers/staging/mt7621-dts/Kconfig deleted file mode 100644 index 6932ab7acadf..000000000000 --- a/drivers/staging/mt7621-dts/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config DTB_GNUBEE1 - bool "GnuBee1 2.5inch NAS" - depends on SOC_MT7621 && DTB_RT_NONE - select BUILTIN_DTB - -config DTB_GNUBEE2 - bool "GnuBee2 3.5inch NAS" - depends on SOC_MT7621 && DTB_RT_NONE - select BUILTIN_DTB - diff --git a/drivers/staging/mt7621-dts/Makefile b/drivers/staging/mt7621-dts/Makefile deleted file mode 100644 index b4ab99fed932..000000000000 --- a/drivers/staging/mt7621-dts/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_DTB_GNUBEE1) += gbpc1.dtb -dtb-$(CONFIG_DTB_GNUBEE2) += gbpc2.dtb - -obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) diff --git a/drivers/staging/mt7621-dts/TODO b/drivers/staging/mt7621-dts/TODO deleted file mode 100644 index 1b758e5c84e0..000000000000 --- a/drivers/staging/mt7621-dts/TODO +++ /dev/null @@ -1,5 +0,0 @@ - -- ensure all usage matches code -- ensure all features used are documented - -Cc: NeilBrown diff --git a/drivers/staging/mt7621-dts/gbpc1.dts b/drivers/staging/mt7621-dts/gbpc1.dts deleted file mode 100644 index 5892bcf71595..000000000000 --- a/drivers/staging/mt7621-dts/gbpc1.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/dts-v1/; - -#include "mt7621.dtsi" - -#include -#include - -/ { - compatible = "gnubee,gb-pc1", "mediatek,mt7621-soc"; - model = "GB-PC1"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x1c000000>, - <0x20000000 0x04000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - palmbus: palmbus@1e000000 { - i2c@900 { - status = "okay"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "green:power"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - system { - label = "green:system"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - linux,default-trigger = "disk-activity"; - }; - }; -}; - -&sdhci { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - broken-flash-reset; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: state-default { - gpio-pinmux { - groups = "rgmii2", "uart3", "wdt"; - function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>; -}; - -&switch0 { - ports { - port@0 { - status = "okay"; - label = "ethblack"; - }; - - port@4 { - status = "okay"; - label = "ethblue"; - }; - }; -}; diff --git a/drivers/staging/mt7621-dts/gbpc2.dts b/drivers/staging/mt7621-dts/gbpc2.dts deleted file mode 100644 index a7fce8de6147..000000000000 --- a/drivers/staging/mt7621-dts/gbpc2.dts +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/dts-v1/; - -#include "mt7621.dtsi" - -#include -#include - -/ { - compatible = "gnubee,gb-pc2", "mediatek,mt7621-soc"; - model = "GB-PC2"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x1c000000>, - <0x20000000 0x04000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - palmbus: palmbus@1e000000 { - i2c@900 { - status = "okay"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; -}; - -&sdhci { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - broken-flash-reset; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: state-default { - gpio-pinmux { - groups = "wdt"; - function = "gpio"; - }; - }; -}; - -ðernet { - gmac1: mac@1 { - status = "okay"; - phy-handle = <ðphy7>; - }; - - mdio-bus { - ethphy7: ethernet-phy@7 { - reg = <7>; - phy-mode = "rgmii-rxid"; - }; - }; -}; - -&switch0 { - ports { - port@0 { - status = "okay"; - label = "ethblack"; - }; - - port@4 { - status = "okay"; - label = "ethblue"; - }; - }; -}; diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi deleted file mode 100644 index 3222684915ac..000000000000 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ /dev/null @@ -1,497 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7621-soc"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "mips,mips1004Kc"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "mips,mips1004Kc"; - reg = <1>; - }; - }; - - cpuintc: cpuintc { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - aliases { - serial0 = &uartlite; - }; - - - mmc_fixed_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "mmc_power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-always-on; - }; - - mmc_fixed_1v8_io: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "mmc_io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - regulator-always-on; - }; - - palmbus: palmbus@1e000000 { - compatible = "palmbus"; - reg = <0x1e000000 0x100000>; - ranges = <0x0 0x1e000000 0x0fffff>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc: syscon@0 { - compatible = "mediatek,mt7621-sysc", "syscon"; - reg = <0x0 0x100>; - #clock-cells = <1>; - #reset-cells = <1>; - ralink,memctl = <&memc>; - clock-output-names = "xtal", "cpu", "bus", - "50m", "125m", "150m", - "250m", "270m"; - }; - - wdt: wdt@100 { - compatible = "mediatek,mt7621-wdt"; - reg = <0x100 0x100>; - }; - - gpio: gpio@600 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "mediatek,mt7621-gpio"; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 95>; - interrupt-controller; - reg = <0x600 0x100>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - i2c: i2c@900 { - compatible = "mediatek,mt7621-i2c"; - reg = <0x900 0x100>; - - clocks = <&sysc MT7621_CLK_I2C>; - clock-names = "i2c"; - resets = <&sysc MT7621_RST_I2C>; - reset-names = "i2c"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - }; - - memc: syscon@5000 { - compatible = "mediatek,mt7621-memc", "syscon"; - reg = <0x5000 0x1000>; - }; - - uartlite: uartlite@c00 { - compatible = "ns16550a"; - reg = <0xc00 0x100>; - - clocks = <&sysc MT7621_CLK_UART1>; - clock-names = "uart1"; - - interrupt-parent = <&gic>; - interrupts = ; - - reg-shift = <2>; - reg-io-width = <4>; - no-loopback-test; - }; - - spi0: spi@b00 { - status = "disabled"; - - compatible = "ralink,mt7621-spi"; - reg = <0xb00 0x100>; - - clocks = <&sysc MT7621_CLK_SPI>; - clock-names = "spi"; - - resets = <&sysc MT7621_RST_SPI>; - reset-names = "spi"; - - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - }; - }; - - pinctrl: pinctrl { - compatible = "ralink,rt2880-pinmux"; - - i2c_pins: i2c0-pins { - pinmux { - groups = "i2c"; - function = "i2c"; - }; - }; - - spi_pins: spi0-pins { - pinmux { - groups = "spi"; - function = "spi"; - }; - }; - - uart1_pins: uart1-pins { - pinmux { - groups = "uart1"; - function = "uart1"; - }; - }; - - uart2_pins: uart2-pins { - pinmux { - groups = "uart2"; - function = "uart2"; - }; - }; - - uart3_pins: uart3-pins { - pinmux { - groups = "uart3"; - function = "uart3"; - }; - }; - - rgmii1_pins: rgmii1-pins { - pinmux { - groups = "rgmii1"; - function = "rgmii1"; - }; - }; - - rgmii2_pins: rgmii2-pins { - pinmux { - groups = "rgmii2"; - function = "rgmii2"; - }; - }; - - mdio_pins: mdio0-pins { - pinmux { - groups = "mdio"; - function = "mdio"; - }; - }; - - pcie_pins: pcie0-pins { - pinmux { - groups = "pcie"; - function = "gpio"; - }; - }; - - nand_pins: nand0-pins { - spi-pinmux { - groups = "spi"; - function = "nand1"; - }; - - sdhci-pinmux { - groups = "sdhci"; - function = "nand2"; - }; - }; - - sdhci_pins: sdhci0-pins { - pinmux { - groups = "sdhci"; - function = "sdhci"; - }; - }; - }; - - sdhci: sdhci@1e130000 { - status = "disabled"; - - compatible = "mediatek,mt7620-mmc"; - reg = <0x1e130000 0x4000>; - - bus-width = <4>; - max-frequency = <48000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&mmc_fixed_3v3>; - vqmmc-supply = <&mmc_fixed_1v8_io>; - disable-wp; - - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&sdhci_pins>; - pinctrl-1 = <&sdhci_pins>; - - clocks = <&sysc MT7621_CLK_SHXC>, - <&sysc MT7621_CLK_50M>; - clock-names = "source", "hclk"; - - interrupt-parent = <&gic>; - interrupts = ; - }; - - xhci: xhci@1e1c0000 { - compatible = "mediatek,mt8173-xhci"; - reg = <0x1e1c0000 0x1000 - 0x1e1d0700 0x0100>; - reg-names = "mac", "ippc"; - - clocks = <&sysc MT7621_CLK_XTAL>; - clock-names = "sys_ck"; - - interrupt-parent = <&gic>; - interrupts = ; - }; - - gic: interrupt-controller@1fbc0000 { - compatible = "mti,gic"; - reg = <0x1fbc0000 0x2000>; - - interrupt-controller; - #interrupt-cells = <3>; - - mti,reserved-cpu-vectors = <7>; - - timer { - compatible = "mti,gic-timer"; - interrupts = ; - clocks = <&sysc MT7621_CLK_CPU>; - }; - }; - - cpc: cpc@1fbf0000 { - compatible = "mti,mips-cpc"; - reg = <0x1fbf0000 0x8000>; - }; - - cdmm: cdmm@1fbf8000 { - compatible = "mti,mips-cdmm"; - reg = <0x1fbf8000 0x8000>; - }; - - ethernet: ethernet@1e100000 { - compatible = "mediatek,mt7621-eth"; - reg = <0x1e100000 0x10000>; - - clocks = <&sysc MT7621_CLK_FE>, - <&sysc MT7621_CLK_ETH>; - clock-names = "fe", "ethif"; - - #address-cells = <1>; - #size-cells = <0>; - - resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>; - reset-names = "fe", "eth"; - - interrupt-parent = <&gic>; - interrupts = ; - - mediatek,ethsys = <&sysc>; - - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - status = "off"; - phy-mode = "rgmii-rxid"; - }; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - switch0: switch0@0 { - compatible = "mediatek,mt7621"; - reg = <0>; - mediatek,mcm; - resets = <&sysc MT7621_RST_MCM>; - reset-names = "mcm"; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - status = "off"; - reg = <0>; - label = "lan0"; - }; - - port@1 { - status = "off"; - reg = <1>; - label = "lan1"; - }; - - port@2 { - status = "off"; - reg = <2>; - label = "lan2"; - }; - - port@3 { - status = "off"; - reg = <3>; - label = "lan3"; - }; - - port@4 { - status = "off"; - reg = <4>; - label = "lan4"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - }; - }; - }; - - pcie: pcie@1e140000 { - compatible = "mediatek,mt7621-pci"; - reg = <0x1e140000 0x100>, /* host-pci bridge registers */ - <0x1e142000 0x100>, /* pcie port 0 RC control registers */ - <0x1e143000 0x100>, /* pcie port 1 RC control registers */ - <0x1e144000 0x100>; /* pcie port 2 RC control registers */ - #address-cells = <3>; - #size-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - - device_type = "pci"; - - ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ - <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ - - #interrupt-cells = <1>; - interrupt-map-mask = <0xF800 0 0 0>; - interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - - status = "disabled"; - - reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; - resets = <&sysc MT7621_RST_PCIE0>; - clocks = <&sysc MT7621_CLK_PCIE0>; - phys = <&pcie0_phy 1>; - phy-names = "pcie-phy0"; - ranges; - }; - - pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; - resets = <&sysc MT7621_RST_PCIE1>; - clocks = <&sysc MT7621_CLK_PCIE1>; - phys = <&pcie0_phy 1>; - phy-names = "pcie-phy1"; - ranges; - }; - - pcie@2,0 { - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - resets = <&sysc MT7621_RST_PCIE2>; - clocks = <&sysc MT7621_CLK_PCIE2>; - phys = <&pcie2_phy 0>; - phy-names = "pcie-phy2"; - ranges; - }; - }; - - pcie0_phy: pcie-phy@1e149000 { - compatible = "mediatek,mt7621-pci-phy"; - reg = <0x1e149000 0x0700>; - clocks = <&sysc MT7621_CLK_XTAL>; - #phy-cells = <1>; - }; - - pcie2_phy: pcie-phy@1e14a000 { - compatible = "mediatek,mt7621-pci-phy"; - reg = <0x1e14a000 0x0700>; - clocks = <&sysc MT7621_CLK_XTAL>; - #phy-cells = <1>; - }; -}; -- cgit v1.2.3