From 0d69ce3c2c63d4db06b369ef67cb6e73b06a8ad8 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 4 Nov 2020 10:58:14 +0900 Subject: dt-bindings: PCI: rcar-pci-host: Convert bindings to json-schema Convert Renesas PCIe Host controller bindings documentation to json-schema. Note that some compatible doesn't contain on the original documentation so that incremental patches are required for it. Link: https://lore.kernel.org/r/1604455096-13923-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Yoshihiro Shimoda Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/rcar-pci-host.yaml | 113 +++++++++++++++++++++ Documentation/devicetree/bindings/pci/rcar-pci.txt | 72 ------------- 2 files changed, 113 insertions(+), 72 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci-host.yaml delete mode 100644 Documentation/devicetree/bindings/pci/rcar-pci.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml new file mode 100644 index 000000000000..40c38a6612a8 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car PCIe Host + +maintainers: + - Marek Vasut + - Yoshihiro Shimoda + +allOf: + - $ref: pci-bus.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,pcie-r8a7742 # RZ/G1H + - renesas,pcie-r8a7743 # RZ/G1M + - renesas,pcie-r8a7744 # RZ/G1N + - renesas,pcie-r8a7790 # R-Car H2 + - renesas,pcie-r8a7791 # R-Car M2-W + - renesas,pcie-r8a7793 # R-Car M2-N + - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1 + - items: + - enum: + - renesas,pcie-r8a774a1 # RZ/G2M + - renesas,pcie-r8a774b1 # RZ/G2N + - renesas,pcie-r8a774c0 # RZ/G2E + - renesas,pcie-r8a7795 # R-Car H3 + - renesas,pcie-r8a7796 # R-Car M3-W + - renesas,pcie-r8a77961 # R-Car M3-W+ + - renesas,pcie-r8a77980 # R-Car V3H + - renesas,pcie-r8a77990 # R-Car E3 + - const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2 + + reg: + maxItems: 1 + + interrupts: + minItems: 3 + maxItems: 3 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: pcie + - const: pcie_bus + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@fe000000 { + compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>, + <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 319>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt deleted file mode 100644 index 14d307deff06..000000000000 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ /dev/null @@ -1,72 +0,0 @@ -* Renesas R-Car PCIe interface - -Required properties: -compatible: "renesas,pcie-r8a7742" for the R8A7742 SoC; - "renesas,pcie-r8a7743" for the R8A7743 SoC; - "renesas,pcie-r8a7744" for the R8A7744 SoC; - "renesas,pcie-r8a774a1" for the R8A774A1 SoC; - "renesas,pcie-r8a774b1" for the R8A774B1 SoC; - "renesas,pcie-r8a774c0" for the R8A774C0 SoC; - "renesas,pcie-r8a7779" for the R8A7779 SoC; - "renesas,pcie-r8a7790" for the R8A7790 SoC; - "renesas,pcie-r8a7791" for the R8A7791 SoC; - "renesas,pcie-r8a7793" for the R8A7793 SoC; - "renesas,pcie-r8a7795" for the R8A7795 SoC; - "renesas,pcie-r8a7796" for the R8A77960 SoC; - "renesas,pcie-r8a77961" for the R8A77961 SoC; - "renesas,pcie-r8a77980" for the R8A77980 SoC; - "renesas,pcie-r8a77990" for the R8A77990 SoC; - "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or - RZ/G1 compatible device. - "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 or - RZ/G2 compatible device. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: base address and length of the PCIe controller registers. -- #address-cells: set to <3> -- #size-cells: set to <2> -- bus-range: PCI bus numbers covered -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions. -- dma-ranges: ranges for the inbound memory regions. -- interrupts: two interrupt sources for MSI interrupts, followed by interrupt - source for hardware related interrupts (e.g. link speed change). -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map: standard PCI properties - to define the mapping of the PCIe interface to interrupt numbers. -- clocks: from common clock binding: clock specifiers for the PCIe controller - and PCIe bus clocks. -- clock-names: from common clock binding: should be "pcie" and "pcie_bus". - -Optional properties: -- phys: from common PHY binding: PHY phandle and specifier (only make sense - for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks). -- phy-names: from common PHY binding: should be "pcie". - -Example: - -SoC-specific DT Entry: - - pcie: pcie@fe000000 { - compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 - 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 - 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 - 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000 - 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; - interrupts = <0 116 4>, <0 117 4>, <0 118 4>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 116 4>; - clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - }; -- cgit v1.2.3 From 2228af80935aa5440dff2e5b3a2c5d25d9d61334 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 4 Nov 2020 10:58:15 +0900 Subject: dt-bindings: PCI: rcar-pci-host: Document r8a77965 bindings Document the R-Car M3-N (R8A77965) SoC in the R-Car PCIe bindings. Link: https://lore.kernel.org/r/1604455096-13923-3-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Yoshihiro Shimoda Signed-off-by: Lorenzo Pieralisi Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/rcar-pci-host.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml index 40c38a6612a8..c93b0d14589e 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml @@ -34,6 +34,7 @@ properties: - renesas,pcie-r8a7795 # R-Car H3 - renesas,pcie-r8a7796 # R-Car M3-W - renesas,pcie-r8a77961 # R-Car M3-W+ + - renesas,pcie-r8a77965 # R-Car M3-N - renesas,pcie-r8a77980 # R-Car V3H - renesas,pcie-r8a77990 # R-Car E3 - const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2 -- cgit v1.2.3 From 64fc0a030987eec45c5362618bacdef7227783d5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 4 Nov 2020 10:58:16 +0900 Subject: dt-bindings: PCI: rcar-pci-host: Document r8a774e1 bindings Document the RZ/G2H (a.k.a. R8A774E1) SoC in the R-Car PCIe bingings. [shimoda: minor change the subject and description] Link: https://lore.kernel.org/r/1604455096-13923-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Lad Prabhakar Signed-off-by: Yoshihiro Shimoda Signed-off-by: Lorenzo Pieralisi Reviewed-by: Marian-Cristian Rotariu Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/rcar-pci-host.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml index c93b0d14589e..4a2bcc0158e2 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml @@ -31,6 +31,7 @@ properties: - renesas,pcie-r8a774a1 # RZ/G2M - renesas,pcie-r8a774b1 # RZ/G2N - renesas,pcie-r8a774c0 # RZ/G2E + - renesas,pcie-r8a774e1 # RZ/G2H - renesas,pcie-r8a7795 # R-Car H3 - renesas,pcie-r8a7796 # R-Car M3-W - renesas,pcie-r8a77961 # R-Car M3-W+ -- cgit v1.2.3 From 4a2b9125c9851b0f7894b93daeaf4900ec95606f Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Fri, 6 Nov 2020 20:41:06 +0530 Subject: dt-bindings: PCI: Make "cdns,max-outbound-regions" optional property Make "cdns,max-outbound-regions" optional property with the default being 32. Link: http://lore.kernel.org/r/20201105165331.GA55814@bogus Link: https://lore.kernel.org/r/20201106151107.3987-2-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml | 3 --- Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 2 -- 2 files changed, 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml index 60b8baf299bb..21e8a8849076 100644 --- a/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml @@ -20,7 +20,4 @@ properties: maximum: 32 default: 32 -required: - - cdns,max-outbound-regions - additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 3ae3e1a2d4b0..aae07b723fb5 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -57,7 +57,6 @@ required: - power-domains - clocks - clock-names - - cdns,max-outbound-regions - dma-coherent - max-functions - phys @@ -86,7 +85,6 @@ examples: power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 239 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; dma-coherent; phys = <&serdes0_pcie_link>; -- cgit v1.2.3 From 83fbffcd1329dfd5254f020b542857b7833d227b Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 13 Nov 2020 18:01:35 +0100 Subject: dt-bindings: PCI: exynos: drop samsung,exynos5440-pcie binding Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM: dts: exynos: Remove Exynos5440"). Drop the obsolete bindings for exynos5440-pcie. Link: https://lore.kernel.org/r/20201113170139.29956-2-m.szyprowski@samsung.com Signed-off-by: Marek Szyprowski Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Reviewed-by: Jingoo Han --- .../bindings/pci/samsung,exynos5440-pcie.txt | 58 ---------------------- 1 file changed, 58 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt deleted file mode 100644 index 651d957d1051..000000000000 --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Samsung Exynos 5440 PCIe interface - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. - -Required properties: -- compatible: "samsung,exynos5440-pcie" -- reg: base addresses and lengths of the PCIe controller, -- reg-names : First name should be set to "elbi". - And use the "config" instead of getting the configuration address space - from "ranges". - NOTE: When using the "config" property, reg-names must be set. -- interrupts: A list of interrupt outputs for level interrupt, - pulse interrupt, special interrupt. -- phys: From PHY binding. Phandle for the generic PHY. - Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt - -For other common properties, refer to - Documentation/devicetree/bindings/pci/designware-pcie.txt - -Example: - -SoC-specific DT Entry (with using PHY framework): - - pcie_phy0: pcie-phy@270000 { - ... - reg = <0x270000 0x1000>, <0x271000 0x40>; - reg-names = "phy", "block"; - ... - }; - - pcie@290000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x290000 0x1000>, <0x40000000 0x1000>; - reg-names = "elbi", "config"; - clocks = <&clock 28>, <&clock 27>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - phys = <&pcie_phy0>; - ranges = <0x81000000 0 0 0x60001000 0 0x00010000 - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - num-lanes = <4>; - }; - -Board-specific DT Entry: - - pcie@290000 { - reset-gpio = <&pin_ctrl 5 0>; - }; - - pcie@2a0000 { - reset-gpio = <&pin_ctrl 22 0>; - }; -- cgit v1.2.3 From eea23e4a00d479eea6d15a78b79f0c58e8ee4467 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 13 Nov 2020 18:01:36 +0100 Subject: dt-bindings: PCI: exynos: add the samsung,exynos-pcie binding Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433 variant). Based on the text dt-binding posted by Jaehoon Chung. Link: https://lore.kernel.org/r/20201113170139.29956-3-m.szyprowski@samsung.com Signed-off-by: Marek Szyprowski Signed-off-by: Lorenzo Pieralisi Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../bindings/pci/samsung,exynos-pcie.yaml | 119 +++++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml new file mode 100644 index 000000000000..1810bf722350 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe Host Controller Device Tree Bindings + +maintainers: + - Marek Szyprowski + - Jaehoon Chung + +description: |+ + Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + designware-pcie.txt. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: samsung,exynos5433-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: External Local Bus interface (ELBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: elbi + - const: config + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PCIe bridge clock + - description: PCIe bus clock + + clock-names: + items: + - const: pcie + - const: pcie_bus + + phys: + maxItems: 1 + + vdd10-supply: + description: + Phandle to a regulator that provides 1.0V power to the PCIe block. + + vdd18-supply: + description: + Phandle to a regulator that provides 1.8V power to the PCIe block. + + num-lanes: + const: 1 + + num-viewport: + const: 3 + +required: + - reg + - reg-names + - interrupts + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + - ranges + - bus-range + - device_type + - num-lanes + - num-viewport + - clocks + - clock-names + - phys + - vdd10-supply + - vdd18-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + pcie: pcie@15700000 { + compatible = "samsung,exynos5433-pcie"; + reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>; + reg-names = "dbi", "elbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = ; + clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>; + clock-names = "pcie", "pcie_bus"; + phys = <&pcie_phy>; + pinctrl-0 = <&pcie_bus &pcie_wlanen>; + pinctrl-names = "default"; + num-lanes = <1>; + num-viewport = <3>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; + vdd10-supply = <&ldo6_reg>; + vdd18-supply = <&ldo7_reg>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + }; +... -- cgit v1.2.3 From a7b4dba9a71d64e07fbc9802bbc1eaad5494f071 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 13 Nov 2020 18:01:37 +0100 Subject: dt-bindings: phy: exynos: add the samsung,exynos-pcie-phy binding Add dt-bindings for the Samsung Exynos PCIe PHY controller (Exynos5433 variant). Based on the text dt-binding posted by Jaehoon Chung. Link: https://lore.kernel.org/r/20201113170139.29956-4-m.szyprowski@samsung.com Signed-off-by: Marek Szyprowski Signed-off-by: Lorenzo Pieralisi Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml new file mode 100644 index 000000000000..ac0af40be52d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe PHY Device Tree Bindings + +maintainers: + - Marek Szyprowski + - Jaehoon Chung + +properties: + "#phy-cells": + const: 0 + + compatible: + const: samsung,exynos5433-pcie-phy + + reg: + maxItems: 1 + + samsung,pmu-syscon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for PMU system controller interface, used to + control PMU registers bits for PCIe PHY + + samsung,fsys-sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for FSYS sysreg interface, used to control + sysreg registers bits for PCIe PHY + +required: + - "#phy-cells" + - compatible + - reg + - samsung,pmu-syscon + - samsung,fsys-sysreg + +additionalProperties: false + +examples: + - | + pcie_phy: pcie-phy@15680000 { + compatible = "samsung,exynos5433-pcie-phy"; + reg = <0x15680000 0x1000>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,fsys-sysreg = <&syscon_fsys>; + #phy-cells = <0>; + }; +... -- cgit v1.2.3 From 80a129afb75cba8434fc5071bd6919172442315c Mon Sep 17 00:00:00 2001 From: Maximilian Luz Date: Mon, 2 Nov 2020 15:15:20 +0100 Subject: PCI: Add sysfs attribute for device power state While PCI power states D0-D3hot can be queried from user-space via lspci, D3cold cannot. lspci cannot provide an accurate value when the device is in D3cold as it has to restore the device to D0 before it can access its power state via the configuration space, leading to it reporting D0 or another on-state. Thus lspci cannot be used to diagnose power consumption issues for devices that can enter D3cold or to ensure that devices properly enter D3cold at all. Add a new sysfs device attribute for the PCI power state, showing the current power state as seen by the kernel. [bhelgaas: drop READ_ONCE(), see discussion at the link] Link: https://lore.kernel.org/r/20201102141520.831630-1-luzmaximilian@gmail.com Signed-off-by: Maximilian Luz Signed-off-by: Bjorn Helgaas --- Documentation/ABI/testing/sysfs-bus-pci | 9 +++++++++ drivers/pci/pci-sysfs.c | 10 ++++++++++ 2 files changed, 19 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci index 77ad9ec3c801..25c9c39770c6 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci +++ b/Documentation/ABI/testing/sysfs-bus-pci @@ -366,3 +366,12 @@ Contact: Heiner Kallweit Description: If ASPM is supported for an endpoint, these files can be used to disable or enable the individual power management states. Write y/1/on to enable, n/0/off to disable. + +What: /sys/bus/pci/devices/.../power_state +Date: November 2020 +Contact: Linux PCI developers +Description: + This file contains the current PCI power state of the device. + The value comes from the PCI kernel device state and can be one + of: "unknown", "error", "D0", D1", "D2", "D3hot", "D3cold". + The file is read only. diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index d15c881e2e7e..fb072f4b3176 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -124,6 +124,15 @@ static ssize_t cpulistaffinity_show(struct device *dev, } static DEVICE_ATTR_RO(cpulistaffinity); +static ssize_t power_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + + return sprintf(buf, "%s\n", pci_power_name(pdev->current_state)); +} +static DEVICE_ATTR_RO(power_state); + /* show resources */ static ssize_t resource_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -581,6 +590,7 @@ static ssize_t driver_override_show(struct device *dev, static DEVICE_ATTR_RW(driver_override); static struct attribute *pci_dev_attrs[] = { + &dev_attr_power_state.attr, &dev_attr_resource.attr, &dev_attr_vendor.attr, &dev_attr_device.attr, -- cgit v1.2.3 From 458168247cccd3b22d9d34805dfb0596c5502888 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 8 Dec 2020 17:44:00 +0530 Subject: dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC Document the PCIe DT bindings for SM8250 SoC. The PCIe IP is similar to the one used on SDM845, hence just add the compatible along with the optional "atu" register region. Link: https://lore.kernel.org/r/20201208121402.178011-2-mani@kernel.org Signed-off-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Pieralisi Reviewed-by: Bjorn Andersson Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 02bc81bb8b2d..3b55310390a0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -13,6 +13,7 @@ - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sdm845" for sdm845 + - "qcom,pcie-sm8250" for sm8250 - reg: Usage: required @@ -27,6 +28,7 @@ - "dbi" DesignWare PCIe registers - "elbi" External local bus interface registers - "config" PCIe configuration space + - "atu" ATU address space (optional) - device_type: Usage: required @@ -131,7 +133,7 @@ - "slave_bus" AXI Slave clock -clock-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -206,7 +208,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: Definition: Should contain the following entries - "pci" PCIe core reset -- cgit v1.2.3 From b6c81be9129344f66b60cc6529369cbed2ce238e Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 10 Dec 2020 18:19:14 +0530 Subject: dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with argument. The argument is the register offset within "syscon" used to configure PCIe controller. This change is as discussed in [1] [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Link: https://lore.kernel.org/r/20201210124917.24185-2-kishon@ti.com Fixes: 431b53b81cdc ("dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC") Fixes: 45b39e928966 ("dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC") Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 11 +++++++---- Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 11 +++++++---- 2 files changed, 14 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index aae07b723fb5..32213b30ce90 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -29,9 +29,12 @@ properties: - const: mem ti,syscon-pcie-ctrl: - description: Phandle to the SYSCON entry required for configuring PCIe mode - and link speed. - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: pcie_ctrl register offset within SYSCON + description: Specifier for configuring PCIe mode and link speed. power-domains: maxItems: 1 @@ -79,7 +82,7 @@ examples: <0x00 0x0d000000 0x00 0x00800000>, <0x00 0x10000000 0x00 0x08000000>; reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index ee7a8eade3f6..2b6a1a5eaf7a 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -29,9 +29,12 @@ properties: - const: cfg ti,syscon-pcie-ctrl: - description: Phandle to the SYSCON entry required for configuring PCIe mode - and link speed. - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: pcie_ctrl register offset within SYSCON + description: Specifier for configuring PCIe mode and link speed. power-domains: maxItems: 1 @@ -90,7 +93,7 @@ examples: <0x00 0x0d000000 0x00 0x00800000>, <0x00 0x10000000 0x00 0x00001000>; reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; -- cgit v1.2.3 From 3f1f870c018ffd0db1a5a123d2090ac45c5fb9e9 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 10 Dec 2020 18:19:15 +0530 Subject: dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC Add host mode dt-bindings for TI's J7200 SoC. Link: https://lore.kernel.org/r/20201210124917.24185-3-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 2b6a1a5eaf7a..0880a613ece6 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -15,8 +15,14 @@ allOf: properties: compatible: - enum: - - ti,j721e-pcie-host + oneOf: + - description: PCIe controller in J7200 + items: + - const: ti,j7200-pcie-host + - const: ti,j721e-pcie-host + - description: PCIe controller in J721E + items: + - const: ti,j721e-pcie-host reg: maxItems: 4 @@ -51,7 +57,11 @@ properties: const: 0x104c device-id: - const: 0xb00d + oneOf: + - items: + - const: 0xb00d + - items: + - const: 0xb00f msi-map: true -- cgit v1.2.3 From 17c5b458a99049eec6915bc4b2188b8540cc22b0 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 10 Dec 2020 18:19:16 +0530 Subject: dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC Add PCIe EP mode dt-bindings for TI's J7200 SoC. Link: https://lore.kernel.org/r/20201210124917.24185-4-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 32213b30ce90..d06f0c4464c6 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -15,8 +15,14 @@ allOf: properties: compatible: - enum: - - ti,j721e-pcie-ep + oneOf: + - description: PCIe EP controller in J7200 + items: + - const: ti,j7200-pcie-ep + - const: ti,j721e-pcie-ep + - description: PCIe EP controller in J721E + items: + - const: ti,j721e-pcie-ep reg: maxItems: 4 -- cgit v1.2.3