From f643490e1bf941600f6105e4d27c49054fb6d562 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Thu, 3 Mar 2022 17:35:42 -0500 Subject: dt-bindings: pwm: Add Xilinx AXI Timer This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a "soft" block, so it has some parameters which would not be configurable in most hardware. This binding is usually automatically generated by Xilinx's tools, so the names and values of some properties should be kept as they are, if possible. In addition, this binding is already in the kernel at arch/microblaze/boot/dts/system.dts, and in user software such as QEMU. The existing driver uses the clock-frequency property, or alternatively the /cpus/timebase-frequency property as its frequency input. Because these properties are deprecated, they have not been included with this schema. All new bindings should use the clocks/clock-names properties to specify the parent clock. Because we need to init timer devices so early in boot, we determine if we should use the PWM driver or the clocksource/clockevent driver by the presence/absence, respectively, of #pwm-cells. Because both counters are used by the PWM, there is no need for a separate property specifying which counters are to be used for the PWM. Signed-off-by: Sean Anderson Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/timer/xlnx,xps-timer.yaml | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml new file mode 100644 index 000000000000..dd168d41d2e0 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding + +maintainers: + - Sean Anderson + +properties: + compatible: + contains: + const: xlnx,xps-timer-1.00.a + + clocks: + maxItems: 1 + + clock-names: + const: s_axi_aclk + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + '#pwm-cells': true + + xlnx,count-width: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16, 32] + default: 32 + description: + The width of the counter(s), in bits. + + xlnx,one-timer-only: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + Whether only one timer is present in this block. + +required: + - compatible + - reg + - xlnx,one-timer-only + +allOf: + - if: + required: + - '#pwm-cells' + then: + allOf: + - required: + - clocks + - properties: + xlnx,one-timer-only: + const: 0 + else: + required: + - interrupts + - if: + required: + - clocks + then: + required: + - clock-names + +additionalProperties: false + +examples: + - | + timer@800e0000 { + clock-names = "s_axi_aclk"; + clocks = <&zynqmp_clk 71>; + compatible = "xlnx,xps-timer-1.00.a"; + reg = <0x800e0000 0x10000>; + interrupts = <0 39 2>; + xlnx,count-width = <16>; + xlnx,one-timer-only = <0x0>; + }; + + timer@800f0000 { + #pwm-cells = <0>; + clock-names = "s_axi_aclk"; + clocks = <&zynqmp_clk 71>; + compatible = "xlnx,xps-timer-1.00.a"; + reg = <0x800e0000 0x10000>; + xlnx,count-width = <32>; + xlnx,one-timer-only = <0x0>; + }; -- cgit v1.2.3 From 1a406a38bc1d66f68bac30cf8d83fcff621ff79c Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Mon, 7 Mar 2022 17:36:55 +0200 Subject: dt-bindings: pwm: Convert atmel pwm to json-schema Convert PWM binding for Atmel/Microchip SoCs to Device Tree Schema format. Signed-off-by: Sergiu Moga Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- .../devicetree/bindings/pwm/atmel,at91sam-pwm.yaml | 42 ++++++++++++++++++++++ .../devicetree/bindings/pwm/atmel-pwm.txt | 35 ------------------ MAINTAINERS | 2 +- 3 files changed, 43 insertions(+), 36 deletions(-) create mode 100644 Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml delete mode 100644 Documentation/devicetree/bindings/pwm/atmel-pwm.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml new file mode 100644 index 000000000000..5e8bb5a8095d --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/atmel,at91sam-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel/Microchip PWM controller + +maintainers: + - Claudiu Beznea + +allOf: + - $ref: "pwm.yaml#" + +properties: + compatible: + enum: + - atmel,at91sam9rl-pwm + - atmel,sama5d3-pwm + - atmel,sama5d2-pwm + - microchip,sam9x60-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pwm0: pwm@f8034000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xf8034000 0x400>; + #pwm-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-pwm.txt deleted file mode 100644 index fbb5325be1f0..000000000000 --- a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt +++ /dev/null @@ -1,35 +0,0 @@ -Atmel PWM controller - -Required properties: - - compatible: should be one of: - - "atmel,at91sam9rl-pwm" - - "atmel,sama5d3-pwm" - - "atmel,sama5d2-pwm" - - "microchip,sam9x60-pwm" - - reg: physical base address and length of the controller's registers - - #pwm-cells: Should be 3. See pwm.yaml in this directory for a - description of the cells format. - -Example: - - pwm0: pwm@f8034000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xf8034000 0x400>; - #pwm-cells = <3>; - }; - - pwmleds { - compatible = "pwm-leds"; - - d1 { - label = "d1"; - pwms = <&pwm0 3 5000 0> - max-brightness = <255>; - }; - - d2 { - label = "d2"; - pwms = <&pwm0 1 5000 1> - max-brightness = <255>; - }; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 009ecbc44a73..6fa5010e8c2d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12959,7 +12959,7 @@ M: Claudiu Beznea L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-pwm@vger.kernel.org S: Supported -F: Documentation/devicetree/bindings/pwm/atmel-pwm.txt +F: Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml F: drivers/pwm/pwm-atmel.c MICROCHIP SAMA5D2-COMPATIBLE ADC DRIVER -- cgit v1.2.3 From f30673a9df34931cbfb9b51da00dd185a3cd4566 Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Mon, 7 Mar 2022 17:36:56 +0200 Subject: dt-bindings: pwm: at91: Add SAMA7G5 compatible strings list Add compatible strings list for SAMA7G5. Signed-off-by: Sergiu Moga Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- .../devicetree/bindings/pwm/atmel,at91sam-pwm.yaml | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml index 5e8bb5a8095d..ab45df80345d 100644 --- a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml @@ -15,11 +15,16 @@ allOf: properties: compatible: - enum: - - atmel,at91sam9rl-pwm - - atmel,sama5d3-pwm - - atmel,sama5d2-pwm - - microchip,sam9x60-pwm + oneOf: + - items: + - enum: + - atmel,at91sam9rl-pwm + - atmel,sama5d3-pwm + - atmel,sama5d2-pwm + - microchip,sam9x60-pwm + - items: + - const: microchip,sama7g5-pwm + - const: atmel,sama5d2-pwm reg: maxItems: 1 -- cgit v1.2.3 From 15452ce3c9467bdd15002f5bc56cd2c13e7b1aa0 Mon Sep 17 00:00:00 2001 From: Hammer Hsieh Date: Tue, 22 Mar 2022 18:43:00 +0800 Subject: dt-bindings: pwm: Add bindings doc for Sunplus SoC SP7021 PWM Driver Add bindings doc for Sunplus SoC SP7021 PWM Driver Reviewed-by: Krzysztof Kozlowski Signed-off-by: Hammer Hsieh Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/pwm/sunplus,sp7021-pwm.yaml | 42 ++++++++++++++++++++++ MAINTAINERS | 5 +++ 2 files changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/sunplus,sp7021-pwm.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/sunplus,sp7021-pwm.yaml b/Documentation/devicetree/bindings/pwm/sunplus,sp7021-pwm.yaml new file mode 100644 index 000000000000..d4fc9e8db1d1 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/sunplus,sp7021-pwm.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/sunplus,sp7021-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SoC SP7021 PWM Controller + +maintainers: + - Hammer Hsieh + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: sunplus,sp7021-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#pwm-cells': + const: 2 + +unevaluatedProperties: false + +required: + - reg + - clocks + +examples: + - | + pwm: pwm@9c007a00 { + compatible = "sunplus,sp7021-pwm"; + reg = <0x9c007a00 0x80>; + clocks = <&clkc 0xa2>; + #pwm-cells = <2>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 6fa5010e8c2d..3c994dbd643f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18873,6 +18873,11 @@ S: Maintained F: Documentation/devicetree/bindings/nvmem/sunplus,sp7021-ocotp.yaml F: drivers/nvmem/sunplus-ocotp.c +SUNPLUS PWM DRIVER +M: Hammer Hsieh +S: Maintained +F: Documentation/devicetree/bindings/pwm/sunplus,sp7021-pwm.yaml + SUNPLUS RTC DRIVER M: Vincent Shih L: linux-rtc@vger.kernel.org -- cgit v1.2.3 From b09b179bac0aa3d58d79729260a7492df8a1e312 Mon Sep 17 00:00:00 2001 From: Xinlei Lee Date: Mon, 18 Apr 2022 20:20:52 +0800 Subject: dt-bindings: pwm: Convert pwm-mtk-disp.txt to mediatek,pwm-disp.yaml format Convert pwm-mtk-disp.txt to mediatek,pwm-disp.yaml format as suggested by maintainer. Signed-off-by: Xinlei Lee Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 66 ++++++++++++++++++++++ .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 45 --------------- 2 files changed, 66 insertions(+), 45 deletions(-) create mode 100644 Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml new file mode 100644 index 000000000000..36f877f819fa --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek DISP_PWM Controller Device Tree Bindings + +maintainers: + - Jitao Shi + - Xinlei Lee + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2701-disp-pwm + - mediatek,mt6595-disp-pwm + - mediatek,mt8173-disp-pwm + - mediatek,mt8183-disp-pwm + - items: + - const: mediatek,mt8167-disp-pwm + - const: mediatek,mt8173-disp-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 2 + + clocks: + items: + - description: Main Clock + - description: Mm Clock + + clock-names: + items: + - const: main + - const: mm + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + pwm0: pwm@1401e000 { + compatible = "mediatek,mt8173-disp-pwm"; + reg = <0x1401e000 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_DISP_PWM026M>, + <&mmsys CLK_MM_DISP_PWM0MM>; + clock-names = "main", "mm"; + }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt deleted file mode 100644 index 691e58b6c223..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt +++ /dev/null @@ -1,45 +0,0 @@ -MediaTek display PWM controller - -Required properties: - - compatible: should be "mediatek,-disp-pwm": - - "mediatek,mt2701-disp-pwm": found on mt2701 SoC. - - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. - - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC. - - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. - - "mediatek,mt8183-disp-pwm": found on mt8183 SoC.$ - - reg: physical base address and length of the controller's registers. - - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of - the cell format. - - clocks: phandle and clock specifier of the PWM reference clock. - - clock-names: must contain the following: - - "main": clock used to generate PWM signals. - - "mm": sync signals from the modules of mmsys. - - pinctrl-names: Must contain a "default" entry. - - pinctrl-0: One property must exist for each entry in pinctrl-names. - See pinctrl/pinctrl-bindings.txt for details of the property values. - -Example: - pwm0: pwm@1401e000 { - compatible = "mediatek,mt8173-disp-pwm", - "mediatek,mt6595-disp-pwm"; - reg = <0 0x1401e000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&mmsys CLK_MM_DISP_PWM026M>, - <&mmsys CLK_MM_DISP_PWM0MM>; - clock-names = "main", "mm"; - pinctrl-names = "default"; - pinctrl-0 = <&disp_pwm0_pins>; - }; - - backlight_lcd: backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 1000000>; - brightness-levels = < - 0 16 32 48 64 80 96 112 - 128 144 160 176 192 208 224 240 - 255 - >; - default-brightness-level = <9>; - power-supply = <&mt6397_vio18_reg>; - enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; - }; -- cgit v1.2.3 From b8ba2b42b0e9cf6d2788e423f8fe2ba4fcc2539d Mon Sep 17 00:00:00 2001 From: Xinlei Lee Date: Mon, 18 Apr 2022 20:20:53 +0800 Subject: dt-bindings: pwm: Add compatible for MediaTek MT8192 Add dt-binding documentation of pwm for MediaTek MT8192 SoC. Signed-off-by: Xinlei Lee Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 36f877f819fa..4bfa8eb42186 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -24,6 +24,10 @@ properties: - items: - const: mediatek,mt8167-disp-pwm - const: mediatek,mt8173-disp-pwm + - items: + - enum: + - mediatek,mt8192-disp-pwm + - const: mediatek,mt8183-disp-pwm reg: maxItems: 1 -- cgit v1.2.3 From 7eafddce08617b4fdbd9485fa88bb749c8c7125a Mon Sep 17 00:00:00 2001 From: Xinlei Lee Date: Mon, 18 Apr 2022 20:20:54 +0800 Subject: dt-bindings: pwm: Add compatible for MediaTek MT8195 Add dt-binding documentation of pwm for MediaTek MT8195 SoC. Signed-off-by: Xinlei Lee Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 4bfa8eb42186..e5da918eaa33 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: - mediatek,mt8192-disp-pwm + - mediatek,mt8195-disp-pwm - const: mediatek,mt8183-disp-pwm reg: -- cgit v1.2.3 From 6ddb156ba4749a64293b5c4079406de178e2e5cd Mon Sep 17 00:00:00 2001 From: Xinlei Lee Date: Mon, 18 Apr 2022 20:20:55 +0800 Subject: dt-bindings: pwm: Add compatible for MediaTek MT8186 Add dt-binding documentation of pwm for MediaTek MT8186 SoC. Signed-off-by: Xinlei Lee Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index e5da918eaa33..4b71bd668d33 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -26,6 +26,7 @@ properties: - const: mediatek,mt8173-disp-pwm - items: - enum: + - mediatek,mt8186-disp-pwm - mediatek,mt8192-disp-pwm - mediatek,mt8195-disp-pwm - const: mediatek,mt8183-disp-pwm -- cgit v1.2.3 From 2bf8ee0faa988b5cec3503ebf2f970a0e84d24ee Mon Sep 17 00:00:00 2001 From: Xinlei Lee Date: Mon, 18 Apr 2022 20:20:56 +0800 Subject: dt-bindings: pwm: Add interrupts property for MediaTek MT8192 Add interrupts property of pwm for MediaTek MT8192 SoC. Signed-off-by: Xinlei Lee Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 4b71bd668d33..e4fe2d1bfef5 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -37,6 +37,9 @@ properties: "#pwm-cells": const: 2 + interrupts: + maxItems: 1 + clocks: items: - description: Main Clock -- cgit v1.2.3 From b76160954cb0fc8b4a389e54daf22a87d4f44fbe Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 3 May 2022 12:54:05 +0200 Subject: dt-bindings: pwm: pwm-mediatek: Add documentation for MT6795 SoC Add binding documentation for the MT6795 Helio X10 SoC. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index 25ed214473d7..033d1fc0f405 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -3,6 +3,7 @@ MediaTek PWM controller Required properties: - compatible: should be "mediatek,-pwm": - "mediatek,mt2712-pwm": found on mt2712 SoC. + - "mediatek,mt6795-pwm": found on mt6795 SoC. - "mediatek,mt7622-pwm": found on mt7622 SoC. - "mediatek,mt7623-pwm": found on mt7623 SoC. - "mediatek,mt7628-pwm": found on mt7628 SoC. -- cgit v1.2.3 From a48d66d87274b7ec538cdf82abc8d3ebf4bf0363 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Thu, 28 Apr 2022 10:04:20 +0000 Subject: dt-bindings: google,cros-ec-pwm: Add the new -type compatible Update google,cros-ec-pwm node documentation to mention the google,cros-ec-pwm-type compatible as a valid alternative. Signed-off-by: Fabio Baltieri Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml index 7ab6912a845f..c8577bdf6c94 100644 --- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml @@ -21,7 +21,14 @@ allOf: properties: compatible: - const: google,cros-ec-pwm + oneOf: + - description: PWM controlled using EC_PWM_TYPE_GENERIC channels. + items: + - const: google,cros-ec-pwm + - description: PWM controlled using CROS_EC_PWM_DT_<...> types. + items: + - const: google,cros-ec-pwm-type + "#pwm-cells": description: The cell specifies the PWM index. const: 1 -- cgit v1.2.3