From 74a6f1e8fb40738e7816c1d16479590e3fbed42d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Jul 2023 16:15:49 +0200 Subject: dt-bindings: usb: qcom,dwc3: drop assigned-clocks The binding does not have to specify assigned-clocks, because they are already allowed by core DT schema. On the other hand, fixed assigned-clocks in the binding will not fit different boards or SoCs. Exactly this is the case for Qualcomm SuperSpeed DWC3 USB SoC controller binding, where few boards have different assigned-clocks: ipq8074-hk10-c1.dtb: usb@8cf8800: assigned-clocks: [[5, 131], [5, 132], [5, 133]] is too long sdm660-xiaomi-lavender.dtb: usb@a8f8800: assigned-clocks: [[37, 92], [37, 91], [38, 64]] is too long Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20230723141550.90223-1-krzysztof.kozlowski@linaro.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 9 --------- 1 file changed, 9 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index 9447b54bfb23..33f299f0685d 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -83,15 +83,6 @@ properties: minItems: 1 maxItems: 9 - assigned-clocks: - items: - - description: Phandle and clock specifier of MOCK_UTMI_CLK. - - description: Phandle and clock specifoer of MASTER_CLK. - - assigned-clock-rates: - items: - - description: Must be 19.2MHz (19200000). - - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode. resets: maxItems: 1 -- cgit v1.2.3