From 3428b96f2f0d7a2c18d95478657d4aba5a0a331a Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 15 Mar 2020 12:16:32 -0700 Subject: dt-bindings: usb: document aspeed vhub device ID/string properties Update device tree binding document for aspeed vhub's device IDs and string properties. Signed-off-by: Tao Ren Signed-off-by: Felipe Balbi --- .../devicetree/bindings/usb/aspeed,usb-vhub.yaml | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/aspeed,usb-vhub.yaml b/Documentation/devicetree/bindings/usb/aspeed,usb-vhub.yaml index 06399ba0d9e4..5b2e8d867219 100644 --- a/Documentation/devicetree/bindings/usb/aspeed,usb-vhub.yaml +++ b/Documentation/devicetree/bindings/usb/aspeed,usb-vhub.yaml @@ -52,6 +52,59 @@ properties: minimum: 1 maximum: 21 + vhub-vendor-id: + description: vhub Vendor ID + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - maximum: 65535 + + vhub-product-id: + description: vhub Product ID + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - maximum: 65535 + + vhub-device-revision: + description: vhub Device Revision in binary-coded decimal + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - maximum: 65535 + + vhub-strings: + type: object + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + '^string@[0-9a-f]+$': + type: object + description: string descriptors of the specific language + + properties: + reg: + maxItems: 1 + description: 16-bit Language Identifier defined by USB-IF + + manufacturer: + description: vhub manufacturer + allOf: + - $ref: /schemas/types.yaml#/definitions/string + + product: + description: vhub product name + allOf: + - $ref: /schemas/types.yaml#/definitions/string + + serial-number: + description: vhub device serial number + allOf: + - $ref: /schemas/types.yaml#/definitions/string + required: - compatible - reg @@ -74,4 +127,19 @@ examples: aspeed,vhub-generic-endpoints = <15>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2ad_default>; + + vhub-vendor-id = <0x1d6b>; + vhub-product-id = <0x0107>; + vhub-device-revision = <0x0100>; + vhub-strings { + #address-cells = <1>; + #size-cells = <0>; + + string@0409 { + reg = <0x0409>; + manufacturer = "ASPEED"; + product = "USB Virtual Hub"; + serial-number = "0000"; + }; + }; }; -- cgit v1.2.3 From cd4b54e2ae1f47c72c004628788e84ffe7c71561 Mon Sep 17 00:00:00 2001 From: Sandeep Maheswaram Date: Thu, 26 Mar 2020 12:36:07 +0530 Subject: dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings Convert USB DWC3 bindings to DT schema format using json-schema. Signed-off-by: Sandeep Maheswaram Signed-off-by: Felipe Balbi --- .../devicetree/bindings/usb/qcom,dwc3.txt | 104 -------------- .../devicetree/bindings/usb/qcom,dwc3.yaml | 158 +++++++++++++++++++++ 2 files changed, 158 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.yaml (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt deleted file mode 100644 index fbdd01756752..000000000000 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt +++ /dev/null @@ -1,104 +0,0 @@ -Qualcomm SuperSpeed DWC3 USB SoC controller - -Required properties: -- compatible: Compatible list, contains - "qcom,dwc3" - "qcom,msm8996-dwc3" for msm8996 SOC. - "qcom,msm8998-dwc3" for msm8998 SOC. - "qcom,sdm845-dwc3" for sdm845 SOC. -- reg: Offset and length of register set for QSCRATCH wrapper -- power-domains: specifies a phandle to PM domain provider node -- clocks: A list of phandle + clock-specifier pairs for the - clocks listed in clock-names -- clock-names: Should contain the following: - "core" Master/Core clock, have to be >= 125 MHz for SS - operation and >= 60MHz for HS operation - "mock_utmi" Mock utmi clock needed for ITP/SOF generation in - host mode. Its frequency should be 19.2MHz. - "sleep" Sleep clock, used for wakeup when USB3 core goes - into low power mode (U3). - -Optional clocks: - "iface" System bus AXI clock. - Not present on "qcom,msm8996-dwc3" compatible. - "cfg_noc" System Config NOC clock. - Not present on "qcom,msm8996-dwc3" compatible. -- assigned-clocks: Should be: - MOCK_UTMI_CLK - MASTER_CLK -- assigned-clock-rates: Should be: - 19.2Mhz (192000000) for MOCK_UTMI_CLK - >=125Mhz (125000000) for MASTER_CLK in SS mode - >=60Mhz (60000000) for MASTER_CLK in HS mode - -Optional properties: -- resets: Phandle to reset control that resets core and wrapper. -- interrupts: specifies interrupts from controller wrapper used - to wakeup from low power/susepnd state. Must contain - one or more entry for interrupt-names property -- interrupt-names: Must include the following entries: - - "hs_phy_irq": The interrupt that is asserted when a - wakeup event is received on USB2 bus - - "ss_phy_irq": The interrupt that is asserted when a - wakeup event is received on USB3 bus - - "dm_hs_phy_irq" and "dp_hs_phy_irq": Separate - interrupts for any wakeup event on DM and DP lines -- qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement. - Used when dwc3 operates without SSPHY and only - HS/FS/LS modes are supported. - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -Phy documentation is provided in the following places: -Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY -Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml - USB2 QUSB2 PHY - -Example device nodes: - - hs_phy: phy@100f8800 { - compatible = "qcom,qusb2-v2-phy"; - ... - }; - - ss_phy: phy@100f8830 { - compatible = "qcom,qmp-v3-usb3-phy"; - ... - }; - - usb3_0: usb30@a6f8800 { - compatible = "qcom,dwc3"; - reg = <0xa6f8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>; - clock-names = "core", "mock_utmi", "sleep"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <133000000>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - reset-names = "core_reset"; - power-domains = <&gcc USB30_PRIM_GDSC>; - qcom,select-utmi-as-pipe-clk; - - dwc3@10000000 { - compatible = "snps,dwc3"; - reg = <0x10000000 0xcd00>; - interrupts = <0 205 0x4>; - phys = <&hs_phy>, <&ss_phy>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - }; - }; - diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file mode 100644 index 000000000000..0f69475566c7 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SuperSpeed DWC3 USB SoC controller + +maintainers: + - Manu Gautam + +properties: + compatible: + items: + - enum: + - qcom,msm8996-dwc3 + - qcom,msm8998-dwc3 + - qcom,sdm845-dwc3 + - const: qcom,dwc3 + + reg: + description: Offset and length of register set for QSCRATCH wrapper + maxItems: 1 + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + power-domains: + description: specifies a phandle to PM domain provider node + maxItems: 1 + + clocks: + description: + A list of phandle and clock-specifier pairs for the clocks + listed in clock-names. + items: + - description: System Config NOC clock. + - description: Master/Core clock, has to be >= 125 MHz + for SS operation and >= 60MHz for HS operation. + - description: System bus AXI clock. + - description: Mock utmi clock needed for ITP/SOF generation + in host mode. Its frequency should be 19.2MHz. + - description: Sleep clock, used for wakeup when + USB3 core goes into low power mode (U3). + + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: mock_utmi + - const: sleep + + assigned-clocks: + items: + - description: Phandle and clock specifier of MOCK_UTMI_CLK. + - description: Phandle and clock specifoer of MASTER_CLK. + + assigned-clock-rates: + maxItems: 2 + items: + - description: Must be 19.2MHz (19200000). + - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode. + + resets: + maxItems: 1 + + interrupts: + items: + - description: The interrupt that is asserted + when a wakeup event is received on USB2 bus. + - description: The interrupt that is asserted + when a wakeup event is received on USB3 bus. + - description: Wakeup event on DM line. + - description: Wakeup event on DP line. + + interrupt-names: + items: + - const: hs_phy_irq + - const: ss_phy_irq + - const: dm_hs_phy_irq + - const: dp_hs_phy_irq + + qcom,select-utmi-as-pipe-clk: + description: + If present, disable USB3 pipe_clk requirement. + Used when dwc3 operates without SSPHY and only + HS/FS/LS modes are supported. + type: boolean + +# Required child node: + +patternProperties: + "^dwc3@[0-9a-f]+$": + type: object + description: + A child node must exist to represent the core DWC3 IP block + The content of the node is defined in dwc3.txt. + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - power-domains + - clocks + - clock-names + +examples: + - | + #include + #include + #include + usb@a6f8800 { + compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x740 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; -- cgit v1.2.3 From b88035625ec9594d4554a307e820aef4b759e35f Mon Sep 17 00:00:00 2001 From: Sandeep Maheswaram Date: Thu, 26 Mar 2020 12:36:08 +0530 Subject: dt-bindings: usb: qcom,dwc3: Add compatible for SC7180 Add compatible for SC7180 in usb dwc3 bindings. Signed-off-by: Sandeep Maheswaram Reviewed-by: Douglas Anderson Acked-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index 0f69475566c7..17e22ff528dd 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -16,6 +16,7 @@ properties: - enum: - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 + - qcom,sc7180-dwc3 - qcom,sdm845-dwc3 - const: qcom,dwc3 -- cgit v1.2.3 From 8f385b67555415cb01079a8ad3b1e16010c5005b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 26 Mar 2020 14:44:53 +0100 Subject: dt-bindings: usb: amlogic,meson-g12a-usb-ctrl: add the Amlogic GXL and GXM Families USB Glue Bindings The Amlogic GXL and GXM is slightly different from the Amlogic G12A Glue. The GXL SoCs only embeds 2 USB2 PHYs and no USB3 PHYs, and the GXM SoCs embeds 3 USB2 PHYs. Reviewed-by: Martin Blumenstingl Signed-off-by: Neil Armstrong Signed-off-by: Felipe Balbi --- .../bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml | 73 ++++++++++++++++++++-- 1 file changed, 69 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml index b0e5e0fe9386..b0af50a7c124 100644 --- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml +++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml @@ -25,9 +25,13 @@ description: | The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in host-only mode. + The Amlogic GXL & GXM SoCs doesn't embed an USB3 PHY. + properties: compatible: enum: + - amlogic,meson-gxl-usb-ctrl + - amlogic,meson-gxm-usb-ctrl - amlogic,meson-g12a-usb-ctrl - amlogic,meson-a1-usb-ctrl @@ -41,6 +45,11 @@ properties: clocks: minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 resets: minItems: 1 @@ -52,10 +61,8 @@ properties: maxItems: 1 phy-names: - items: - - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used - - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used - - const: usb3-phy0 # USB3 PHY if USB3_0 is used + minItems: 1 + maxItems: 3 phys: minItems: 1 @@ -89,6 +96,61 @@ required: - dr_mode allOf: + - if: + properties: + compatible: + enum: + - amlogic,meson-g12a-usb-ctrl + + then: + properties: + phy-names: + items: + - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used + - const: usb3-phy0 # USB3 PHY if USB3_0 is used + - if: + properties: + compatible: + enum: + - amlogic,meson-gxl-usb-ctrl + + then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: usb_ctrl + - const: ddr + phy-names: + items: + - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used + required: + - clock-names + - if: + properties: + compatible: + enum: + - amlogic,meson-gxm-usb-ctrl + + then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: usb_ctrl + - const: ddr + phy-names: + items: + - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used + - const: usb2-phy2 # USB2 PHY2 if USBOTG_C port is used + + required: + - clock-names - if: properties: compatible: @@ -97,6 +159,9 @@ allOf: then: properties: + phy-names: + items: + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used clocks: minItems: 3 clock-names: -- cgit v1.2.3 From 5f3173370ecfa984942c12378d8f5af2bda77b7c Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 7 May 2020 22:47:32 +0100 Subject: dt-bindings: usb: Add TI tps6598x device tree binding documentation Add device tree binding documentation for the Texas Instruments tps6598x Type-C chip driver. Cc: Rob Herring Cc: Heikki Krogerus Cc: Greg Kroah-Hartman Cc: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20200507214733.1982696-2-bryan.odonoghue@linaro.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/usb/ti,tps6598x.yaml | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/ti,tps6598x.yaml (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml b/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml new file mode 100644 index 000000000000..8eaf4b6c4735 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/ti,tps6598x.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments 6598x Type-C Port Switch and Power Delivery controller DT bindings + +maintainers: + - Bryan O'Donoghue + +description: | + Texas Instruments 6598x Type-C Port Switch and Power Delivery controller + +properties: + compatible: + enum: + - ti,tps6598x + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: irq + +required: + - compatible + - reg + - interrupts + - interrupt-names + +examples: + - | + #include + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + tps6598x: tps6598x@38 { + compatible = "ti,tps6598x"; + reg = <0x38>; + + interrupt-parent = <&msmgpio>; + interrupts = <107 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + + pinctrl-names = "default"; + pinctrl-0 = <&typec_pins>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + port { + typec_ep: endpoint { + remote-endpoint = <&otg_ep>; + }; + }; + }; + }; + }; +... -- cgit v1.2.3 From 4e6cc9d07f28307bc67ce6e1a983c09509d22c9c Mon Sep 17 00:00:00 2001 From: Al Cooper Date: Tue, 12 May 2020 11:00:16 -0400 Subject: dt-bindings: Add Broadcom STB USB support Add DT bindings for Broadcom STB USB EHCI and XHCI drivers. NOTE: The OHCI driver is not included because it uses the generic platform driver. Signed-off-by: Al Cooper Reviewed-by: Rob Herring Reviewed-by: Florian Fainelli Link: https://lore.kernel.org/r/20200512150019.25903-3-alcooperx@gmail.com Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/usb/brcm,bcm7445-ehci.yaml | 59 ++++++++++++++++++++++ Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 + 2 files changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/brcm,bcm7445-ehci.yaml (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/brcm,bcm7445-ehci.yaml b/Documentation/devicetree/bindings/usb/brcm,bcm7445-ehci.yaml new file mode 100644 index 000000000000..2a9acf2b5a64 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/brcm,bcm7445-ehci.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/brcm,bcm7445-ehci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom STB USB EHCI Controller Device Tree Bindings + +allOf: + - $ref: "usb-hcd.yaml" + +maintainers: + - Al Cooper + +properties: + compatible: + const: brcm,bcm7445-ehci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: Clock specifier for the EHCI clock + + clock-names: + const: sw_usb + + phys: + maxItems: 1 + + phy-names: + const: usbphy + +required: + - compatible + - reg + - interrupts + - phys + - clocks + +additionalProperties: false + +examples: + - | + usb@f0b00300 { + compatible = "brcm,bcm7445-ehci"; + reg = <0xf0b00300 0xa8>; + interrupts = <0x0 0x5a 0x0>; + phys = <&usbphy_0 0x0>; + phy-names = "usbphy"; + clocks = <&usb20>; + clock-names = "sw_usb"; + }; + +... diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt index dc025f126d71..23e89d798b1b 100644 --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt @@ -24,6 +24,7 @@ Required properties: device - "renesas,rcar-gen3-xhci" for a generic R-Car Gen3 or RZ/G2 compatible device + - "brcm,bcm7445-xhci" for Broadcom STB SoCs with XHCI - "xhci-platform" (deprecated) When compatible with the generic version, nodes must list the -- cgit v1.2.3 From 55b209c5c4a76d3dd1677e52de80a8b47136970a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 16 Apr 2020 14:19:09 +0200 Subject: doc: dt: bindings: usb: dwc3: remove amlogic compatible entries Acked-by: Rob Herring Signed-off-by: Neil Armstrong Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/dwc3.txt | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 9946ff9ba735..d03edf9d3935 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -15,8 +15,6 @@ Required properties: Exception for clocks: clocks are optional if the parent node (i.e. glue-layer) is compatible to one of the following: - "amlogic,meson-axg-dwc3" - "amlogic,meson-gxl-dwc3" "cavium,octeon-7130-usb-uctl" "qcom,dwc3" "samsung,exynos5250-dwusb3" -- cgit v1.2.3 From 0bcf42d3d0531e9a97c454faff3b07194320b25c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 16 Apr 2020 14:19:10 +0200 Subject: dt-bindings: usb: dwc3: remove old DWC3 wrapper There is now an updated bindings for these SoCs making the old compatible obsolete. Acked-by: Rob Herring Signed-off-by: Martin Blumenstingl Signed-off-by: Neil Armstrong Signed-off-by: Felipe Balbi --- .../devicetree/bindings/usb/amlogic,dwc3.txt | 42 ---------------------- 1 file changed, 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/amlogic,dwc3.txt (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt deleted file mode 100644 index 9a8b631904fd..000000000000 --- a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt +++ /dev/null @@ -1,42 +0,0 @@ -Amlogic Meson GX DWC3 USB SoC controller - -Required properties: -- compatible: depending on the SoC this should contain one of: - * amlogic,meson-axg-dwc3 - * amlogic,meson-gxl-dwc3 -- clocks: a handle for the "USB general" clock -- clock-names: must be "usb_general" -- resets: a handle for the shared "USB OTG" reset line -- reset-names: must be "usb_otg" - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -PHY documentation is provided in the following places: -- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt -- Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt - -Example device nodes: - usb0: usb@ff500000 { - compatible = "amlogic,meson-axg-dwc3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>; - clock-names = "usb_general"; - resets = <&reset RESET_USB_OTG>; - reset-names = "usb_otg"; - - dwc3: dwc3@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = ; - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - phys = <&usb3_phy>, <&usb2_phy0>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; -- cgit v1.2.3 From 394b012a422d4bb00b69dadcf63148acf3b5d459 Mon Sep 17 00:00:00 2001 From: Nagarjuna Kristam Date: Mon, 4 May 2020 12:04:39 +0530 Subject: dt-bindings: usb: tegra-xudc: Add Tegra194 XUSB controller support Extend the Tegra XUSB controller device tree binding with Tegra194 support. Signed-off-by: Nagarjuna Kristam Acked-by: Thierry Reding Acked-by: Rob Herring Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index b84ed8ee8cfc..75ea946d22e9 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -21,6 +21,7 @@ properties: - enum: - nvidia,tegra210-xudc # For Tegra210 - nvidia,tegra186-xudc # For Tegra186 + - nvidia,tegra194-xudc # For Tegra194 reg: minItems: 2 @@ -144,6 +145,7 @@ allOf: contains: enum: - nvidia,tegra186-xudc + - nvidia,tegra194-xudc then: properties: reg: -- cgit v1.2.3 From 4db120d93d53f668770f07a41567a404b88891fb Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 7 May 2020 17:56:50 +0200 Subject: dt-bindings: usb: atmel: Mark EP child node as deprecated There is no need to describe the end point in the deice tree. These properties won't be use anymore, so mark them as deprecated to keep the old device tree documented. Reviewed-by: Rob Herring Signed-off-by: Gregory CLEMENT Signed-off-by: Felipe Balbi --- .../devicetree/bindings/usb/atmel-usb.txt | 56 ++-------------------- 1 file changed, 3 insertions(+), 53 deletions(-) (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index 44e80153b148..423b99a8fd97 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt @@ -88,13 +88,15 @@ Required properties: - clock-names: Should contain two strings "pclk" for the peripheral clock "hclk" for the host clock + +Deprecated property: - ep childnode: To specify the number of endpoints and their properties. Optional properties: - atmel,vbus-gpio: If present, specifies a gpio that allows to detect whether vbus is present (USB is connected). -Required child node properties: +Deprecated child node properties: - name: Name of the endpoint. - reg: Num of the endpoint. - atmel,fifo-size: Size of the fifo. @@ -112,56 +114,4 @@ usb2: gadget@fff78000 { clocks = <&utmi>, <&udphs_clk>; clock-names = "hclk", "pclk"; atmel,vbus-gpio = <&pioB 19 0>; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; }; -- cgit v1.2.3 From 1805cdde37c8cc90b298c3d9afbc2aa4c9890635 Mon Sep 17 00:00:00 2001 From: Sandeep Maheswaram Date: Wed, 1 Apr 2020 10:45:42 +0530 Subject: dt-bindings: usb: qcom,dwc3: Introduce interconnect properties for Qualcomm DWC3 driver Add documentation for the interconnects and interconnect-names properties for USB. Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Sandeep Maheswaram Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index 17e22ff528dd..ec1ec47b51cb 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -70,6 +70,14 @@ properties: resets: maxItems: 1 + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: usb-ddr + - const: apps-usb + interrupts: items: - description: The interrupt that is asserted -- cgit v1.2.3 From 1883a934e15638efc39cf444908c928bef51b2a0 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Wed, 13 May 2020 16:07:07 +0300 Subject: dt-bindings: usb: convert keystone-usb.txt to YAML Convert keystone-usb documentation to YAML format. Signed-off-by: Roger Quadros Signed-off-by: Felipe Balbi --- .../devicetree/bindings/usb/keystone-usb.txt | 56 ------------------ .../devicetree/bindings/usb/ti,keystone-dwc3.yaml | 67 ++++++++++++++++++++++ 2 files changed, 67 insertions(+), 56 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/keystone-usb.txt create mode 100644 Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/keystone-usb.txt b/Documentation/devicetree/bindings/usb/keystone-usb.txt deleted file mode 100644 index 77df82e36138..000000000000 --- a/Documentation/devicetree/bindings/usb/keystone-usb.txt +++ /dev/null @@ -1,56 +0,0 @@ -TI Keystone Soc USB Controller - -DWC3 GLUE - -Required properties: - - compatible: should be - "ti,keystone-dwc3" for Keystone 2 SoCs - "ti,am654-dwc3" for AM654 SoC - - #address-cells, #size-cells : should be '1' if the device has sub-nodes - with 'reg' property. - - reg : Address and length of the register set for the USB subsystem on - the SOC. - - interrupts : The irq number of this device that is used to interrupt the - MPU. - - ranges: allows valid 1:1 translation between child's address space and - parent's address space. - -SoC-specific Required Properties: -The following are mandatory properties for Keystone 2 66AK2HK, 66AK2L and 66AK2E -SoCs only: - -- clocks: Clock ID for USB functional clock. -- clock-names: Must be "usb". - - -The following are mandatory properties for 66AK2G and AM654: - -- power-domains: Should contain a phandle to a PM domain provider node - and an args specifier containing the USB device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt - -Sub-nodes: -The dwc3 core should be added as subnode to Keystone DWC3 glue. -- dwc3 : - The binding details of dwc3 can be found in: - Documentation/devicetree/bindings/usb/dwc3.txt - -Example: - usb: usb@2680000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2680000 0x10000>; - clocks = <&clkusb>; - clock-names = "usb"; - interrupts = ; - ranges; - - dwc3@2690000 { - compatible = "synopsys,dwc3"; - reg = <0x2690000 0x70000>; - interrupts = ; - usb-phy = <&usb_phy>, <&usb_phy>; - }; - }; diff --git a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml new file mode 100644 index 000000000000..14d2fe329b93 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Keystone Soc USB Controller + +maintainers: + - Roger Quadros + +properties: + compatible: + oneOf: + - const: "ti,keystone-dwc3" + - const: "ti,am654-dwc3" + + reg: + maxItems: 1 + description: Address and length of the register set for the USB subsystem on + the SOC. + + interrupts: + maxItems: 1 + description: The irq number of this device that is used to interrupt the MPU. + + + clocks: + description: Clock ID for USB functional clock. + + power-domains: + description: Should contain a phandle to a PM domain provider node + and an args specifier containing the USB device id + value. This property is as per the binding, + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + + dwc3: + description: This is the node representing the DWC3 controller instance + Documentation/devicetree/bindings/usb/dwc3.txt + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + #include + + usb: usb@2680000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2680000 0x10000>; + clocks = <&clkusb>; + clock-names = "usb"; + interrupts = ; + ranges; + + dwc3@2690000 { + compatible = "synopsys,dwc3"; + reg = <0x2690000 0x70000>; + interrupts = ; + usb-phy = <&usb_phy>, <&usb_phy>; + }; + }; -- cgit v1.2.3 From 15aeb360e4a0d144cb64e2adb6f71b444bafc238 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 25 May 2020 10:10:47 +0300 Subject: dt-bindings: usb: ti,keystone-dwc3.yaml: Add USB3.0 PHY property AM654 SoC requires USB3.0 PHY to be turned on before the USB controller. For this SoC, the 'phys' property is used to provide the USB3.0 reference. Signed-off-by: Roger Quadros Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml index 14d2fe329b93..f127535feb0b 100644 --- a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml @@ -34,6 +34,16 @@ properties: value. This property is as per the binding, Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + phys: + description: + PHY specifier for the USB3.0 PHY. Some SoCs need the USB3.0 PHY + to be turned on before the controller. + Documentation/devicetree/bindings/phy/phy-bindings.txt + + phy-names: + items: + - const: "usb3-phy" + dwc3: description: This is the node representing the DWC3 controller instance Documentation/devicetree/bindings/usb/dwc3.txt -- cgit v1.2.3 From c4ff8628476937635b91500dc78a14e337facb7c Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 29 May 2020 10:26:49 +0200 Subject: Revert "dt-bindings: usb: qcom,dwc3: Introduce interconnect properties for Qualcomm DWC3 driver" This reverts commit 1805cdde37c8cc90b298c3d9afbc2aa4c9890635 as it should be going in through Rob's tree instead to resolve conflicts. Reported-by: Stephen Rothwell Cc: Rob Herring Cc: Stephen Boyd Cc: Sandeep Maheswaram Cc: Felipe Balbi Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 8 -------- 1 file changed, 8 deletions(-) (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index ec1ec47b51cb..17e22ff528dd 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -70,14 +70,6 @@ properties: resets: maxItems: 1 - interconnects: - maxItems: 2 - - interconnect-names: - items: - - const: usb-ddr - - const: apps-usb - interrupts: items: - description: The interrupt that is asserted -- cgit v1.2.3 From 99d33ea7f8b0f0641abb1e4aa30ab66c407987e4 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 29 May 2020 10:28:48 +0200 Subject: Revert "dt-bindings: usb: qcom,dwc3: Add compatible for SC7180" This reverts commit b88035625ec9594d4554a307e820aef4b759e35f as the file should be coming in through Rob's tree instead. Reported-by: Stephen Rothwell Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Rob Herring Cc: Stephen Boyd Cc: Felipe Balbi Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index 17e22ff528dd..0f69475566c7 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -16,7 +16,6 @@ properties: - enum: - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 - - qcom,sc7180-dwc3 - qcom,sdm845-dwc3 - const: qcom,dwc3 -- cgit v1.2.3 From 906d0c8b89de833d98071b082252db7013fca659 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 29 May 2020 10:29:40 +0200 Subject: Revert "dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings" This reverts commit cd4b54e2ae1f47c72c004628788e84ffe7c71561 as the change should be coming in through Rob's tree instead. Reported-by: Stephen Rothwell Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Rob Herring Cc: Stephen Boyd Cc: Felipe Balbi Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/usb/qcom,dwc3.txt | 104 ++++++++++++++ .../devicetree/bindings/usb/qcom,dwc3.yaml | 158 --------------------- 2 files changed, 104 insertions(+), 158 deletions(-) create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt delete mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.yaml (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt new file mode 100644 index 000000000000..fbdd01756752 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt @@ -0,0 +1,104 @@ +Qualcomm SuperSpeed DWC3 USB SoC controller + +Required properties: +- compatible: Compatible list, contains + "qcom,dwc3" + "qcom,msm8996-dwc3" for msm8996 SOC. + "qcom,msm8998-dwc3" for msm8998 SOC. + "qcom,sdm845-dwc3" for sdm845 SOC. +- reg: Offset and length of register set for QSCRATCH wrapper +- power-domains: specifies a phandle to PM domain provider node +- clocks: A list of phandle + clock-specifier pairs for the + clocks listed in clock-names +- clock-names: Should contain the following: + "core" Master/Core clock, have to be >= 125 MHz for SS + operation and >= 60MHz for HS operation + "mock_utmi" Mock utmi clock needed for ITP/SOF generation in + host mode. Its frequency should be 19.2MHz. + "sleep" Sleep clock, used for wakeup when USB3 core goes + into low power mode (U3). + +Optional clocks: + "iface" System bus AXI clock. + Not present on "qcom,msm8996-dwc3" compatible. + "cfg_noc" System Config NOC clock. + Not present on "qcom,msm8996-dwc3" compatible. +- assigned-clocks: Should be: + MOCK_UTMI_CLK + MASTER_CLK +- assigned-clock-rates: Should be: + 19.2Mhz (192000000) for MOCK_UTMI_CLK + >=125Mhz (125000000) for MASTER_CLK in SS mode + >=60Mhz (60000000) for MASTER_CLK in HS mode + +Optional properties: +- resets: Phandle to reset control that resets core and wrapper. +- interrupts: specifies interrupts from controller wrapper used + to wakeup from low power/susepnd state. Must contain + one or more entry for interrupt-names property +- interrupt-names: Must include the following entries: + - "hs_phy_irq": The interrupt that is asserted when a + wakeup event is received on USB2 bus + - "ss_phy_irq": The interrupt that is asserted when a + wakeup event is received on USB3 bus + - "dm_hs_phy_irq" and "dp_hs_phy_irq": Separate + interrupts for any wakeup event on DM and DP lines +- qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement. + Used when dwc3 operates without SSPHY and only + HS/FS/LS modes are supported. + +Required child node: +A child node must exist to represent the core DWC3 IP block. The name of +the node is not important. The content of the node is defined in dwc3.txt. + +Phy documentation is provided in the following places: +Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY +Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml - USB2 QUSB2 PHY + +Example device nodes: + + hs_phy: phy@100f8800 { + compatible = "qcom,qusb2-v2-phy"; + ... + }; + + ss_phy: phy@100f8830 { + compatible = "qcom,qmp-v3-usb3-phy"; + ... + }; + + usb3_0: usb30@a6f8800 { + compatible = "qcom,dwc3"; + reg = <0xa6f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core", "mock_utmi", "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133000000>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + power-domains = <&gcc USB30_PRIM_GDSC>; + qcom,select-utmi-as-pipe-clk; + + dwc3@10000000 { + compatible = "snps,dwc3"; + reg = <0x10000000 0xcd00>; + interrupts = <0 205 0x4>; + phys = <&hs_phy>, <&ss_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + }; + }; + diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml deleted file mode 100644 index 0f69475566c7..000000000000 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ /dev/null @@ -1,158 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SuperSpeed DWC3 USB SoC controller - -maintainers: - - Manu Gautam - -properties: - compatible: - items: - - enum: - - qcom,msm8996-dwc3 - - qcom,msm8998-dwc3 - - qcom,sdm845-dwc3 - - const: qcom,dwc3 - - reg: - description: Offset and length of register set for QSCRATCH wrapper - maxItems: 1 - - "#address-cells": - enum: [ 1, 2 ] - - "#size-cells": - enum: [ 1, 2 ] - - power-domains: - description: specifies a phandle to PM domain provider node - maxItems: 1 - - clocks: - description: - A list of phandle and clock-specifier pairs for the clocks - listed in clock-names. - items: - - description: System Config NOC clock. - - description: Master/Core clock, has to be >= 125 MHz - for SS operation and >= 60MHz for HS operation. - - description: System bus AXI clock. - - description: Mock utmi clock needed for ITP/SOF generation - in host mode. Its frequency should be 19.2MHz. - - description: Sleep clock, used for wakeup when - USB3 core goes into low power mode (U3). - - clock-names: - items: - - const: cfg_noc - - const: core - - const: iface - - const: mock_utmi - - const: sleep - - assigned-clocks: - items: - - description: Phandle and clock specifier of MOCK_UTMI_CLK. - - description: Phandle and clock specifoer of MASTER_CLK. - - assigned-clock-rates: - maxItems: 2 - items: - - description: Must be 19.2MHz (19200000). - - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode. - - resets: - maxItems: 1 - - interrupts: - items: - - description: The interrupt that is asserted - when a wakeup event is received on USB2 bus. - - description: The interrupt that is asserted - when a wakeup event is received on USB3 bus. - - description: Wakeup event on DM line. - - description: Wakeup event on DP line. - - interrupt-names: - items: - - const: hs_phy_irq - - const: ss_phy_irq - - const: dm_hs_phy_irq - - const: dp_hs_phy_irq - - qcom,select-utmi-as-pipe-clk: - description: - If present, disable USB3 pipe_clk requirement. - Used when dwc3 operates without SSPHY and only - HS/FS/LS modes are supported. - type: boolean - -# Required child node: - -patternProperties: - "^dwc3@[0-9a-f]+$": - type: object - description: - A child node must exist to represent the core DWC3 IP block - The content of the node is defined in dwc3.txt. - -required: - - compatible - - reg - - "#address-cells" - - "#size-cells" - - power-domains - - clocks - - clock-names - -examples: - - | - #include - #include - #include - usb@a6f8800 { - compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - - #address-cells = <2>; - #size-cells = <2>; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <150000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x740 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; -- cgit v1.2.3