From 7ec13d42f6d7e37fabe09dfd0d257a87f6bf2ee9 Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Tue, 23 Apr 2013 10:33:44 +1200 Subject: dts: vt8500: Fix invalid/missing cpu nodes for soc files. vt8500, wm8650 and wm8850 have no cpu node specified. wm8505 has a cpu node which contains an invalid compatible string, and is missing the other required properties. Signed-off-by: Tony Prisk --- arch/arm/boot/dts/vt8500.dtsi | 10 ++++++++++ arch/arm/boot/dts/wm8505.dtsi | 8 ++++++-- arch/arm/boot/dts/wm8650.dtsi | 10 ++++++++++ arch/arm/boot/dts/wm8850.dtsi | 11 +++++++++++ 4 files changed, 37 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi index 4a4b96f6827e..a0b490d51519 100644 --- a/arch/arm/boot/dts/vt8500.dtsi +++ b/arch/arm/boot/dts/vt8500.dtsi @@ -11,6 +11,16 @@ / { compatible = "via,vt8500"; + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index b2bf359e852f..35d9ead79513 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -12,8 +12,12 @@ compatible = "wm,wm8505"; cpus { - cpu@0 { - compatible = "arm,arm926ejs"; + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; }; }; diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi index dd8464eeb40d..7dce5c18615c 100644 --- a/arch/arm/boot/dts/wm8650.dtsi +++ b/arch/arm/boot/dts/wm8650.dtsi @@ -11,6 +11,16 @@ / { compatible = "wm,wm8650"; + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi index fc790d0aee66..3aa131538935 100644 --- a/arch/arm/boot/dts/wm8850.dtsi +++ b/arch/arm/boot/dts/wm8850.dtsi @@ -11,6 +11,17 @@ / { compatible = "wm,wm8850"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x0>; + }; + }; + aliases { serial0 = &uart0; serial1 = &uart1; -- cgit v1.2.3 From 4606c48051db62db14756e1085fe0f8821a0e116 Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Tue, 23 Apr 2013 10:55:57 +1200 Subject: dts: vt8500: Add devicetree support for WM8750 SoC and APC8750 board This patch adds support for the WonderMedia WM8750 SoC and the VIA APC8750 board. Signed-off-by: Tony Prisk --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/wm8750-apc8750.dts | 26 +++ arch/arm/boot/dts/wm8750.dtsi | 334 +++++++++++++++++++++++++++++++++++ 3 files changed, 361 insertions(+) create mode 100644 arch/arm/boot/dts/wm8750-apc8750.dts create mode 100644 arch/arm/boot/dts/wm8750.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b9f7121e6ecf..ecdd51dc9c0f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -205,6 +205,7 @@ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ wm8505-ref.dtb \ wm8650-mid.dtb \ + wm8750-apc8750.dtb \ wm8850-w70v2.dtb dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/wm8750-apc8750.dts new file mode 100644 index 000000000000..62675eba9666 --- /dev/null +++ b/arch/arm/boot/dts/wm8750-apc8750.dts @@ -0,0 +1,26 @@ +/* + * wm8750-apc8750.dts + * - Device tree file for VIA APC8750 + * + * Copyright (C) 2012 Tony Prisk + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +/include/ "wm8750.dtsi" + +/ { + model = "VIA APC8750"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&i2c>; + + i2c: i2c { + wm,pins = <168 169 170 171>; + wm,function = <2>; /* alt */ + wm,pull = <2>; /* pull-up */ + }; +}; diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi new file mode 100644 index 000000000000..462de589a2fe --- /dev/null +++ b/arch/arm/boot/dts/wm8750.dtsi @@ -0,0 +1,334 @@ +/* + * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC + * + * Copyright (C) 2012 Tony Prisk + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "wm,wm8750"; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm1176ej-s"; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc0>; + + intc0: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + /* Secondary IC cascaded to intc0 */ + intc1: interrupt-controller@d8150000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xD8150000 0x10000>; + interrupts = <56 57 58 59 60 61 62 63>; + }; + + pinctrl: pinctrl@d8110000 { + compatible = "wm,wm8750-pinctrl"; + reg = <0xd8110000 0x10000>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + ref25: ref25M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + plla: plla { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x200>; + }; + + pllb: pllb { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x204>; + }; + + pllc: pllc { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x20C>; + }; + + plle: plle { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x210>; + }; + + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + + clkuart0: uart0 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <24>; + }; + + clkuart1: uart1 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <25>; + }; + + clkuart2: uart2 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <26>; + }; + + clkuart3: uart3 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <27>; + }; + + clkuart4: uart4 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <28>; + }; + + clkuart5: uart5 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <29>; + }; + + clkpwm: pwm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x350>; + enable-reg = <0x250>; + enable-bit = <17>; + }; + + clksdhc: sdhc { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x330>; + divisor-mask = <0x3f>; + enable-reg = <0x250>; + enable-bit = <0>; + }; + + clki2c0: i2c0clk { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x3A0>; + enable-reg = <0x250>; + enable-bit = <8>; + }; + + clki2c1: i2c1clk { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x3A4>; + enable-reg = <0x250>; + enable-bit = <9>; + }; + }; + }; + + pwm: pwm@d8220000 { + #pwm-cells = <3>; + compatible = "via,vt8500-pwm"; + reg = <0xd8220000 0x100>; + clocks = <&clkpwm>; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007900 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007900 0x200>; + interrupts = <26>; + }; + + uhci@d8007b00 { + compatible = "platform-uhci"; + reg = <0xd8007b00 0x200>; + interrupts = <26>; + }; + + uhci@d8008d00 { + compatible = "platform-uhci"; + reg = <0xd8008d00 0x200>; + interrupts = <26>; + }; + + uart0: uart@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&clkuart0>; + }; + + uart1: uart@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&clkuart1>; + }; + + uart2: uart@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&clkuart2>; + }; + + uart3: uart@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&clkuart3>; + }; + + uart4: uart@d8370000 { + compatible = "via,vt8500-uart"; + reg = <0xd8370000 0x1040>; + interrupts = <30>; + clocks = <&clkuart4>; + }; + + uart5: uart@d8380000 { + compatible = "via,vt8500-uart"; + reg = <0xd8380000 0x1040>; + interrupts = <43>; + clocks = <&clkuart5>; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + + sdhc@d800a000 { + compatible = "wm,wm8505-sdhc"; + reg = <0xd800a000 0x1000>; + interrupts = <20 21>; + clocks = <&clksdhc>; + bus-width = <4>; + sdon-inverted; + }; + + i2c_0: i2c@d8280000 { + compatible = "wm,wm8505-i2c"; + reg = <0xd8280000 0x1000>; + interrupts = <19>; + clocks = <&clki2c0>; + clock-frequency = <400000>; + }; + + i2c_1: i2c@d8320000 { + compatible = "wm,wm8505-i2c"; + reg = <0xd8320000 0x1000>; + interrupts = <18>; + clocks = <&clki2c1>; + clock-frequency = <400000>; + }; + }; +}; -- cgit v1.2.3 From 55954f8522cf108e8c894130b2656516b9ae6991 Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Tue, 23 Apr 2013 14:23:26 +1200 Subject: dts: vt8500: Update serial nodes and disable by default in SoC files Missing aliases for uarts on vt8500, wm8505, wm8650 added. Nodes incorrectly labelled uart@.., changed to serial@... on all SoCs. Set each uarts default status = "disabled" as they generally don't exist. For each board file, we only need to enable uart0 as no other uarts are physically present on any of these boards. Signed-off-by: Tony Prisk --- arch/arm/boot/dts/vt8500-bv07.dts | 4 ++++ arch/arm/boot/dts/vt8500.dtsi | 19 +++++++++++++++---- arch/arm/boot/dts/wm8505-ref.dts | 4 ++++ arch/arm/boot/dts/wm8505.dtsi | 27 +++++++++++++++++++++------ arch/arm/boot/dts/wm8650-mid.dts | 3 +++ arch/arm/boot/dts/wm8650.dtsi | 11 +++++++++-- arch/arm/boot/dts/wm8750-apc8750.dts | 4 ++++ arch/arm/boot/dts/wm8750.dtsi | 18 ++++++++++++------ arch/arm/boot/dts/wm8850-w70v2.dts | 4 ++++ arch/arm/boot/dts/wm8850.dtsi | 12 ++++++++---- 10 files changed, 84 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts index 877b33afa7ed..87f33310e2bc 100644 --- a/arch/arm/boot/dts/vt8500-bv07.dts +++ b/arch/arm/boot/dts/vt8500-bv07.dts @@ -30,3 +30,7 @@ }; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi index a0b490d51519..51d0e912c8f5 100644 --- a/arch/arm/boot/dts/vt8500.dtsi +++ b/arch/arm/boot/dts/vt8500.dtsi @@ -21,6 +21,13 @@ }; }; + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -121,32 +128,36 @@ reg = <0xd8050400 0x100>; }; - uart@d8200000 { + uart0: serial@d8200000 { compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; clocks = <&clkuart0>; + status = "disabled"; }; - uart@d82b0000 { + uart1: serial@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; clocks = <&clkuart1>; + status = "disabled"; }; - uart@d8210000 { + uart2: serial@d8210000 { compatible = "via,vt8500-uart"; reg = <0xd8210000 0x1040>; interrupts = <47>; clocks = <&clkuart2>; + status = "disabled"; }; - uart@d82c0000 { + uart3: serial@d82c0000 { compatible = "via,vt8500-uart"; reg = <0xd82c0000 0x1040>; interrupts = <50>; clocks = <&clkuart3>; + status = "disabled"; }; rtc@d8100000 { diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts index edd2cec3d37f..e3e6b9eb09d0 100644 --- a/arch/arm/boot/dts/wm8505-ref.dts +++ b/arch/arm/boot/dts/wm8505-ref.dts @@ -30,3 +30,7 @@ }; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index 35d9ead79513..060b5fca2c16 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -21,6 +21,15 @@ }; }; + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -167,46 +176,52 @@ reg = <0xd8050400 0x100>; }; - uart@d8200000 { + uart0: serial@d8200000 { compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; clocks = <&clkuart0>; + status = "disabled"; }; - uart@d82b0000 { + uart1: serial@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; clocks = <&clkuart1>; + status = "disabled"; }; - uart@d8210000 { + uart2: serial@d8210000 { compatible = "via,vt8500-uart"; reg = <0xd8210000 0x1040>; interrupts = <47>; clocks = <&clkuart2>; + status = "disabled"; }; - uart@d82c0000 { + uart3: serial@d82c0000 { compatible = "via,vt8500-uart"; reg = <0xd82c0000 0x1040>; interrupts = <50>; clocks = <&clkuart3>; + status = "disabled"; }; - uart@d8370000 { + uart4: serial@d8370000 { compatible = "via,vt8500-uart"; reg = <0xd8370000 0x1040>; interrupts = <31>; clocks = <&clkuart4>; + status = "disabled"; }; - uart@d8380000 { + uart5: serial@d8380000 { compatible = "via,vt8500-uart"; reg = <0xd8380000 0x1040>; interrupts = <30>; clocks = <&clkuart5>; + status = "disabled"; }; rtc@d8100000 { diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts index 61671a0d9ede..dd0d1b602388 100644 --- a/arch/arm/boot/dts/wm8650-mid.dts +++ b/arch/arm/boot/dts/wm8650-mid.dts @@ -32,3 +32,6 @@ }; }; +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi index 7dce5c18615c..4fdae5ce4dfb 100644 --- a/arch/arm/boot/dts/wm8650.dtsi +++ b/arch/arm/boot/dts/wm8650.dtsi @@ -21,6 +21,11 @@ }; }; + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -150,18 +155,20 @@ reg = <0xd8050400 0x100>; }; - uart@d8200000 { + uart0: serial@d8200000 { compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; clocks = <&clkuart0>; + status = "disabled"; }; - uart@d82b0000 { + uart1: serial@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; clocks = <&clkuart1>; + status = "disabled"; }; rtc@d8100000 { diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/wm8750-apc8750.dts index 62675eba9666..37e4a408bf39 100644 --- a/arch/arm/boot/dts/wm8750-apc8750.dts +++ b/arch/arm/boot/dts/wm8750-apc8750.dts @@ -24,3 +24,7 @@ wm,pull = <2>; /* pull-up */ }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi index 462de589a2fe..e4a1e8553e30 100644 --- a/arch/arm/boot/dts/wm8750.dtsi +++ b/arch/arm/boot/dts/wm8750.dtsi @@ -258,46 +258,52 @@ interrupts = <26>; }; - uart0: uart@d8200000 { + uart0: serial@d8200000 { compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; clocks = <&clkuart0>; + status = "disabled"; }; - uart1: uart@d82b0000 { + uart1: serial@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; clocks = <&clkuart1>; + status = "disabled"; }; - uart2: uart@d8210000 { + uart2: serial@d8210000 { compatible = "via,vt8500-uart"; reg = <0xd8210000 0x1040>; interrupts = <47>; clocks = <&clkuart2>; + status = "disabled"; }; - uart3: uart@d82c0000 { + uart3: serial@d82c0000 { compatible = "via,vt8500-uart"; reg = <0xd82c0000 0x1040>; interrupts = <50>; clocks = <&clkuart3>; + status = "disabled"; }; - uart4: uart@d8370000 { + uart4: serial@d8370000 { compatible = "via,vt8500-uart"; reg = <0xd8370000 0x1040>; interrupts = <30>; clocks = <&clkuart4>; + status = "disabled"; }; - uart5: uart@d8380000 { + uart5: serial@d8380000 { compatible = "via,vt8500-uart"; reg = <0xd8380000 0x1040>; interrupts = <43>; clocks = <&clkuart5>; + status = "disabled"; }; rtc@d8100000 { diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts index 32d22532cd6c..90e913fb64be 100644 --- a/arch/arm/boot/dts/wm8850-w70v2.dts +++ b/arch/arm/boot/dts/wm8850-w70v2.dts @@ -41,3 +41,7 @@ }; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi index 3aa131538935..fc60e3204589 100644 --- a/arch/arm/boot/dts/wm8850.dtsi +++ b/arch/arm/boot/dts/wm8850.dtsi @@ -189,32 +189,36 @@ interrupts = <26>; }; - uart0: uart@d8200000 { + uart0: serial@d8200000 { compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; clocks = <&clkuart0>; + status = "disabled"; }; - uart1: uart@d82b0000 { + uart1: serial@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; clocks = <&clkuart1>; + status = "disabled"; }; - uart2: uart@d8210000 { + uart2: serial@d8210000 { compatible = "via,vt8500-uart"; reg = <0xd8210000 0x1040>; interrupts = <47>; clocks = <&clkuart2>; + status = "disabled"; }; - uart3: uart@d82c0000 { + uart3: serial@d82c0000 { compatible = "via,vt8500-uart"; reg = <0xd82c0000 0x1040>; interrupts = <50>; clocks = <&clkuart3>; + status = "disabled"; }; rtc@d8100000 { -- cgit v1.2.3 From 7d4c6f3c5fdb216dfd36573d117eff602146cdcd Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Thu, 9 May 2013 07:35:13 +1200 Subject: dts: clk: vt8500: Update SoC dtsi to use WM8850 PLL clocks Change the WM8850 SoC dtsi to use the new wm8850 specific PLL clock binding. Previously, the WM8850 used the wm8750 pll clock which is actually different to the wm8850 pll clock. Signed-off-by: Tony Prisk --- arch/arm/boot/dts/wm8850.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi index fc60e3204589..9239c0a3aeb7 100644 --- a/arch/arm/boot/dts/wm8850.dtsi +++ b/arch/arm/boot/dts/wm8850.dtsi @@ -83,14 +83,14 @@ plla: plla { #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; + compatible = "wm,wm8850-pll-clock"; clocks = <&ref25>; reg = <0x200>; }; pllb: pllb { #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; + compatible = "wm,wm8850-pll-clock"; clocks = <&ref25>; reg = <0x204>; }; -- cgit v1.2.3 From 5c2b0a8531f594db82abc29e786b4c2d38fa298b Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Fri, 10 May 2013 17:35:11 +1200 Subject: dts: vt8500: Populate missing PLL nodes Add the missing devicetree nodes for PLL's found on the WM8505, WM8650 and WM8850 SoCs. Signed-off-by: Tony Prisk --- arch/arm/boot/dts/wm8505.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/wm8650.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/wm8850.dtsi | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+) diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index 060b5fca2c16..702d866b6f57 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -81,6 +81,13 @@ clock-frequency = <25000000>; }; + plla: plla { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x200>; + }; + pllb: pllb { #clock-cells = <0>; compatible = "via,vt8500-pll-clock"; @@ -88,6 +95,20 @@ reg = <0x204>; }; + pllc: pllc { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "via,vt8500-pll-clock"; + clocks = <&ref25>; + reg = <0x20c>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi index 4fdae5ce4dfb..46a4603c9c53 100644 --- a/arch/arm/boot/dts/wm8650.dtsi +++ b/arch/arm/boot/dts/wm8650.dtsi @@ -92,6 +92,27 @@ reg = <0x204>; }; + pllc: pllc { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x20c>; + }; + + plle: plle { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x210>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi index 9239c0a3aeb7..59aaad98f544 100644 --- a/arch/arm/boot/dts/wm8850.dtsi +++ b/arch/arm/boot/dts/wm8850.dtsi @@ -95,6 +95,41 @@ reg = <0x204>; }; + pllc: pllc { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref25>; + reg = <0x208>; + }; + + plld: plld { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref25>; + reg = <0x20c>; + }; + + plle: plle { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref25>; + reg = <0x210>; + }; + + pllf: pllf { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref25>; + reg = <0x214>; + }; + + pllg: pllg { + #clock-cells = <0>; + compatible = "wm,wm8850-pll-clock"; + clocks = <&ref25>; + reg = <0x218>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; -- cgit v1.2.3 From 9e7b6d3eda8551912b0cf9507ca5f489a476d522 Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Fri, 10 May 2013 17:44:58 +1200 Subject: dts: vt8500: Add ARM, AHB, APB and DDR clock nodes to SoC files Add support for the ARM, AHB, APB and DDR clocks found on the WM8505, WM8650, WM8750 and WM8850 SoCs. These clocks are gateable, but the enable part of the clock definition is left out as there are no users for these clocks, and we don't want them being disabled at boot, but it does provide users the ability to check the current rate of these clocks. Signed-off-by: Tony Prisk --- arch/arm/boot/dts/wm8505.dtsi | 28 ++++++++++++++++++++++++++++ arch/arm/boot/dts/wm8650.dtsi | 37 +++++++++++++++++++++++++++++-------- arch/arm/boot/dts/wm8750.dtsi | 7 +++++++ arch/arm/boot/dts/wm8850.dtsi | 28 ++++++++++++++++++++++++++++ 4 files changed, 92 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index 702d866b6f57..a1a854b8a454 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -109,6 +109,34 @@ reg = <0x20c>; }; + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x350>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi index 46a4603c9c53..7525982262ac 100644 --- a/arch/arm/boot/dts/wm8650.dtsi +++ b/arch/arm/boot/dts/wm8650.dtsi @@ -113,6 +113,34 @@ reg = <0x210>; }; + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x320>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; @@ -129,14 +157,7 @@ enable-bit = <2>; }; - arm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - sdhc: sdhc { + clksdhc: sdhc { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; clocks = <&pllb>; diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi index e4a1e8553e30..557a9c2ace49 100644 --- a/arch/arm/boot/dts/wm8750.dtsi +++ b/arch/arm/boot/dts/wm8750.dtsi @@ -133,6 +133,13 @@ divisor-reg = <0x304>; }; + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x320>; + }; + clkddr: ddr { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi index 59aaad98f544..1f49f54c38d2 100644 --- a/arch/arm/boot/dts/wm8850.dtsi +++ b/arch/arm/boot/dts/wm8850.dtsi @@ -130,6 +130,34 @@ reg = <0x218>; }; + clkarm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + clkahb: ahb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x304>; + }; + + clkapb: apb { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x320>; + }; + + clkddr: ddr { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plld>; + divisor-reg = <0x310>; + }; + clkuart0: uart0 { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; -- cgit v1.2.3 From e36572b64df358f0bc3a508e8761c81d7f3b8215 Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Fri, 17 May 2013 21:30:05 +1200 Subject: dts: vt8500: Correct reference clock on WM8850 SoCs WM8850 SoCs use a 24Mhz reference clock for the PLLs but the SoC file currently parents all PLLs to the 25Mhz reference clock. This patch corrects the PLL parent clock references. Signed-off-by: Tony Prisk --- arch/arm/boot/dts/wm8850.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi index 1f49f54c38d2..d98386dd2882 100644 --- a/arch/arm/boot/dts/wm8850.dtsi +++ b/arch/arm/boot/dts/wm8850.dtsi @@ -84,49 +84,49 @@ plla: plla { #clock-cells = <0>; compatible = "wm,wm8850-pll-clock"; - clocks = <&ref25>; + clocks = <&ref24>; reg = <0x200>; }; pllb: pllb { #clock-cells = <0>; compatible = "wm,wm8850-pll-clock"; - clocks = <&ref25>; + clocks = <&ref24>; reg = <0x204>; }; pllc: pllc { #clock-cells = <0>; compatible = "wm,wm8850-pll-clock"; - clocks = <&ref25>; + clocks = <&ref24>; reg = <0x208>; }; plld: plld { #clock-cells = <0>; compatible = "wm,wm8850-pll-clock"; - clocks = <&ref25>; + clocks = <&ref24>; reg = <0x20c>; }; plle: plle { #clock-cells = <0>; compatible = "wm,wm8850-pll-clock"; - clocks = <&ref25>; + clocks = <&ref24>; reg = <0x210>; }; pllf: pllf { #clock-cells = <0>; compatible = "wm,wm8850-pll-clock"; - clocks = <&ref25>; + clocks = <&ref24>; reg = <0x214>; }; pllg: pllg { #clock-cells = <0>; compatible = "wm,wm8850-pll-clock"; - clocks = <&ref25>; + clocks = <&ref24>; reg = <0x218>; }; -- cgit v1.2.3