From 0ed626d35ea2ec744826b3ebcb1d190a6c670d56 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 17 Aug 2017 13:32:11 +0200 Subject: arm64: defconfig: Enable Renesas R8A77995 SoC Enable support for the Renesas R-Car D3 SoC. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 34480e9af2e7..a83012a7f4b8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -51,6 +51,7 @@ CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_R8A7795=y CONFIG_ARCH_R8A7796=y +CONFIG_ARCH_R8A77995=y CONFIG_ARCH_STRATIX10=y CONFIG_ARCH_TEGRA=y CONFIG_ARCH_SPRD=y -- cgit v1.2.3 From 545dc83ed09b5c04f663b766a92cbc8bb02c5f15 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 18 Aug 2017 12:12:38 +0100 Subject: ARM: multi_v7_defconfig: Enable BQ32000 RTC driver The iWave RZ/G1M Q7 SOM supports RTC (TI BQ32000). To increase hardware support enable the driver in the multi_v7_defconfig multiplatform configuration. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 0cacdbf84a71..90f546766f38 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -767,6 +767,7 @@ CONFIG_RTC_DRV_MAX8997=m CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_RK808=m CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_BQ32K=m CONFIG_RTC_DRV_PALMAS=y CONFIG_RTC_DRV_ST_LPC=y CONFIG_RTC_DRV_TWL4030=y -- cgit v1.2.3 From 8e5f2d651f5b8ebf4b462aac02f51fe6075f88c0 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 16 Aug 2017 11:20:10 +0100 Subject: ARM: debug-ll: Add support for r8a7745 Enable low-level debugging support for RZ/G1E (r8a7745). RZ/G1E uses SCIF4 for the debug console. Signed-off-by: Fabrizio Castro Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/Kconfig.debug | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 6dcea8e8e941..31bf312be7d5 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -911,6 +911,13 @@ choice Say Y here if you want kernel low-level debugging support via SCIF2 on Renesas R-Car E2 (R8A7794). + config DEBUG_RCAR_GEN2_SCIF4 + bool "Kernel low-level debugging messages via SCIF4 on R8A7745" + depends on ARCH_R8A7745 + help + Say Y here if you want kernel low-level debugging support + via SCIF4 on Renesas RZ/G1E (R8A7745). + config DEBUG_RMOBILE_SCIFA0 bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4" depends on ARCH_R8A73A4 @@ -1451,6 +1458,7 @@ config DEBUG_LL_INCLUDE default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2 + default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4 default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0 default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1 default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4 @@ -1570,6 +1578,7 @@ config DEBUG_UART_PHYS default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4 default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2 default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0 + default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4 default 0xe8008000 if DEBUG_R7S72100_SCIF2 default 0xf0000be0 if ARCH_EBSA110 default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE @@ -1604,6 +1613,7 @@ config DEBUG_UART_PHYS DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \ DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \ DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \ + DEBUG_RCAR_GEN2_SCIF4 || \ DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \ DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \ DEBUG_S3C64XX_UART || \ -- cgit v1.2.3 From c5d43be52e0c7380f985585ef72dac1a6a89b59d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 1 Sep 2017 10:37:44 +0200 Subject: ARM: Add definition for monitor mode provides *_MODE definitions for the various processor modes, but monitor mode was missing. Add MON_MODE to avoid code using the hardcoded value. Suggested-by: Marc Zyngier Signed-off-by: Geert Uytterhoeven Tested-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/include/uapi/asm/ptrace.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h index 5af0ed1b825a..70ff6bf489f3 100644 --- a/arch/arm/include/uapi/asm/ptrace.h +++ b/arch/arm/include/uapi/asm/ptrace.h @@ -53,6 +53,7 @@ #endif #define FIQ_MODE 0x00000011 #define IRQ_MODE 0x00000012 +#define MON_MODE 0x00000016 #define ABT_MODE 0x00000017 #define HYP_MODE 0x0000001a #define UND_MODE 0x0000001b -- cgit v1.2.3 From 3fd45a136ff61bb54deab70fb2d534a85e40481f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 1 Sep 2017 10:37:45 +0200 Subject: ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15 On Cortex-A7, the arch timer CNTVOFF register is uninitialized. Ideally it should be initialized by the boot loader, but it isn't. For the boot CPU, CNTVOFF is initialized by Linux since commit 9ce3fa6816c2fb59 ("ARM: shmobile: rcar-gen2: Add CA7 arch_timer initialization for r8a7794"). For secondary CPU cores, no such initialization is done. Hence when enabling SMP on r8a7794, the kernel log is spammed with: WARNING: Underflow in clocksource 'arch_sys_counter' observed, time update ignored. Please report this, consider using a different clocksource, if possible. Your kernel is probably still fine. As Marc Zyngier pointed out that Cortex-A15 and Cortex-A7 are similar with respect to CNTVOFF, we have been very lucky this just worked on R-Car Gen2 SoCs with Cortex-A15 cores. To fix this: - Move the existing inline asm code to initialize CNTVOFF to an assembler source file (adding comments and replacing hardcoded constants by definitions in the process), so it can be reused, - Perform the initialization of CNTVOFF on the boot CPU (Cortex-A15 or Cortex-A7) on all R-Car Gen2 and RZ/G1 parts, - Wrap the standard secondary_startup() routine inside a routine which initializes CNTVOFF. Based on patches by Hisashi Nakamura in the BSP. Signed-off-by: Geert Uytterhoeven Tested-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/common.h | 2 ++ arch/arm/mach-shmobile/headsmp-apmu.S | 37 ++++++++++++++++++++++++++++++++ arch/arm/mach-shmobile/platsmp-apmu.c | 2 +- arch/arm/mach-shmobile/setup-rcar-gen2.c | 20 ++--------------- 5 files changed, 43 insertions(+), 19 deletions(-) create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 64611a1b4276..32176a00c664 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -22,6 +22,7 @@ cpu-y := platsmp.o headsmp.o # Shared SoC family objects obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y) CFLAGS_setup-rcar-gen2.o += -march=armv7-a +obj-$(CONFIG_ARCH_RCAR_GEN2) += headsmp-apmu.o obj-$(CONFIG_ARCH_R8A7790) += regulator-quirk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7791) += regulator-quirk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7793) += regulator-quirk-rcar-gen2.o diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h index 1a8f7b3ab449..ea6e9e2be3f7 100644 --- a/arch/arm/mach-shmobile/common.h +++ b/arch/arm/mach-shmobile/common.h @@ -1,6 +1,7 @@ #ifndef __ARCH_MACH_COMMON_H #define __ARCH_MACH_COMMON_H +extern void shmobile_init_cntvoff(void); extern void shmobile_init_delay(void); extern void shmobile_boot_vector(void); extern unsigned long shmobile_boot_fn; @@ -11,6 +12,7 @@ extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, unsigned long arg); extern bool shmobile_smp_cpu_can_disable(unsigned int cpu); extern bool shmobile_smp_init_fallback_ops(void); +extern void shmobile_boot_apmu(void); extern void shmobile_boot_scu(void); extern void shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys, unsigned int max_cpus); diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S b/arch/arm/mach-shmobile/headsmp-apmu.S new file mode 100644 index 000000000000..db4743d2bf91 --- /dev/null +++ b/arch/arm/mach-shmobile/headsmp-apmu.S @@ -0,0 +1,37 @@ +/* + * SMP support for APMU based systems with Cortex A7/A15 + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +ENTRY(shmobile_init_cntvoff) + /* + * CNTVOFF has to be initialized either from non-secure Hypervisor + * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled + * then it should be handled by the secure code + */ + cps #MON_MODE + mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */ + orr r0, r1, #1 + mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */ + instr_sync + mov r0, #0 + mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */ + instr_sync + mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */ + instr_sync + cps #SVC_MODE + ret lr +ENDPROC(shmobile_init_cntvoff) + +ENTRY(shmobile_boot_apmu) + bl shmobile_init_cntvoff + b secondary_startup +ENDPROC(shmobile_boot_apmu) diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index 3ca2c13346f0..4422b615a6ee 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c @@ -204,7 +204,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus, int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) { /* For this particular CPU register boot vector */ - shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0); + shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_apmu), 0); return apmu_wrap(cpu, apmu_power_on); } diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 7ab1690fab82..5561dbed7a33 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -70,28 +70,12 @@ void __init rcar_gen2_timer_init(void) void __iomem *base; u32 freq; + shmobile_init_cntvoff(); + if (of_machine_is_compatible("renesas,r8a7745") || of_machine_is_compatible("renesas,r8a7792") || of_machine_is_compatible("renesas,r8a7794")) { freq = 260000000 / 8; /* ZS / 8 */ - /* CNTVOFF has to be initialized either from non-secure - * Hypervisor mode or secure Monitor mode with SCR.NS==1. - * If TrustZone is enabled then it should be handled by the - * secure code. - */ - asm volatile( - " cps 0x16\n" - " mrc p15, 0, r1, c1, c1, 0\n" - " orr r0, r1, #1\n" - " mcr p15, 0, r0, c1, c1, 0\n" - " isb\n" - " mov r0, #0\n" - " mcrr p15, 4, r0, r0, c14\n" - " isb\n" - " mcr p15, 0, r1, c1, c1, 0\n" - " isb\n" - " cps 0x13\n" - : : : "r0", "r1"); } else { /* At Linux boot time the r8a7790 arch timer comes up * with the counter disabled. Moreover, it may also report -- cgit v1.2.3 From 86f0a075111d16e3b48d79b44858e141ea86cad7 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 18 Sep 2017 20:31:13 +0200 Subject: arm64: defconfig: enable thermal driver for Renesas R-Car Gen3 We want this driver to detect critical temperatures in time. Signed-off-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index a83012a7f4b8..1eb054469927 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -316,6 +316,7 @@ CONFIG_CPU_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_BRCMSTB_THERMAL=m CONFIG_EXYNOS_THERMAL=y +CONFIG_RCAR_GEN3_THERMAL=y CONFIG_ROCKCHIP_THERMAL=m CONFIG_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y -- cgit v1.2.3 From f0f838fd8cd53d8df8220b4081d7dec042ac9dd7 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:37 -0700 Subject: ARM: dts: Add missing dma hwmods property for omap3 On omap3, we are missing a ti,hwmods property for dma that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index bdaf30c8c405..90b5c7148feb 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -215,6 +215,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <96>; + ti,hwmods = "dma"; }; gpio1: gpio@48310000 { -- cgit v1.2.3 From b0142a10db149daadbc2cc94c890dd00b3fa58ad Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:38 -0700 Subject: ARM: dts: Configure pmu without interrupt for omap4430 On omap4430, the PMU is not configure unlike on omap4460 because of the missing handling. The missing pmu node with the missing ti,hwmods entry will cause boot time errors when the legacy platform data is removed as the SoC interconnect code needs it. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Let's fix the issue by configuring PMU but without the interrupts. Then when cross trigger interface (CTI) is supported, we can add interrupts also for omap4430. Cc: Jon Hunter Cc: Will Deacon Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 64d00f5893a6..47bc41954e2e 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -51,6 +51,17 @@ }; }; + /* + * Note that 4430 needs cross trigger interface (CTI) supported + * before we can configure the interrupts. This means sampling + * events are not supported for pmu. Note that 4460 does not use + * CTI, see also 4460.dtsi. + */ + pmu { + compatible = "arm,cortex-a9-pmu"; + ti,hwmods = "debugss"; + }; + gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; -- cgit v1.2.3 From 1d6a332ae8b7d8eacb9fe4c0a09370550f0b3eee Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:39 -0700 Subject: ARM: dts: Add missing properties for omap4 control modules On omap4, we are missing several ti,hwmods properties and IO ranges for system control modules. These are needed by the SoC interconnect code. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. In order to add these, we need to move omap4_pmx_wkup to be a child of omap4_padconf_wkup. On omap4 there are separate modules for control module and control module pads. For control module core, we have this already configured except for the missing ti,hwmods and reg entries. Cc: Mark Rutland Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/arm/omap/ctrl.txt | 2 ++ arch/arm/boot/dts/omap4.dtsi | 39 ++++++++++++++++------ 2 files changed, 31 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt index 3a4e5901ce31..ce8dabf8c0f9 100644 --- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt +++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt @@ -21,6 +21,8 @@ Required properties: "ti,omap3-scm" "ti,omap4-scm-core" "ti,omap4-scm-padconf-core" + "ti,omap4-scm-wkup" + "ti,omap4-scm-padconf-wkup" "ti,omap5-scm-core" "ti,omap5-scm-padconf-core" "ti,dra7-scm-core" diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 47bc41954e2e..16ec0bd29209 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -174,6 +174,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2000 0x1000>; + ti,hwmods = "ctrl_module_core"; scm_conf: scm_conf@0 { compatible = "syscon"; @@ -186,9 +187,11 @@ omap4_padconf_core: scm@100000 { compatible = "ti,omap4-scm-padconf-core", "simple-bus"; + reg = <0x100000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x100000 0x1000>; + ti,hwmods = "ctrl_module_pad_core"; omap4_pmx_core: pinmux@40 { compatible = "ti,omap4-padconf", @@ -263,17 +266,33 @@ }; }; - omap4_pmx_wkup: pinmux@1e040 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x1e040 0x0038>; + omap4_scm_wkup: scm@c000 { + compatible = "ti,omap4-scm-wkup"; + reg = <0xc000 0x1000>; + ti,hwmods = "ctrl_module_wkup"; + }; + + omap4_padconf_wkup: padconf@1e000 { + compatible = "ti,omap4-scm-padconf-wkup", + "simple-bus"; + reg = <0x1e000 0x1000>; #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; + #size-cells = <1>; + ranges = <0 0x1e000 0x1000>; + ti,hwmods = "ctrl_module_pad_wkup"; + + omap4_pmx_wkup: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; }; }; }; -- cgit v1.2.3 From 370ad6b4670adfc3c5c7d5aad63347e8db839762 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:40 -0700 Subject: ARM: dts: Add missing hwmods property for omap4 dma On omap4, we are missing a ti,hwmods property for dma that the that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 16ec0bd29209..24a3f70f1eef 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -312,6 +312,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + ti,hwmods = "dma_system"; }; gpio1: gpio@4a310000 { -- cgit v1.2.3 From 514b2da46fcc10bd5f42446b9fa746ba2c80aaf1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:41 -0700 Subject: ARM: dts: Add missing smartreflex node and binding for omap4 We are missing smartreflex device tree nodes for omap4 with their related "ti,hwmods" properties that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. And since we're missing the device tree binding for smartreflex, let's also add it and document the existing omap3 use too. Note that the related driver also needs to be updated to probe using device tree and get the platform data passed to it using auxdata with arch/arm/mach-omap2/pdata-quirks.c. Cc: Mark Rutland Cc: Nishanth Menon Cc: Rafael J. Wysocki Cc: Tero Kristo Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/power/ti-smartreflex.txt | 47 ++++++++++++++++++++++ arch/arm/boot/dts/omap4.dtsi | 21 ++++++++++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/ti-smartreflex.txt diff --git a/Documentation/devicetree/bindings/power/ti-smartreflex.txt b/Documentation/devicetree/bindings/power/ti-smartreflex.txt new file mode 100644 index 000000000000..9780957c9115 --- /dev/null +++ b/Documentation/devicetree/bindings/power/ti-smartreflex.txt @@ -0,0 +1,47 @@ +Texas Instruments SmartReflex binding + +SmartReflex is used to set and adjust the SoC operating points. + + +Required properties: + +compatible: Shall be one of the following: + "ti,omap3-smartreflex-core" + "ti,omap3-smartreflex-iva" + "ti,omap4-smartreflex-core" + "ti,omap4-smartreflex-mpu" + "ti,omap4-smartreflex-iva" + +reg: Shall contain the device instance IO range + +interrupts: Shall contain the device instance interrupt + + +Optional properties: + +ti,hwmods: Shall contain the TI interconnect module name if needed + by the SoC + + +Example: + + smartreflex_iva: smartreflex@4a0db000 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0x4a0db000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_iva"; + }; + + smartreflex_core: smartreflex@4a0dd000 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0x4a0dd000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_core"; + }; + + smartreflex_mpu: smartreflex@4a0d9000 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0x4a0d9000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_mpu"; + }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 24a3f70f1eef..c48b7e8713ca 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -442,6 +442,27 @@ clock-frequency = <48000000>; }; + smartreflex_iva: smartreflex@4a0db000 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0x4a0db000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_iva"; + }; + + smartreflex_core: smartreflex@4a0dd000 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0x4a0dd000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_core"; + }; + + smartreflex_mpu: smartreflex@4a0d9000 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0x4a0d9000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_mpu"; + }; + hwspinlock: spinlock@4a0f6000 { compatible = "ti,omap4-hwspinlock"; reg = <0x4a0f6000 0x1000>; -- cgit v1.2.3 From d6e1a2381694c9a15f5a2ea9877fd20017470e95 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:43 -0700 Subject: ARM: dts: Add missing onewire node for omap4 On omap4 we're missing the onewire node with it's related "ti,hwmods" property that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index c48b7e8713ca..69d129b420e0 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -541,6 +541,13 @@ dma-names = "tx0", "rx0", "tx1", "rx1"; }; + hdqw1w: 1w@480b2000 { + compatible = "ti,omap3-1w"; + reg = <0x480b2000 0x1000>; + interrupts = ; + ti,hwmods = "hdq1w"; + }; + mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; reg = <0x480b8000 0x200>; -- cgit v1.2.3 From 8be8576fcf2d90a8bc679bfb25a4121d0eebe0de Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 13:25:20 -0700 Subject: ARM: dts: Add missing hsi node for omap4 On omap4 we're missing the hsi node with it's related "ti,hwmods" property that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Let's also update the binding accrodingly while at it. Cc: Mark Rutland Cc: Rob Herring Reviewed-by: Sebastian Reichel Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/hsi/omap-ssi.txt | 13 +++++++-- arch/arm/boot/dts/omap4.dtsi | 34 ++++++++++++++++++++++ 2 files changed, 44 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/hsi/omap-ssi.txt b/Documentation/devicetree/bindings/hsi/omap-ssi.txt index b8eca3c7810d..955e335e7e56 100644 --- a/Documentation/devicetree/bindings/hsi/omap-ssi.txt +++ b/Documentation/devicetree/bindings/hsi/omap-ssi.txt @@ -1,10 +1,12 @@ OMAP SSI controller bindings -OMAP Synchronous Serial Interface (SSI) controller implements a legacy -variant of MIPI's High Speed Synchronous Serial Interface (HSI). +OMAP3's Synchronous Serial Interface (SSI) controller implements a +legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI), +while the controller found inside OMAP4 is supposed to be fully compliant +with the HSI standard. Required properties: -- compatible: Should include "ti,omap3-ssi". +- compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi" - reg-names: Contains the values "sys" and "gdd" (in this order). - reg: Contains a matching register specifier for each entry in reg-names. @@ -27,6 +29,7 @@ Each port is represented as a sub-node of the ti,omap3-ssi device. Required Port sub-node properties: - compatible: Should be set to the following value ti,omap3-ssi-port (applicable to OMAP34xx devices) + ti,omap4-hsi-port (applicable to OMAP44xx devices) - reg-names: Contains the values "tx" and "rx" (in this order). - reg: Contains a matching register specifier for each entry in reg-names. @@ -38,6 +41,10 @@ Required Port sub-node properties: property. If it's missing the port will not be enabled. +Optional properties: +- ti,hwmods: Shall contain TI interconnect module name if needed + by the SoC + Example for Nokia N900: ssi-controller@48058000 { diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 69d129b420e0..a3c4d3541e3d 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -624,6 +624,40 @@ dma-names = "tx", "rx"; }; + hsi: hsi@4a058000 { + compatible = "ti,omap4-hsi"; + reg = <0x4a058000 0x4000>, + <0x4a05c000 0x1000>; + reg-names = "sys", "gdd"; + ti,hwmods = "hsi"; + + clocks = <&hsi_fck>; + clock-names = "hsi_fck"; + + interrupts = ; + interrupt-names = "gdd_mpu"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a058000 0x4000>; + + hsi_port1: hsi-port@2000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x2000 0x800>, + <0x2800 0x800>; + reg-names = "tx", "rx"; + interrupts = ; + }; + + hsi_port2: hsi-port@3000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x3000 0x800>, + <0x3800 0x800>; + reg-names = "tx", "rx"; + interrupts = ; + }; + }; + mmu_dsp: mmu@4a066000 { compatible = "ti,omap4-iommu"; reg = <0x4a066000 0x100>; -- cgit v1.2.3 From 5750d6717b54ac9461912264710a3b60cda153bb Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:46 -0700 Subject: ARM: dts: Add missing wdt3 node for omap4 On omap4 we're missing the wdt3 node with it's related "ti,hwmods" property that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index a3c4d3541e3d..70ecd840772d 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -682,6 +682,14 @@ ti,hwmods = "wd_timer2"; }; + wdt3: wdt@40130000 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x40130000 0x80>, /* MPU private access */ + <0x49030000 0x80>; /* L3 Interconnect */ + interrupts = ; + ti,hwmods = "wd_timer3"; + }; + mcpdm: mcpdm@40132000 { compatible = "ti,omap4-mcpdm"; reg = <0x40132000 0x7f>, /* MPU private access */ -- cgit v1.2.3 From ef90bfb8be2b0f7f1d9308ff3defa1b441c661f9 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:51 -0700 Subject: ARM: dts: Add missing dma hwmod property for omap5 On omap5 we're missing the dma "ti,hwmods" property that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index eaff2a5751dd..b86ac7df620d 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -295,6 +295,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + ti,hwmods = "dma_system"; }; gpio1: gpio@4ae10000 { -- cgit v1.2.3 From cd57dc5a2099a43c99fb39cb7c953246149db816 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:52 -0700 Subject: ARM: dts: Add missing hwmod related nodes for am33xx On am33xx we're missing the pmu and emif nodes with their related "ti,hwmods" properties that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Let's also update the related binding documentation while at it. Cc: Mark Rutland Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/memory-controllers/ti/emif.txt | 6 ++++-- arch/arm/boot/dts/am33xx.dtsi | 10 +++++++++- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt index 0db60470ebb6..fd823d6091b2 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt +++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt @@ -7,8 +7,10 @@ of the EMIF IP and memory parts attached to it. Required properties: - compatible : Should be of the form "ti,emif-" where - is the IP revision of the specific EMIF instance. - For am437x should be ti,emif-am4372. + is the IP revision of the specific EMIF instance. For newer controllers, + compatible should be one of the following: + "ti,emif-am3352" + "ti,emif-am4372" - phy-type : indicating the DDR phy type. Following are the allowed values diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 7d7ca054c557..08653552db71 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -128,9 +128,11 @@ }; }; - pmu { + pmu@4b000000 { compatible = "arm,cortex-a8-pmu"; interrupts = <3>; + reg = <0x4b000000 0x1000000>; + ti,hwmods = "debugss"; }; /* @@ -927,6 +929,12 @@ }; }; + emif: emif@4c000000 { + compatible = "ti,emif-am3352"; + reg = <0x4c000000 0x1000000>; + ti,hwmods = "emif"; + }; + gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; -- cgit v1.2.3 From 288cdbbff2dcfc5188a708a9a3e7aaedc41512f1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:53 -0700 Subject: ARM: dts: Add missing hwmod related properties for dra7 On dra7 we're missing two "ti,hwmods" properties that the SoC interconnect code needs. For hdq 1-wire, we need to add the node for that. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Cc: Nishanth Menon Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 02a136a4661a..a33023ca4390 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -457,6 +457,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + ti,hwmods = "dma_system"; }; edma: edma@43300000 { @@ -1069,6 +1070,13 @@ max-frequency = <192000000>; }; + hdqw1w: 1w@480b2000 { + compatible = "ti,omap3-1w"; + reg = <0x480b2000 0x1000>; + interrupts = ; + ti,hwmods = "hdq1w"; + }; + mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; -- cgit v1.2.3 From 6963c58461b31c10cff221a7bbe4c61d803656c6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 29 Aug 2017 10:03:32 -0700 Subject: ARM: OMAP2+: Fix MMC address space mismatch for am33xx and am43xx The address space currently set up for the interconnect data is different compared to the dts data. We have hwmod data with offset 0x100 to account for the revision, sysc and syss register offsets. Let's fix the issue by correcting the MMC register offsets in hwmod data and removing the unnecessary duplicate IO range data that we get from device tree anyways. Cc: Lokesh Vutla Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren --- .../omap_hwmod_33xx_43xx_interconnect_data.c | 30 ---------------------- .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 6 ++--- 2 files changed, 3 insertions(+), 33 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c index 8236e5c49ec3..a88cb013fef9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c @@ -286,56 +286,26 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { }; /* l4 ls -> mmc0 */ -static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { - { - .pa_start = 0x48060100, - .pa_end = 0x48060100 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_mmc0_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_mmc0_addr_space, .user = OCP_USER_MPU, }; /* l4 ls -> mmc1 */ -static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { - { - .pa_start = 0x481d8100, - .pa_end = 0x481d8100 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_mmc1_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_mmc1_addr_space, .user = OCP_USER_MPU, }; /* l3 s -> mmc2 */ -static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { - { - .pa_start = 0x47810100, - .pa_end = 0x47810100 + SZ_64K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { .master = &am33xx_l3_s_hwmod, .slave = &am33xx_mmc2_hwmod, .clk = "l3s_gclk", - .addr = am33xx_mmc2_addr_space, .user = OCP_USER_MPU, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index de06a1d5ffab..4bcf9f3e1544 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -778,9 +778,9 @@ struct omap_hwmod am33xx_mcasp1_hwmod = { /* 'mmc' class */ static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { - .rev_offs = 0x1fc, - .sysc_offs = 0x10, - .syss_offs = 0x14, + .rev_offs = 0x2fc, + .sysc_offs = 0x110, + .syss_offs = 0x114, .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), -- cgit v1.2.3 From 8823ddf25d34e32c8691b9244e9b8aa120f1cff6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 29 Aug 2017 10:03:33 -0700 Subject: ARM: OMAP2+: Fix overwriting of clkctrl and modulemode values We are currently overwiting the hwmod clkctrl registers if we configure a clock ctrl clock from device tree. While this does not expose any bugs except for kernel coders when debugging things, it should be fixed for correctness. It is now impossible to use the hwmod data for checking the clkctrl register values after booting for debugging or generating dts data from hwmod data. Let's fix the issue by adding a helper to detect if clkctrl clock is configured. Cc: Lokesh Vutla Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 49 +++++++++++++++++++++++++++++++++------- arch/arm/mach-omap2/omap_hwmod.h | 3 +++ 2 files changed, 44 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2dbd63239c54..d50101d44795 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -993,6 +993,34 @@ static int _enable_clocks(struct omap_hwmod *oh) return 0; } +/** + * _omap4_clkctrl_managed_by_clkfwk - true if clkctrl managed by clock framework + * @oh: struct omap_hwmod * + */ +static bool _omap4_clkctrl_managed_by_clkfwk(struct omap_hwmod *oh) +{ + if (oh->prcm.omap4.flags & HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK) + return true; + + return false; +} + +/** + * _omap4_has_clkctrl_clock - returns true if a module has clkctrl clock + * @oh: struct omap_hwmod * + */ +static bool _omap4_has_clkctrl_clock(struct omap_hwmod *oh) +{ + if (oh->prcm.omap4.clkctrl_offs) + return true; + + if (!oh->prcm.omap4.clkctrl_offs && + oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET) + return true; + + return false; +} + /** * _disable_clocks - disable hwmod main clock and interface clocks * @oh: struct omap_hwmod * @@ -1030,7 +1058,8 @@ static int _disable_clocks(struct omap_hwmod *oh) */ static void _omap4_enable_module(struct omap_hwmod *oh) { - if (!oh->clkdm || !oh->prcm.omap4.modulemode) + if (!oh->clkdm || !oh->prcm.omap4.modulemode || + _omap4_clkctrl_managed_by_clkfwk(oh)) return; pr_debug("omap_hwmod: %s: %s: %d\n", @@ -1061,8 +1090,10 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh) if (oh->flags & HWMOD_NO_IDLEST) return 0; - if (!oh->prcm.omap4.clkctrl_offs && - !(oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET)) + if (_omap4_clkctrl_managed_by_clkfwk(oh)) + return 0; + + if (!_omap4_has_clkctrl_clock(oh)) return 0; return omap_cm_wait_module_idle(oh->clkdm->prcm_partition, @@ -1847,7 +1878,8 @@ static int _omap4_disable_module(struct omap_hwmod *oh) { int v; - if (!oh->clkdm || !oh->prcm.omap4.modulemode) + if (!oh->clkdm || !oh->prcm.omap4.modulemode || + _omap4_clkctrl_managed_by_clkfwk(oh)) return -EINVAL; /* @@ -2829,8 +2861,10 @@ static int _omap4_wait_target_ready(struct omap_hwmod *oh) if (!_find_mpu_rt_port(oh)) return 0; - if (!oh->prcm.omap4.clkctrl_offs && - !(oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET)) + if (_omap4_clkctrl_managed_by_clkfwk(oh)) + return 0; + + if (!_omap4_has_clkctrl_clock(oh)) return 0; /* XXX check module SIDLEMODE, hardreset status */ @@ -2986,8 +3020,7 @@ static int _omap4_disable_direct_prcm(struct omap_hwmod *oh) if (!oh) return -EINVAL; - oh->prcm.omap4.clkctrl_offs = 0; - oh->prcm.omap4.modulemode = 0; + oh->prcm.omap4.flags |= HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK; return 0; } diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index a8f779381fd8..89daf35d7f8a 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -446,9 +446,12 @@ struct omap_hwmod_omap2_prcm { * HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET: Some IP blocks have a valid CLKCTRL * offset of zero; this flag bit should be set in those cases to * distinguish from hwmods that have no clkctrl offset. + * HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK: Module clockctrl clock is managed + * by the common clock framework and not hwmod. */ #define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT (1 << 0) #define HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET (1 << 1) +#define HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK (1 << 2) /** * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data -- cgit v1.2.3 From 680dc624f1e136fbd11e354b978a1873c4736aba Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 29 Aug 2017 10:03:34 -0700 Subject: ARM: OMAP2+: Drop unused omap_init_hdq We now boot all of mach-omap2 in device tree only mode and this is now dead code. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/hdq1w.c | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c index f3897d82e53e..2bc4db23ca56 100644 --- a/arch/arm/mach-omap2/hdq1w.c +++ b/arch/arm/mach-omap2/hdq1w.c @@ -75,25 +75,3 @@ int omap_hdq1w_reset(struct omap_hwmod *oh) return 0; } - -#ifndef CONFIG_OF -static int __init omap_init_hdq(void) -{ - int id = -1; - struct platform_device *pdev; - struct omap_hwmod *oh; - char *oh_name = "hdq1w"; - char *devname = "omap_hdq"; - - oh = omap_hwmod_lookup(oh_name); - if (!oh) - return 0; - - pdev = omap_device_build(devname, id, oh, NULL, 0); - WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", - devname, oh->name); - - return 0; -} -omap_arch_initcall(omap_init_hdq); -#endif -- cgit v1.2.3 From dd33074ac6166dff6f156c0a3ddfc0d3094fcf6b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 29 Aug 2017 10:03:35 -0700 Subject: ARM: OMAP2+: Drop unused omap_hwmod_mux_info This is no longer used as we boot in device tree only mode. Cc: Lokesh Vutla Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.h | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 89daf35d7f8a..7dfd5989b665 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -21,7 +21,6 @@ * * To do: * - add interconnect error log structures - * - add pinmuxing * - init_conn_id_bit (CONNID_BIT_VECTOR) * - implement default hwmod SMS/SDRC flags? * - move Linux-specific data ("non-ROM data") out @@ -150,22 +149,6 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3; #define DEBUG_AM33XXUART1_FLAGS DEBUG_OMAPUART_FLAGS #endif -/** - * struct omap_hwmod_mux_info - hwmod specific mux configuration - * @pads: array of omap_device_pad entries - * @nr_pads: number of omap_device_pad entries - * - * Note that this is currently built during init as needed. - */ -struct omap_hwmod_mux_info { - int nr_pads; - struct omap_device_pad *pads; - int nr_pads_dynamic; - struct omap_device_pad **pads_dynamic; - int *irqs; - bool enabled; -}; - /** * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod * @name: name of the IRQ channel (module local name) @@ -673,7 +656,6 @@ struct omap_hwmod { const char *name; struct omap_hwmod_class *class; struct omap_device *od; - struct omap_hwmod_mux_info *mux; struct omap_hwmod_irq_info *mpu_irqs; struct omap_hwmod_dma_info *sdma_reqs; struct omap_hwmod_rst_info *rst_lines; -- cgit v1.2.3 From cb5f1b9d22bfc7802b3eccb2c650ccf2bd8b358e Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 1 Sep 2017 09:53:19 -0500 Subject: ARM: davinci_all_defconfig: enable MTD_CMDLINE_PARTS There is some disagreement between the partition table map in Linux for the DA850-EVM and the corresponding partition map in U-Boot. To prevent breaking the Kernel, this patch enables MTD_CMDLINE_PARTS which will allow the U-Boot to pass the partition map so future partitions match without breaking backwards compatibility. While at it, also sync to savedefconfig which leads to removal of CONFIG_MMC_BLOCK_BOUNCE. Signed-off-by: Adam Ford Signed-off-by: Sekhar Nori --- arch/arm/configs/davinci_all_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 27d9720f7207..4d432cf1ee79 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -59,6 +59,7 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DA8XX_MSTPRI=y CONFIG_MTD=m CONFIG_MTD_TESTS=m +CONFIG_MTD_CMDLINE_PARTS=m CONFIG_MTD_BLOCK=m CONFIG_MTD_CFI=m CONFIG_MTD_CFI_INTELEXT=m @@ -195,7 +196,6 @@ CONFIG_USB_G_SERIAL=m CONFIG_USB_G_PRINTER=m CONFIG_USB_CDC_COMPOSITE=m CONFIG_MMC=y -# CONFIG_MMC_BLOCK_BOUNCE is not set CONFIG_MMC_DAVINCI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=m -- cgit v1.2.3 From 6dee349e8c618a0dbb7e7dd0cf31da1a3eadd31a Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Mon, 18 Sep 2017 09:58:06 +0200 Subject: arm64: defconfig: enable the Marvell 10G PHY as a module The Marvell 10G PHY is present on mvebu platforms. Enable it as a module so that the network works on these platforms. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 34480e9af2e7..4c9d4f6692dc 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -204,6 +204,7 @@ CONFIG_STMMAC_ETH=m CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_AT803X_PHY=m CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m CONFIG_MESON_GXL_PHY=m CONFIG_MICREL_PHY=y CONFIG_REALTEK_PHY=m -- cgit v1.2.3 From a18615b7ef8d35c799a055013b9af1ec69cf244d Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 18 Sep 2017 09:58:07 +0200 Subject: arm64: defconfig: enable Marvell CP110 comphy The comphy is an hardware block giving access to common PHYs that can be used by various other engines (Network, SATA, ...). This is used on Marvell 7k/8k platforms for now. Enable the corresponding driver. Signed-off-by: Miquel Raynal Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4c9d4f6692dc..8495b88a0966 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -535,6 +535,7 @@ CONFIG_PWM_TEGRA=m CONFIG_PHY_RCAR_GEN3_USB2=y CONFIG_PHY_HI6220_USB=y CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_MVEBU_CP110_COMPHY=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_EMMC=y CONFIG_PHY_ROCKCHIP_PCIE=m -- cgit v1.2.3 From 5cd6bc681582e283661be6c16034b6493b9a8683 Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Wed, 30 Aug 2017 22:17:51 +0530 Subject: ARM: mxs: constify platform_suspend_ops platform_suspend_ops are not supposed to change at runtime. Functions suspend_set_ops working with const platform_suspend_ops. So mark the non-const structs as const. Signed-off-by: Arvind Yadav Signed-off-by: Shawn Guo --- arch/arm/mach-mxs/pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c index 0170e99fd70f..6ae057c2cf9f 100644 --- a/arch/arm/mach-mxs/pm.c +++ b/arch/arm/mach-mxs/pm.c @@ -30,7 +30,7 @@ static int mxs_suspend_enter(suspend_state_t state) return 0; } -static struct platform_suspend_ops mxs_suspend_ops = { +static const struct platform_suspend_ops mxs_suspend_ops = { .enter = mxs_suspend_enter, .valid = suspend_valid_only_mem, }; -- cgit v1.2.3 From bad29933fef76fb6ee577f4a0b6d145c1f52f663 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sun, 9 Jul 2017 04:17:46 +0200 Subject: ARM: owl: smp: Use __pa_symbol() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace an occurrence of virt_to_phys() with __pa_symbol() macro. See 64fc2a947a9873700929ec0ef02b4654a04e0476 ("ARM: 8641/1: treewide: Replace uses of virt_to_phys with __pa_symbol"). Fixes: 172067e0bc87 ("ARM: owl: Implement CPU enable-method for S500") Reported-by: Florian Fainelli Signed-off-by: Andreas Färber --- arch/arm/mach-actions/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c index 12a9e331b432..7238926ab015 100644 --- a/arch/arm/mach-actions/platsmp.c +++ b/arch/arm/mach-actions/platsmp.c @@ -71,7 +71,7 @@ static int s500_wakeup_secondary(unsigned int cpu) /* wait for CPUx to run to WFE instruction */ udelay(200); - writel(virt_to_phys(owl_secondary_startup), + writel(__pa_symbol(owl_secondary_startup), timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); writel(OWL_CPUx_FLAG_BOOT, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); -- cgit v1.2.3 From 6c2eb3e76fb84e2eb46d484f71fab469c0d9532c Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 3 Jul 2017 19:18:04 +0200 Subject: ARM: owl: smp: Drop owl_secondary_boot() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 18cfd9429d8a82c49add8f3ca9d366599bfcac45 simplified the S500 SMP code by removing a loop for pen_release in owl_secondary_boot(). Since then it is only calling owl_v7_invalidate_l1() before branching to secondary_startup(). The owl_v7_invalidate_l1() assembler function is superfluous, too. Therefore drop owl_secondary_boot() and use secondary_boot() directly. Fixes: 18cfd9429d8a ("ARM: owl: smp: Drop bogus holding pen") Cc: David Liu Signed-off-by: Andreas Färber --- arch/arm/mach-actions/Makefile | 4 +--- arch/arm/mach-actions/headsmp.S | 52 ----------------------------------------- arch/arm/mach-actions/platsmp.c | 2 +- 3 files changed, 2 insertions(+), 56 deletions(-) delete mode 100644 arch/arm/mach-actions/headsmp.S diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile index c0f116241da7..13831037d8cd 100644 --- a/arch/arm/mach-actions/Makefile +++ b/arch/arm/mach-actions/Makefile @@ -1,3 +1 @@ -obj-${CONFIG_SMP} += platsmp.o headsmp.o - -AFLAGS_headsmp.o := -Wa,-march=armv7-a +obj-${CONFIG_SMP} += platsmp.o diff --git a/arch/arm/mach-actions/headsmp.S b/arch/arm/mach-actions/headsmp.S deleted file mode 100644 index 65f53bdb69e7..000000000000 --- a/arch/arm/mach-actions/headsmp.S +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2012 Actions Semi Inc. - * Author: Actions Semi, Inc. - * - * Copyright (c) 2017 Andreas Färber - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -ENTRY(owl_v7_invalidate_l1) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp< Date: Sun, 3 Sep 2017 10:43:44 -0700 Subject: ARM: ep93xx: switch to SPARSEMEM The EP93xx has four chip selects that can be used for the SDRAM memory. These chip selects are decoded to specify an address domain: SDCS3 0x00000000-0x0fffffff with Boot Option ASDO=1 SDCS0 0xc0000000-0xcfffffff SDCS1 0xd0000000-0xdfffffff SDCS2 0xe0000000-x0efffffff SDCS3 0xf0000000-0xffffffff with Boot Option ASDO=0 Because of the row/column/bank architecture of SDRAM, the mapping of these memories into the processor's memory space is discontiguous. Most ep93xx systems only use one of the chip selects. For these systems, ARCH_HAS_HOLES_MEMORYMODEL has worked fine to handle the discontiguous memory. But, some of the TS-72xx boards use multiple chip selects. The TS-7300 in particular uses SDCS3 (with ASDO=1) and SDCS2. On that system with ARCH_HAS_HOLES_MEMORYMODEL the SDCS2 memory does not get handled correctly and results in the system not booting. Change the EP93xx to ARCH_SPARSEMEM_ENABLE. This handles the discontiguous memory for all configurations. This has been tested on the following ep93xx platforms: EDB9307A with 64 MiB on SDCS0 Vision EP9307 with 64 MiB on SDCS0 TS-7300 with 64 MiB on SDCS3 (with ASDO=1) and 64 MiB on SDCS2 sim.one with 64 MiB on SDCS0 Signed-off-by: H Hartley Sweeten Tested-by: Linus Walleij Cc: Russell King Tested-by: Florian Fainelli Tested-by: Alexander Sverdlin Signed-off-by: Linus Walleij --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7888c9803eb0..19af0885466e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -378,7 +378,7 @@ config ARCH_EBSA110 config ARCH_EP93XX bool "EP93xx-based" - select ARCH_HAS_HOLES_MEMORYMODEL + select ARCH_SPARSEMEM_ENABLE select ARM_AMBA imply ARM_PATCH_PHYS_VIRT select ARM_VIC -- cgit v1.2.3 From 14cd18a89337b2fe509f2a70bea734c488d7a698 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Sun, 3 Sep 2017 10:43:45 -0700 Subject: ARM: ep93xx: simone: let the mmc_spi driver handle the card detect This board uses a GPIO for the MMC card detect. Let the mmc_spi driver handle it instead of the platform code. Signed-off-by: H Hartley Sweeten Tested-by: Linus Walleij Reviewed-by: Alexander Sverdlin Signed-off-by: Linus Walleij --- arch/arm/mach-ep93xx/simone.c | 54 +++---------------------------------------- 1 file changed, 3 insertions(+), 51 deletions(-) diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c index c7a40f245892..1c353868f211 100644 --- a/arch/arm/mach-ep93xx/simone.c +++ b/arch/arm/mach-ep93xx/simone.c @@ -43,60 +43,12 @@ static struct ep93xxfb_mach_info __initdata simone_fb_info = { .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING, }; -/* - * GPIO lines used for MMC card detection. - */ -#define MMC_CARD_DETECT_GPIO EP93XX_GPIO_LINE_EGPIO0 - -/* - * MMC card detection GPIO setup. - */ - -static int simone_mmc_spi_init(struct device *dev, - irqreturn_t (*irq_handler)(int, void *), void *mmc) -{ - unsigned int gpio = MMC_CARD_DETECT_GPIO; - int irq, err; - - err = gpio_request(gpio, dev_name(dev)); - if (err) - return err; - - err = gpio_direction_input(gpio); - if (err) - goto fail; - - irq = gpio_to_irq(gpio); - if (irq < 0) - goto fail; - - err = request_irq(irq, irq_handler, IRQF_TRIGGER_FALLING, - "MMC card detect", mmc); - if (err) - goto fail; - - printk(KERN_INFO "%s: using irq %d for MMC card detection\n", - dev_name(dev), irq); - - return 0; -fail: - gpio_free(gpio); - return err; -} - -static void simone_mmc_spi_exit(struct device *dev, void *mmc) -{ - unsigned int gpio = MMC_CARD_DETECT_GPIO; - - free_irq(gpio_to_irq(gpio), mmc); - gpio_free(gpio); -} - static struct mmc_spi_platform_data simone_mmc_spi_data = { - .init = simone_mmc_spi_init, - .exit = simone_mmc_spi_exit, .detect_delay = 500, .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .flags = MMC_SPI_USE_CD_GPIO, + .cd_gpio = EP93XX_GPIO_LINE_EGPIO0, + .cd_debounce = 1, }; static struct spi_board_info simone_spi_devices[] __initdata = { -- cgit v1.2.3 From 97c3bca922468996c864917c9a8ea6a410233985 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Sun, 3 Sep 2017 10:43:46 -0700 Subject: ARM: ep93xx: tidy up TS-72xx Watchdog resources The ts-72xx watchdog uses two byte sized registers. Tidy up the resource declaration so that the proper information is shown in /proc/iomem. Signed-off-by: H Hartley Sweeten Reviewed-by: Alexander Sverdlin Signed-off-by: Linus Walleij --- arch/arm/mach-ep93xx/ts72xx.c | 20 +++++++++----------- arch/arm/mach-ep93xx/ts72xx.h | 3 --- 2 files changed, 9 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index 8745162ec05d..eb9be7ef59fc 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -186,24 +186,22 @@ static struct platform_device ts72xx_rtc_device = { .num_resources = ARRAY_SIZE(ts72xx_rtc_resources), }; +/************************************************************************* + * Watchdog (in CPLD) + *************************************************************************/ +#define TS72XX_WDT_CONTROL_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03800000) +#define TS72XX_WDT_FEED_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03c00000) + static struct resource ts72xx_wdt_resources[] = { - { - .start = TS72XX_WDT_CONTROL_PHYS_BASE, - .end = TS72XX_WDT_CONTROL_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = TS72XX_WDT_FEED_PHYS_BASE, - .end = TS72XX_WDT_FEED_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(TS72XX_WDT_CONTROL_PHYS_BASE, 0x01), + DEFINE_RES_MEM(TS72XX_WDT_FEED_PHYS_BASE, 0x01), }; static struct platform_device ts72xx_wdt_device = { .name = "ts72xx-wdt", .id = -1, - .num_resources = ARRAY_SIZE(ts72xx_wdt_resources), .resource = ts72xx_wdt_resources, + .num_resources = ARRAY_SIZE(ts72xx_wdt_resources), }; static struct ep93xx_eth_data __initdata ts72xx_eth_data = { diff --git a/arch/arm/mach-ep93xx/ts72xx.h b/arch/arm/mach-ep93xx/ts72xx.h index 2255ba29fdd6..4e6519b2a3c4 100644 --- a/arch/arm/mach-ep93xx/ts72xx.h +++ b/arch/arm/mach-ep93xx/ts72xx.h @@ -38,9 +38,6 @@ #define TS72XX_OPTIONS2_TS9420 0x04 #define TS72XX_OPTIONS2_TS9420_BOOT 0x02 -#define TS72XX_WDT_CONTROL_PHYS_BASE 0x23800000 -#define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000 - #ifndef __ASSEMBLY__ static inline int ts72xx_model(void) -- cgit v1.2.3 From 7aef828dfc41565f7e2f7af99be8134639d3f769 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Sun, 3 Sep 2017 10:43:47 -0700 Subject: ARM: ep93xx: Add lm70 HWMON sensor to TS-72xx boards Register the TI TMP122 (lm70) temperature sensor driver for the TS-72xx boards. Originaly from Florian Fainelli. Updated to the new spi-ep93xx chip select method. Signed-off-by: H Hartley Sweeten Signed-off-by: Florian Fainelli Reviewed-by: Alexander Sverdlin Signed-off-by: Linus Walleij --- arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index eb9be7ef59fc..f386ebae0163 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -18,7 +18,10 @@ #include #include #include +#include +#include +#include #include #include @@ -230,6 +233,27 @@ static struct platform_device ts73xx_fpga_device = { #endif +/************************************************************************* + * SPI Bus + *************************************************************************/ +static struct spi_board_info ts72xx_spi_devices[] __initdata = { + { + .modalias = "tmp122", + .max_speed_hz = 2 * 1000 * 1000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static int ts72xx_spi_chipselects[] __initdata = { + EP93XX_GPIO_LINE_F(2), /* DIO_17 */ +}; + +static struct ep93xx_spi_info ts72xx_spi_info __initdata = { + .chipselect = ts72xx_spi_chipselects, + .num_chipselect = ARRAY_SIZE(ts72xx_spi_chipselects), +}; + static void __init ts72xx_init_machine(void) { ep93xx_init_devices(); @@ -242,6 +266,8 @@ static void __init ts72xx_init_machine(void) if (board_is_ts7300()) platform_device_register(&ts73xx_fpga_device); #endif + ep93xx_register_spi(&ts72xx_spi_info, ts72xx_spi_devices, + ARRAY_SIZE(ts72xx_spi_devices)); } MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") -- cgit v1.2.3 From 5627453efabf8eef84ce1dce6767d1268570a6c5 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 20 Sep 2017 13:01:32 -0500 Subject: ARM: davinci_all_defconfig: enable CMA options Enable the CMA and DMA_CMA Kconfig options by default for Davinci platforms. Davinci remoteproc driver is one of the modules that depends on these options, and this allows the driver to be made visible for selection with menuconfig. Signed-off-by: Suman Anna Signed-off-by: Sekhar Nori --- arch/arm/configs/davinci_all_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 4d432cf1ee79..bd0cf22f9ceb 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -34,6 +34,7 @@ CONFIG_DAVINCI_MUX_WARNINGS=y CONFIG_DAVINCI_RESET_CLOCKS=y CONFIG_PREEMPT=y CONFIG_AEABI=y +CONFIG_CMA=y CONFIG_SECCOMP=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 @@ -56,6 +57,7 @@ CONFIG_NETFILTER=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FW_LOADER is not set +CONFIG_DMA_CMA=y CONFIG_DA8XX_MSTPRI=y CONFIG_MTD=m CONFIG_MTD_TESTS=m -- cgit v1.2.3 From 3f8dc9478738e2ae8cbf3ccd11914df2cd286321 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 16 Sep 2017 21:46:26 -0300 Subject: ARM: imx_v6_v7_defconfig: Select CONFIG_MUX_MMIO In order to get ADV7180 analog video decoder to probe on a Gateworks GW51xx we need select CONFIG_MUX_MMIO, otherwise /dev/media node does not get created. Select CONFIG_MUX_MMIO, so that the ADV7180 driver can be correctly probed. Reported-by: Tim Harvey Suggested-by: Steve Longerbeam Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 32acac9ab81a..addac53e9c54 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -365,6 +365,7 @@ CONFIG_PWM=y CONFIG_PWM_FSL_FTM=y CONFIG_PWM_IMX=y CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_MUX_MMIO=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y -- cgit v1.2.3 From b69116cd96ec641168ced9460675360fa6df84c8 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 22 Aug 2017 13:23:20 +0800 Subject: dt-bindings: add compatible string for Allwinner V3s SoC The compatible string for Allwinner V3s SoC used to be missing. Add it to the binding document. Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC") Acked-by: Rob Herring Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index d2c46449b4eb..f35c6ada5a65 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -14,6 +14,7 @@ using one of the following compatible strings: allwinner,sun8i-a83t allwinner,sun8i-h2-plus allwinner,sun8i-h3 + allwinner,sun8i-v3s allwinner,sun9i-a80 allwinner,sun50i-a64 nextthing,gr8 -- cgit v1.2.3 From 9e8dda2df7cc209d0165618e6d18b324c02c8348 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 22 Aug 2017 13:23:21 +0800 Subject: ARM: sunxi: fix the core number of V3s in sunxi README The Allwinner V3s SoC is not quad-core, but single-core. Fix this in the README file. Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC") Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- Documentation/arm/sunxi/README | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README index d7b1f016bd62..de791e18ccef 100644 --- a/Documentation/arm/sunxi/README +++ b/Documentation/arm/sunxi/README @@ -33,6 +33,11 @@ SunXi family - Next Thing Co GR8 (sun5i) + * Single ARM Cortex-A7 based SoCs + - Allwinner V3s (sun8i) + + Datasheet + http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf + * Dual ARM Cortex-A7 based SoCs - Allwinner A20 (sun7i) + User Manual @@ -71,10 +76,6 @@ SunXi family + Datasheet http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf - - Allwinner V3s (sun8i) - + Datasheet - http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf - * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs - Allwinner A80 + Datasheet -- cgit v1.2.3 From 14e25a03682f7ca0464ac7e3f3f10f02d885fed4 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 22 Aug 2017 13:23:22 +0800 Subject: ARM: sunxi: add support for R40 SoC Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals like A20. Add support for it. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- Documentation/arm/sunxi/README | 6 ++++++ Documentation/devicetree/bindings/arm/sunxi.txt | 1 + arch/arm/mach-sunxi/sunxi.c | 1 + 3 files changed, 8 insertions(+) diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README index de791e18ccef..f8efc21998bf 100644 --- a/Documentation/arm/sunxi/README +++ b/Documentation/arm/sunxi/README @@ -76,6 +76,12 @@ SunXi family + Datasheet http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf + - Allwinner R40 (sun8i) + + Datasheet + https://github.com/tinalinux/docs/raw/r40-v1.y/R40_Datasheet_V1.0.pdf + + User Manual + https://github.com/tinalinux/docs/raw/r40-v1.y/Allwinner_R40_User_Manual_V1.0.pdf + * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs - Allwinner A80 + Datasheet diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index f35c6ada5a65..e4beec3d9ad3 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -14,6 +14,7 @@ using one of the following compatible strings: allwinner,sun8i-a83t allwinner,sun8i-h2-plus allwinner,sun8i-h3 + allwinner-sun8i-r40 allwinner,sun8i-v3s allwinner,sun9i-a80 allwinner,sun50i-a64 diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 7ab353fb25f2..5e9602ce1573 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -65,6 +65,7 @@ static const char * const sun8i_board_dt_compat[] = { "allwinner,sun8i-a83t", "allwinner,sun8i-h2-plus", "allwinner,sun8i-h3", + "allwinner,sun8i-r40", "allwinner,sun8i-v3s", NULL, }; -- cgit v1.2.3 From bb58b29899ff9c6d1e97727ec05b500e832ebd7d Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Sep 2017 00:36:25 +0300 Subject: arm64: defconfig: enable R8A77970 SoC Enable the Renesas R-Car V3M (R8A77970) SoC in the ARM64 defconfig. Suggested-by: Simon Horman Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 1eb054469927..cb5b37fe1e14 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -51,6 +51,7 @@ CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_R8A7795=y CONFIG_ARCH_R8A7796=y +CONFIG_ARCH_R8A77970=y CONFIG_ARCH_R8A77995=y CONFIG_ARCH_STRATIX10=y CONFIG_ARCH_TEGRA=y -- cgit v1.2.3 From 1d66af81905a4e2f3d03913f5449a8e9b5d3facd Mon Sep 17 00:00:00 2001 From: Danilo Krummrich Date: Fri, 9 Jun 2017 00:29:00 +0200 Subject: clk: bcm2835: remove remains from stub clk driver This commit removes the fixed clocks introduced as a stub clock driver added with commit 75fabc3f6448 ("ARM: bcm2835: add stub clock driver"). Originally they were used to drive the AMBA bus and PL011 uart driver. Now these clocks are derived by the CPRMAN clock driver and configured in DT. Additionally, get rid of init_machine function in bcm2835 board file as there's nothing to do any longer. Signed-off-by: Danilo Krummrich Acked-by: Eric Anholt Acked-by: Stephen Boyd Signed-off-by: Stefan Wahren --- arch/arm/mach-bcm/board_bcm2835.c | 7 ------- drivers/clk/bcm/clk-bcm2835-aux.c | 1 - drivers/clk/bcm/clk-bcm2835.c | 30 ------------------------------ include/linux/clk/bcm2835.h | 24 ------------------------ 4 files changed, 62 deletions(-) delete mode 100644 include/linux/clk/bcm2835.h diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-bcm/board_bcm2835.c index 0c1edfc98696..24af33f91705 100644 --- a/arch/arm/mach-bcm/board_bcm2835.c +++ b/arch/arm/mach-bcm/board_bcm2835.c @@ -15,16 +15,10 @@ #include #include #include -#include #include #include -static void __init bcm2835_init(void) -{ - bcm2835_init_clocks(); -} - static const char * const bcm2835_compat[] = { #ifdef CONFIG_ARCH_MULTI_V6 "brcm,bcm2835", @@ -36,6 +30,5 @@ static const char * const bcm2835_compat[] = { }; DT_MACHINE_START(BCM2835, "BCM2835") - .init_machine = bcm2835_init, .dt_compat = bcm2835_compat MACHINE_END diff --git a/drivers/clk/bcm/clk-bcm2835-aux.c b/drivers/clk/bcm/clk-bcm2835-aux.c index bd750cf2238d..77e276d61702 100644 --- a/drivers/clk/bcm/clk-bcm2835-aux.c +++ b/drivers/clk/bcm/clk-bcm2835-aux.c @@ -14,7 +14,6 @@ #include #include -#include #include #include #include diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 58ce6af8452d..44301a3d9963 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -37,7 +37,6 @@ #include #include #include -#include #include #include #include @@ -416,35 +415,6 @@ static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, return regdump ? 0 : -ENOMEM; } -/* - * These are fixed clocks. They're probably not all root clocks and it may - * be possible to turn them on and off but until this is mapped out better - * it's the only way they can be used. - */ -void __init bcm2835_init_clocks(void) -{ - struct clk_hw *hw; - int ret; - - hw = clk_hw_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 126000000); - if (IS_ERR(hw)) - pr_err("apb_pclk not registered\n"); - - hw = clk_hw_register_fixed_rate(NULL, "uart0_pclk", NULL, 0, 3000000); - if (IS_ERR(hw)) - pr_err("uart0_pclk not registered\n"); - ret = clk_hw_register_clkdev(hw, NULL, "20201000.uart"); - if (ret) - pr_err("uart0_pclk alias not registered\n"); - - hw = clk_hw_register_fixed_rate(NULL, "uart1_pclk", NULL, 0, 125000000); - if (IS_ERR(hw)) - pr_err("uart1_pclk not registered\n"); - ret = clk_hw_register_clkdev(hw, NULL, "20215000.uart"); - if (ret) - pr_err("uart1_pclk alias not registered\n"); -} - struct bcm2835_pll_data { const char *name; u32 cm_ctrl_reg; diff --git a/include/linux/clk/bcm2835.h b/include/linux/clk/bcm2835.h deleted file mode 100644 index aa937f6c17da..000000000000 --- a/include/linux/clk/bcm2835.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2010 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __LINUX_CLK_BCM2835_H_ -#define __LINUX_CLK_BCM2835_H_ - -void __init bcm2835_init_clocks(void); - -#endif -- cgit v1.2.3 From 88bbe85dcd37aa2662c1a83962c15009fc12503e Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 6 Aug 2017 17:52:02 +0200 Subject: irqchip: bcm2836: Move SMP startup code to arch/arm (v2) In order to easily provide SMP for BCM2837 on 32-bit and 64-bit the SMP startup code was placed in irq-bcm2836. That's not the right approach. So move this code where it belongs. Signed-off-by: Stefan Wahren Fixes: 41f4988cc287 ("irqchip/bcm2836: Add SMP support for the 2836") Tested-by: Eric Anholt Acked-by: Marc Zyngier --- arch/arm/mach-bcm/Makefile | 5 +++ arch/arm/mach-bcm/board_bcm2835.c | 6 ++- arch/arm/mach-bcm/platsmp.c | 35 ++++++++++++++++ arch/arm/mach-bcm/platsmp.h | 10 +++++ drivers/irqchip/irq-bcm2836.c | 79 +------------------------------------ include/linux/irqchip/irq-bcm2836.h | 70 ++++++++++++++++++++++++++++++++ 6 files changed, 127 insertions(+), 78 deletions(-) create mode 100644 arch/arm/mach-bcm/platsmp.h create mode 100644 include/linux/irqchip/irq-bcm2836.h diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index 980f5850097c..62a59008c5a8 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -43,6 +43,11 @@ endif # BCM2835 obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o +ifeq ($(CONFIG_ARCH_BCM2835),y) +ifeq ($(CONFIG_ARM),y) +obj-$(CONFIG_SMP) += platsmp.o +endif +endif # BCM5301X obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-bcm/board_bcm2835.c index 24af33f91705..8cff865ace04 100644 --- a/arch/arm/mach-bcm/board_bcm2835.c +++ b/arch/arm/mach-bcm/board_bcm2835.c @@ -19,16 +19,20 @@ #include #include +#include "platsmp.h" + static const char * const bcm2835_compat[] = { #ifdef CONFIG_ARCH_MULTI_V6 "brcm,bcm2835", #endif #ifdef CONFIG_ARCH_MULTI_V7 "brcm,bcm2836", + "brcm,bcm2837", #endif NULL }; DT_MACHINE_START(BCM2835, "BCM2835") - .dt_compat = bcm2835_compat + .dt_compat = bcm2835_compat, + .smp = smp_ops(bcm2836_smp_ops), MACHINE_END diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c index 9e3f275934eb..34506a608fea 100644 --- a/arch/arm/mach-bcm/platsmp.c +++ b/arch/arm/mach-bcm/platsmp.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -287,6 +288,35 @@ out: return ret; } +static int bcm2836_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + void __iomem *intc_base; + struct device_node *dn; + char *name; + + name = "brcm,bcm2836-l1-intc"; + dn = of_find_compatible_node(NULL, NULL, name); + if (!dn) { + pr_err("unable to find intc node\n"); + return -ENODEV; + } + + intc_base = of_iomap(dn, 0); + of_node_put(dn); + + if (!intc_base) { + pr_err("unable to remap intc base register\n"); + return -ENOMEM; + } + + writel(virt_to_phys(secondary_startup), + intc_base + LOCAL_MAILBOX3_SET0 + 16 * cpu); + + iounmap(intc_base); + + return 0; +} + static const struct smp_operations kona_smp_ops __initconst = { .smp_prepare_cpus = bcm_smp_prepare_cpus, .smp_boot_secondary = kona_boot_secondary, @@ -305,3 +335,8 @@ static const struct smp_operations nsp_smp_ops __initconst = { .smp_boot_secondary = nsp_boot_secondary, }; CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops); + +const struct smp_operations bcm2836_smp_ops __initconst = { + .smp_boot_secondary = bcm2836_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(bcm_smp_bcm2836, "brcm,bcm2836-smp", &bcm2836_smp_ops); diff --git a/arch/arm/mach-bcm/platsmp.h b/arch/arm/mach-bcm/platsmp.h new file mode 100644 index 000000000000..b8b8b3fa350d --- /dev/null +++ b/arch/arm/mach-bcm/platsmp.h @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2017 Stefan Wahren + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + */ + +extern const struct smp_operations bcm2836_smp_ops; diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c index dc8c1e3eafe7..667b9e14b032 100644 --- a/drivers/irqchip/irq-bcm2836.c +++ b/drivers/irqchip/irq-bcm2836.c @@ -19,62 +19,9 @@ #include #include #include -#include - -#define LOCAL_CONTROL 0x000 -#define LOCAL_PRESCALER 0x008 +#include -/* - * The low 2 bits identify the CPU that the GPU IRQ goes to, and the - * next 2 bits identify the CPU that the GPU FIQ goes to. - */ -#define LOCAL_GPU_ROUTING 0x00c -/* When setting bits 0-3, enables PMU interrupts on that CPU. */ -#define LOCAL_PM_ROUTING_SET 0x010 -/* When setting bits 0-3, disables PMU interrupts on that CPU. */ -#define LOCAL_PM_ROUTING_CLR 0x014 -/* - * The low 4 bits of this are the CPU's timer IRQ enables, and the - * next 4 bits are the CPU's timer FIQ enables (which override the IRQ - * bits). - */ -#define LOCAL_TIMER_INT_CONTROL0 0x040 -/* - * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and - * the next 4 bits are the CPU's per-mailbox FIQ enables (which - * override the IRQ bits). - */ -#define LOCAL_MAILBOX_INT_CONTROL0 0x050 -/* - * The CPU's interrupt status register. Bits are defined by the the - * LOCAL_IRQ_* bits below. - */ -#define LOCAL_IRQ_PENDING0 0x060 -/* Same status bits as above, but for FIQ. */ -#define LOCAL_FIQ_PENDING0 0x070 -/* - * Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and - * these bits are organized by mailbox number and then CPU number. We - * use mailbox 0 for IPIs. The mailbox's interrupt is raised while - * any bit is set. - */ -#define LOCAL_MAILBOX0_SET0 0x080 -#define LOCAL_MAILBOX3_SET0 0x08c -/* Mailbox write-to-clear bits. */ -#define LOCAL_MAILBOX0_CLR0 0x0c0 -#define LOCAL_MAILBOX3_CLR0 0x0cc - -#define LOCAL_IRQ_CNTPSIRQ 0 -#define LOCAL_IRQ_CNTPNSIRQ 1 -#define LOCAL_IRQ_CNTHPIRQ 2 -#define LOCAL_IRQ_CNTVIRQ 3 -#define LOCAL_IRQ_MAILBOX0 4 -#define LOCAL_IRQ_MAILBOX1 5 -#define LOCAL_IRQ_MAILBOX2 6 -#define LOCAL_IRQ_MAILBOX3 7 -#define LOCAL_IRQ_GPU_FAST 8 -#define LOCAL_IRQ_PMU_FAST 9 -#define LAST_IRQ LOCAL_IRQ_PMU_FAST +#include struct bcm2836_arm_irqchip_intc { struct irq_domain *domain; @@ -215,24 +162,6 @@ static int bcm2836_cpu_dying(unsigned int cpu) cpu); return 0; } - -#ifdef CONFIG_ARM -static int __init bcm2836_smp_boot_secondary(unsigned int cpu, - struct task_struct *idle) -{ - unsigned long secondary_startup_phys = - (unsigned long)virt_to_phys((void *)secondary_startup); - - writel(secondary_startup_phys, - intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu); - - return 0; -} - -static const struct smp_operations bcm2836_smp_ops __initconst = { - .smp_boot_secondary = bcm2836_smp_boot_secondary, -}; -#endif #endif static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = { @@ -249,10 +178,6 @@ bcm2836_arm_irqchip_smp_init(void) bcm2836_cpu_dying); set_smp_cross_call(bcm2836_arm_irqchip_send_ipi); - -#ifdef CONFIG_ARM - smp_set_ops(&bcm2836_smp_ops); -#endif #endif } diff --git a/include/linux/irqchip/irq-bcm2836.h b/include/linux/irqchip/irq-bcm2836.h new file mode 100644 index 000000000000..218a6e1b18d8 --- /dev/null +++ b/include/linux/irqchip/irq-bcm2836.h @@ -0,0 +1,70 @@ +/* + * Root interrupt controller for the BCM2836 (Raspberry Pi 2). + * + * Copyright 2015 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define LOCAL_CONTROL 0x000 +#define LOCAL_PRESCALER 0x008 + +/* + * The low 2 bits identify the CPU that the GPU IRQ goes to, and the + * next 2 bits identify the CPU that the GPU FIQ goes to. + */ +#define LOCAL_GPU_ROUTING 0x00c +/* When setting bits 0-3, enables PMU interrupts on that CPU. */ +#define LOCAL_PM_ROUTING_SET 0x010 +/* When setting bits 0-3, disables PMU interrupts on that CPU. */ +#define LOCAL_PM_ROUTING_CLR 0x014 +/* + * The low 4 bits of this are the CPU's timer IRQ enables, and the + * next 4 bits are the CPU's timer FIQ enables (which override the IRQ + * bits). + */ +#define LOCAL_TIMER_INT_CONTROL0 0x040 +/* + * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and + * the next 4 bits are the CPU's per-mailbox FIQ enables (which + * override the IRQ bits). + */ +#define LOCAL_MAILBOX_INT_CONTROL0 0x050 +/* + * The CPU's interrupt status register. Bits are defined by the the + * LOCAL_IRQ_* bits below. + */ +#define LOCAL_IRQ_PENDING0 0x060 +/* Same status bits as above, but for FIQ. */ +#define LOCAL_FIQ_PENDING0 0x070 +/* + * Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and + * these bits are organized by mailbox number and then CPU number. We + * use mailbox 0 for IPIs. The mailbox's interrupt is raised while + * any bit is set. + */ +#define LOCAL_MAILBOX0_SET0 0x080 +#define LOCAL_MAILBOX3_SET0 0x08c +/* Mailbox write-to-clear bits. */ +#define LOCAL_MAILBOX0_CLR0 0x0c0 +#define LOCAL_MAILBOX3_CLR0 0x0cc + +#define LOCAL_IRQ_CNTPSIRQ 0 +#define LOCAL_IRQ_CNTPNSIRQ 1 +#define LOCAL_IRQ_CNTHPIRQ 2 +#define LOCAL_IRQ_CNTVIRQ 3 +#define LOCAL_IRQ_MAILBOX0 4 +#define LOCAL_IRQ_MAILBOX1 5 +#define LOCAL_IRQ_MAILBOX2 6 +#define LOCAL_IRQ_MAILBOX3 7 +#define LOCAL_IRQ_GPU_FAST 8 +#define LOCAL_IRQ_PMU_FAST 9 +#define LAST_IRQ LOCAL_IRQ_PMU_FAST -- cgit v1.2.3 From 968f76417df671338ea3a1fd33b2c93a048cc1b1 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 8 Aug 2017 12:04:55 +0100 Subject: ARM: bcm2836: Send event when onlining other cores Secondary cores should enter a low-power idle state when waiting to be started. The "wfe" instruction causes a core to wait until an event or interrupt arrives before continuing to the next instruction, and the "sev" instruction sends a wakeup event to the other cores. Add an "sev" (and a memory barrier) to bcm2836_boot_secondary, the function that wakes the waiting cores during booting. This is required if the secondary cores are sitting in "wfe", and harmless if not. Signed-off-by: Phil Elwell Signed-off-by: Eric Anholt Reviewed-by: Eric Anholt --- arch/arm/mach-bcm/platsmp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c index 34506a608fea..7d954830eb57 100644 --- a/arch/arm/mach-bcm/platsmp.c +++ b/arch/arm/mach-bcm/platsmp.c @@ -312,6 +312,9 @@ static int bcm2836_boot_secondary(unsigned int cpu, struct task_struct *idle) writel(virt_to_phys(secondary_startup), intc_base + LOCAL_MAILBOX3_SET0 + 16 * cpu); + dsb(sy); + sev(); + iounmap(intc_base); return 0; -- cgit v1.2.3 From c14963521502b237a6817aceda6f3379296db75c Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 29 Aug 2017 11:03:39 -0700 Subject: ARM: brcmstb: Add appropriate ARM_BE8() macros for swapping Building a big-endian kernel for ARCH_BRCMSTB revealed that we would not be correctly polling for the right bit in the busyuart macro, turns out there are a few transformations needed to work with big-endian kernels. First we need to swap the value we read from SUN_TOP_CTRL to properly compare it against our local tables. Then, just like 8250.S we need to swap the value before storing it, and conversely swap it after a load. Signed-off-by: Florian Fainelli --- arch/arm/include/debug/brcmstb.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S index 52aaed2b936f..c826f15d2f80 100644 --- a/arch/arm/include/debug/brcmstb.S +++ b/arch/arm/include/debug/brcmstb.S @@ -58,6 +58,7 @@ /* Check SUN_TOP_CTRL base */ ldr \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA ldr \rv, [\rp, #0] @ get register contents +ARM_BE8( rev \rv, \rv ) and \rv, \rv, #0xffffff00 @ strip revision bits [7:0] /* Chip specific detection starts here */ @@ -98,11 +99,13 @@ .endm .macro store, rd, rx:vararg +ARM_BE8( rev \rd, \rd ) str \rd, \rx .endm .macro load, rd, rx:vararg ldr \rd, \rx +ARM_BE8( rev \rd, \rd ) .endm .macro senduart,rd,rx -- cgit v1.2.3 From 5fe74e0a72474eb48fa8abe1eb49dedb16b2537b Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 27 Sep 2017 17:58:22 +0200 Subject: arm64: defconfig: enable NAND on Armada 7K/8K SoCs The PXA3xx NAND driver supports also the NAND controller found on the Armada 7K/8K SoCs, so enable it. Signed-off-by: Gregory CLEMENT --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8495b88a0966..c7fda967719b 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -156,6 +156,7 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_PXA3xx=y CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m -- cgit v1.2.3 From 70f8e9cc2362bbbd9ba482dcfa2245bd18c700ba Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 10 Jan 2017 13:43:37 +0100 Subject: ARM: integrator: Delete the V3 PCI driver Before adding a proper PCI driver in drivers/pci/host, clean out the cruft by deleting the old driver from the machine. Signed-off-by: Linus Walleij --- arch/arm/mach-integrator/Makefile | 2 - arch/arm/mach-integrator/integrator_ap.c | 2 - arch/arm/mach-integrator/pci_v3.c | 900 ------------------------------- arch/arm/mach-integrator/pci_v3.h | 9 - 4 files changed, 913 deletions(-) delete mode 100644 arch/arm/mach-integrator/pci_v3.c delete mode 100644 arch/arm/mach-integrator/pci_v3.h diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile index 1ebe45356b09..99b63946b61e 100644 --- a/arch/arm/mach-integrator/Makefile +++ b/arch/arm/mach-integrator/Makefile @@ -7,6 +7,4 @@ obj-y := core.o lm.o obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o - -obj-$(CONFIG_PCI) += pci_v3.o obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index a1af634f8709..8efe484fac13 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -36,7 +36,6 @@ #include "hardware.h" #include "cm.h" #include "common.h" -#include "pci_v3.h" #include "lm.h" /* Regmap to the AP system controller */ @@ -74,7 +73,6 @@ static struct map_desc ap_io_desc[] __initdata __maybe_unused = { static void __init ap_map_io(void) { iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); - pci_v3_early_init(); } #ifdef CONFIG_PM diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c deleted file mode 100644 index 2565f0e7b5cf..000000000000 --- a/arch/arm/mach-integrator/pci_v3.c +++ /dev/null @@ -1,900 +0,0 @@ -/* - * linux/arch/arm/mach-integrator/pci_v3.c - * - * PCI functions for V3 host PCI bridge - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2000-2001 Deep Blue Solutions Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include