From 0526efb53fc541ddc00bac2e5285f1459335d788 Mon Sep 17 00:00:00 2001 From: Ji Sheng Teoh Date: Wed, 24 Jan 2024 16:59:59 +0800 Subject: riscv: dts: starfive: dubhe: Add zihintpause isa-extension Add zihintpause isa-extension which is supported in Dubhe-80 and Dubhe-90 Signed-off-by: Ji Sheng Teoh --- arch/riscv/boot/dts/starfive/dubhe.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/dubhe.dtsi b/arch/riscv/boot/dts/starfive/dubhe.dtsi index d87f7ac08ea5..1eba9acfd644 100755 --- a/arch/riscv/boot/dts/starfive/dubhe.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe.dtsi @@ -20,7 +20,7 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", "zbc", "zbs", "zicntr", "zicsr", "zifencei", - "zihpm", "sscofpmf"; + "zihintpause", "zihpm", "sscofpmf"; tlb-split; cpu0_intc: interrupt-controller { @@ -39,7 +39,7 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", "zbc", "zbs", "zicntr", "zicsr", "zifencei", - "zihpm", "sscofpmf"; + "zihintpause", "zihpm", "sscofpmf"; tlb-split; cpu1_intc: interrupt-controller { -- cgit v1.2.3