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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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tools
/
testing
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cxl
Age
Commit message (
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Author
Files
Lines
2022-07-25
cxl/hdm: Commit decoder state to hardware
Dan Williams
1
-0
/
+46
2022-07-22
cxl/region: Add region creation support
Ben Widawsky
1
-0
/
+1
2022-07-21
cxl/core: Define a 'struct cxl_endpoint_decoder'
Dan Williams
1
-3
/
+7
2022-07-21
cxl/core: Define a 'struct cxl_switch_decoder'
Dan Williams
1
-7
/
+16
2022-07-10
tools/testing/cxl: Fix decoder default state
Dan Williams
1
-1
/
+0
2022-07-10
tools/testing/cxl: Add partition support
Dan Williams
2
-63
/
+28
2022-07-10
tools/testing/cxl: Expand CFMWS windows
Dan Williams
1
-5
/
+5
2022-07-10
tools/testing/cxl: Move cxl_test resources to the top of memory
Dan Williams
1
-1
/
+2
2022-07-10
cxl/mem: Convert partition-info to resources
Dan Williams
1
-1
/
+1
2022-07-10
cxl/core: Rename ->decoder_range ->hpa_range
Dan Williams
1
-1
/
+1
2022-06-29
tools/testing/cxl: Fix cxl_hdm_decode_init() calling convention
Dan Williams
1
-3
/
+5
2022-05-19
cxl/port: Reuse 'struct cxl_hdm' context for hdm init
Dan Williams
1
-2
/
+3
2022-05-19
cxl/pci: Drop @info argument to cxl_hdm_decode_init()
Dan Williams
1
-6
/
+3
2022-05-19
cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()
Dan Williams
3
-16
/
+5
2022-05-19
cxl/mem: Consolidate CXL DVSEC Range enumeration in the core
Dan Williams
3
-10
/
+17
2022-05-19
cxl/pci: Move cxl_await_media_ready() to the core
Dan Williams
3
-7
/
+16
2022-04-13
cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init()
Dan Williams
1
-1
/
+1
2022-02-09
tools/testing/cxl: Add a physical_node link
Dan Williams
1
-2
/
+19
2022-02-09
tools/testing/cxl: Enumerate mock decoders
Dan Williams
1
-20
/
+98
2022-02-09
tools/testing/cxl: Mock one level of switches
Dan Williams
1
-41
/
+97
2022-02-09
tools/testing/cxl: Fix root port to host bridge assignment
Dan Williams
1
-1
/
+1
2022-02-09
tools/testing/cxl: Mock dvsec_ranges()
Dan Williams
1
-0
/
+10
2022-02-09
cxl/mem: Add the cxl_mem driver
Ben Widawsky
2
-0
/
+16
2022-02-09
cxl/memdev: Add numa_node attribute
Dan Williams
1
-0
/
+1
2022-02-09
cxl/pci: Emit device serial number
Dan Williams
1
-0
/
+1
2022-02-09
cxl/pci: Implement wait for media active
Ben Widawsky
1
-0
/
+8
2022-02-09
cxl/core/port: Remove @host argument for dport + decoder enumeration
Dan Williams
3
-30
/
+21
2022-02-09
cxl/port: Add a driver for 'struct cxl_port' objects
Ben Widawsky
2
-2
/
+5
2022-02-09
cxl/core/hdm: Add CXL standard decoder enumeration to the core
Dan Williams
4
-0
/
+86
2022-02-09
cxl/core: Generalize dport enumeration in the core
Dan Williams
5
-128
/
+71
2022-02-09
cxl/port: Up-level cxl_add_dport() locking requirements to the caller
Dan Williams
1
-0
/
+4
2022-02-09
cxl/pmem: Introduce a find_cxl_root() helper
Dan Williams
2
-26
/
+0
2022-02-09
cxl/core/port: Rename bus.c to port.c
Dan Williams
1
-1
/
+1
2021-11-15
cxl/test: Mock acpi_table_parse_cedt()
Dan Williams
4
-48
/
+59
2021-11-15
tools/testing/cxl: add mock output for the GET_HEALTH_INFO command
Vishal Verma
1
-0
/
+49
2021-11-15
cxl/memdev: Change cxl_mem to a more descriptive name
Ira Weiny
1
-25
/
+25
2021-09-22
tools/testing/cxl: Introduce a mock memory device + driver
Dan Williams
5
-1
/
+354
2021-09-21
tools/testing/cxl: Introduce a mocked-up CXL port hierarchy
Dan Williams
7
-0
/
+871