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Currently both the oscillator and the PLL are powered up in
set_bias_level. This can be problematic when using output clocks from
the wm8804 for other devices. The snd_soc_codec_set_pll API defines that
a clock should be available once the call returns, however, with all the
clocking controlled in set_bias_level this is not currently the case.
This patch enables pm_runtime for the wm8804, enabling both the
regulators and the oscillator when the chip resumes, and enabling the
PLL in the snd_soc_codec_set_pll call. Naturally the enabling the PLL
will also cause the chip to resume.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Simplify dependencies by using new style split out bus interfaces.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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WM8804 can run with PLL frequencies of 256xfs and 128xfs for
most sample rates. At 192kHz only 128xfs is supported. The
existing driver selects 128xfs automatically for some lower
samples rates. By using an additional mclk_div divider, it
is now possible to control the behaviour. This allows using
256xfs PLL frequency on all sample rates up to 96kHz. It
should allow lower jitter and better signal quality. The
behavior has to be controlled by the sound card driver,
because some sample frequency share the same setting. e.g.
192kHz and 96kHz use 24.576MHz master clock. The only
difference is the MCLK divider.
Signed-off-by: Daniel Matuschek <daniel@matuschek.net>
Tested-by: Florian Meier <florian.meier@koalo.de>
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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The WM8804 is a high performance consumer mode S/PDIF transceiver with
support for 1 received channel and 1 transmitted channel.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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