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2021-04-07clk: divider: add devm_clk_hw_register_dividerDmitry Baryshkov1-0/+17
Add devm_clk_hw_register_divider() - devres version of clk_hw_register_divider(). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210331105735.3690009-3-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-04-07clk: mux: provide devm_clk_hw_register_mux()Dmitry Baryshkov1-0/+13
Add devm_clk_hw_register_mux() - devres-managed version of clk_hw_register_mux(). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210331105735.3690009-2-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-04-07drm/msm: Add param for userspace to query suspend countRob Clark1-0/+1
Performance counts, and ALWAYS_ON counters used for capturing GPU timestamps, lose their state across suspend/resume cycles. Userspace tooling for performance monitoring needs to be aware of this. For example, after a suspend userspace needs to recalibrate it's offset between CPU and GPU time. Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Jordan Crouse <jordan@cosmicpenguin.net> Link: https://lore.kernel.org/r/20210325012358.1759770-3-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-04-07cpuidle: Use s64 as exit_latency_ns and target_residency_ns data typeRafael J. Wysocki1-2/+2
Subsequent changes will cause the exit_latency_ns and target_residency_ns fields in struct cpuidle_state to be used in computations in which data type conversions to u64 may turn a negative number close to zero into a verly large positive number leading to incorrect results. In preparation for that, change the data type of the fields mentioned above to s64, but ensure that they will not be negative themselves. No intentional functional impact. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07PM: core: Remove duplicate declaration from header fileWan Jiabing1-1/+0
struct device is declared twice, so remove the duplicate. Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: Update version to 20210331Bob Moore1-1/+1
ACPICA commit eb423b7d5440472d0d2115cb81b52b1b7c56d95a Link: https://github.com/acpica/acpica/commit/eb423b7d Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: IORT: Updates for revision E.bShameer Kolothum1-6/+20
ACPICA commit 8710a708faed728ea2672b8da842b2e9af1cf5bd IORT revision E.b (ARM DEN 0049E.b) contains a few additions like, -Added an identifier field in the node descriptors to aid table cross-referencing. -Introduced the Reserved Memory Range(RMR) node. This is used to describe memory ranges that are used by endpoints and require a unity mapping in SMMU. -Introduced a flag in the RC node to express support for PRI. -Added a flag in the RC node to declare support for PASID forward information. Please note that IORT Rev E and E.a have known issues and are not supported. Link: https://github.com/acpica/acpica/commit/8710a708 Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: acpisrc: Add missing conversion for VIOT supportJean-Philippe Brucker1-4/+4
ACPICA commit 856a96fdf4b51b2b8da17529df0255e6f51f1b5b struct acpi_viot_header is missing from identifier table, causing linuxize failures. Link: https://github.com/acpica/acpica/commit/856a96fd Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: iASL: Decode subtable type field for VIOTBob Moore1-0/+1
For the table disassembler, decode the subtable type field to a descriptive string. ACPICA commit 2197e354fb5dcafaddd2016ffeb0620e5bc3d5e2 Link: https://github.com/acpica/acpica/commit/2197e354 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: iASL: Add support for CEDT tableBob Moore1-1/+2
Also, update the CEDT template. ACPICA commit 1e6dded267b13c4aa0c3e16de0fa89d3b9c880e9 Link: https://github.com/acpica/acpica/commit/1e6dded2 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: ACPI 6.4: add support for PHAT tableErik Kaneda1-0/+61
ACPICA commit de805b6a355c01f3aff4044a4ba60e9845b7668c This table displays health information about the platform firmware. For full definition, see the ACPI specification. Link: https://github.com/acpica/acpica/commit/de805b6a Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: ACPI 6.4: add CSI2Bus resource templateBob Moore1-1/+8
This commit the result of squashing the following: ACPICA commit 21a316fdaa46b3fb245a1920f3829cb05d6ced6e ACPICA commit f5506fc7dad08c2a25ef52cf836c2d67385a612c Link: https://github.com/acpica/acpica/commit/21a316fd Link: https://github.com/acpica/acpica/commit/f5506fc7 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: ACPI 6.4: PMTT: add new fields/structuresBob Moore1-18/+35
ACPICA commit 036290735ad8020f762c4d94bcbc0e84b2e307b6 Link: https://github.com/acpica/acpica/commit/03629073 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: CXL 2.0: CEDT: Add new CEDT tableBen Widawsky1-0/+43
ACPICA commit 0b03aa8ebd7a5b2b9407893f123ee587af45926f This sets up all of the boilerplate without actually doing anything. Link: https://github.com/acpica/acpica/commit/0b03aa8e Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: iASL: Add definitions for the VIOT tableJean-Philippe Brucker1-0/+66
ACPICA commit fc4e33319c1ee08f20f5c44853dd8426643f6dfd Add definitions for the VIOT table and its subtables. Link: https://github.com/acpica/acpica/commit/fc4e3331 Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: ACPI 6.4: add SDEV secure access componentsErik Kaneda1-0/+41
ACPICA commit 44ca5f4f9be24bf64524cdb1de46322509319056 This entails adding an optional subtable indicating secure access components as well as two different types of secure access components (ID-based or Memory). For definitons and uses, consult the ACPI specification. Link: https://github.com/acpica/acpica/commit/44ca5f4f Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: ACPI 6.4: Add new flags in SRATBob Moore1-1/+2
ACPICA commit 44633fa72f1e4ede718733aec16e7fb7572042f8 Link: https://github.com/acpica/acpica/commit/44633fa7 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: ACPI 6.4: HMAT: add new fields/flagsBob Moore1-3/+7
ACPICA commit 18a77ca6fc3edd26a24d8f32ae5c0ea66d84ccff Link: https://github.com/acpica/acpica/commit/18a77ca6 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: ACPI 6.4: NFIT: add Location Cookie fieldBob Moore1-0/+2
Also, update struct size to reflect these changes in nfit core driver. ACPICA commit af60199a9a1de9e6844929fd4cc22334522ed195 Link: https://github.com/acpica/acpica/commit/af60199a Cc: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: Tree-wide: fix various typos and spelling mistakesColin Ian King2-2/+2
This commit squashes the following: ACPICA commit bc8939e2d902653e71bb1601b129a993c37fcfad ACPICA commit 2d9e5e98e23f2a569e5691e6bed183146e25798d ACPICA commit 937358156631ea7a0eef3569c213c82a031097d5 Fix more spelling issues found using the codespell checker and found without tools. Link: https://github.com/acpica/acpica/commit/bc8939e2 Link: https://github.com/acpica/acpica/commit/2d9e5e98 Link: https://github.com/acpica/acpica/commit/93735815 Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: ACPI 6.4: PPTT: add new version of subtable type 1Erik Kaneda1-0/+7
This commit squashes the following: ACPICA commit 475c5e89f8f701ccdfee6ca567e33c854ecd6c9e ACPICA commit 82cf78ac175a4b7d8842c5b786be24031c817cfd This new subtable is only valid for PPTT version 3. Elyes fixed a misspelled identifier in this commit. Link: https://github.com/acpica/acpica/commit/475c5e89 Link: https://github.com/acpica/acpica/commit/82cf78ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: ACPI 6.4: PCCT: add support for subtable type 5Erik Kaneda1-1/+20
ACPICA commit 208d7e27ebc473feb4182cc8e58f3789c4efaca6 Link: https://github.com/acpica/acpica/commit/208d7e27 Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: ACPI 6.4: MADT: add Multiprocessor Wakeup StructureErik Kaneda1-1/+11
ACPICA commit b9eb6f3a19b816824d6f47a6bc86fd8ce690e04b Link: https://github.com/acpica/acpica/commit/b9eb6f3a Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: ACPI 6.4: add USB4 capabilities UUIDErik Kaneda1-0/+1
ACPICA commit 619e6df02edbebe95b2765cdd5159f02607e45fc This change allows iASL to a list of know UUID's. iASL uses this list to point out any UUID's that are not publically known. Link: https://github.com/acpica/acpica/commit/619e6df0 Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: Add parsing for IVRS IVHD 40h and device entry F0hAlexander Monakov1-1/+16
ACPICA commit eefb865355514048380d921de5efcf30027d6b02 IVHD type 40h uses the same field layout as type 11h, but adds support for a new device entry type F0h (ACPI HID device entry). The new device entry type has variable length: after fixed-length fields occupying 22 bytes, there's a field of length up to 255 (as given by the preceding field). Link: https://github.com/acpica/acpica/commit/eefb8653 Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07KVM: arm64: Add support for the KVM PTP serviceJianyong Wu2-0/+17
Implement the hypervisor side of the KVM PTP interface. The service offers wall time and cycle count from host to guest. The caller must specify whether they want the host's view of either the virtual or physical counter. Signed-off-by: Jianyong Wu <jianyong.wu@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20201209060932.212364-7-jianyong.wu@arm.com
2021-04-07clocksource: Add clocksource id for arm arch counterJianyong Wu1-0/+1
Add clocksource id to the ARM generic counter so that it can be easily identified from callers such as ptp_kvm. Cc: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jianyong Wu <jianyong.wu@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20201209060932.212364-6-jianyong.wu@arm.com
2021-04-07time: Add mechanism to recognize clocksource in time_get_snapshotThomas Gleixner3-5/+24
System time snapshots are not conveying information about the current clocksource which was used, but callers like the PTP KVM guest implementation have the requirement to evaluate the clocksource type to select the appropriate mechanism. Introduce a clocksource id field in struct clocksource which is by default set to CSID_GENERIC (0). Clocksource implementations can set that field to a value which allows to identify the clocksource. Store the clocksource id of the current clocksource in the system_time_snapshot so callers can evaluate which clocksource was used to take the snapshot and act accordingly. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jianyong Wu <jianyong.wu@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20201209060932.212364-5-jianyong.wu@arm.com
2021-04-07ptp: Reorganize ptp_kvm.c to make it arch-independentJianyong Wu1-0/+19
Currently, the ptp_kvm module contains a lot of x86-specific code. Let's move this code into a new arch-specific file in the same directory, and rename the arch-independent file to ptp_kvm_common.c. Acked-by: Richard Cochran <richardcochran@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jianyong Wu <jianyong.wu@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20201209060932.212364-4-jianyong.wu@arm.com
2021-04-07Merge tag 'ti-k3-dt-for-v5.13' of ↵Arnd Bergmann1-1/+4
git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt Devicetree changes for TI K3 platforms for v5.13 merge window: * New SoCs: - AM642 mean for industrial control, motor control, remote IO, IoT gateway etc. * New Boards: - AM65: Siemens SIMATIC IOT2050 advanced and basic boards - AM64: EVM and SK boards * New peripherals: - AM65: watchdog - AM65,J721E: ICSSG - J7200: OSPI, GPIO * Fixes: - AM65: pcie node fixup, ospi speed updates - J721e, J7200: MMC speed updates, ospi speed updates and compatibles fixups. * tag 'ti-k3-dt-for-v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (39 commits) arm64: dts: ti: k3-am64-main: Fix ospi compatible arm64: dts: ti: k3-j7200-mcu: Fix ospi compatible arm64: dts: ti: k3-j721e-mcu: Fix ospi compatible arm64: dts: ti: k3-j7200: Add support for higher speed modes and update delay select values for MMCSD subsystems arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio modules arm64: dts: ti: k3-j7200: Add gpio nodes arm64: dts: ti: k3-am642-evm/sk: Add IPC sub-mailbox nodes arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes arm64: dts: ti: k3-am64-main: Add hwspinlock node arm64: dts: ti: k3-am642: reserve gpio in mcu domain for firmware usage arm64: dts: ti: k3-am64: Add GPIO DT nodes arm64: dts: ti: k3-am64-evm/sk: Add OSPI flash DT node arm64: dts: ti: k3-am64-main: Add OSPI node arm64: dts: ti: k3-am64-main: Add ADC nodes arm64: dts: ti: k3-am642-evm: Add USB support arm64: dts: ti: k3-am64-main: Add DT node for USB subsystem arm64: dts: ti: Add support for Siemens IOT2050 boards dt-bindings: arm: ti: Add bindings for Siemens IOT2050 boards dt-bindings: Add Siemens vendor prefix arm64: dts: ti: k3-am642-evm: Add support for SPI EEPROM ... Link: https://lore.kernel.org/r/20210405155336.smohb7uzkperqwuz@reflex Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-07Merge tag 'phy-for-5.13' of ↵Greg Kroah-Hartman5-13/+72
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next Vinod writes: phy-for-5.13 - Updates: - Yaml conversion for mvebu-utmi binding, bcm-ns-usb2 and bcm-ns-usb3 bindings - Mediatek dsi and hdmi phy updates - TI j721e-wiz updates for AM64 - Cadence-torrent phy updates for SGMII/QSGMII - New support: - usb3-dp phy for Qualcomm SM8250 - UTMI phy for Armada CP110 - USB phy for Qualcomm SC7280 - Binding and driver for Sparx5 ethernet serdes * tag 'phy-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (75 commits) phy: fix resource_size.cocci warnings phy: Sparx5 Eth SerDes: Use direct register operations phy: hisilicon: Use the correct HiSilicon copyright phy: marvell: phy-mvebu-cp11i-utmi needs USB_COMMON phy: qcom-qmp: add support for sm8250-usb3-dp phy phy: qcom-qmp: rename common registers phy: qcom-qmp: move DP functions to callbacks dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SM8250 dt-bindings: phy: qcom,qmp-usb3-dp-phy: move usb3 compatibles back to qcom,qmp-phy.yaml phy: ti: j721e-wiz: Configure 'p_standard_mode' only for DP/QSGMII dt-bindings: phy: fix dt_binding_check warning in mediatek, ufs-phy.yaml phy: zynqmp: Handle the clock enable/disable properly dt-bindings: phy: bcm-ns-usb3-phy: convert to yaml dt-bindings: phy: bcm-ns-usb2-phy: convert to yaml phy: microchip: PHY_SPARX5_SERDES should depend on ARCH_SPARX5 phy: cadence-torrent: Add delay for PIPE clock to be stable phy: cadence-torrent: Explicitly request exclusive reset control phy: cadence-torrent: Do not configure SERDES if it's already configured phy: cadence-torrent: Group reset APIs and clock APIs phy: ti: j721e-wiz: Do not configure wiz if its already configured ...
2021-04-07Merge tag 'soundwire-5.13-rc1' of ↵Greg Kroah-Hartman1-1/+35
git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire into char-misc-next Vinod writes: soundwire updates for 5.13-rc1 Updates for v5.13-rc1 are: Core: - Ability to add quirks for masters - static checker cleanup for bus code Drivers: - DMI quirks for Intel controllers - static checker cleanup for drivers - add auto enumeration support qcom controller * tag 'soundwire-5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire: (45 commits) soundwire: intel_init: test link->cdns soundwire: qcom: handle return correctly in qcom_swrm_transport_params soundwire: qcom: cleanup internal port config indexing soundwire: qcom: wait for fifo space to be available before read/write soundwire: qcom: add static port map support soundwire: qcom: update port map allocation bit mask soundwire: add static port mapping support soundwire: stream: fix memory leak in stream config error path soundwire: qcom: use signed variable for error return soundwire: qcom: wait for enumeration to be complete in probe soundwire: qcom: add auto enumeration support soundwire: export sdw_compare_devid, sdw_extract_slave_id and sdw_slave_add soundwire: qcom: add support to new interrupts soundwire: qcom: update register read/write routine soundwire: qcom: start the clock during initialization soundwire: qcom: set continue execution flag for ignored commands soundwire: qcom: add support to missing transport params dt-bindings: soundwire: qcom: clarify data port bus parameters soundwire: cadence: only prepare attached devices on clock stop soundwire: generic_allocation: fix confusion between group and packing ...
2021-04-07irqdomain: Get rid of irq_create_identity_mapping()Marc Zyngier1-6/+0
The sole user of irq_create_identity_mapping() having been converted, get rid of the unused helper. Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-04-07HID: input: map battery capacity (00850065)John Chen1-0/+3
This is the capacity in percentage, relative to design capacity. Specifically, it is present in Apple Magic Mouse 2. In contrast, usage 00850064 is also the capacity in percentage, but is relative to full capacity. It is not mapped here because I don't have such device. Signed-off-by: John Chen <johnchen902@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2021-04-07iommu/vt-d: Invalidate PASID cache when root/context entry changedLu Baolu1-0/+1
When the Intel IOMMU is operating in the scalable mode, some information from the root and context table may be used to tag entries in the PASID cache. Software should invalidate the PASID-cache when changing root or context table entries. Suggested-by: Ashok Raj <ashok.raj@intel.com> Fixes: 7373a8cc38197 ("iommu/vt-d: Setup context and enable RID2PASID support") Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Link: https://lore.kernel.org/r/20210320025415.641201-4-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/amd: Move a few prototypes to include/linux/amd-iommu.hChristoph Hellwig1-0/+12
A few functions that were intentended for the perf events support are currently declared in arch/x86/events/amd/iommu.h, which mens they are not in scope for the actual function definition. Also amdkfd has started using a few of them using externs in a .c file. End that misery by moving the prototypes to the proper header. Signed-off-by: Christoph Hellwig <hch@lst.de> Link: https://lore.kernel.org/r/20210402143312.372386-5-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/amd: Remove the unused device errata codeChristoph Hellwig1-18/+0
The device errata mechism is entirely unused, so remove it. Signed-off-by: Christoph Hellwig <hch@lst.de> Link: https://lore.kernel.org/r/20210402143312.372386-2-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove iommu_domain_{get,set}_attrChristoph Hellwig1-36/+0
Remove the now unused iommu attr infrastructure. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20210401155256.298656-21-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove DOMAIN_ATTR_IO_PGTABLE_CFGChristoph Hellwig2-5/+11
Use an explicit set_pgtable_quirks method instead that just passes the actual quirk bitmask instead. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-20-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove DOMAIN_ATTR_DMA_USE_FLUSH_QUEUERobin Murphy1-1/+3
Instead make the global iommu_dma_strict paramete in iommu.c canonical by exporting helpers to get and set it and use those directly in the drivers. This make sure that the iommu.strict parameter also works for the AMD and Intel IOMMU drivers on x86. As those default to lazy flushing a new IOMMU_CMD_LINE_STRICT is used to turn the value into a tristate to represent the default if not overriden by an explicit parameter. [ported on top of the other iommu_attr changes and added a few small missing bits] Signed-off-by: Robin Murphy <robin.murphy@arm.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Link: https://lore.kernel.org/r/20210401155256.298656-19-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove DOMAIN_ATTR_NESTINGChristoph Hellwig1-1/+3
Use an explicit enable_nesting method instead. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-17-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove DOMAIN_ATTR_GEOMETRYChristoph Hellwig1-1/+0
The geometry information can be trivially queried from the iommu_domain struture. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-16-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove DOMAIN_ATTR_PAGINGChristoph Hellwig1-1/+0
DOMAIN_ATTR_PAGING is never used. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-15-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/fsl_pamu: enable the liodn when attaching a deviceChristoph Hellwig1-1/+0
Instead of a separate call to enable all devices from the list, just enable the liodn once the device is attached to the iommu domain. This also remove the DOMAIN_ATTR_FSL_PAMU_ENABLE iommu_attr. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-11-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/fsl_pamu: replace DOMAIN_ATTR_FSL_PAMU_STASH with a direct callChristoph Hellwig1-1/+0
Add a fsl_pamu_configure_l1_stash API that qman_portal can call directly instead of indirecting through the iommu attr API. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-8-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/fsl_pamu: remove ->domain_window_enableChristoph Hellwig1-17/+0
The only thing that fsl_pamu_window_enable does for the current caller is to fill in the prot value in the only dma_window structure, and to propagate a few values from the iommu_domain_geometry struture into the dma_window. Remove the dma_window entirely, hardcode the prot value and otherwise use the iommu_domain_geometry structure instead. Remove the now unused ->domain_window_enable iommu method. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-7-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/fsl_pamu: remove support for multiple windowsChristoph Hellwig1-1/+0
The only domains allocated forces use of a single window. Remove all the code related to multiple window support, as well as the need for qman_portal to force a single window. Remove the now unused DOMAIN_ATTR_WINDOWS iommu_attr. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-6-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/fsl_pamu: remove fsl_pamu_get_domain_attrChristoph Hellwig1-4/+0
None of the values returned by this function are ever queried. Also remove the DOMAIN_ATTR_FSL_PAMUV1 enum value that is not otherwise used. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-3-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove the unused domain_window_disable methodChristoph Hellwig1-2/+0
domain_window_disable is wired up by fsl_pamu, but never actually called. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-2-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: Add a page fault handlerJean-Philippe Brucker1-0/+2
Some systems allow devices to handle I/O Page Faults in the core mm. For example systems implementing the PCIe PRI extension or Arm SMMU stall model. Infrastructure for reporting these recoverable page faults was added to the IOMMU core by commit 0c830e6b3282 ("iommu: Introduce device fault report API"). Add a page fault handler for host SVA. IOMMU driver can now instantiate several fault workqueues and link them to IOPF-capable devices. Drivers can choose between a single global workqueue, one per IOMMU device, one per low-level fault queue, one per domain, etc. When it receives a fault event, most commonly in an IRQ handler, the IOMMU driver reports the fault using iommu_report_device_fault(), which calls the registered handler. The page fault handler then calls the mm fault handler, and reports either success or failure with iommu_page_response(). After the handler succeeds, the hardware retries the access. The iopf_param pointer could be embedded into iommu_fault_param. But putting iopf_param into the iommu_param structure allows us not to care about ordering between calls to iopf_queue_add_device() and iommu_register_device_fault_handler(). Tested-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Link: https://lore.kernel.org/r/20210401154718.307519-7-jean-philippe@linaro.org Signed-off-by: Joerg Roedel <jroedel@suse.de>
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