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2023-11-01Add ISP control for video2 and video3.zejian.su1-0/+23
Signed-off-by: zejian.su <zejian.su@starfivetech.com>
2023-11-01Expand 2 bytes after the SC buffer for the AE/AWB flag and copy the ↵zejian.su1-0/+33
histogram data to the SC buffer.
2023-11-01Add 16 ISP controls, remove the frame SYNC event to video7 (SC) These ↵zejian.su1-3/+45
controls are: WB, CAR, CCM, CFA, CTC, DBC, DNYUV, GMARGB, LCCF, OBC, OECF, R2Y, SAT, SHRP, YCRV, SC
2023-11-01media: satrfive: stf_isp: Add new conctrl supportChanghuang Liang2-0/+259
Add new conctrl for jh7110 isp. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
2023-07-10etherdevice: Adjust ether_addr* prototypes to silence -Wstringop-overeadKees Cook1-3/+2
With GCC 12, -Wstringop-overread was warning about an implicit cast from char[6] to char[8]. However, the extra 2 bytes are always thrown away, alignment doesn't matter, and the risk of hitting the edge of unallocated memory has been accepted, so this prototype can just be converted to a regular char *. Silences: net/core/dev.c: In function ‘bpf_prog_run_generic_xdp’: net/core/dev.c:4618:21: warning: ‘ether_addr_equal_64bits’ reading 8 bytes from a region of size 6 [-Wstringop-overread] 4618 | orig_host = ether_addr_equal_64bits(eth->h_dest, > skb->dev->dev_addr); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ net/core/dev.c:4618:21: note: referencing argument 1 of type ‘const u8[8]’ {aka ‘const unsigned char[8]’} net/core/dev.c:4618:21: note: referencing argument 2 of type ‘const u8[8]’ {aka ‘const unsigned char[8]’} In file included from net/core/dev.c:91: include/linux/etherdevice.h:375:20: note: in a call to function ‘ether_addr_equal_64bits’ 375 | static inline bool ether_addr_equal_64bits(const u8 addr1[6+2], | ^~~~~~~~~~~~~~~~~~~~~~~ Reported-by: Marc Kleine-Budde <mkl@pengutronix.de> Tested-by: Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/netdev/20220212090811.uuzk6d76agw2vv73@pengutronix.de Cc: Jakub Kicinski <kuba@kernel.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: netdev@vger.kernel.org Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2023-06-28Merge branch 'CR_5620_DMA_NONCOHERENT_samin.guo' into 'jh7110-5.15.y-devel'andy.hu1-0/+22
CR5620： Add non-coherent DMA handling See merge request sdk/linux!881
2023-06-27soc: sifive: l2_cache: Add sifive_ccache_flush_rangeSamin Guo1-0/+1
Add sifive_ccache_flush_range to be compatible with new code Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-06-26soc: sifive: ccache: Add non-coherent DMA handlingEmil Renner Berthing1-0/+21
Add functions to flush the caches and handle non-coherent DMA. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2023-06-25uart: 8250: Add dw auto flow ctrl supportMinda Chen2-0/+3
Add designeware 8250 auto flow ctrl support. Enable it by add auto-flow-control in dts. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-06-07driver/include/sound: Normalize the copyright licensesXingyu Wu3-3/+6
Normalize the copyright licenses about clocktree/watchdog/timer/spdif/pwmdac. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2023-04-26reset: starfive: jh7110: Standardize the copyrightHal Feng1-1/+2
Standardize the StarFive copyright information. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-03-16pinctrl: starfive: jh7110: Correct the ioconfig register address and bit ↵Hal Feng1-1/+1
definitions 1. Correct the io_conf_reg address when pin number >= PAD_QSPI_SCLK. 2. The pull-down bit is the fourth bit, so the mask is 0x10. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-01-03RISC-V: Add sscofpmf extension supportAtish Patra1-0/+2
The sscofpmf extension allows counter overflow and filtering for programmable counters. Enable the perf driver to handle the overflow interrupt. The overflow interrupt is a hart local interrupt. Thus, per cpu overflow interrupts are setup as a child under the root INTC irq domain. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Add perf platform driver based on SBI PMU extensionAtish Patra2-2/+5
RISC-V SBI specification added a PMU extension that allows to configure start/stop any pmu counter. The RISC-V perf can use most of the generic perf features except interrupt overflow and event filtering based on privilege mode which will be added in future. It also allows to monitor a handful of firmware counters that can provide insights into firmware activity during a performance analysis. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Add a simple platform driver for RISC-V legacy perfAtish Patra1-0/+6
The old RISC-V perf implementation allowed counting of only cycle/instruction counters using perf. Restore that feature by implementing a simple platform driver under a separate config to provide backward compatibility. Any existing software stack will continue to work as it is. However, it provides an easy way out in future where we can remove the legacy driver. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2023-01-03RISC-V: Add a perf core library for pmu driversAtish Patra1-0/+65
Implement a perf core library that can support all the essential perf features in future. It can also accommodate any type of PMU implementation in future. Currently, both SBI based perf driver and legacy driver implemented uses the library. Most of the common perf functionalities are kept in this core library wile PMU specific driver can implement PMU specific features. For example, the SBI specific functionality will be implemented in the SBI specific driver. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com>
2022-10-28driver: regulator: Add axp15060 pmic regulator driverKevin.xie1-0/+47
Add support for the axp15060 pmic. Signed-off-by: Kevin.xie <kevin.xie@starfivetech.com>
2022-09-07Merge branch 'CR_2026_compatible_5.15_ziv.xu' into 'jh7110-5.15.y-devel'andy.hu2-24/+24
CR_2026_compatible_standard_515 See merge request sdk/linux!459
2022-09-05linux:drivers: revise 'stf' to 'starfive'Ziv.Xu2-24/+24
revise "stf" to "starfive" for PCIE, CPUfreq, CPUidle, PMIC driver. Signed-off-by: Ziv.Xu <Ziv.Xu@starfivetech.com>
2022-08-31v4l2: modify v4l2 compatible namechanghuang.liang1-1/+1
dts/starfive: modify v4l2 compatible name Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-08-26CR_1827_cannot_record_play_simultaneouslyWalker Chen1-0/+9
1.Resolved playback and record can work simultaneously. 2.Rearrange audio configuration in kernel menu. Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-08-19clk:starfive:Modify 'stg_apb' clockXingyu Wu1-14/+15
Change 'stg_apb' clock from external clock to internal clock. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-08-11[Audio: I2S] Support WM8960 one channel play and captruecurry.zhang1-0/+1
Fixed BUG 1754 Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
2022-07-20dt-bindings:clock:Delete external clock definitionsxingyu.wu3-34/+0
Move external clock definitions to C files that avoid illegal use. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-08v4l2: delete csiphy1 and csi1 subdevchanghuang.liang1-3/+2
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-07-01Merge branch 'CR_1456_Reset_5.15_clivia.cai' into 'jh7110-5.15.y-devel'andy.hu1-5/+5
reset:starfive:jh7110: update macro definition. See merge request sdk/linux!219
2022-07-01Merge branch 'CR_1459_V4L2_515_mason.huo' into 'jh7110-5.15.y-devel'andy.hu1-15/+11
Cr 1459 v4 l2 515 mason.huo See merge request sdk/linux!224
2022-07-01media: starfive: Remove isp1 for jh7110mason.huo1-24/+10
For jh7110 soc, there is only one isp controller. To avoid the system errors when config to support dual isp, remove the all isp1 related source code from driver. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-07-01media: starfive: Add dual isp configmason.huo1-1/+5
Add STF_DUAL_ISP Kconfig to config single isp or dual isp. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-07-01v4l2: ISP update irq handlerliuxl03271-1/+7
Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-07-01Add a pm function for GPUWalker Chen1-0/+111
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-07-01reset:starfive:jh7110: update macro definition.Clivia.Cai1-5/+5
remove all “si5“ keyword from reset header file. Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-07-01PMU: Power Domain Controller Driver for JH7110 SOCWalker Chen2-111/+18
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-06-07regulator: stf7110: Add regulator support for JH7110 evbmason.huo1-0/+24
Add 7 regulators base on regulator framework for JH7110 evb HW design. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-06-07soc: starfive: Remove pmic drivermason.huo1-41/+0
The pmic driver should employ regulator framework, rather than a driver in soc. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-05-26v4l2: add macor and ov4689 4dlane configurechanghuang.liang1-2/+38
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-05-26pmic: modify pmic functionchanghuang.liang1-3/+1
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-05-26soc/pmic: add pmic supportchanghuang.liang1-0/+43
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-04-29pmu:starfive:jh7110: Fix some errors and standardize variable namingsamin1-25/+30
Fixed interrupt enabler logic error, fixed PMU_HARD_EVENT definition error, changed some variable names, for better code style. Note: This is an interim version of the pmu driver that provides the power_domian switch function. It can be used in modules such as VPU/JPU/GPU/ISP/VOUT. /* do not upstram */ Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-28Merge branch 'CR_907_GPU_shanlong.li' into 'jh7110_fpga_dev_5.15'andy.hu1-0/+2
Cr 907 gpu shanlong.li See merge request sdk/sft-riscvpi-linux-5.10!37
2022-04-28Merge branch 'CR_737_CLOCK_TREE_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'andy.hu1-0/+53
clk:starfive: Add isp clock tree driver See merge request sdk/sft-riscvpi-linux-5.10!32
2022-04-28driver:pmu : add turn off mask apishanlong.li1-0/+2
add turn off mask api Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-28clk:starfive: Add isp clock tree driverxingyu.wu1-0/+53
Clock references refer to include/dt-bindings/clock/starfive-jh7110-isp.h Enable the isp clock tree driver in dts file if use it. If the fpga is not connetted with isp board, the isp clock tree must be disabled. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-28crypto: add patch for 5.15william.qiu2-0/+170
crypto need this patch to work. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-19update pinctrl marco to more linesjianlong.huang1-730/+1202
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-19reset:starfive:jh7110: Fix wrong macro definition.samin1-4/+4
Fix wrong macro definition. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-14riscv: dts: starfive: Improve the structure of device treeHal Feng1-231/+236
Divide the old device tree into several files according to different layers. Make the device tree clearer and more readable. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-13clk:starfive: Add vout clock tree driverxingyu.wu1-0/+66
Clock references refer to include/dt-bindings/clock/starfive-jh7110-vout.h Change the value about 'status' of clkvout node in dts file when want to use vout clock. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-13clk:starfive: Add JH7110 clock tree driver for kernel 5.15xingyu.wu1-0/+394
Add clock driver about sys, stg and aon clock for JH7110. Clock references refer to include/dt-bindings/clock/starfive-jh7110-clkgen.h Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-07[pinctrl]Synchronize vic7100&jh7110 pinctrl subsystem“jenny.zhang”1-1/+6
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