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path: root/include/linux/intel-iommu.h
AgeCommit message (Expand)AuthorFilesLines
2021-04-07iommu/vt-d: Invalidate PASID cache when root/context entry changedLu Baolu1-0/+1
2021-04-07iommu/vt-d: Remove svm_dev_opsLu Baolu1-3/+0
2021-03-18iommu/vt-d: Report more information about invalidation errorsLu Baolu1-0/+6
2021-02-04iommu/vt-d: Audit IOMMU Capabilities and add helper functionsKyung Min Park1-18/+21
2021-02-04iommu/vt-d: Fix 'physical' typosBjorn Helgaas1-1/+1
2021-01-28iommu/vt-d: Preset Access/Dirty bits for IOVA over FLLu Baolu1-0/+2
2021-01-07iommu/vt-d: Fix general protection fault in aux_detach_device()Liu Yi L1-5/+11
2021-01-07iommu/vt-d: Move intel_iommu info from struct intel_svm to struct intel_svm_devLiu Yi L1-1/+1
2020-11-18iommu/vt-d: Avoid panic if iommu init fails in tboot systemZhenzhong Duan1-1/+0
2020-10-14Merge tag 'iommu-updates-v5.10' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-0/+1
2020-10-12Merge tag 'x86-irq-2020-10-12' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds1-0/+7
2020-09-17iommu/vt-d: Change flags type to unsigned int in binding mmFenghua Yu1-1/+1
2020-09-17drm, iommu: Change type of pasid to u32Fenghua Yu1-6/+6
2020-09-16iommm/vt-d: Store irq domain in struct deviceThomas Gleixner1-0/+7
2020-09-04iommu/vt-d: Move intel_iommu_gfx_mapped to Intel IOMMU headerAndy Shevchenko1-0/+1
2020-07-24iommu/vt-d: Skip TE disabling on quirky gfx dedicated iommuLu Baolu1-0/+2
2020-07-24iommu/vt-d: Add page response ops supportLu Baolu1-0/+3
2020-07-24iommu/vt-d: Refactor device_to_iommu() helperLu Baolu1-2/+1
2020-07-24iommu/vt-d: Remove global page support in devTLB flushJacob Pan1-2/+1
2020-07-24iommu/vt-d: Enforce PASID devTLB field maskLiu Yi L1-2/+2
2020-06-23iommu/vt-d: Set U/S bit in first level page table by defaultLu Baolu1-0/+1
2020-05-29iommu/vt-d: Allocate domain info for real DMA sub-devicesJon Derrick1-0/+1
2020-05-18iommu/vt-d: Add page request draining supportLu Baolu1-0/+4
2020-05-18iommu/vt-d: Multiple descriptors per qi_submit_sync()Lu Baolu1-1/+8
2020-05-18iommu/vt-d: Replace intel SVM APIs with generic SVA APIsJacob Pan1-0/+6
2020-05-18iommu/vt-d: Add get_domain_info() helperLu Baolu1-0/+1
2020-05-18iommu/vt-d: Add custom allocator for IOASIDJacob Pan1-0/+7
2020-05-18iommu/vt-d: Enlightened PASID allocationLu Baolu1-0/+1
2020-05-18iommu/vt-d: Support flushing more translation cache typesJacob Pan1-4/+17
2020-05-18iommu/vt-d: Add bind guest PASID supportJacob Pan1-1/+5
2020-05-18iommu/vt-d: Add nested translation helper functionJacob Pan1-0/+20
2020-05-18iommu/vt-d: Move domain helper to headerJacob Pan1-0/+6
2020-03-13iommu/vt-d: Fix debugfs register readsMegha Dey1-0/+2
2020-01-07iommu/vt-d: debugfs: Add support to show page table internalsLu Baolu1-0/+2
2020-01-07iommu/vt-d: Flush PASID-based iotlb for iova over first levelLu Baolu1-0/+2
2020-01-07iommu/vt-d: Setup pasid entries for iova over first levelLu Baolu1-6/+10
2020-01-07iommu/vt-d: Fix CPU and IOMMU SVM feature matching checksJacob Pan1-1/+4
2019-11-11iommu/vt-d: Fix QI_DEV_IOTLB_PFSID and QI_DEV_EIOTLB_PFSID macrosEric Auger1-2/+4
2019-09-11Merge branches 'arm/omap', 'arm/exynos', 'arm/smmu', 'arm/mediatek', 'arm/qco...Joerg Roedel1-0/+2
2019-09-11iommu/vt-d: Add Scalable Mode fault informationKyung Min Park1-0/+2
2019-09-03iommu/vt-d: Remove global page flush supportJacob Pan1-3/+0
2019-07-04Merge branches 'x86/vt-d', 'x86/amd', 'arm/smmu', 'arm/omap', 'generic-dma-op...Joerg Roedel1-13/+1
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 320Thomas Gleixner1-13/+1
2019-05-28iommu/vt-d: Cleanup get_valid_domain_for_dev()Lu Baolu1-1/+0
2019-05-27iommu/vt-d: Introduce macros useful for dumping DMAR tableSai Praneeth Prakhya1-0/+6
2019-04-11iommu/vt-d: Aux-domain specific domain attach/detachLu Baolu1-0/+10
2019-04-11iommu/vt-d: Add per-device IOMMU feature ops entriesLu Baolu1-0/+1
2019-04-11iommu/vt-d: Make intel_iommu_enable_pasid() more genericLu Baolu1-1/+1
2019-01-11iommu/vt-d: Support page request in scalable modeJacob Pan1-12/+9
2018-12-11iommu/vt-d: Remove deferred invalidationLu Baolu1-8/+0
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