index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
include
/
kvm
/
arm_pmu.h
Age
Commit message (
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)
Author
Files
Lines
2016-02-29
arm64: KVM: Add a new vcpu device control group for PMUv3
Shannon Zhao
1
-0
/
+23
2016-02-29
arm64: KVM: Add a new feature bit for PMUv3
Shannon Zhao
1
-0
/
+2
2016-02-29
arm64: KVM: Free perf event of PMU when destroying vcpu
Shannon Zhao
1
-0
/
+2
2016-02-29
arm64: KVM: Reset PMU state when resetting vcpu
Shannon Zhao
1
-0
/
+2
2016-02-29
arm64: KVM: Add PMU overflow interrupt routing
Shannon Zhao
1
-0
/
+5
2016-02-29
arm64: KVM: Add helper to handle PMCR register bits
Shannon Zhao
1
-0
/
+2
2016-02-29
arm64: KVM: Add access handler for PMSWINC register
Shannon Zhao
1
-0
/
+2
2016-02-29
arm64: KVM: Add access handler for PMOVSSET and PMOVSCLR register
Shannon Zhao
1
-0
/
+2
2016-02-29
arm64: KVM: PMU: Add perf event map and introduce perf event creating function
Shannon Zhao
1
-0
/
+4
2016-02-29
arm64: KVM: Add access handler for PMCNTENSET and PMCNTENCLR register
Shannon Zhao
1
-0
/
+9
2016-02-29
arm64: KVM: Add access handler for event counter register
Shannon Zhao
1
-0
/
+11
2016-02-29
arm64: KVM: Add access handler for PMCR register
Shannon Zhao
1
-0
/
+4
2016-02-29
arm64: KVM: Define PMU data structure for each vcpu
Shannon Zhao
1
-0
/
+42