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2020-06-01Merge branches 'clk-vc5', 'clk-hsdk', 'clk-mediatek' and 'clk-baikal' into ↵Stephen Boyd3-0/+386
clk-next - Support IDT VersaClock 5P49V5925 - Bunch of updates for HSDK clock generation unit (CGU) driver - New clk driver for Baikal-T1 SoCs * clk-vc5: dt: Add bindings for IDT VersaClock 5P49V5925 clk: vc5: Add support for IDT VersaClock 5P49V6965 * clk-hsdk: CLK: HSDK: CGU: add support for 148.5MHz clock CLK: HSDK: CGU: support PLL bypassing CLK: HSDK: CGU: check if PLL is bypassed first * clk-mediatek: clk: mediatek: assign the initial value to clk_init_data of mtk_mux clk: mediatek: Add MT6765 clock support clk: mediatek: add mt6765 clock IDs dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC * clk-baikal: clk: Add Baikal-T1 CCU Dividers driver clk: Add Baikal-T1 CCU PLLs driver dt-bindings: clk: Add Baikal-T1 CCU Dividers binding dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
2020-06-01Merge branches 'clk-mmp', 'clk-intel', 'clk-ingenic', 'clk-qcom' and ↵Stephen Boyd10-28/+598
'clk-silabs' into clk-next - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs - Add support for X1830 and X1000 Ingenic SoC clk controllers - Add support for Qualcomm's MSM8939 Generic Clock Controller - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver - Enable supply regulators for GPU gdscs on Qualcomm SoCs - Add support for Si5342, Si5344 and Si5345 chips * clk-mmp: clk: mmp2: Add audio clock controller driver dt-bindings: clock: Add Marvell MMP Audio Clock Controller binding clk: mmp2: Add support for power islands dt-bindings: marvell,mmp2: Add ids for the power domains dt-bindings: clock: Make marvell,mmp2-clock a power controller clk: mmp2: Add the audio clock clk: mmp2: Add the I2S clocks clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init() clk: mmp2: Move thermal register defines up a bit dt-bindings: marvell,mmp2: Add clock id for the Audio clock dt-bindings: marvell,mmp2: Add clock id for the I2S clocks clk: mmp: frac: Allow setting bits other than the numerator/denominator clk: mmp: frac: Do not lose last 4 digits of precision * clk-intel: clk: intel: remove redundant initialization of variable rate64 clk: intel: Add CGU clock driver for a new SoC dt-bindings: clk: intel: Add bindings document & header file for CGU * clk-ingenic: clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused clk: X1000: Add FIXDIV for SSI clock of X1000. dt-bindings: clock: Add and reorder ABI for X1000. clk: Ingenic: Add CGU driver for X1830. dt-bindings: clock: Add X1830 clock bindings. clk: Ingenic: Adjust cgu code to make it compatible with X1830. clk: Ingenic: Remove unnecessary spinlock when reading registers. * clk-qcom: clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src dt-bindings: clock: Add YAML schemas for QCOM A53 PLL clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller clk: qcom: gcc: Add support for Secure control source clock dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID clk: qcom: gcc: Add support for a new frequency for SC7180 clk: qcom: Add DT bindings for MSM8939 GCC clk: qcom: gcc: Add missing UFS clocks for SM8150 clk: qcom: gcc: Add GPU and NPU clocks for SM8150 clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdsc clk: qcom: gdsc: Handle GDSC regulator supplies clk: qcom: msm8916: Fix the address location of pll->config_reg * clk-silabs: clk: clk-si5341: Add support for the Si5345 series
2020-06-01Merge branches 'clk-unisoc', 'clk-trivial', 'clk-bcm', 'clk-st' and ↵Stephen Boyd1-0/+5
'clk-ast2600' into clk-next * clk-unisoc: clk: sprd: add mipi_csi_xx gate clocks clk: sprd: add dt-bindings include for mipi_csi_xx clocks dt-bindings: clk: sprd: add mipi_csi_xx clocks for SC9863A clk: sprd: check its parent status before reading gate clock clk: sprd: return correct type of value for _sprd_pll_recalc_rate clk: sprd: mark the local clock symbols static * clk-trivial: clk: versatile: remove redundant assignment to pointer clk clk: clk-xgene: Fix a typo in Kconfig clk: Remove unused inline function clk_debug_reparent * clk-bcm: clk: bcm2835: Constify struct debugfs_reg32 clk: bcm2835: Remove casting to bcm2835_clk_register clk: bcm2835: Fix return type of bcm2835_register_gate * clk-st: clk: clk-flexgen: fix clock-critical handling * clk-ast2600: clk: ast2600: Fix AHB clock divider for A1
2020-06-01Merge branches 'clk-tegra', 'clk-imx', 'clk-zynq', 'clk-socfpga', 'clk-at91' ↵Stephen Boyd5-5/+170
and 'clk-ti' into clk-next - Support custom flags in Xilinx zynq firmware - Various small fixes to the Xilinx clk driver - Support for Intel Agilex clks * clk-tegra: clk: tegra: Add Tegra210 CSI TPG clock gate clk: tegra30: Use custom CCLK implementation clk: tegra20: Use custom CCLK implementation clk: tegra: cclk: Add helpers for handling PLLX rate changes clk: tegra: pll: Add pre/post rate-change hooks clk: tegra: Add custom CCLK implementation clk: tegra: Remove the old emc_mux clock for Tegra210 clk: tegra: Implement Tegra210 EMC clock clk: tegra: Export functions for EMC clock scaling clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 clk: tegra: Rename Tegra124 EMC clock source file dt-bindings: clock: tegra: Add clock ID for CSI TPG clock * clk-imx: clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice clk: imx: add imx8m_clk_hw_composite_bus clk: imx: add mux ops for i.MX8M composite clk clk: imx8m: migrate A53 clk root to use composite core clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code clk: imx8mp: Define gates for pll1/2 fixed dividers clk: imx: imx8mp: fix pll mux bit clk: imx8m: drop clk_hw_set_parent for A53 dt-bindings: clocks: imx8mp: Add ids for audiomix clocks clk: imx: Add helpers for passing the device as argument clk: imx: pll14xx: Add the device as argument when registering clk: imx: gate2: Allow single bit gating clock clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock wait clk: imx: clk-sscg-pll: Remove unnecessary blank lines clk: imx: drop the dependency on ARM64 for i.MX8M clk: imx7ulp: make it easy to change ARM core clk clk: imx: imx6ul: change flexcan clock to support CiA bitrates * clk-zynq: clk: zynqmp: Make zynqmp_clk_get_max_divisor static clk: zynqmp: Update fraction clock check from custom type flags clk: zynqmp: Add support for custom type flags clk: zynqmp: fix memory leak in zynqmp_register_clocks clk: zynqmp: Fix invalid clock name queries clk: zynqmp: Fix divider2 calculation clk: zynqmp: Limit bestdiv with maxdiv * clk-socfpga: clk: socfpga: agilex: add clock driver for the Agilex platform dt-bindings: documentation: add clock bindings information for Agilex clk: socfpga: add const to _ops data structures clk: socfpga: remove clk_ops enable/disable methods clk: socfpga: stratix10: use new parent data scheme * clk-at91: clk: at91: allow setting all PMC clock parents via DT clk: at91: allow setting PCKx parent via DT clk: at91: optimize pmc data allocation clk: at91: pmc: decrement node's refcount clk: at91: pmc: do not continue if compatible not located clk: at91: Add peripheral clock for PTC * clk-ti: clk: ti: dra7: remove two unused symbols clk: ti: dra7xx: fix RNG clock parent clk: ti: dra7xx: mark MCAN clock as DRA76x only clk: ti: dra7xx: fix gpu clkctrl parent clk: ti: omap5: Add proper parent clocks for l4-secure clocks clk: ti: omap4: Add proper parent clocks for l4-secure clocks clk: ti: composite: fix memory leak
2020-06-01Merge branches 'clk-selectable', 'clk-amlogic', 'clk-renesas', 'clk-samsung' ↵Stephen Boyd3-0/+72
and 'clk-allwinner' into clk-next - Allow the COMMON_CLK config to be selectable * clk-selectable: clk: Move HAVE_CLK config out of architecture layer MIPS: Loongson64: Drop asm/clock.h include ARM: mmp: Remove legacy clk code clk: Allow the common clk framework to be selectable mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OF MIPS: Remove redundant CLKDEV_LOOKUP selects h8300: Remove redundant CLKDEV_LOOKUP selects arm64: tegra: Remove redundant CLKDEV_LOOKUP selects ARM: Remove redundant CLKDEV_LOOKUP selects ARM: Remove redundant COMMON_CLK selects * clk-amlogic: clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers clk: meson: meson8b: Make the CCF use the glitch-free VPU mux clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits clk: meson: meson8b: Fix the polarity of the RESET_N lines clk: meson: meson8b: Fix the first parent of vid_pll_in_sel clk: meson: g12a: Prepare the GPU clock tree to change at runtime clk: meson: gxbb: Prepare the GPU clock tree to change at runtime clk: meson: meson8b: make the hdmi_sys clock tree mutable clk: meson8b: export the HDMI system clock * clk-renesas: dt-bindings: clock: renesas: mstp: Convert to json-schema dt-bindings: clock: renesas: div6: Convert to json-schema clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects clk: renesas: cpg-mssr: Add R8A7742 support dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding clk: renesas: Add r8a7742 CPG Core Clock Definitions dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros MAINTAINERS: Add DT Bindings for Renesas Clock Generators clk: renesas: r9a06g032: Fix some typo in comments dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support * clk-samsung: clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1 ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough; clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical * clk-allwinner: clk: sunxi: Fix incorrect usage of round_down()
2020-05-31dt-bindings: mailbox: Add devicetree binding for Qcom IPCCManivannan Sadhasivam1-0/+33
Add devicetree YAML binding for Qualcomm Inter-Processor Communication Controller (IPCC) block. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30dt-bindings: clk: Add Baikal-T1 CCU Dividers bindingSerge Semin2-0/+57
After being gained by the CCU PLLs the signals must be transformed to be suitable for the clock-consumers. This is done by a set of dividers embedded into the CCU. A first block of dividers is used to create reference clocks for AXI-bus of high-speed peripheral IP-cores of the chip. The second block dividers alter the PLLs output signals to be then consumed by SoC peripheral devices. Both block DT nodes are ordinary clock-providers with standard set of properties supported. But in addition to that each clock provider can be used to reset the corresponding clock domain. This makes the AXI-bus and System Devices CCU DT nodes to be also reset-providers. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-mips@vger.kernel.org Link: https://lore.kernel.org/r/20200526222056.18072-3-Sergey.Semin@baikalelectronics.ru Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-30dt-bindings: clk: Add Baikal-T1 CCU PLLs bindingSerge Semin1-0/+16
Baikal-T1 Clocks Control Unit is responsible for transformation of a signal coming from an external oscillator into clocks of various frequencies to propagate them then to the corresponding clocks consumers (either individual IP-blocks or clock domains). In order to create a set of high-frequency clocks the external signal is firstly handled by the embedded into CCU PLLs. So the corresponding dts-node is just a normal clock-provider node with standard set of properties. Note as being part of the Baikal-T1 System Controller its DT node is supposed to be a child the system controller node. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-mips@vger.kernel.org Link: https://lore.kernel.org/r/20200526222056.18072-2-Sergey.Semin@baikalelectronics.ru Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-29clk: mediatek: add mt6765 clock IDsMars Cheng1-0/+313
Add MT6765 clock dt-bindings, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1582278742-1626-5-git-send-email-macpaul.lin@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-29clk: qcom: Add missing msm8998 ufs_unipro_core_clk_srcJeffrey Hugo1-0/+1
ufs_unipro_core_clk_src is required to allow UFS to clock scale for power savings. Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20200528142205.44003-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-29dt-bindings: clock: Add and reorder ABI for X1000.周琰杰 (Zhou Yanjie)1-28/+36
1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not directly derived from the output of SSIPLL, but from the clock obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2" is added for this purpose, it must between "X1000_CLK_SSIPLL" and "X1000_CLK_SSIMUX", otherwise an error will occurs when initializing the clock. These ABIs are only used for X1000, and I'm sure that no other devicetree out there is using these ABIs, so we should be able to reorder them. 2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU are also added. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200528031549.13846-7-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-29dt-bindings: clock: Add X1830 clock bindings.周琰杰 (Zhou Yanjie)1-0/+55
Add the clock bindings for the X1830 Soc from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200528031549.13846-5-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28dt-bindings: clock: Add Marvell MMP Audio Clock Controller bindingLubomir Rintel1-0/+10
This describes the bindings for a controller that generates master and bit clocks for the I2S interface. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200519224151.2074597-13-lkundrak@v3.sk Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28dt-bindings: marvell,mmp2: Add ids for the power domainsLubomir Rintel1-0/+11
On MMP2 the audio and GPU blocks are on separate power islands. On MMP3 the camera block's power is also controlled separately. Add the numbers that we could use to refer to the power domains for respective power islands from the device tree. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200519224151.2074597-11-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28dt-bindings: marvell,mmp2: Add clock id for the Audio clockLubomir Rintel1-0/+1
This clocks the Audio block. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200519224151.2074597-5-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28dt-bindings: marvell,mmp2: Add clock id for the I2S clocksLubomir Rintel1-0/+2
There are two of these on a MMP2. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200519224151.2074597-4-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27clk: sprd: add dt-bindings include for mipi_csi_xx clocksChunyan Zhang1-0/+5
mipi_csi_xx clocks are used by camera sensors. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200527053638.31439-4-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27clk: at91: allow setting all PMC clock parents via DTMichał Mirosław1-0/+3
We need to have clocks accessible via phandle to select them as peripheral clock parent using assigned-clock-parents in DT. Add support for PLLACK/PLLBCK/AUDIOPLLCK clocks where available. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lkml.kernel.org/r/fa39cc10dab8341ea4bc2b7152be9217b2cd34a5.1588630999.git.mirq-linux@rere.qmqm.pl Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27clk: at91: allow setting PCKx parent via DTMichał Mirosław1-0/+1
This exposes PROGx clocks for use in assigned-clocks DeviceTree property for selecting PCKx parent clock. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Link: https://lkml.kernel.org/r/0054532c00163ddf405dad658b32f0d7d97fcc8e.1588630999.git.mirq-linux@rere.qmqm.pl Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock IDTaniya Das1-0/+1
The gcc_sec_ctrl_clk_src clock is required to be controlled by the secure controller driver. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1589709861-27580-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27dt-bindings: documentation: add clock bindings information for AgilexDinh Nguyen1-0/+70
Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200512181647.5071-4-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27dt-bindings: clk: intel: Add bindings document & header file for CGURahul Tanwar1-0/+165
Clock generation unit(CGU) is a clock controller IP of Intel's Lightning Mountain(LGM) SoC. Add DT bindings include file and document for CGU clock controller driver of LGM. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com> Link: https://lkml.kernel.org/r/8dce2be13195aab20c6b11fca6af0fffe22d5241.1587102634.git.rahul.tanwar@linux.intel.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26Merge tag 'amlogic-dt64' of ↵Arnd Bergmann1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.8 Highlights: - new boards :Beelink GT-King Pro (G12B SoC), Smartlabs SML-5442TW (S905D), Hardkernel ODROID-C4 (SM1) - audio: support for GX-family SoCs - audio: internal DAC support - use the new USB control driver for GXL and GXM * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (33 commits) arm64: dts: meson-g12b-gtking-pro: add initial device-tree dt-bindings: arm: amlogic: add support for the Beelink GT-King Pro arm64: dts: meson-g12b-gtking: add initial device-tree dt-bindings: arm: amlogic: add support for the Beelink GT-King arm64: dts: meson: convert ugoos-am6 to common w400 dtsi arm64: dts: meson: add ethernet interrupt to wetek dtsi arm64: dts: meson: add support for the Smartlabs SML-5442TW dt-bindings: arm: amlogic: add support for the Smartlabs SML-5442TW dt-bindings: add vendor prefix for Smartlabs LLC arm64: dts: meson: g12: add internal DAC glue arm64: dts: meson: g12: add internal DAC arm64: dts: meson: libretech-pc: add internal DAC support arm64: dts: meson: libretech-ac: add internal DAC support arm64: dts: meson: libretech-cc: add internal DAC support arm64: dts: meson: p230-q200: add internal DAC support arm64: dts: meson: gxl: add acodec support arm64: dts: meson-sm1: add support for Hardkernel ODROID-C4 dt-bindings: arm: amlogic: add odroid-c4 bindings arm64: dts: meson-sm1: add cpu thermal nodes arm64: dts: meson-g12b: move G12B thermal nodes to meson-g12b.dtsi ... Link: https://lore.kernel.org/r/5ec6f56a.1c69fb81.fc5d5.9ca6@mx.google.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-26Merge tag 'imx-drivers-5.8' of ↵Arnd Bergmann1-0/+84
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX drivers update for 5.8: - Optimize imx-scu driver to use one TX and one RX instead of four for talking to SCU. - Fix one possible message header corruption where the response is longer than the request. - Move System Control defines into dt-bindings header, so that DT can use them as well. - A couple of small fixups. * tag 'imx-drivers-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: firmware: imx: scu: Fix possible memory leak in imx_scu_probe() dt-bindings: firmware: imx: Add more system controls and PM clock types dt-bindings: firmware: imx: Move system control into dt-binding headfile firmware: imx: scu: Fix corruption of header firmware: imx-scu: Support one TX and one RX soc: imx8m: No need to put node when of_find_compatible_node() failed Link: https://lore.kernel.org/r/20200523032516.11016-1-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-26Merge tag 'tegra-for-5.8-media' of ↵Arnd Bergmann5-30/+30
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers media: tegra: Changes for v5.8-rc1 This contains a V4L2 video capture driver for Tegra210. * tag 'tegra-for-5.8-media' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: media: tegra-video: Do not enable COMPILE_TEST MAINTAINERS: correct path in TEGRA VIDEO DRIVER media: tegra-video: Make tegra210_video_formats static MAINTAINERS: Add Tegra Video driver section media: tegra-video: Add Tegra210 Video input driver dt-bindings: i2c: tegra: Document Tegra210 VI I2C dt-bindings: tegra: Add VI and CSI bindings dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 dt-bindings: memory: tegra: Add external memory controller binding for Tegra210 dt-bindings: clock: tegra: Remove PMC clock IDs dt-bindings: clock: tegra: Add clock ID for CSI TPG clock Link: https://lore.kernel.org/r/20200515145311.1580134-7-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-26Merge tag 'qcom-drivers-for-5.8' of ↵Arnd Bergmann1-0/+12
git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm driver updates for v5.8 This contains a large set of cleanups, bug fixes, general improvements and documentation fixes for the RPMH driver. It adds a debugfs mechanism for inspecting Command DB. Socinfo got the "soc_id" attribute defines and definitions for a various variants of MSM8939. RPMH, RPMPD and RPMHPD where made possible to build as modules, but RPMH had to be reverted due to a compilation issue when tracing is enabled. RPMHPD gained power-domains for the SM8250 voltage corners. The SCM driver gained fixes for two build warnings and the SMP2P had an unnecessary error print removed. * tag 'qcom-drivers-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (42 commits) Revert "soc: qcom: rpmh: Allow RPMH driver to be loaded as a module" soc: qcom: rpmh-rsc: Remove the pm_lock soc: qcom: rpmh-rsc: Simplify locking by eliminating the per-TCS lock kernel/cpu_pm: Fix uninitted local in cpu_pm soc: qcom: rpmh-rsc: We aren't notified of our own failure w/ NOTIFY_BAD soc: qcom: rpmh-rsc: Correctly ignore CPU_CLUSTER_PM notifications firmware: qcom_scm-legacy: Replace zero-length array with flexible-array soc: qcom: rpmh-rsc: Timeout after 1 second in write_tcs_reg_sync() soc: qcom: rpmh-rsc: Factor "tcs_reg_addr" and "tcs_cmd_addr" calculation soc: qcom: socinfo: add msm8936/39 and apq8036/39 soc ids soc: qcom: aoss: Add SM8250 compatible soc: qcom: pdr: Remove impossible error condition soc: qcom: rpmh: Dirt can only make you dirtier, not cleaner soc: qcom: rpmhpd: Add SM8250 power domains firmware: qcom_scm: fix bogous abuse of dma-direct internals dt-bindings: soc: qcom: apr: Use generic node names for APR services firmware: qcom_scm: Remove unneeded conversion to bool soc: qcom: cmd-db: Properly endian swap the slv_id for debugfs soc: qcom: cmd-db: Use 5 digits for printing address soc: qcom: cmd-db: Cast sizeof() to int to silence field width warning ... Link: https://lore.kernel.org/r/20200519052533.1250024-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-25Merge tag 'reset-for-v5.8' of git://git.pengutronix.de/pza/linux into ↵Arnd Bergmann3-29/+79
arm/drivers Reset controller updates for v5.8 This tag adds support for i.MX8MP and i.MX8MN SoCs to the i.MX7 reset controller driver, extends the Hi6220 reset driver to support the AO reset controller used to bring the Mali450 GPU out of reset, and adds a define for the internal DAC reset line on Amlogic GXL SoCs. * tag 'reset-for-v5.8' of git://git.pengutronix.de/pza/linux: reset: hi6220: Add support for AO reset controller reset: imx7: Add support for i.MX8MP SoC dt-bindings: reset: imx7: Document usage on i.MX8MP SoC dt-bindings: reset: imx7: Add support for i.MX8MN dt-bindings: reset: meson: add gxl internal dac reset Link: https://lore.kernel.org/r/20200515143844.GA17201@pengutronix.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-25Merge tag 'amlogic-drivers' of ↵Arnd Bergmann2-0/+26
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/drivers soc: amlogic: driver updates for v5.8 - support GX SoCs in the EE power-controller driver * tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: soc: amlogic: meson-ee-pwrc: add support for the Meson GX SoCs soc: amlogic: meson-ee-pwrc: add support for Meson8/Meson8b/Meson8m2 dt-bindings: power: meson-ee-pwrc: add support for the Meson GX SoCs dt-bindings: power: meson-ee-pwrc: add support for Meson8/8b/8m2 Link: https://lore.kernel.org/r/5ec6f570.1c69fb81.a3753.711b@mx.google.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-22Merge tag 'v5.8-rockchip-dts64-1' of ↵Arnd Bergmann1-11/+0
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt New soc variant the rk3326 which is essentially a px30 with only one display controller and a new board using it, the Odroid Advance Go. sdcard regulator for the rockpro64 and a lot of devicetree fixes making the dt-binding check a lot happier. * tag 'v5.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (22 commits) arm64: dts: rockchip: fix pinctrl-names for gpio-leds node on rk3326-odroid-go2 arm64: dts: rockchip: fix pd_tcpc0 and pd_tcpc1 node position on rk3399 arm64: dts: rockchip: add bus-width properties to mmc nodes for px30 arm64: dts: rockchip: remove disable-wp from rk3308-roc-cc emmc node arm64: dts: rockchip: rename and label gpio-led subnodes arm64: dts: rockchip: fix defines in pd_vio node for rk3399 arm64: dts: rockchip: fix &pinctrl phy sub nodename for rk3399-orangepi arm64: dts: rockchip: fix rtl8211e nodename for rk3399-orangepi arm64: dts: rockchip: fix &pinctrl phy sub nodename for rk3399-nanopi4 arm64: dts: rockchip: fix rtl8211e nodename for rk3399-nanopi4 arm64: dts: rockchip: fix rtl8211f nodename for rk3328 Beelink A1 arm64: dts: rockchip: fix phy nodename for rk3328 include: dt-bindings: rockchip: remove unused defines arm64: dts: rockchip: replace RK_FUNC defines in rk3326-odroid-go2 arm64: dts: rockchip: Define the rockchip Video Decoder node on rk3399 arm64: dts: rockchip: remove #sound-dai-cells from &spdif node of rk3399-hugsun-x99.dts arm64: dts: rockchip: remove #sound-dai-cells from &i2s1 node of rk3399-pinebook-pro.dts arm64: dts: rockchip: add Odroid Advance Go dt-bindings: Add binding for Hardkernel Odroid Go Advance arm64: dts: rockchip: add core devicetree for rk3326 ... Link: https://lore.kernel.org/r/1970481.V9vR1fIhX2@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'tegra-for-5.8-dt-bindings' of ↵Arnd Bergmann5-30/+30
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.8-rc1 This adds bindings for the CSI TPG clock on Tegra210, moves various clocks from the clock and reset controller to the PMC where their controls really are, adds bindings for the external memory controller and video capture controller on Tegra210, as well as CPU frequency scaling on Tegra20 and Tegra30. * tag 'tegra-for-5.8-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: i2c: tegra: Document Tegra210 VI I2C dt-bindings: tegra: Add VI and CSI bindings dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 dt-bindings: memory: tegra: Add external memory controller binding for Tegra210 dt-bindings: clock: tegra: Remove PMC clock IDs dt-bindings: clock: tegra: Add clock ID for CSI TPG clock Link: https://lore.kernel.org/r/20200515145311.1580134-4-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'renesas-arm-dt-for-v5.8-tag2' of ↵Arnd Bergmann2-0/+71
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.8 (take two) - Initial support for the Renesas RZ/G1H SoC on the iWave RainboW Qseven SOM (G21M) and board (G21D), - Support for the AISTARVISION MIPI Adapter V2.1 camera board on the Silicon Linux EK874 RZ/G2E evaluation kit. * tag 'renesas-arm-dt-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: r8a774c0-cat874: Add support for AISTARVISION MIPI Adapter V2.1 ARM: dts: r8a7742: Add GPIO nodes ARM: dts: r8a7742: Add [H]SCIF{A|B} support ARM: dts: r8a7742: Add IRQC support ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM ARM: dts: r8a7742: Initial SoC device tree clk: renesas: Add r8a7742 CPG Core Clock Definitions dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros Link: https://lore.kernel.org/r/20200515100547.14671-3-geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-20clk: imx8mp: use imx8m_clk_hw_composite_core to simplify codePeng Fan1-1/+10
Use imx8m_clk_hw_composite_core to simpliy clks that belong to core clk slice. Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-20clk: imx8mp: Define gates for pll1/2 fixed dividersPeng Fan1-1/+18
Inspried from commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers") On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate. Only one of these gates (the one "dividing" by one) is currently defined and it's incorrectly set as the parent of all the fixed-factor dividers. Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed dividers. Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-20dt-bindings: power: meson-ee-pwrc: add support for the Meson GX SoCsMartin Blumenstingl1-0/+13
The power domains on the GX SoCs are very similar to G12A. The only known differences so far are: - The GX SoCs do not have the HHI_VPU_MEM_PD_REG2 register (for the VPU power-domain) - The GX SoCs have an additional reset line called "dvin" Add a new compatible string and adjust the reset line expectations for these SoCs. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200515204709.1505498-3-martin.blumenstingl@googlemail.com
2020-05-20dt-bindings: power: meson-ee-pwrc: add support for Meson8/8b/8m2Martin Blumenstingl1-0/+13
The power domains on the 32-bit Meson8/Meson8b/Meson8m2 SoCs are very similar to what G12A still uses. The (known) differences are: - Meson8 doesn't use any reset lines at all - Meson8b and Meson8m2 use the same reset lines, which are different from what the 64-bit SoCs use - there is no "vapb" clock on the older SoCs - amlogic,ao-sysctrl cannot point to the whole AO sysctrl region but only the power management related registers Add a new compatible string and adjust clock and reset line expectations for each SoC. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200515204709.1505498-2-martin.blumenstingl@googlemail.com
2020-05-19dt-bindings: phy: Add PHY_TYPE_XPCS definitionDilip Kota1-0/+1
Add definition for Ethernet PCS phy type. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Acked-by: Rob Herring <robh@kernel.org> Acked-By: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/6091f0d2a1046f1e3656d9e33b6cc433d5465eaf.1589868358.git.eswara.kota@linux.intel.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-19include: dt-bindings: rockchip: remove unused definesJohan Jonker1-11/+0
The Rockchip dtsi and dts files have been bulk-converted for the remaining raw gpio numbers into their descriptive counterparts and also got rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings, so remove the unused defines in 'rockchip.h' to prevent that someone start using them again. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20200512203524.7317-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-05-15clk: qcom: Add DT bindings for MSM8939 GCCBryan O'Donoghue2-0/+316
Add compatible strings and the include files for the MSM8939 GCC. Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Vincent Knecht <vincent.knecht@mailoo.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lkml.kernel.org/r/20200512115023.2856617-2-bryan.odonoghue@linaro.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-13dt-bindings: firmware: imx: Add more system controls and PM clock typesDong Aisheng1-1/+34
Add more system controls and PM clock types for usage. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-13dt-bindings: firmware: imx: Move system control into dt-binding headfileDong Aisheng1-0/+51
i.MX8 SoCs DTS file needs system control macro definitions, so move them into dt-binding headfile, then include/linux/firmware/imx/types.h can be removed and those drivers using it should be changed accordingly. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-12clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210Joseph Lo1-2/+2
Introduce the low jitter path of PLLP and PLLMB which can be used as EMC clock source. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12dt-bindings: clock: tegra: Add clock ID for CSI TPG clockSowjanya Komatineni1-1/+1
Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock ID for this CSI TPG clock from PLLD. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12dt-bindings: clock: tegra: Remove PMC clock IDsSowjanya Komatineni5-29/+29
clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so these clocks should be provided by the Tegra PMC. IDs for these clocks have been defined in dt-bindings/soc/tegra-pmc.h. This patch removes the IDs for these clocks from the Tegra clock device tree bindings. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-06dt-bindings: reset: meson: add gxl internal dac resetJerome Brunet1-1/+1
Add the reset line of the internal DAC found on the amlogic gxl SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-05-06dt-bindings: reset: imx7: Document usage on i.MX8MP SoCAnson Huang1-0/+50
The driver now supports i.MX8MP, so update bindings accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-05-06dt-bindings: reset: imx7: Add support for i.MX8MNAnson Huang1-28/+28
i.MX8MN can reuse i.MX8MQ's reset driver, update the compatible property and related info to support i.MX8MN. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-04-29dt-bindings: clocks: imx8mp: Add ids for audiomix clocksAbel Vesa1-0/+62
Add all the clock ids for the audiomix clocks. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-28interconnect: imx: Add platform driver for imx8mnLeonard Crestez1-0/+41
Add a platform driver for the i.MX8MN SoC describing bus topology, based on internal documentation. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Link: https://lore.kernel.org/r/338a5409ce88811ba6c940ba06441db3faa8c187.1586174566.git.leonard.crestez@nxp.com Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
2020-04-28interconnect: imx: Add platform driver for imx8mqLeonard Crestez1-0/+48
Add a platform driver for the i.MX8MQ SoC describing bus topology, based on internal documentation. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Tested-by: Martin Kepplinger <martin.kepplinger@puri.sm> Link: https://lore.kernel.org/r/864310d1f2599c3bd621e70b77028a6e89f6410e.1586174566.git.leonard.crestez@nxp.com Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
2020-04-28interconnect: imx: Add platform driver for imx8mmLeonard Crestez1-0/+50
Add a platform driver for the i.MX8MM SoC describing bus topology. Bandwidth adjustments is currently only supported on the DDRC and main NOC. Scaling for the vpu/gpu/display NICs could be added in the future. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Link: https://lore.kernel.org/r/b14eef179dbd837a486619724b8033490f49db72.1586174566.git.leonard.crestez@nxp.com Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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