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2024-09-26Merge tag 'soc-ep93xx-dt-6.12' of ↵Linus Torvalds1-0/+46
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC update from Arnd Bergmann: "Convert ep93xx to devicetree This concludes a long journey towards replacing the old board files with devictree description on the Cirrus Logic EP93xx platform. Nikita Shubin has been working on this for a long time, for details see the last post on https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/" * tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits) dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config net: cirrus: use u8 for addr to calm down sparse dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0 dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe() pinctrl: ep93xx: Fix raster pins typo spi: ep93xx: update kerneldoc comments for ep93xx_spi clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate() clk: ep93xx: add module license dmaengine: cirrus: remove platform code ASoC: cirrus: edb93xx: Delete driver ARM: ep93xx: soc: drop defines ARM: ep93xx: delete all boardfiles ata: pata_ep93xx: remove legacy pinctrl use pwm: ep93xx: drop legacy pinctrl ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms ARM: dts: ep93xx: Add EDB9302 DT ARM: dts: ep93xx: add ts7250 board ARM: dts: add Cirrus EP93XX SoC .dtsi ...
2024-09-22Merge branches 'clk-devm', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into ↵Stephen Boyd20-133/+1181
clk-next * clk-devm: clk: provide devm_clk_get_optional_enabled_with_rate() clk: fixed-rate: add devm_clk_hw_register_fixed_rate_parent_data() * clk-samsung: clk: samsung: add top clock support for ExynosAuto v920 SoC clk: samsung: clk-pll: Add support for pll_531x dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS clk: samsung: clk-pll: Add support for pll_1418x clk: samsung: exynosautov9: add dpum clock support dt-bindings: clock: exynosautov9: add dpum clock clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix dt-bindings: clock: exynos7885: Add indices for USB clocks dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices dt-bindings: clock: exynos7885: Fix duplicated binding clk: samsung: exynos850: Add TMU clock dt-bindings: clock: exynos850: Add TMU clock * clk-rockchip: dt-bindings: clock, reset: fix top-comment indentation rk3576 headers clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitions clk: rockchip: fix error for unknown clocks clk: rockchip: rk3588: drop unused code clk: rockchip: Add clock controller for the RK3576 clk: rockchip: Add new pll type pll_rk3588_ddr dt-bindings: clock, reset: Add support for rk3576 dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: rk3368: Drop CLK_NR_CLKS usage clk: rockchip: rk3328: Drop CLK_NR_CLKS usage clk: rockchip: rk3308: Drop CLK_NR_CLKS usage clk: rockchip: rk3288: Drop CLK_NR_CLKS usage clk: rockchip: rk3228: Drop CLK_NR_CLKS usage clk: rockchip: rk3036: Drop CLK_NR_CLKS usage clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228 * clk-qcom: (47 commits) clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC's clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src dt-bindings: usb: qcom,dwc3: Update ipq5332 clock details dt-bindings: interconnect: Add Qualcomm IPQ5332 support clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions clk: qcom: Fix SM_CAMCC_8150 dependencies clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table clk: qcom: gcc-sc8180x: Add GPLL9 support dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x clk: qcom: clk-rpmh: Fix overflow in BCM vote dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camcc dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videocc dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschema dt-bindings: clock: Add x1e80100 LPASSCC reset controller ...
2024-09-22Merge branches 'clk-amlogic', 'clk-microchip' and 'clk-imx' into clk-nextStephen Boyd3-0/+14
* clk-amlogic: clk: meson: introduce symbol namespace for amlogic clocks clk: meson: axg-audio: add sm1 earcrx clocks clk: meson: axg-audio: setup regmap max_register based on the SoC dt-bindings: clock: axg-audio: add earcrx clock ids clk: meson: s4: pll: Constify struct regmap_config clk: meson: s4: peripherals: Constify struct regmap_config clk: meson: c3: pll: Constify struct regmap_config clk: meson: c3: peripherals: Constify struct regmap_config clk: meson: a1: pll: Constify struct regmap_config clk: meson: a1: peripherals: Constify struct regmap_config * clk-microchip: clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs clk: at91: sam9x7: add sam9x7 pmc driver dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT clk: at91: sama7g5: move mux table macros to header file clk: at91: sam9x7: add support for HW PLL freq dividers clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller dt-bindings: clocks: atmel,at91sam9x5-sckc: add sam9x7 * clk-imx: (27 commits) clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL clk: imx95: enable the clock of NETCMIX block control dt-bindings: clock: add RMII clock selection dt-bindings: clock: add i.MX95 NETCMIX block control clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data clk: imx: composite-7ulp: Use NULL instead of 0 clk: imx: add missing MODULE_DESCRIPTION() macros clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate clk: imx: fracn-gppll: update rate table clk: imx: imx8qxp: Parent should be initialized earlier than the clock clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks clk: imx: imx8qxp: Add LVDS bypass clocks clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one clk: imx: imx8mn: add sai7_ipg_clk clock settings clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D clk: imx: imx8mp: fix clock tree update of TF-A managed clocks clk: imx: fracn-gppll: fix fractional part of PLL getting lost clk: imx: composite-7ulp: Check the PCC present bit ...
2024-09-12dt-bindings: soc: Add Cirrus EP93xxNikita Shubin1-0/+46
Add device tree bindings for the Cirrus Logic EP93xx SoC. Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me> Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-10dt-bindings: clock, reset: fix top-comment indentation rk3576 headersHeiko Stuebner1-6/+6
Block comments should align the * on each line, as checkpatch rightfully pointed out, so fix that style issue on the newly added rk3576 headers. Fixes: 49c04453db81 ("dt-bindings: clock, reset: Add support for rk3576") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240909223149.85364-1-heiko@sntech.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-29dt-bindings: clock, reset: Add support for rk3576Detlev Casanova1-0/+592
Add clock and reset ID defines for rk3576. Compared to the downstream bindings written by Elaine, this uses continous gapless IDs starting at 0. Thus all numbers are different between downstream and upstream, but names are kept exactly the same. Also add documentation for the rk3576 CRU core. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/0102019199a76766-f3a2b53f-d063-458b-b0d1-dfbc2ea1893c-000000@eu-west-1.amazonses.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-29dt-bindings: clock: add RMII clock selectionWei Fang1-0/+3
Add RMII clock selection for ENETC0 and ENETC1. Signed-off-by: Wei Fang <wei.fang@nxp.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240829011849.364987-3-wei.fang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-08-28dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKSJohan Jonker8-20/+0
CLK_NR_CLKS and CLKPMU_NR_CLKS should not be part of the binding. Remove since the kernel code no longer uses it. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/a3292ed0-3489-4887-8567-40ea4983c592@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-23dt-bindings: clock: add ExynosAuto v920 SoC CMU bindingsSunyeal Hong1-0/+191
Add dt-schema for ExynosAuto v920 SoC clock controller. Add device tree clock binding definitions for below CMU blocks. - CMU_TOP - CMU_PERIC0/1 - CMU_MISC - CMU_HSI0/1 Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> Link: https://lore.kernel.org/r/20240821232652.1077701-2-sunyeal.hong@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-16Merge branch '20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr' into clk-for-6.12Bjorn Andersson1-0/+5
Merge updates to MSM8998 GCC binding include file through topic branch, to make available the newly added constants to both clock and DeviceTree branch.
2024-08-16dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitionsAngeloGioacchino Del Regno1-0/+5
Add definitions for the Q6 BIMC, LPASS core and adsp smmu clocks, required to enable audio functionality on MSM8998. Add the GDSC definitions for the LPASS_ADSP_GDSC and LPASS_CORE_GDSC as a final step to enable the required clock tree for the lpass iommu and for the audio dsp itself. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180xSatya Priya Kakitapalli1-0/+1
Add the missing GPLL9 which is required for the gcc sdcc2 clock. Fixes: 0fadcdfdcf57 ("dt-bindings: clock: Add SC8180x GCC binding") Cc: stable@vger.kernel.org Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-2-8b3eaa5fb856@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15Merge branch '20240611133752.2192401-1-quic_ajipan@quicinc.com' into ↵Bjorn Andersson3-0/+219
clk-for-6.12 Merge the SM4450 display, camera and GPU bindings through a topic branch, to make it possible to merge them into the DeviceTree source branch as well.
2024-08-15dt-bindings: clock: qcom: add GPUCC clocks on SM4450Ajit Pandey1-0/+62
Add device tree bindings for the graphics clock controller on Qualcomm SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20240611133752.2192401-7-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15dt-bindings: clock: qcom: add CAMCC clocks on SM4450Ajit Pandey1-0/+106
Add device tree bindings for the camera clock controller on Qualcomm SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240611133752.2192401-5-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15dt-bindings: clock: qcom: add DISPCC clocks on SM4450Ajit Pandey1-0/+51
Add device tree bindings for the display clock controller on Qualcomm SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240611133752.2192401-3-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-11dt-bindings: clock: exynosautov9: add dpum clockKwanghoon Son1-0/+11
Add dpum clock definitions and compatibles. Also used clock name 'bus' instead of full clock name dout_clkcmu_dpum_bus like other board cmu schema (GS101). Signed-off-by: Kwanghoon Son <k.son@samsung.com> Link: https://lore.kernel.org/r/20240809-clk_dpum-v3-1-359decc30fe2@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-08dt-bindings: clock: exynos7885: Add indices for USB clocksDavid Virag1-11/+19
Exynos7885 SoC has a DWC3 USB Controller with Exynos USB PHY which in theory supports USB3 SuperSpeed, but is only used as USB2 in all known devices. These, of course, need some clocks. Add indices for these clocks. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240806121157.479212-4-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-08dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indicesDavid Virag1-0/+2
Add indices for missing MUX clocks from PLLs in CMU_TOP. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240806121157.479212-3-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-08dt-bindings: clock: exynos7885: Fix duplicated bindingDavid Virag1-1/+1
The numbering in Exynos7885's FSYS CMU bindings has 4 duplicated by accident, with the rest of the bindings continuing with 5. Fix this by moving CLK_MOUT_FSYS_USB30DRD_USER to the end as 11. Since CLK_MOUT_FSYS_USB30DRD_USER is not used in any device tree as of now, and there are no other clocks affected (maybe apart from CLK_MOUT_FSYS_MMC_SDIO_USER which the number was shared with, also not used in a device tree), this is the least impactful way to solve this problem. Fixes: cd268e309c29 ("dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS") Cc: stable@vger.kernel.org Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20240806121157.479212-2-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-07dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DTVarshini Rajendran1-0/+4
Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE clock from phandle in DT for sam9x7 SoC family. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20240729070803.1990916-1-varshini.rajendran@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-08-02dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPGLad Prabhakar1-0/+21
Document the device tree bindings for the Renesas RZ/V2H(P) SoC Clock Pulse Generator (CPG). CPG block handles the below operations: - Generation and control of clock signals for the IP modules - Generation and control of resets - Control over booting - Low power consumption and power supply domains Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the core clocks are a subset of the ones which are listed as part of section 4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240729202645.263525-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-01Merge branch '20240717-dispcc-sm8550-fixes-v2-7-5c4a3128c40b@linaro.org' ↵Bjorn Andersson1-102/+1
into clk-for-6.12 Merge the SM8550/SM8650 display clock controller binding header file merge through a topic branch, to ensure the bindings are kept in sync between clock and DeviceTree source branches.
2024-08-01dt-bindings: clock: qcom,sm8650-dispcc: replace with symlinkDmitry Baryshkov1-102/+1
The display clock controller indices for SM8650 and SM8550 are completely equal. Replace the header file for qcom,sm8650-dispcc with the symlink to the qcom,sm8550-dispcc header file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-7-5c4a3128c40b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-01Merge branch '20240731062916.2680823-7-quic_skakitap@quicinc.com' into ↵Bjorn Andersson1-0/+135
clk-for-6.12 Merge SM8150 camera clock controller binding through topic branch, to allow this to be shared with DeviceTree source branches as well.
2024-08-01dt-bindings: clock: qcom: Add SM8150 camera clock controllerSatya Priya Kakitapalli1-0/+135
Add device tree bindings for the camera clock controller on Qualcomm SM8150 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240731062916.2680823-7-quic_skakitap@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-01dt-bindings: clock: qcom: Add missing USB MP resetsBjorn Andersson1-0/+4
The USB multiport controller needs a few missing resets, describe them in the binding. Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240730-sc8180x-usb-mp-v2-1-a7dc4265b553@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31dt-bindings: clock: exynos850: Add TMU clockSam Protsenko1-0/+1
Add a constant for TMU PCLK clock. It acts simultaneously as an interface clock (to access TMU registers) and an operating clock which makes TMU IP-core functional. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240723163311.28654-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-07-29dt-bindings: clock: axg-audio: add earcrx clock idsJerome Brunet1-0/+7
Add clock IDs for the eARC Rx device found on sm1 SoCs Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240719093934.3985139-2-jbrunet@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-07-16Merge branches 'clk-qcom', 'clk-rockchip', 'clk-sophgo' and 'clk-thead' into ↵Stephen Boyd14-4/+836
clk-next - Add support for the AP sub-system clock controller in the T-Head TH1520 * clk-qcom: (71 commits) clk: qcom: Park shared RCGs upon registration clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks clk: qcom: common: Add interconnect clocks support interconnect: icc-clk: Add devm_icc_clk_register interconnect: icc-clk: Specify master/slave ids dt-bindings: clock: qcom: Add AHB clock for SM8150 clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks dt-bindings: interconnect: Add Qualcomm IPQ9574 support clk: qcom: kpss-xcc: Return of_clk_add_hw_provider to transfer the error clk: qcom: lpasscc-sc8280xp: Constify struct regmap_config clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocks clk: qcom: gcc-ipq6018: update sdcc max clock frequency clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver dt-bindings: clock: qcom: Add SM8650 camera clock controller dt-bindings: clock: qcom: Update the order of SC8280XP camcc header clk: qcom: videocc-sm8550: Add SM8650 video clock controller clk: qcom: videocc-sm8550: Add support for videocc XO clk ares dt-bindings: clock: qcom: Add SM8650 video clock controller dt-bindings: clock: qcom: Update SM8450 videocc header file name clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's ... * clk-rockchip: dt-bindings: clock: rk3188-cru-common: remove CLK_NR_CLKS clk: rockchip: rk3188: Drop CLK_NR_CLKS usage clk: rockchip: Switch to use kmemdup_array() clk: rockchip: rk3128: Add HCLK_SFC dt-bindings: clock: rk3128: Add HCLK_SFC dt-bindings: clock: rk3128: Drop CLK_NR_CLKS clk: rockchip: rk3128: Drop CLK_NR_CLKS usage clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks clk: rockchip: rk3128: Export PCLK_MIPIPHY dt-bindings: clock: rk3128: Add PCLK_MIPIPHY * clk-sophgo: clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate() clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id() clk: sophgo: Add SG2042 clock driver dt-bindings: clock: sophgo: add clkgen for SG2042 dt-bindings: clock: sophgo: add RP gate clocks for SG2042 dt-bindings: clock: sophgo: add pll clocks for SG2042 * clk-thead: clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller
2024-07-16Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and ↵Stephen Boyd12-714/+282
'clk-samsung' into clk-next * clk-renesas: clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C clk: renesas: r8a779h0: Add Audio clocks clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP dt-bindings: clock: rcar-gen2: Remove obsolete header files dt-bindings: clock: r8a7779: Remove duplicate newline clk: renesas: Drop "Renesas" from individual driver descriptions clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments clk: renesas: r8a779h0: Add VIN clocks dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock clk: renesas: r8a77970: Use common cpg_lock clk: renesas: r8a779h0: Add CSI-2 clocks clk: renesas: r8a779h0: Add ISPCS clocks * clk-amlogic: clk: meson: add missing MODULE_DESCRIPTION() macros dt-bindings: clock: meson: a1: peripherals: support sys_pll input dt-bindings: clock: meson: a1: pll: introduce new syspll bindings clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL clk: meson: c3: add c3 clock peripherals controller driver clk: meson: c3: add support for the C3 SoC PLL clock dt-bindings: clock: add Amlogic C3 peripherals clock controller dt-bindings: clock: add Amlogic C3 SCMI clock controller support dt-bindings: clock: add Amlogic C3 PLL clock controller dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format clk: meson: s4: fix pwm_j_div parent clock clk: meson: s4: fix fixed_pll_dco clock * clk-allwinner: clk: sunxi-ng r40: Constify struct regmap_config clk: sunxi-ng: h616: Add clock/reset for GPADC dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks clk: sunxi: Remove unused struct 'gates_data' clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros * clk-samsung: clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical clk: samsung: Switch to use kmemdup_array() clk: samsung: exynos-clkout: Remove misleading of_match_table/MODULE_DEVICE_TABLE
2024-07-11dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controllerDrew Fustini1-0/+96
Document bindings for the T-Head TH1520 AP sub-system clock controller. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf Co-developed-by: Yangtao Li <frank.li@vivo.com> Signed-off-by: Yangtao Li <frank.li@vivo.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> Link: https://lore.kernel.org/r/20240623-th1520-clk-v2-1-ad8d6432d9fb@tenstorrent.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-07-04dt-bindings: clock: rk3188-cru-common: remove CLK_NR_CLKSJohan Jonker1-2/+0
CLK_NR_CLKS should not be part of the binding. Remove since the kernel code no longer uses it. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/6f21c09b-e8d2-4749-aca6-572c79df775d@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-06-26Merge branch '20240602114439.1611-1-quic_jkona@quicinc.com' into clk-for-6.11Bjorn Andersson2-0/+218
Merge SM8650 video and camera clock drivers through topic branch, to make available the DeviceTree binding includes to the DeviceTree source branches as well.
2024-06-26dt-bindings: clock: qcom: Add SM8650 camera clock controllerJagadeesh Kona1-0/+195
Add device tree bindings for the camera clock controller on Qualcomm SM8650 platform. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240602114439.1611-7-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-26dt-bindings: clock: qcom: Add SM8650 video clock controllerJagadeesh Kona1-0/+23
SM8650 video clock controller has most clocks same as SM8450, but it also has few additional clocks and resets. Add device tree bindings for the video clock controller on Qualcomm SM8650 platform by defining these additional clocks and resets on top of SM8450. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240602114439.1611-3-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-24dt-bindings: clock: rcar-gen2: Remove obsolete header filesGeert Uytterhoeven5-713/+0
The clock definitions in <dt-bindings/clock/r8a779?-clock.h> were superseded by those in <dt-bindings/clock/r8a779?-cpg-mssr.h> a long time ago. The last DTS user of these files was removed in commit 362b334b17943d84 ("ARM: dts: r8a7791: Convert to new CPG/MSSR bindings") in v4.15. Driver support for the old bindings was removed in commit 58256143cff7c2e0 ("clk: renesas: Remove R-Car Gen2 legacy DT clock support") in v5.5, so there is no point to keep on carrying these. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/d4abb688d666be35e99577a25b16958cbb4c3c98.1718796005.git.geert+renesas@glider.be
2024-06-24dt-bindings: clock: r8a7779: Remove duplicate newlineMarek Vasut1-1/+0
Drop duplicate newline. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240616160038.45937-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-06-23dt-bindings: clock: rk3128: Add HCLK_SFCAlex Bee1-0/+1
Add a clock id for SFC's AHB clock. Signed-off-by: Alex Bee <knaerzche@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240606143401.32454-5-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-06-23dt-bindings: clock: rk3128: Drop CLK_NR_CLKSAlex Bee1-2/+0
CLK_NR_CLKS should not be part of the binding. Let's drop it, since the kernel code no longer uses it either. Signed-off-by: Alex Bee <knaerzche@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240606143401.32454-4-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-06-22dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocksChris Morgan1-0/+1
Add the required clock bindings for the GPADC. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240605172049.231108-2-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-06-14dt-bindings: clock: sophgo: add clkgen for SG2042Chen Wang1-0/+111
Add bindings for the clock generator of divider/mux and gates working for other subsystem than RP subsystem for Sophgo SG2042. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Rob Herring <robh@kernel.org>
2024-06-14dt-bindings: clock: sophgo: add RP gate clocks for SG2042Chen Wang1-0/+58
Add bindings for the gate clocks of RP subsystem for Sophgo SG2042. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Rob Herring <robh@kernel.org>
2024-06-14dt-bindings: clock: sophgo: add pll clocks for SG2042Chen Wang1-0/+14
Add bindings for the pll clocks for Sophgo SG2042. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Guo Ren <guoren@kernel.org>
2024-06-13Merge branch '20240606-topic-rb1_gpu-v4-1-4bc0c19da4af@linaro.org' into ↵Bjorn Andersson1-0/+32
clk-for-6.11 Merge the QCM2290 GPUCC binding through a topic branch to allow for it to also be merged into the DeviceTree branch.
2024-06-13dt-bindings: clock: Add Qcom QCM2290 GPUCCKonrad Dybcio1-0/+32
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's QCM2290 SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-1-4bc0c19da4af@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-13dt-bindings: clock: add qca8386/qca8084 clock and reset definitionsLuo Jie1-0/+101
QCA8386/QCA8084 includes the clock & reset controller that is accessed by MDIO bus. Two work modes are supported, qca8386 works as switch mode, qca8084 works as PHY mode. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240605124541.2711467-3-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-10dt-bindings: clock: meson: a1: peripherals: support sys_pll inputDmitry Rokosov1-0/+1
The 'sys_pll' input is an optional clock that can be used to generate 'sys_pll_div16', which serves as one of the sources for the GEN clock. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240515185103.20256-5-ddrokosov@salutedevices.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-06-10dt-bindings: clock: meson: a1: pll: introduce new syspll bindingsDmitry Rokosov1-0/+1
The 'syspll' PLL is a general-purpose PLL designed specifically for the CPU clock. It is capable of producing output frequencies within the range of 768MHz to 1536MHz. The 'syspll_in' source clock is an optional parent connection from the peripherals clock controller. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240515185103.20256-3-ddrokosov@salutedevices.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-06-04dt-bindings: clock: add Amlogic C3 peripherals clock controllerXianwei Zhao1-0/+212
Add the peripherals clock controller dt-bindings for Amlogic C3 SoC family Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Co-developed-by: Chuan Liu <chuan.liu@amlogic.com> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/r/20240522082727.3029656-4-xianwei.zhao@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-23 00:05:43 +0300