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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
include
/
dt-bindings
/
clock
/
tegra210-car.h
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Commit message (
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Author
Files
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2021-01-27
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
Sowjanya Komatineni
1
-1
/
+1
2020-06-10
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
1
-2
/
+2
2020-05-12
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
Joseph Lo
1
-2
/
+2
2020-05-12
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
Sowjanya Komatineni
1
-1
/
+1
2020-05-12
dt-bindings: clock: tegra: Remove PMC clock IDs
Sowjanya Komatineni
1
-7
/
+7
2020-02-17
dt-bindings: clock: tegra: Add IDs for OSC clocks
Sowjanya Komatineni
1
-1
/
+3
2019-11-11
clk: tegra: Reimplement SOR clocks on Tegra210
Thierry Reding
1
-3
/
+3
2019-11-11
clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
Thierry Reding
1
-1
/
+0
2019-10-29
dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT
Thierry Reding
1
-1
/
+2
2018-03-08
clk: tegra: Add la clock for Tegra210
Peter De Schrijver
1
-1
/
+1
2017-11-17
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/ar...
Linus Torvalds
1
-0
/
+1
2017-11-02
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Greg Kroah-Hartman
1
-0
/
+1
2017-10-17
dt-bindings: clock: tegra: Add sor1_out clock
Thierry Reding
1
-0
/
+1
2017-04-04
clk: tegra: Add missing Tegra210 clocks
Peter De Schrijver
1
-8
/
+8
2017-03-20
clk: tegra: Add aclk
Peter De Schrijver
1
-0
/
+2
2017-03-20
clk: tegra: Define Tegra210 DMIC sync clocks
Peter De Schrijver
1
-1
/
+8
2017-03-20
clk: tegra: Add CEC clock
Peter De Schrijver
1
-1
/
+1
2017-03-20
clk: tegra: Fix ISP clock modelling
Peter De Schrijver
1
-2
/
+2
2016-06-17
clk: tegra: Enable sor1 and sor1_src on Tegra210
Thierry Reding
1
-1
/
+1
2016-04-28
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Rhyland Klein
1
-1
/
+1
2016-02-02
clk: tegra: Add the APB2APE audio clock on Tegra210
Jon Hunter
1
-1
/
+1
2015-11-16
clk: tegra: Add Tegra210 device tree binding
Thierry Reding
1
-0
/
+401