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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
include
/
dt-bindings
/
clock
/
meson8b-clkc.h
Age
Commit message (
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)
Author
Files
Lines
2018-11-23
dt-bindings: clock: meson8b: export the CPU post dividers
Martin Blumenstingl
1
-0
/
+4
2018-04-25
dt-bindings: clock: meson8b: export the NAND clock
Martin Blumenstingl
1
-0
/
+1
2017-11-02
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Greg Kroah-Hartman
1
-0
/
+1
2017-08-04
clk: meson8b: expose every clock in the bindings
Jerome Brunet
1
-0
/
+70
2017-06-12
clk: meson8b: export the ethernet gate clock
Martin Blumenstingl
1
-0
/
+1
2017-06-12
clk: meson8b: export the USB clocks
Martin Blumenstingl
1
-0
/
+5
2017-06-12
clk: meson8b: export the gate clock for the HW random number generator
Martin Blumenstingl
1
-0
/
+1
2017-06-12
clk: meson8b: export the SDIO clock
Martin Blumenstingl
1
-0
/
+1
2017-06-12
clk: meson8b: export the SAR ADC clocks
Martin Blumenstingl
1
-0
/
+2
2016-09-02
clk: meson: Copy meson8b CLKID defines to private header file
Alexander Müller
1
-2
/
+0
2016-06-23
clk: meson8b: clean up composite clocks
Michael Turquette
1
-1
/
+3
2015-06-06
clk: meson: Add support for Meson clock controller
Carlo Caione
1
-0
/
+25